JP7307680B2 - Slew control of high-side switch - Google Patents

Description

TECHNICAL FIELD This disclosure relates to transistor-based switches and, more particularly, to slew control of high-side switches.

(Priority application)
This application claims priority to Indian Patent Application No. 201711012738 filed on April 10, 2017, the entire contents of which are incorporated herein.

High-side switches can be used to drive a variety of loads and therefore can be used in a number of different applications. Typical systems and methods for driving high-side switches utilize charge pumps. A charge pump is a DC-DC converter that uses capacitors as energy storage elements to generate either a high voltage or a low voltage power supply. With respect to the high-side switch, a charge pump is employed to supply other circuit components (such as amplifiers) in addition to supplying DC current to drive the high-side switch. This method requires the use of large capacitors within the charge pump to supply the DC load current. Large capacitors can occupy valuable surface area if an on-chip integrated solution is required. To solve this problem, some systems implement an external capacitor to supply the DC current. Although this reduces the required surface area of the chip, extra pins are included to connect the external capacitors. Using a charge pump design to drive the high-side switch does not contribute to situations where chip size needs to be reduced or pin count needs to be reduced due to cost considerations. Additionally, using a charge pump design requires as few external components as possible, such as external capacitors, as they add to the overall bill of materials (BOM) and cost. do not contribute to the situation.

Generally speaking, a high-side switch includes three main elements: a pass element, a gate control block, and an input logic block. The pass element is usually a transistor, which is typically a metal-oxide-semiconductor field-effect transistor (MOSFET) or a laterally diffused metal-oxide semiconductor transistor. metal oxide semiconductor transistors, LDMOS). LDMOS transistors are considered a type of MOSFET. A pass element operates in the linear region to pass current from the source to the load. A gate control block provides a voltage to the gate of the pass element to switch it "on" or "off." The input logic block interprets the on/off signal and triggers the gate control block to switch the pass element "on" or "off."

In electronics, slew rate is defined as the change in voltage per unit time. Exceeding the slew rate of the circuit can cause signal distortion. Also, exceeding the slew rate increases the amount of electromagnetic emission (EME), thereby violating electromagnetic compatibility (EMC) standards and potentially interfering with other electronic devices. There is fear. Therefore, slew rate can impose significant limitations on the operation of corresponding circuits. Adding a current limiter may provide some control over the slew rate, but this solution still requires the use of a large charge pump.

FIG. 1 is a circuit level schematic diagram of known systems and methods for driving a high side switch that includes an additional current limiter. As shown, charge pump 2 is connected to current controller 4 . Current controller 4 includes amplifier 6 and transistor 10 . The transistor 10 used here is a p-channel metal-oxide semiconductor (pMOS). The current controller 4 is powered by the charge pump 2 and controls its output based on the voltage difference developed across the resistors 12,24. The positive rail of amplifier 6 is powered by charge pump 2 and the negative rail of amplifier 6 is powered by supply voltage 8 . A current sensing resistor 12 is connected between charge pump 2 and amplifier 6 . A current sense FET 14 is connected between amplifier 6 and output pin 18 . A high-side switch FET 16 has its drain side connected to charge pump 2 , its gate side connected to the output of amplifier 6 via transistor 10 , and its source side connected to output pin 18 . Output pin 18 is used to connect the system to circuit load 20 . Additionally, a resistor 32 is connected between the gate and source sides of FET 16 . The circuit further includes a clock generator 22 . A resistor 24 is connected between the charge pump 2 and the amplifier 6 . The circuit further includes load reference 26 . Also shown is FET 28 connected in series with resistor 30 when high side switch FET 16 is turned "off". Current limiter 34 is used to provide some control over the slew rate of high side switch FET 16 .

Still referring to FIG. 1, charge pump 2 must deliver significant output current due to its connection to amplifier 6 and high side switch FET 16 . Rapidly charging the gate of the high side switch to the desired voltage V _GS using current controller 4 draws a substantial amount of current from charge pump 2 . Charge pump 2 therefore includes a relatively large capacitor, which makes it difficult to integrate the circuit of FIG. 1 onto a single chip. Large integrated capacitors increase silicon die size, thereby increasing product cost. If the large capacitor is located externally, additional pins are required and any external capacitor can increase the BOM cost and therefore the overall system cost. Using current limiter 34 to control the slew rate of high side switch FET 16 results in the need for large charge pump 2 .

Therefore, there is a need for improved systems and methods for controlling the slew rate of high side switches.

The above needs are met by the disclosed system and method for controlling high side switch slew rate that includes sampling and level shifting circuitry.

An exemplary circuit for high side switch slew rate control is disclosed. The circuit comprises a sample and level shift circuit. A sample and level shift circuit is connected to the high side switch. The circuit further comprises a sampling capacitor configured to sample an input voltage corresponding to the sample and level shift circuit. Additionally, the circuit includes a charge limiting mechanism that can be implemented as a circuit. A sampling capacitor is configured to charge the gate capacitance of the high side switch. A charge limiting mechanism is configured to limit the rate of charge transferred to the gate capacitance of the high side switch per unit time.

An exemplary method is disclosed for controlling the slew rate of a high side switch. The method includes providing an input current to a sample and level shift circuit. The method further includes sampling the input voltage. A sampling capacitor is configured for sampling the input voltage. Additionally, the method includes level shifting the input voltage. The method includes using a sampling capacitor to charge the gate capacitance of the high side switch. Additionally, the method includes limiting the charge supplied to the sampling capacitor, the charge being limited by at least one current sink.
The present invention provides, for example, the following.
(Item 1)
A circuit for slew rate control of a high side switch, comprising:
a sample and level shift circuit connected to the high side switch;
a charge limiting circuit;
A sampling capacitor, the sampling capacitor comprising:
sampling an input voltage corresponding to the sample and level shift circuit; and
a sampling capacitor configured to charge a gate capacitance of the high-side switch;
A circuit, wherein the charge limiting circuit is configured to limit the rate of charge transferred to the gate capacitance of the high side switch per unit time.
(Item 2)
2. The circuit of item 1, wherein the charge limiting circuit is further configured to limit current associated with the sampling capacitor.
(Item 3)
2. The circuit of item 1, wherein the charge limiting circuit is further configured to limit the voltage associated with the sampling capacitor.
(Item 4)
4. The circuit of any one of items 1-3, wherein the charge limiting circuit is further configured to limit the sampling capacitance associated with the sample and level shift circuit.
(Item 5)
4. The circuit of any one of items 1-3, wherein the charge limiting circuit is further configured to limit the frequency associated with the sample and level shift circuit.
(Item 6)
6. The circuit of any one of items 1-5, wherein the high-side switch is an n-channel metal oxide semiconductor field effect transistor (nMOS transistor).
(Item 7)
7. The circuit of any one of items 1-6, wherein the slew rate control circuit for the high side switch is an integrated circuit on a single chip.
(Item 8)
8. The circuit of any one of items 1-7, wherein the charge limiting circuit comprises an adjustable voltage source.
(Item 9)
9. The circuit of any one of items 1-8, wherein the charge limiting circuit comprises the sampling capacitor.
(Item 10)
the sampling capacitor is an adjustable sampling capacitor;
10. The circuit of any one of items 1-9, wherein the charge limiting circuit comprises the sampling capacitor.
(Item 11)
A method for controlling the slew rate of a high side switch, comprising:
providing an input current to the sample and level shift circuit;
sampling an input voltage with a sampling capacitor configured for said sampling of said input voltage;
level shifting the input voltage;
charging the gate capacitance of the high-side switch using the sampling capacitor;
limiting the charge supplied to the sampling capacitor, the charge being limited by at least one current sink.
(Item 12)
12. The method of claim 11, further comprising: connecting a transistor in parallel with said at least one current sink; and turning on said transistor to remove any charge limit corresponding to said at least one current sink. the method of.
(Item 13)
13. A method according to item 11 or 12, further comprising selecting one of said at least one current sink or said at least one current sink corresponding to different high side switch slew rates.
(Item 14)
14. The method of any one of items 11-13, further comprising limiting the current associated with the sampling capacitor.
(Item 15)
14. The method of any one of items 11-13, further comprising limiting the voltage corresponding to the sampling capacitor.
(Item 16)
16. The method of any one of items 11-15, further comprising limiting a sampling capacitance corresponding to said sample and level shift circuit.
(Item 17)
17. The method of any one of items 11-16, further comprising limiting frequencies corresponding to the sample and level shift circuits.
(Item 18)
A method according to any one of items 11 to 17, wherein the high side switch is an n-channel metal oxide semiconductor field effect transistor (nMOS transistor).
(Item 19)
19. The method of any one of items 11-18, wherein the slew rate is controlled from an integrated circuit on a single chip.
(Item 20)
20. The method of any one of items 11-19, wherein charge limiting is performed by an adjustable voltage source.
(Item 21)
21. A method according to any one of items 11 to 20, wherein charge limiting is further performed by said sampling capacitor.
(Item 22)
A switch device,
high side switch,
A switch device comprising any of the circuits of items 1-10.
(Item 23)
a microcontroller,
high side switch,
A microcontroller comprising any of the circuits of items 1-10.

1 is a circuit level schematic of known systems and methods for driving a high side switch that includes a current limiter; FIG. 1 is a circuit level schematic diagram of one embodiment of a system and method for controlling the slew rate of a high side switch according to the present disclosure; FIG. FIG. 4 is a circuit level schematic diagram of another embodiment of a system and method for controlling the slew rate of a high side switch according to the present disclosure; FIG. 4 is a circuit level schematic diagram of another embodiment of a system and method for controlling the slew rate of a high side switch according to the present disclosure; FIG. 4 is a circuit level schematic diagram of another embodiment of a system and method for controlling the slew rate of a high side switch according to the present disclosure;

Before describing any embodiments of the present invention in detail, the present invention is not limited in its application to the details of construction and arrangement of components set forth in the following description or illustrated in the following drawings. Please understand. The invention is capable of being practiced or carried out in other embodiments and in various ways. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," or "having," and variations thereof herein includes the items listed thereafter and equivalents thereof, as well as additional items. means to Unless otherwise specified or limited, the terms "attached," "connected," "supported," and "coupled," and variations thereof, are used broadly to refer to direct and indirect attachment, connection, and connection. , supporting, and connecting. Furthermore, "connected" and "coupled" are not limited to physical or mechanical connections or couplings.

The following discussion is presented to enable any person skilled in the art to make and use embodiments of the invention. Various modifications to the illustrated embodiments will be readily apparent to those skilled in the art, and the general principles herein may be applied to other embodiments and applications without departing from embodiments of the invention. Accordingly, embodiments of the invention are not intended to be limited to the embodiments shown, but are to be accorded the widest scope consistent with the principles and features disclosed herein. The following detailed description should be read with reference to the figures, in which similar elements in different figures have similar reference numerals. The figures are not necessarily to scale, depict selected embodiments, and are not intended to limit the scope of embodiments of the invention. Those skilled in the art will recognize that the examples provided herein have many useful alternatives that fall within the scope of embodiments of the present invention.

Embodiments of the present disclosure provide systems and methods for controlling the slew rate of high-side switches for use in selectively providing power to output loads.

FIG. 2 is a circuit-level schematic diagram of one embodiment of a system and method for controlling the slew rate of a high-side switch according to the present disclosure; In one embodiment, a sample and level shift circuit 40 may be provided. Sample and level shift circuit 40 may be connected to voltage source 42 . Voltage source 42 may be the output of an amplifier (eg, operational amplifier). Alternatively, voltage source 42 may provide a fixed or variable supply voltage. In certain embodiments, it may be beneficial for voltage source 42 to be 1.8, 2.5, 3.3, or 5 volts. Alternatively, any other voltage level may be provided by voltage source 42 . Sample and level shift circuit 40 may include multiple switches 50 , 52 , 54 , 56 . Sample and level shift circuit 40 may further include a sampling capacitor 58 . Additionally, the sample and level shift circuit 40 may include a field-effect transistor (FET) 60 . Slew control 80 may include current sinks 82, 84, 86 that may be connected in parallel. Slew control 80 may be connected in parallel with FET 60 .

In one non-limiting example, as shown in FIG. 2, the high-side switch 70 can be an n-channel metal oxide semiconductor field effect transistor (nMOS transistor) or an n-channel laterally diffused metal oxide semiconductor transistor (nLDMOS transistor). can do. An nLDMOS transistor is considered a type of nMOS transistor. In certain situations it may be beneficial to use different types of transistors. One output of sample and level shift circuit 40 may be connected to the gate side of high side switch 70 . The drain side of high side switch 70 may be connected to voltage source 48 . Output pin 72 may be connected to a circuit load. In certain non-limiting embodiments, a low side switch may be included and connected to output pin 72 such that high side switch 70 and low side switch form a half bridge configuration.

Still referring to FIG. 2, the sample and level shift circuit 40 may eliminate the need for a charge pump when driving the high side switch 70. FIG. Sampling capacitor 58 may sample the voltage of voltage source 42 . Sampling capacitor 58 may then be used to charge the gate side capacitance of high side switch 70 . Charging the gate-side capacitance may allow the high-side switch 70 to turn "on." In one non-limiting embodiment, the input voltage may be supplied to the circuit load when the high side switch 70 is "on."

In another non-limiting embodiment, the gate capacitance of high side switch 70 can act as a holding capacitor. Therefore, a DC load may not be required on the holding capacitor. Sample and level shift circuit 40 may provide any DC current. In another non-limiting embodiment, an explicit holding capacitor may be connected in parallel with the gate capacitance of high side switch 70 . Again, the holding capacitor may not require a DC load.

In certain non-limiting embodiments, the voltage sources 48, 42 may provide fixed voltages as opposed to having charge pump power amplifiers. In situations where the amplifier functions as voltage source 42, the amplifier may function as a short circuit current controller. In certain situations, it may be beneficial to use different amplifier configurations, or different types of amplifiers. In certain situations, it may be beneficial to include an amplifier configured to operate within a common-mode voltage range from voltage source 48 to several volts below voltage source 48 . Amplifiers can be specially designed to handle high input common-mode voltages and low output common-mode voltages.

In certain circumstances, it may be beneficial to include voltage sources 48, 42 that provide 3.3 volts. Alternatively, voltage sources 48, 42 may provide any other predetermined voltage level, including 5, 12, 14, 24, and 48 volts. In certain circumstances, it may be beneficial to use the vehicle battery for at least one of the voltage sources 48,42. In certain circumstances, it may be beneficial for at least one of the voltage sources 48, 42 to have a supply voltage within the range of 4.5 volts to 60 volts. In one non-limiting embodiment, voltage sources 48, 42 may be configured to increase their respective supply voltages (ie, ramp voltages) over a predetermined period of time.

In one non-limiting embodiment, the disclosed system can be an integrated circuit on a single chip. An integrated circuit may use 1/3 of the chip surface area used by a charge pump system, as shown in FIG. Alternatively, the disclosed system may use up to 99% of the chip surface area used by the charge pump system, as shown in FIG. In certain circumstances, it may be beneficial to specifically include sampling capacitor 58 within an integrated circuit on a single chip. In one non-limiting embodiment, sampling capacitor 58 may be smaller than the capacitor associated with the charge pump system shown in FIG. In some non-limiting embodiments, the sampling capacitor can range in capacitance from 2 pF to 250 pF.

In one non-limiting embodiment, the number of pins included by the present disclosure may be less than the number of pins included by the charge pump system as shown in FIG. In one non-limiting example, the present disclosure may include one less pin than the charge pump system shown in FIG. In another non-limiting example, the present disclosure may include three fewer pins than the charge pump system shown in FIG.

In one non-limiting embodiment, current sinks 82 , 84 , 86 may each control the amount of charge stored on sampling capacitor 58 . By selecting which of the current sinks 82, 84, 86 are active, the slew rate of charging of the high side switch 70 can also be selected. Accordingly, each of current sinks 82 , 84 , 86 may correspond to different slew rate charging of high side switch 70 . FET 60 may be used to short each of current sinks 82, 84, 86 when slew rate control is not desired. By controlling the amount of charge stored in sampling capacitor 58, it may be possible to control the charging rate of high-side switch 70 to _VGS . When FET 60 shorts current sinks 82, 84, 86, sampling capacitor 58 may reach full charge and the slew rate of charging high side switch 70 may be relatively high. The slew rate of high side switch 70 may be programmable.

FIG. 3 is a circuit-level schematic diagram of another embodiment of a system and method for controlling the slew rate of a high-side switch according to the present disclosure; In one embodiment, a sample and level shift circuit 40 may be provided. Sample and level shift circuit 40 may be connected to voltage source 42 . Voltage source 42 may be the output of an amplifier (eg, operational amplifier). Alternatively, voltage source 42 may provide a fixed or variable supply voltage. In certain embodiments, it may be beneficial for voltage source 42 to be 1.8, 2.5, 3.3, or 5 volts. Alternatively, any other voltage level may be provided by voltage source 42 . Sample and level shift circuit 40 may include multiple switches 50 , 52 , 54 , 56 . Sample and level shift circuit 40 may further include a sampling capacitor 58 . Additionally, the sample and level shift circuit 40 may include a field effect transistor (FET) 60 . Slew control 88 may include at least one current sink 82 that may be variable. Slew control 88 may be connected in parallel with FET 60 .

In one non-limiting example, as shown in FIG. 3, the high-side switch 70 can be an n-channel metal oxide semiconductor field effect transistor (nMOS transistor) or an n-channel laterally diffused metal oxide semiconductor transistor (nLDMOS transistor). can do. An nLDMOS transistor is considered a type of nMOS transistor. In certain situations it may be beneficial to use different types of transistors. One output of sample and level shift circuit 40 may be connected to the gate side of high side switch 70 . The drain side of high side switch 70 may be connected to voltage source 48 . Output pin 72 may be connected to a circuit load. In certain non-limiting embodiments, a low side switch may be included and connected to output pin 72 such that high side switch 70 and low side switch form a half bridge configuration.

Still referring to FIG. 3, the sample and level shift circuit 40 may eliminate the need for a charge pump when driving the high side switch 70. FIG. Sampling capacitor 58 may sample the voltage of voltage source 42 . Sampling capacitor 58 may then be used to charge the gate side capacitance of high side switch 70 . Charging the gate-side capacitance may allow the high-side switch 70 to turn "on." In one non-limiting embodiment, the input voltage may be supplied to the circuit load when the high side switch 70 is "on."

In one non-limiting embodiment, current sink 82 controls the amount of charge stored in sampling capacitor 58 . By selecting the current sink 82, the slew rate of charging of the high side switch 70 can also be selected. FET 60 can be used to short current sink 82 when slew rate control is not desired. By controlling the amount of charge stored in sampling capacitor 58, it may be possible to control the charging rate of high-side switch 70 to _VGS . When FET 60 shorts current sink 82, sampling capacitor 58 may reach full charge and the slew rate charging high-side switch 70 may be relatively high. The slew rate of high side switch 70 may be programmable.

2 and 3, it becomes clear that when at least one current sink 82 is implemented, it may be possible to implement any number of current sinks. Referring to FIG. 2, one non-limiting embodiment includes three current sinks 82, 84, 86 connected in parallel. Alternatively, any number of current sinks connected in parallel may be included. Any of the current sinks 82, 84, 86 may be variable and selectable.

FIG. 4 is a circuit-level schematic diagram of another embodiment of a system and method for controlling the slew rate of a high-side switch according to the present disclosure; In one embodiment, a sample and level shift circuit 90 may be provided. A sample and level shift circuit 90 may be connected to the voltage source 42 . Voltage source 42 may be the output of an amplifier (eg, operational amplifier). Alternatively, voltage source 42 may provide a fixed or variable supply voltage. In certain embodiments, it may be beneficial for voltage source 42 to be 1.8, 2.5, 3.3, or 5 volts. Alternatively, any other voltage level may be provided by voltage source 42 . Sample and level shift circuit 40 may include multiple switches 50 , 52 , 54 , 56 . Sample and level shift circuit 40 may further include a sampling capacitor 92 . Slew control may be implemented via sampling capacitor 92 .

In one non-limiting example, as shown in FIG. 4, the high-side switch 70 can be an n-channel metal oxide semiconductor field effect transistor (nMOS transistor) or an n-channel laterally diffused metal oxide semiconductor transistor (nLDMOS transistor). can do. An nLDMOS transistor is considered a type of nMOS transistor. In certain situations it may be beneficial to use different types of transistors. One output of sample and level shift circuit 40 may be connected to the gate side of high side switch 70 . The drain side of high side switch 70 may be connected to voltage source 48 . Output pin 72 may be connected to a circuit load. In certain non-limiting embodiments, a low side switch may be included and connected to output pin 72 such that high side switch 70 and low side switch form a half bridge configuration.

Still referring to FIG. 4, the sample and level shift circuit 90 may eliminate the need for a charge pump when driving the high side switch 70. FIG. Sampling capacitor 92 may sample the voltage of voltage source 42 . Sampling capacitor 92 may then be used to charge the gate side capacitance of high side switch 70 . Charging the gate-side capacitance may allow the high-side switch 70 to turn "on." In one non-limiting embodiment, the input voltage may be supplied to the circuit load when the high side switch 70 is "on."

In one non-limiting embodiment, sampling capacitor 92 may be adjustable. In certain circumstances, it may be beneficial to include an adjustable sampling capacitor 92, as the sampling capacitor 92 may then be used as a charge limiting mechanism. In this non-limiting embodiment, the sampling capacitor corresponds to the sample and level shift circuit. Therefore, adjusting the capacitance of sampling capacitor 92 may allow slew control of high-side switch 70 .

FIG. 5 is a circuit-level schematic diagram of another embodiment of a system and method for controlling the slew rate of a high-side switch according to the present disclosure; In one embodiment, a sample and level shift circuit 96 may be provided. A sample and level shift circuit 96 may be connected to a voltage source 98 . Sample and level shift circuit 40 may include multiple switches 50 , 52 , 54 , 56 . Sample and level shift circuit 40 may further include a sampling capacitor 58 .

In one non-limiting example, as shown in FIG. 5, the high-side switch 70 can be an n-channel metal oxide semiconductor field effect transistor (nMOS transistor) or an n-channel laterally diffused metal oxide semiconductor transistor (nLDMOS transistor). can do. An nLDMOS transistor is considered a type of nMOS transistor. In certain situations it may be beneficial to use different types of transistors. One output of sample and level shift circuit 96 may be connected to the gate side of high side switch 70 . The drain side of high side switch 70 may be connected to voltage source 48 . Output pin 72 may be connected to a circuit load. In certain non-limiting embodiments, a low side switch may be included and connected to output pin 72 such that high side switch 70 and low side switch form a half bridge configuration.

Still referring to FIG. 5, the sample and level shift circuit 96 may eliminate the need for a charge pump when driving the high side switch 70. FIG. Sampling capacitor 96 may sample the voltage of voltage source 98 . Sampling capacitor 96 may then be used to charge the gate side capacitance of high side switch 70 . Charging the gate-side capacitance may allow the high-side switch 70 to turn "on." In one non-limiting embodiment, the input voltage may be supplied to the circuit load when the high side switch 70 is "on."

Voltage source 98 may provide a fixed or variable supply voltage. In certain embodiments, it may be beneficial for voltage source 42 to be 1.8, 2.5, 3.3, or 5 volts. Alternatively, any other voltage level may be provided by voltage source 42 . In one non-limiting embodiment, voltage source 98 may be configured to increase the supply voltage (ie, ramp voltage) over a predetermined period of time. In one non-limiting embodiment, voltage source 98 may be used as a charge limiting mechanism. An adjustable voltage source 98 may limit the voltage corresponding to the charging of the sampling capacitor. In that way the slew rate of the high side switch can be controlled.

In one non-limiting embodiment, the slew control circuit may include other types of charge limiting mechanisms. A charge limiting mechanism may limit the sampled current of sampling capacitor 58 . In certain non-limiting embodiments, the charge limiting mechanism may limit the sampled voltage on sampling capacitor 58 . The sampled current can be in the range of 5uA to 5mA. The sampled voltage can be in the range of 0% to 100% of the final target gate-source voltage. A charge limiting mechanism may be configured to limit the frequencies corresponding to the sample and level shift circuits.

Although the present invention has been described above in connection with specific embodiments and examples, the present invention is not necessarily so limited and many other embodiments from the embodiments, examples, and applications , examples, uses, modifications and developments are intended to be covered by the claims appended hereto. The entire disclosure of each patent and publication cited herein is incorporated by reference as if each such patent or publication was individually incorporated herein by reference. Various features and advantages of the invention are set forth in the following claims.

Claims (15)

A circuit for slew rate control of a high side switch connected to a voltage source, comprising:
a sample and level shift circuit connected to the high side switch, the sample and level shift circuit including four switches;
a charge limiting circuit;
A sampling capacitor, the sampling capacitor comprising:
a sampling capacitor configured to sample an input voltage corresponding to the sample and level shift circuit and to charge the gate capacitance of the high side switch;
the charge limiting circuit,
including a current sink configured to limit charge;
a transistor connected in parallel with the current sink, the transistor being configured to remove any charge limit associated with the current sink; and the gate capacitance of the high-side switch per unit time. is configured to limit the velocity of charge transferred to
the sample and level shift circuit is connected to the source and gate of the high side switch;
When the input voltage is sampled, the first two of the four switches are opened and the remaining two of the four switches are closed to implement level shifting, thereby causing the The charge stored on the sampling capacitor is applied to the gate of the high side switch, causing the high side switch to close , and the voltage applied to the gate of the high side switch is reduced to the supply voltage with respect to ground. A circuit that is shifted by a corresponding amount. 2. The circuit of claim 1, wherein said charge limiting circuit is further configured to limit current flow through said sampling capacitor. 2. The circuit of claim 1, wherein said charge limiting circuit is further configured to limit the voltage applied to said sampling capacitor. A circuit according to any one of claims 1 to 3, wherein said high-side switch is an n-channel metal oxide semiconductor field effect transistor (nMOS transistor). A circuit according to any preceding claim, wherein the circuit for slew rate control of the high side switch is an integrated circuit on a single chip. A circuit according to any preceding claim, wherein the voltage source is an adjustable voltage source. A circuit as claimed in any preceding claim, wherein the sampling capacitor is an adjustable sampling capacitor. A method for controlling the slew rate of a high side switch, comprising:
providing input current to a sample and level shift circuit, the sample and level shift circuit including four switches;
sampling an input voltage with a sampling capacitor, said sampling capacitor configured for said sampling of said input voltage;
level shifting the input voltage;
charging the gate capacitance of the high-side switch using the sampling capacitor;
limiting the charge supplied to the sampling capacitor, the charge being limited by at least one current sink;
connecting a transistor in parallel with the at least one current sink;
turning on said transistor to remove any charge limit corresponding to said at least one current sink, wherein when an input voltage is sampled first two of said four switches are opened. , the remaining two of the four switches are closed to perform a level shift, whereby the charge stored in the sampling capacitor is applied to the gate of the high side switch and the high side switch is applied to the high side switch. A method, wherein a switch is caused to close and the voltage applied to the gate of the high side switch is shifted by an amount corresponding to the supply voltage with respect to ground. each of the at least one current sinks corresponding to a mutually different high side switch slew rate, and the method comprises one of the at least one current sinks corresponding to a predetermined high side switch slew rate or the 9. The method of claim 8, further comprising selecting at least one current sink . 10. The method of any one of claims 8-9, further comprising limiting the current flowing through the sampling capacitor. 10. The method of any one of claims 8-9, further comprising limiting the voltage applied to the sampling capacitor. A method according to any one of claims 8 to 11, wherein said high-side switch is an n-channel metal oxide semiconductor field effect transistor (nMOS transistor). A method according to any one of claims 8 to 12, wherein said slew rate is controlled from an integrated circuit on a single chip. A switch device,
high side switch,
A switching device comprising any of the circuits of claims 1-7. a microcontroller,
high side switch,
A microcontroller comprising any of the circuits of claims 1-7.

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