TW201839988A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device including a semiconductor substrate, a first well, a second well, a first doped region, a second doped region, a third doped region, and a fourth doped region is provided. The semiconductor substrate has a first conductivity type. The first well is formed in the semiconductor substrate and has a second conductivity type. The first well comprises a first region and a second region. The doping concentration of the first region is greater than that of the second region. The second well is formed in the first region and has the first conductivity type. The first doped region is formed in the first region and has the second conductivity type different from the first conductivity type. The second doped region is formed in the second well and has the first conductivity type. The third doped region is formed in the second region and has the first conductivity type. The fourth doped region is formed in the first region and has the second conductivity type.

Description

 Semiconductor device and method of manufacturing same  

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a PN junction.

The transistor is mainly classified into a bipolar junction transistor (BJT) and a field effect transistor (FET). Since the structure of the field effect transistor is simpler than that of the bipolar junction transistor, it is often used. The field effect transistor is further divided into a metal oxide semiconductor FET (MOSFET) and a junction field effect transistor (JFET). However, the junction field effect transistor can only provide a small current. When there is a demand for a large current, it is often only possible to increase the size of the junction field effect transistor, but it will increase the cost.

The present invention provides a semiconductor device including a semiconductor substrate, a first well region, a second well region, a first doped region, a second doped region, a third doped region, and a fourth doping region. Area. The semiconductor substrate has a first conductivity type. The first well region is formed in the semiconductor substrate and has a second conductivity type. The first well region has a first region and a second region. The doping concentration of the first region is higher than the doping concentration of the second region. The second well region has a first conductivity type and is formed in the first region. The first doped region has a second conductivity type and is formed in the first region. The second conductivity type is different from the first conductivity type. The second doped region has a first conductivity type and is formed in the second well region. The third doped region has a first conductivity type and is formed in the second region. The fourth doped region has a second conductivity type and is formed in the first region.

The present invention further provides a method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming a first well region in the semiconductor substrate, wherein the first well region has a second conductivity type; a first region in the first well region, wherein the first region has a first conductivity type; a second region is formed in the first well region, wherein the second region has a first conductivity type, wherein the first region The doping concentration is higher than the doping concentration of the second region; forming a second well region in the first region, wherein the second well region has a first conductivity type; forming a first doping region in the first region Wherein the first doped region has a second conductivity type, and the second conductivity type is different from the first conductivity type; forming a second doped region in the second well region, wherein the second doped region has the first conductive region Forming a third doped region in the second region, wherein the third doped region has a first conductivity type; and forming a fourth doped region in the first region, wherein the third doped region has The second conductivity type.

100, 200, 300‧‧‧ semiconductor devices

110, 210, 310‧‧‧ semiconductor substrate

120, 130, 220, 230, 320, 330‧‧‧ well areas

141~144, 241~244, 341~344‧‧‧ doped area

121, 122, 221~223, 321, 322‧‧‧ areas

W ₁₄₃ , W ₁₂₂ , W ₃₄₃ , W ₃₂₂ ‧ ‧ width

151~154, 251~254, 351~354‧‧‧ isolation structure

160, 260, 360‧‧‧ insulation

171~173, 271~273, 371~373‧‧‧Interconnected structure

Figure 1 is a schematic cross-sectional view showing one of the semiconductor devices of the present invention.

Figure 2 is a schematic cross-sectional view showing another embodiment of the semiconductor device of the present invention.

Figure 3 is a schematic cross-sectional view showing another embodiment of the semiconductor device of the present invention.

4A to 4D are schematic views showing a method of manufacturing a semiconductor device of the present invention.

In order to make the objects, features and advantages of the present invention more comprehensible, the embodiments of the invention are described in detail below. The present specification provides various embodiments to illustrate the technical features of various embodiments of the present invention. The arrangement of the various elements in the embodiments is for illustrative purposes and is not intended to limit the invention. In addition, the overlapping portions of the drawings in the embodiments are for the purpose of simplifying the description, and do not mean the relationship between the different embodiments.

Here, the terms "about" and "about" are usually expressed within 20% of a given value or range, preferably within 10%, and more preferably within 5%. The quantity given here is an approximate quantity, meaning that the meaning of "about" or "about" may be implied without specific explanation.

Figure 1 is a schematic cross-sectional view showing one of the semiconductor devices of the present invention. As shown, the semiconductor device 100 includes a semiconductor substrate 110, well regions 120, 130, and doped regions 141-144. The semiconductor substrate 110 has a first conductivity type. In one possible embodiment, the semiconductor substrate 110 is a germanium substrate or other suitable semiconductor substrate. In other embodiments, the semiconductor substrate 110 can also be a lightly doped substrate, such as a lightly doped P-type or N-type substrate.

The well region 120 is formed in the semiconductor substrate 110 and has a second conductivity type. The second conductivity type is different from the first conductivity type. In a possible embodiment, the first conductivity type is a P type and the second conductivity type is an N type. In another possible embodiment, the first conductivity type is an N type, and the second conductivity type is a P type. In other embodiments, the well region 120 can be formed by an ion implantation step. For example, when the second conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in the region where the well region 120 is to be formed to form the well region 120. However, when the second conductivity type is a P-type, boron ions or indium ions may be implanted in a region where the well region 120 is to be formed to form the well region 120. In some embodiments, well zone 120 is a high pressure well zone.

In the present embodiment, the well region 120 has regions 121 and 122. The doping concentration of the region 121 is higher than the doping concentration of the region 122. As shown, region 122 is formed in region 121. The invention does not limit the manner in which the regions 122 are formed. In a possible embodiment, the ion implantation step is performed only for region 121. In this example, the region 122 is not subjected to an ion implantation step. However, although the region 122 does not perform the ion implantation step, impurities in the region 121 may diffuse laterally into the region 122. Therefore, the regions 122 and 121 have the same conductivity type, such as the second conductivity type, but the doping concentration of the region 122 is lower than the doping concentration of the region 121. In another possible embodiment, the first ion implantation step is performed for the region 121, and the second ion implantation step is performed for the region 122, wherein the first ion implantation step is doped with an impurity concentration higher than the second ion cloth. The concentration of impurities doped in the implant step. Therefore, the doping concentration of the region 121 is higher than the doping concentration of the region 122.

The well region 130 is formed in the region 121 and has a first conductivity type. In a possible embodiment, the well region 130 can also be formed by an ion implantation step. For example, when the first conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the well region 130 is to be formed to form the well region 130. However, when the first conductivity type is a P-type, boron ions or indium ions may be implanted in a region where the well region 130 is to be formed to form the well region 130. In the present embodiment, the doping concentration of the well region 130 is higher than the doping concentration of the semiconductor substrate 110.

The doped region 141 is formed in the region 121 and has a second conductivity type. In a possible embodiment, the doping concentration of the doping region 141 is higher than the doping concentration of the region 121. Doped region 142 is formed in well region 130 and has a first conductivity type. In a possible embodiment, the doping concentration of the doped region 142 is higher than the doping concentration of the well region 130. In the present embodiment, the doping region 142 is located between the doping regions 141 and 143.

The doped region 143 has a first conductivity type and is formed in the region 122. In the present embodiment, the doping region 143 is located between the doping regions 142 and 144. In a possible embodiment, the doping concentration of the doped region 143 is higher than the doping concentration of the well region 130. In another possible embodiment, the doping concentration of the doping region 143 is approximately equal to the doping concentration of the doping region 142. In the present embodiment, the width W ₁₄₃ of the doped region 143 is approximately equal to the width W _{122 of the} region ₁₂₂ . Thus, doped region 143 completely covers region 122, but is not intended to limit the invention. In other embodiments, the width W _{143 of the} doped region 143 may be greater or less than the width W _{122 of the} region ₁₂₂ . In the present embodiment, since the conductivity type of the doping region 143 is different from the conductivity type of the region 122, the doping region 143 and the region 122 have a PN junction. In a possible embodiment, the conductivity type of the doped region 143 is a P type, and the conductivity type of the region 122 is an N type. In another possible embodiment, the conductivity type of the doped region 143 is N-type, and the conductivity type of the region 122 is P-type.

The doped region 144 has a second conductivity type and is formed in the region 121. In a possible embodiment, the doping concentration of the doped region 144 is higher than the doping concentration of the region 121. In another possible embodiment, the doping concentration of the doping region 144 is approximately equal to the doping concentration of the doping region 141. In addition, in the present embodiment, the doping region 144 directly contacts the doping region 143, but is not intended to limit the present invention. In other embodiments, doped regions 144 and 143 are spatially separated from one another.

In a possible embodiment, the semiconductor device 100 further includes isolation structures 151-154. The isolation structure 151 contacts the doped region 141, but is not intended to limit the invention. In other embodiments, the isolation structure 151 is spatially separated from the doped regions 141. Isolation structure 152 is located between doped regions 141 and 142 to separate doped regions 141 and 142. As shown, the isolation structure 152 directly contacts the doped regions 141 and 142, but is not intended to limit the invention. In other embodiments, the isolation structure 152 does not contact at least one of the doped regions 141 and 142.

The isolation structure 153 is located between the doping regions 142 and 143 to separate the doping regions 142 and 143. As shown, the isolation structure 153 directly contacts the doped regions 142 and 143, but is not intended to limit the invention. In other embodiments, the isolation structure 153 does not contact at least one of the doped regions 142 and 143. The isolation structure 154 contacts the doped region 144, but is not intended to limit the invention. In other embodiments, the isolation structure 154 is spatially separated from the doped regions 144.

In other embodiments, the semiconductor structure 100 further includes an insulating layer 160 and interconnect structures 171-173. The insulating layer 160 is formed over the substrate 110 and covers the isolation structures 151 to 154 and the doping regions 141 to 144. In this embodiment, the interconnect structure 171 is electrically connected to the doping region 141 to serve as a source electrode. The interconnect structure 172 is electrically connected to the doped region 142 to serve as a gate electrode. The interconnect structure 173 is electrically connected to the doped regions 143 and 144 to serve as a drain electrode.

In this embodiment, the semiconductor structure 100 provides a junction field effect transistor, wherein the interconnect structure 172 serves as a gate electrode of the junction field effect transistor, and the interconnect structure 171 serves as a source of the junction field effect transistor. The electrode, interconnect structure 173 serves as the drain electrode of the junction field effect transistor. When the interconnect structure 173 delivers a drain voltage pre-doped regions 143 and 144, since the region 122 has a lower doping concentration, the equivalent diode between the doped region 143 and the region 122 will rapidly follow. The conduction is such that the semiconductor structure 100 provides a large current. Furthermore, by adjusting the width W _{122 of the} region 122, the conduction time of the PN junction between the doped region 143 and the region 122 can be controlled. In a possible embodiment, the width W _{122 of the} region 122 is between about 0 and 20 um.

2 is another possible cross-sectional view of a semiconductor device of the present invention. Fig. 2 is similar to Fig. 1, except that the well region 220 of Fig. 2 has regions 221 to 223. In the present embodiment, the doping concentration of the region 222 is lower than the doping concentration of the regions 221 and 223. In a possible embodiment, the doping concentration of region 221 is approximately equal to the doping concentration of region 223.

The invention does not limit the manner in which the regions 222 are formed. In a possible embodiment, the ion cloth value is performed only in predetermined regions of the regions 221 and 223, and the ion cloth value is not performed in a predetermined region of the region 222. In this case, impurities of regions 221 and 223 may diffuse into region 222. Therefore, the conductivity type of the region 222 is the same as that of the regions 221 and 223, as is the second conductivity type. However, the impurity concentration of the region 222 is lower than the impurity concentration of the regions 221 and 223.

In another possible embodiment, the first ion cloth value step is performed in a predetermined region of the regions 221 and 223, and the second ion cloth value step is performed in a predetermined region of the region 222, wherein the impurity concentration doped in the region 222 is lower than The impurity concentration doped in the region 221 .

The characteristics of the substrate 210, the well region 230, the doping regions 241-244, the isolation structures 251 to 254, the insulating layer 260, and the interconnect structures 271 to 273 of the semiconductor device 200 of FIG. 2 and the substrate 110 and well of FIG. The characteristics of the region 130, the doped regions 141 to 144, the isolation structures 151 to 154, the insulating layer 160, and the interconnect structures 171 to 173 are similar, and therefore will not be described again.

Figure 3 is another schematic cross-sectional view of the semiconductor device of the present invention. 3 is similar to FIG. 1 except that the width W ₃₂₂ of the region 322 of FIG. 3 is smaller than the width W _{343 of the} doped region ₃₄₃ . As shown, the doped region 343 covers a portion of the region 321 . In the present embodiment, the conductivity type of the doping region 343 is different from that of the region 322. Furthermore, the conductivity type of the region 321 is the same as that of the region 322, but the doping concentration of the region 321 is lower than the doping concentration of the region 322.

The characteristics of the substrate 310, the well regions 320, 330, the doping regions 341 to 344, the isolation structures 351 to 354, the insulating layer 360, and the interconnect structures 371 to 373 of the semiconductor device 300 of FIG. 3 and the substrate 110 of FIG. 1 The characteristics of the well region 130, the doped regions 141 to 144, the isolation structures 151 to 154, the insulating layer 160, and the interconnect structures 171 to 173 are similar, and therefore will not be described again.

4A to 4D are schematic views showing a method of manufacturing a semiconductor device of the present invention. Referring to FIG. 4A, a semiconductor substrate 110, such as a germanium substrate or other suitable semiconductor substrate, is provided. In other embodiments, the semiconductor substrate 110 can also be a lightly doped substrate, such as a lightly doped P-type or N-type substrate. In the present embodiment, the semiconductor substrate 110 has a first conductivity type.

Then, the well region 120 may be formed in a predetermined region of the semiconductor substrate 110 by a process such as a doping process (for example, ion cloth value) and thermal diffusion. The well region 120 has a second conductivity type. In the present embodiment, the well region 120 has regions 121 and 122, wherein the doping concentration of the region 121 is higher than the doping concentration of the region 122. In a possible embodiment, the doping process is not performed on the region 122, and the doping process is performed on the region 121 outside the region 122. Since the impurities of the region 121 may laterally diffuse to the region 122, the regions 122 and 121 each have a second conductivity type. In another possible embodiment, the first doping process is performed on the region 121, and the second doping process is performed on the region 122, wherein the doping concentration of the first doping process is higher than the doping concentration of the second doping process. . In other embodiments, region 122 is located in region 121.

Next, the well region 130 may be formed in a predetermined region of the region 121 by a process such as a doping process (e.g., ion cloth value) and thermal diffusion. In a possible embodiment, the well region 130 has a first conductivity type. In other embodiments, the doping concentration of the well region 130 is higher than the doping concentration of the semiconductor substrate 110.

Referring to FIG. 4B, isolation structures 151 to 154 are formed on the semiconductor substrate 110. The isolation structure 151 extends into the area 121. The isolation structure 152 extends into the region 121 and the well region 130. In the present embodiment, the isolation structures 151 and 152 define a doped region 141 to be formed. The isolation structure 153 extends into the well region 130 and the region 121. Isolation structures 152 and 153 define doped regions 142 to be formed. Isolation structures 153 and 154 define doped regions 143 and 144 to be formed. The isolation structure 154 extends into the region 121.

Referring to FIG. 4C, doped regions 141-144 may be formed by a doping process such as ion cloth value. In the present embodiment, the doping region 141 is formed in the region 121 and is located between the isolation structures 151 and 152. Doped regions 142 are formed in well region 130 and are located between isolation structures 152 and 153. In the present embodiment, the doping region 142 is located between the doping regions 141 and 143.

A doped region 143 is formed in the region 122. As shown, doped region 143 is between doped regions 142 and 144. In the present embodiment, doped region 143 covers region 122, but is not intended to limit the invention. In other embodiments, doped region 143 more covers portions of region 121. In some embodiments, doped region 143 covers a portion of region 122. A doped region 144 is formed in the region 121 and between the isolation structure 154 and the doped region 143. In the present embodiment, the doped region 144 is in direct contact with the doped region 143, but is not intended to limit the invention. In other embodiments, doped regions 144 and 143 are spatially separated. Moreover, in one possible embodiment, doped regions 141 and 143 have a second conductivity type and dopings 142 and 144 have a first conductivity type.

Referring to FIG. 4D, an insulating layer 160 is formed over the isolation structures 151-154 and the doped regions 141-144. Next, the interconnect structures 171 to 173 are formed on the insulating layer 160 through a metallization process. The interconnect structure 171 is electrically connected to the doped region 141 to serve as a source electrode of a junction field effect transistor. The interconnect structure 172 is electrically connected to the doped region 142 to serve as a gate electrode of the junction field effect transistor. The interconnect structure 173 is electrically connected to the doped regions 143 and 144 to serve as a drain electrode of the junction field effect transistor. In this way, the fabrication of the semiconductor device 100 is completed.

Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning Moreover, unless expressly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related art, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. . For example, the system, apparatus or method of the embodiments of the present invention may be implemented in a physical embodiment of a combination of hardware, software or hardware and software. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (20)

 A semiconductor device comprising: a semiconductor substrate having a first conductivity type; a first well region formed in the semiconductor substrate and having a second conductivity type, wherein the first well region has a first region and a second region, the doping concentration of the first region is higher than a doping concentration of the second region; a second well region having the first conductivity type and formed in the first region; a doped region having the second conductivity type and formed in the first region, wherein the second conductivity type is different from the first conductivity type; a second doped region having the first conductivity type, and Formed in the second well region; a third doped region having the first conductivity type and formed in the second region; and a fourth doped region having the second conductivity type, and Formed in the first region.    The semiconductor device of claim 1, wherein the third doped region completely covers the second region.    The semiconductor device of claim 1, wherein the third doped region covers a portion of the first region.    The semiconductor device of claim 1, wherein the second doped region is between the first and third doped regions.    The semiconductor device of claim 4, wherein the third doped region is between the second and fourth doped regions.    The semiconductor device of claim 1, wherein the third doped region directly contacts the fourth doped region.    The semiconductor device of claim 1, further comprising: a first interconnect structure electrically connected to the first doped region; a second interconnect structure electrically connected to the second doped region; a third interconnect structure electrically connected to the third and fourth doped regions, wherein the first interconnect structure serves as a source of a junction field effect transistor, and the second interconnect structure serves as the junction A gate of the field effect transistor, the third interconnect structure acts as a drain of the junction field effect transistor.    The semiconductor device according to claim 1, wherein the first conductivity type is a P type, and the second conductivity type is an N type.    The semiconductor device according to claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type.    The semiconductor device of claim 1, wherein the second region is located in the first region.    A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming a first well region in the semiconductor substrate, wherein the first well region has a second conductivity type; forming a first An area in the first well region, wherein the first region has the first conductivity type; forming a second region in the first well region, wherein the second region has the first conductivity type, wherein The doping concentration of the first region is higher than the doping concentration of the second region; forming a second well region in the first region, wherein the second well region has the first conductivity type; forming a first a doped region in the first region, wherein the first doped region has the second conductivity type, and the second conductivity type is different from the first conductivity type; forming a second doped region in the second region In the well region, wherein the second doped region has the first conductivity type; forming a third doped region in the second region, wherein the third doped region has the first conductivity type; and forming a fourth doped region in the first region, wherein the third doping The impurity region has the second conductivity type.    The method of fabricating a semiconductor device according to claim 11, wherein the third doped region completely covers the second region.    The method of fabricating a semiconductor device according to claim 11, wherein the third doped region covers a portion of the first region.    The method of fabricating a semiconductor device according to claim 11, wherein the second doped region is located between the first and third doped regions.    The method of fabricating a semiconductor device according to claim 14, wherein the third doped region is located between the second and fourth doped regions.    The method of fabricating a semiconductor device according to claim 11, wherein the third doped region directly contacts the fourth doped region.    The method of manufacturing the semiconductor device of claim 11, further comprising: forming a first interconnect structure, wherein the first interconnect structure is electrically connected to the first doped region for use as a junction Forming a second interconnect structure, wherein the second interconnect structure is electrically connected to the second doped region as a gate of the junction field effect transistor; Forming a third interconnect structure, wherein the third interconnect structure is electrically connected to the third and fourth doped regions for use as a drain of the junction field effect transistor.    The method of manufacturing a semiconductor device according to claim 11, wherein the first conductivity type is a P type and the second conductivity type is an N type.    The method of manufacturing a semiconductor device according to claim 11, wherein the first conductivity type is an N type, and the second conductivity type is a P type.    The method of fabricating a semiconductor device according to claim 11, wherein the second region is located in the first region.