TW201839947A - Fan-out semiconductor package - Google Patents

Abstract

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the first connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip.

Description

Fan-out semiconductor package

The present invention relates to a semiconductor package, and more specifically, to a fan-out type semiconductor package in which connection terminals can extend outside a region where a semiconductor wafer is arranged. [Cross-reference to related applications]

This application claims the priority of Korean Patent Application No. 10-2016-0094624 filed on July 26, 2016 at the Korean Intellectual Property Office, and the application filed at the Korean Intellectual Property Office on March 17, 2017 The priority of Korean Patent Application No. 10-2017-0033803, the entire disclosure content of each Korean patent application mentioned above is incorporated in this case for reference.

Recently, the recent significant trend in the development of semiconductor wafer-related technologies has been to reduce the size of semiconductor wafers. Therefore, in the field of packaging technology, as the demand for small-sized semiconductor wafers and the like has rapidly increased, there has been an increased demand for a semiconductor package that includes multiple pins and has a compact size at the same time.

One packaging technology proposed to meet the above technical requirements is the fan-out packaging. This fan-out type package has a compact size and can achieve multiple input / output (I / O) pins by rewiring the connection terminals outside the area where the semiconductor chip is arranged Make.

The aspect of the present disclosure can provide a fan-out semiconductor package in which power supply efficiency is excellent and cost can be reduced.

One of several solutions proposed in the present disclosure is to introduce a first connection member having a through hole in which a semiconductor wafer is disposed and form a coil pattern layer in the first connection member, the coil pattern layer It will be electrically connected to the semiconductor wafer to implement a power inductor.

According to the aspect of the present disclosure, a fan-out semiconductor package may include: a first connection member having a through hole; a semiconductor chip disposed in the through hole of the first connection member and having an active surface and the The active surface is opposite to the passive surface, and the active surface is provided with a connection pad; an encapsulation body covering at least part of the first connection member and the passive surface of the semiconductor chip; and a second connection member, configured On the first connection member and on the active surface of the semiconductor wafer. The first connection member and the second connection member each include a redistribution layer, the redistribution layer is electrically connected to the connection pad of the semiconductor wafer, and the first connection member includes an electrical connection to A coil pattern layer of the connection pad of the semiconductor wafer.

Hereinafter, each exemplary embodiment of the present invention will be explained with reference to the drawings. In the drawings, the shape, size, etc. of each component may be exaggerated or shortened for clarity.

The term "exemplary embodiment" as used herein does not refer to the same exemplary embodiment, but is provided to emphasize specific features or characteristics that are different from the specific features or characteristics of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be able to be implemented by combining with each other in whole or in part. For example, even if an element described in a specific exemplary embodiment is not set forth in another exemplary embodiment, the element can be understood as unless the contrary or contradictory description is provided herein. Description related to another exemplary embodiment.

The meaning of “connection” between a component and another component in the description includes indirect connection via a third component and direct connection between the two components. In addition, "electrically connected" means to include the concept of physical connection and physical disconnection. It should be understood that when elements are referred to as "first" and "second", the elements are not limited thereby. The use of "first" and "second" may only serve the purpose of distinguishing the element from other elements, and may not limit the order or importance of the elements. In some cases, the first element may be referred to as the second element without departing from the scope of the patent application filed herein. Similarly, the second element can also be referred to as the first element.

Herein, the upper part, the lower part, the upper side, the lower side, the upper surface, the lower surface, etc. are judged in the drawings. For example, the first connection member is disposed at a higher level than the second connection member. However, the patent scope of this application is not limited to this. In the present invention, the vertical direction refers to the above upward and downward directions, and the horizontal direction refers to the direction perpendicular to the above upward and downward directions. In this case, the vertical cross section refers to a case taken along a plane in the vertical direction, and an example of the vertical cross section may be a cross-sectional view shown in the drawing. In addition, the horizontal cross section refers to a case taken along a plane in the horizontal direction, and an example of the horizontal cross section may be a plan view shown in the drawings.

The terminology used herein is merely to illustrate exemplary embodiments and not to limit the present invention. In this case, unless otherwise explained in the context, singular forms include plural forms. Electronic device

FIG. 1 is a schematic block diagram illustrating an example of an electronic device system.

Referring to FIG. 1, the electronic device 1000 can accommodate a motherboard 1010. The motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc. that are physically connected or electrically connected to the motherboard 1010. These components can be connected to other components described below to form various signal lines 1090.

The chip-related components 1020 may include: memory chips, such as volatile memory (eg, dynamic random access memory (DRAM)), non-volatile memory (eg, read only memory) memory, ROM)), flash memory, etc .; application processor chips, such as central processing unit (eg, central processing unit (CPU)), graphics processor (eg, graphic processing unit, GPU)), digital signal processor, cryptographic processor, microprocessor, microcontroller, etc .; and logic chips, such as analog-to-digital converters, application-specific integrated circuits (ASIC) Etc .; or similar wafers. However, the wafer-related components 1020 are not limited thereto, but may include other types of wafer-related components. In addition, wafer related components 1020 may be combined with each other.

The network-related components 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, etc.), global interoperable microwave access (worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high-speed packet access + (high speed packet access +, HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + (HSUPA +), enhanced data GSM environment (enhanced data GSM environment, EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code multiple access (code division multiple access (CDMA), Time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G agreement, 4G agreement and 5G agreement and any other wireless agreement specified after the above agreement And cable agreements. However, the network-related component 1030 is not limited to this, but may include various other wireless standards or protocols or wired standards or protocols. In addition, the network-related components 1030 can be combined with the above-mentioned chip-related components 1020 together.

Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), and electromagnetic interference , EMI) filter, multilayer ceramic capacitor (MLCC), etc. However, the other components 1040 are not limited thereto, but may include passive components and the like for various other purposes. In addition, other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 or network-related components 1030.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may be physically connected or electrically connected to the motherboard 1010 or may not be physically connected or electrically connected to the motherboard 1010. These other components may include, for example, camera module 1050, antenna 1060, display device 1070, battery 1080, audio codec, video codec, power amplifier, compass, accelerometer, gyroscope, speaker, mass storage unit ( For example, hard disk drive), compact disk (CD) drive, digital versatile disk (DVD) drive, etc. However, these other components are not limited thereto, but may include other components for various purposes depending on the type of the electronic device 1000 and the like.

The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop Personal computers, portable netbook PCs, TVs, video game machines, smart watches, automotive components, etc. However, the electronic device 1000 is not limited to this, and may be any other electronic device capable of processing data.

2 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 2, the semiconductor package may be used in various electronic devices 1000 as described above for various purposes. For example, the motherboard 1110 may be housed in the main body 1101 of the smartphone 1100, and various electronic components 1120 may be physically connected or electrically connected to the motherboard 1110. In addition, other components (for example, the camera module 1130) that may be physically connected or electrically connected to the main board 1110 or may not be physically connected or electrically connected to the main board 1110 may be accommodated in the main body 1101. Some of the electronic components 1120 may be wafer-related components, and the semiconductor package 100 may be, for example, an application processor in the wafer-related components, but it is not limited thereto. The electronic device need not be limited to the smartphone 1100, but may be other electronic devices as described above. Semiconductor packaging

Generally speaking, many fine circuits are integrated in the semiconductor chip. However, the semiconductor wafer itself cannot be used as a finished semiconductor product and can be damaged due to external physical or chemical influence. Therefore, the semiconductor wafer cannot be used alone, but is packaged in an electronic device or the like and used in a packaged state in the electronic device or the like.

In terms of electrical connection, there is a difference in circuit width between the semiconductor chip and the main board of the electronic device, so semiconductor packaging is required. In detail, the size of the connection pads of the semiconductor chip and the spacing between the connection pads of the semiconductor chip are very fine, but the size of the component mounting pads of the motherboard used in the electronic device and between the component mounting pads of the motherboard The spacing is significantly larger than the size of the connection pads of the semiconductor chip and the separation between the connection pads. Therefore, it may be difficult to directly mount the semiconductor wafer on the main board, and a packaging technology for buffering the difference in circuit width between the semiconductor wafer and the main board is required.

According to the structure and purpose of semiconductor packages, semiconductor packages manufactured using packaging technology can be divided into fan-in semiconductor packages and fan-out semiconductor packages.

Hereinafter, the fan-in type semiconductor package and the fan-out type semiconductor package will be explained in more detail with reference to the drawings. Fan-in semiconductor package

3A and 3B are schematic cross-sectional views illustrating the state of the fan-in semiconductor package before and after being packaged.

4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawing, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in a bare state. The semiconductor wafer 2220 includes a body 2221 including silicon (Si), germanium (Ge), and gallium arsenide ( GaAs) etc .; a connection pad 2222 formed on one surface of the body 2221 and containing a conductive material such as aluminum (Al); and a protective layer 2223 such as an oxide film or a nitride film formed on one surface of the body 2221 and At least part of the connection pad 2222 is covered. Here, since the connection pad 2222 is very small, it is difficult to mount an integrated circuit (IC) on an intermediate level printed circuit board (PCB), a motherboard of an electronic device, or the like.

Therefore, depending on the size of the semiconductor wafer 2220, a connection member 2240 may be formed on the semiconductor wafer 2220 to rewire the connection pad 2222. The connection member 2240 can be formed by the following steps: forming an insulating layer 2241 on the semiconductor wafer 2220 using an insulating material such as photoimagable dielectric (PID) resin; forming a through hole 2243h that opens the connection pad 2222; and Next, wiring patterns 2242 and through holes 2243 are formed. Next, a protective layer 2250 for protecting the connection member 2240, an opening 2251 can be formed, an under bump metal layer 2260, etc. can be formed. That is, the fan-in semiconductor package 2200 including, for example, the semiconductor chip 2220, the connection member 2240, the protective layer 2250, and the under bump metal layer 2260 can be manufactured through a series of processes.

As described above, the fan-in type semiconductor package may have a package in which all the connection pads (eg, input / output (I / O) terminals) of the semiconductor wafer are arranged in the semiconductor wafer The form can have excellent electrical properties and can be produced at low cost. Therefore, many components installed in smart phones have been manufactured in the form of fan-in semiconductor packages. In detail, many components installed in smart phones have been developed to enable fast signal transfer while having a compact size.

However, since all input / output terminals need to be arranged in the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has significant space limitations. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of input / output terminals or a semiconductor wafer having a compact size. In addition, due to the above disadvantages, the fan-in semiconductor package cannot be directly installed and used on the motherboard of the electronic device. The reason is that even though the size of the input / output terminals of the semiconductor chip and the interval between the input / output terminals of the semiconductor chip are increased by the rewiring process, the size of the input / output terminals of the semiconductor chip and the various input / output of the semiconductor chip The spacing between the output terminals is still insufficient to directly mount the fan-in semiconductor package on the motherboard of the electronic device.

5 is a schematic cross-sectional view illustrating a fan-in type semiconductor package mounted on an interposer substrate and finally mounted on a main board of an electronic device.

6 is a schematic cross-sectional view illustrating a fan-in type semiconductor package embedded in an interposer substrate and finally mounted on a main board of an electronic device.

Referring to the drawing, in the fan-in semiconductor package 2200, the connection pads 2222 (ie, input / output terminals) of the semiconductor chip 2220 can be re-routed again via the interposer 2301, and the fan-in semiconductor package 2200 can be included therein The fan-in semiconductor package 2200 is finally mounted on the motherboard 2500 of the electronic device in a state where it is mounted on the interposer substrate 2301. Here, the solder balls 2270 and the like may be fixed by underfilling the resin 2280 and the like, and the outer surface of the semiconductor wafer 2220 may be covered with the molding material 2290 and the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pads 2222 (ie, input / output terminals) of the semiconductor chip 2220 may be embedded in the interposer substrate 2302 in the fan-in semiconductor package 2200 In the state of the re-wiring through the interposer substrate 2302, the fan-in semiconductor package 2200 can be finally installed on the motherboard 2500 of the electronic device.

As described above, it may be difficult to directly install and use a fan-in type semiconductor package on the main board of the electronic device. Therefore, the fan-in semiconductor package can be mounted on a separate interposer substrate and then can be mounted on the main board of the electronic device by a packaging process, or can be in the electronic device in a state where the fan-in semiconductor package is embedded in the interposer substrate Installed and used on the motherboard. Fan-out semiconductor package

7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

Referring to the drawing, in the fan-out semiconductor package 2100, for example, the outer surface of the semiconductor chip 2120 can be protected by the encapsulant 2130, and the connection pad 2122 of the semiconductor chip 2120 can be connected to Rewiring is performed outside the wafer 2120. In this case, a protective layer 2150 may be further formed on the connection member 2140, and an under bump metal layer 2160 may be further formed in the opening of the protective layer 2150. Solder balls 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit (IC) including a main body 2121, a connection pad 2122, a protective layer, and the like. The connection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a via 2143 electrically connecting the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out semiconductor package may have the input / output terminals of the semiconductor wafer reconnected and arranged on the semiconductor wafer by the connection member formed on the semiconductor wafer Other forms. As described above, in the fan-in semiconductor package, all input / output terminals of the semiconductor wafer need to be arranged in the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, it is necessary to reduce the size and pitch of the balls, thereby making it impossible to use a standardized ball layout in the fan-in type semiconductor package. On the other hand, the fan-out type semiconductor package has a form in which the input / output terminals of the semiconductor wafer are rewired outside the semiconductor wafer and arranged outside the semiconductor wafer by the connection member formed on the semiconductor wafer as described above . Therefore, even in the case where the size of the semiconductor wafer is reduced, the standardized ball layout can actually be used in the fan-out semiconductor package, thereby enabling the fan-out semiconductor package to be used without using a separate interposer substrate Installed on the motherboard of the electronic device, as explained below.

8 is a schematic cross-sectional view illustrating a fan-out type semiconductor package mounted on a main board of an electronic device.

Referring to the drawing, the fan-out semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device through solder balls 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 includes the connection member 2140 formed on the semiconductor wafer 2120 and capable of rewiring the connection pad 2122 to a fan-out area outside the size of the semiconductor wafer 2120, thereby making the actual The standardized ball layout can be used in the fan-out semiconductor package 2100. Therefore, the fan-out semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device without using a separate interposer or the like.

As described above, since the fan-out semiconductor package can be mounted on the main board of an electronic device without using a separate interposer substrate, the fan-out semiconductor package can be compared to the fan-in semiconductor package using an interposer substrate The thickness of the small thickness is implemented. Therefore, the fan-out semiconductor package can be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal and electrical characteristics, which makes the fan-out semiconductor package particularly suitable for mobile products. Therefore, the fan-out type semiconductor package can be implemented in a more compact form than a general package-on-package (POP) type using a printed circuit board (PCB), and can solve the problem of warpage (Warpage) phenomenon.

At the same time, the fan-out semiconductor package is a packaging technology for mounting a semiconductor chip on a motherboard of an electronic device or the like as described above and protecting the semiconductor chip from external influences, and is printed with an intermediate substrate or the like The circuit board (PCB) differs in concept. The printed circuit board has different specifications, purposes, etc. from the fan-out semiconductor package, and the fan-in semiconductor package is embedded in the printed circuit board.

Hereinafter, a fan-out semiconductor package in which power supply efficiency is excellent and cost can be reduced will be explained with reference to drawings.

9A and 9B are schematic diagrams illustrating a fan-out type semiconductor package according to an exemplary embodiment of the present invention.

FIG. 10 is a schematic plan view taken along section line II ′ of the fan-out semiconductor package shown in FIG. 9A.

Referring to the drawings, the fan-out semiconductor package 100A according to the present exemplary embodiment may include: a first connection member 110 having a through hole 110H; a semiconductor wafer 120 disposed in the through hole 110H and located on the semiconductor wafer 120 A connection pad 122 is disposed on one surface; an encapsulant 130 covering at least part of the first connection member 110 and the semiconductor wafer 120; a second connection member 140 disposed on the first connection member 110 and the surface of the semiconductor wafer 120 And rewire the connection pad 122 to the fan-out area; the protective layer 150 is disposed on the surface of the second connection member 140 and has an opening 151 that exposes at least part of the redistribution layer 142 of the second connection member 140; The under-bump metal layer 160 is disposed on the opening 151 of the protective layer 150; and the connection terminal 170 is disposed on the under-bump metal layer 160 and is electrically connected to the connection pad 122 via the second connection member 140. In this case, a coil 180a electrically connected to the semiconductor wafer 120 may be formed in the patterned shape on the first connection member 110, such as a power inductor (PI).

Recently, as the demand for high-speed portable electronic devices increases, the necessity of stably supplying power to semiconductor packages has increased. Therefore, a voltage regulator such as a DC-DC converter has been used to stably receive the power supplied by the power source, and various passive components have been connected to the power line from the motherboard of the electronic device to the semiconductor chip. For example, power input from a battery or the like has been distributed in a power management integrated circuit (PMIC) installed on the motherboard and distributed through a chip-type power inductor installed on the motherboard Power is supplied to the semiconductor package to promote power stability. However, in this form, the paths in the semiconductor package, power management integrated circuit, and power inductor are significantly larger, which in turn makes the power supply efficiency low. In addition, the chip-type power inductor that is separately manufactured and installed on the main board of the electronic device or embedded in the second connection member has a limitation in reducing costs. In addition, the chip-type power inductor manufactured separately and installed on the main board of the electronic device or embedded in the second connection member may have limitations in achieving a quality factor (Q factor) due to space constraints.

On the other hand, in the fan-out semiconductor package 100A according to the present exemplary embodiment, the coil 180a (eg, power inductor) may be formed in the pattern shape on the first connection member 110 surrounding the semiconductor wafer 120, and the power inductor The connection path between the device and the semiconductor wafer 120 may therefore be very short. According to this, the power supply efficiency can be significantly improved. In addition, there is no need to manufacture and install the power inductor in the form of a separate wafer, and the cost can therefore be reduced. In addition, the space utilization rate is more excellent than the power inductor installed in the form of a single chip, which in turn makes it possible to achieve a high quality factor.

The respective components included in the fan-out type semiconductor package according to the exemplary embodiment will be explained in more detail below.

The first connection member 110 may support the fan-out semiconductor package 100A. In addition, the first connection member 110 can easily ensure the thickness uniformity of the encapsulation 130. In addition, the first connection member 110 may provide a wiring area to form a redistribution layer, thereby reducing the number of layers of the second connection member 140. According to this, the defects that occur in the process of forming the second connection member 140 are resolved. The first connection member 110 may have a through hole 110H. The semiconductor wafer 120 may be disposed in the through hole 110H to be spaced apart from the first connection member 110 by a predetermined distance. That is, the side surface of the semiconductor wafer 120 may be surrounded by the first connection member 110. However, the form of the first connection member 110 is not limited to this, but may be modified into other forms in various ways.

The first connection member 110 may include: a first insulation layer 111a contacting the second connection member 140; a first heavy wiring layer 112a contacting the second connection member 140 and embedded in the first insulation layer 111a; a second heavy wiring layer 112b , Disposed on the other surface of the first insulating layer 111a opposite to the surface embedded with the first rewiring layer 112a; the second insulating layer 111b, disposed on the first insulating layer 111a and covering the second rewiring layer 112b; and The third redistribution layer 112c is disposed on the second insulating layer 111b. Since the first connection member 110 may include a large number of redistribution layers 112a, redistribution layers 112b, and redistribution layers 112c, the second connection member 140 may be further simplified. Therefore, it is possible to improve the decrease in yield caused by defects occurring in the process of forming the second connection member 140. Since the first redistribution layer 112a is embedded in the first insulation layer 111a, the insulation distance of the insulation layer 141 of the second connection member 140 may be relatively constant. The first redistribution layer 112a may be recessed in the first insulation layer 111a, so that the lower surface of the first insulation layer 111a may have a step with respect to the lower surface of the first redistribution layer 112a. Therefore, the phenomenon that the material of the encapsulation body 130 permeates the first redistribution layer 112a can be prevented. The first redistribution layer 112a, the second redistribution layer 112b, and the third redistribution layer 112c may be electrically connected to each other through the via layer 113a and the via layer 113b penetrating through the first insulating layer 111a and the second insulating layer 111b .

The materials of the first insulating layer 111a and the second insulating layer 111b are not particularly limited, as long as the first insulating layer 111a and the second insulating layer 111b can support the fan-out semiconductor package. For example, an insulating material can be used as the material of the first insulating layer 111a and the second insulating layer 111b. In this case, the following materials can be used as the insulating material: thermosetting resin, such as epoxy resin; thermoplastic resin, such as polyimide resin; glass cloth or inorganic filler, for example, immersed in thermosetting resin and thermoplastic resin Resins such as prepreg, Ajinomoto Build up Film (ABF), FR-4, bismaleimide triazine (BT), etc. Alternatively, a photosensitive imaging dielectric (PID) resin may be used as the insulating material.

The rewiring layer 112a, the rewiring layer 112b, and the rewiring layer 112c can be used to rewire the connection pads 122 of the semiconductor wafer 120, and for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn) can be used ), Gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof as conductive materials for each of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c. The redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may perform various functions according to the design of their corresponding layers. For example, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and so on. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power supply (PWR) pattern, etc., such as a data signal. In addition, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may include via pads, connection terminal pads, and the like. If necessary, a surface treatment layer may be further formed on the portion of the redistribution layer 112c exposed from the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c through the opening 131 formed in the encapsulation 130. The surface treatment layer is not particularly limited as long as the surface treatment layer is known in the related art, and the surface treatment layer can use, for example, electrolytic gold plating, electroless gold plating, organic solderability protection (organic Solderability preservative (OSP), electroless tin, electroless silver, electroless nickel / displacement gold plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL), etc.

The via layer 113 a and the via layer 113 b may electrically connect the redistribution layer 112 a and the redistribution layer 112 b formed on different layers, thereby generating an electrical path in the first connection member 110. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys can be used as The material of each of the hole layer 113a and the via layer 113b. Each of the via layer 113a and the via layer 113b may be completely filled with a conductive material, or the conductive material may also be formed along the wall of each via. In addition, each of the through-hole layer 113a and the through-hole layer 113b may have all shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like.

The first connection member 110 may include: a first coil pattern layer 112a-i contacting the second connection member 140 and embedded in the first insulating layer 111a; a second coil pattern layer 112b-i disposed on the first insulating layer 111a On the other surface, it is opposite to the surface where the first coil pattern layers 112a-i are embedded; and the third coil pattern layer 112c-i is disposed on the second insulating layer 111b. The first coil pattern layer 112a-i, the second coil pattern layer 112b-i, and the third coil pattern layer 112c-i may include coil patterns, respectively, and the coil patterns may pass through the first insulating layer 111a and the second insulation The through holes 183a-i and the through holes 183b-i of the layer 111b are electrically connected to each other to form a center axis corresponding to the first coil pattern layer 112a-i, the second coil pattern layer 112b-i, and the third coil pattern layer 112c -The coil 180a in the stacking direction of i. The first coil pattern layer 112a-i, the second coil pattern layer 112b-i, and the third coil pattern layer 112c-i can be formed by known circuit processes such as electrolytic copper plating, electroless copper plating, and the like. More specifically, the first coil pattern layers 112a-i, the second coil pattern layers 112b-i, and the third coil pattern layers 112c-i can be formed by, for example, the following methods: chemical vapor deposition (CVD), Physical vapor deposition (PVD), sputtering, subtractive process (subtractive process), additive process (additive process), semi-additive process (semi-additive process (SAP), modified semi-additive process (Modified semi-additive process, MSAP), etc., but not limited to this. The coil 180a may be a power inductor electrically connected to the semiconductor chip 120, but it is not limited thereto. The figure illustrates one coil 180a, but the number of coils 180a is not limited to this. That is, a plurality of coils 180a may be arranged at various positions of the first connection member 110. When viewed in a plan view, a pattern constituting the coil 180a may be implemented in various shapes such as a rectangle, square, circle, ellipse, or the like. On the other hand, referring to FIG. 10, when four regions of the semiconductor wafer 120 surrounding the first connection member 110 are referred to as first to fourth regions, the coil 180a may be formed in, for example, the first to fourth regions In a single area, but not limited to this.

The semiconductor wafer 120 may be an integrated circuit (IC) configured to integrate a number of hundreds to millions of elements or more into a single wafer. The integrated circuit may be a known semiconductor chip such as an application processor (AP), for example, a central processor (eg, central processing unit), a graphics processor (eg, graphics processing unit), or a digital signal Processors, cryptographic processors, microprocessors, microcontrollers, etc. Alternatively, the integrated circuit may be a power management integrated circuit. The application processor as the semiconductor chip 120 and the power management integrated circuit may be disposed in the through hole 110H of the first connection member 110 together. Alternatively, the application processor and the power management integrated circuit may be integrated into one chip and disposed in the through hole 110H of the first connection member 110. One end and the other end of the coil 180a (such as a power inductor (PI)) can be electrically connected to the application processor and the power management integrated circuit, respectively. In detail, one end and the other end of the coil 180a (such as a power inductor (PI)) can be electrically connected to the voltage input terminal V _{in of the} application processor and the voltage output terminal V _{out of the} power management integrated circuit, respectively.

The semiconductor wafer 120 may include a body 121, a connection pad 122 formed on the surface of the body 121, and a protective layer 123 formed on the body 121 and covering a portion of the connection pad 122. The body 121 may be formed based on, for example, an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like can be used as the basic material of the main body 121. The connection pad 122 may electrically connect the semiconductor wafer 120 to other components, and a conductive material such as aluminum (Al) may be used as the material of each of the connection pads 122. The connection pad 122 may be rewired by the second connection member 140, the first connection member 110, and the like. The surface of the semiconductor wafer 120 on which the connection pad 122 is formed may be an active surface, and the surface of the semiconductor wafer 120 opposite to the active surface may be a passive surface. The protective layer 123 may be used to protect the body 121 from external influences, and may be formed of, for example, an oxide film formed of silicon oxide (SiO) or the like, a nitride film formed of silicon nitride (SiN), or the like, or may include an oxide The double layer of the film and the nitride film is formed. In addition, an insulating layer formed of silicon oxide (SiO) or the like may be further disposed between the main body 121 and the connection pad 112 or between the main body 121 and the protective layer 123.

The lower surface of the first redistribution layer 112 a of the first connection member 110 may be disposed at a level higher than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the second connection member 140 and the first redistribution layer 112a of the first connection member 110 may be greater than that between the redistribution layer 142 of the second connection member 140 and the connection pad 122 of the semiconductor wafer 120 The distance between. The reason is that the first redistribution layer 112a may be recessed in the first insulating layer 111a. That is, the lower surface of the first insulating layer 111a may have a step with respect to the lower surface of the first redistribution layer 112a. Similarly, the lower surface of the first coil pattern layers 112a-i of the first connection member 110 may be disposed at a higher level than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the second connection member 140 and the first coil pattern layers 112 a-i of the first connection member 110 may be greater than the connection pad of the redistribution layer 142 of the second connection member 140 and the semiconductor wafer 120 The distance between 122. That is, the lower surface of the first insulating layer 111a may have a step with respect to the lower surface of the first coil pattern layers 182a-i. The second redistribution layer 112b of the first connection member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120. The first connection member 110 may be formed with a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the second redistribution layer 112b formed in the first connection member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120. Similarly, the second coil pattern layers 112b-i of the first connection member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120.

The encapsulation body 130 may be configured to protect the first connection member 110 or the semiconductor wafer 120. The coating form of the encapsulation body 130 is not particularly limited, and may be a form in which the encapsulation body 130 surrounds at least part of the first connection member 110 or at least part of the semiconductor wafer 120. For example, the encapsulant 130 may fill the first connection member 110, the other surface of the semiconductor wafer 120, and the space between the first connection member 110 and the semiconductor wafer 120 in the through hole 110H. In addition, the encapsulant 130 may also fill at least part of the space between the protective layer 123 of the semiconductor wafer 120 and the second connection member 140. At the same time, the encapsulant 130 may fill the through hole 110H to thereby act as an adhesive and reduce the bending of the semiconductor wafer 120 according to the material. An opening may be formed in the encapsulation body 130 to expose at least part of the second redistribution layer 112b formed on the other surface of the first connection member 110. The exposed portions of the second redistribution layer 112b may be used as a marking pattern. Alternatively, a separate connection terminal or the like may be connected to the exposed portion of the second redistribution layer 112b to thereby be applied to the stacked package structure, and the surface mount technology (SMT) component may be configured in the second On the exposed portion of the redistribution layer 112b.

The material of the encapsulating body 130 is not particularly limited, and may be an insulating material, for example. More specifically, as the material of the encapsulation body 130, for example, an Ajinomoto film containing inorganic fillers and insulating resins but not glass cloth may be used. In this case, the void problem or delamination problem can be solved. Meanwhile, the inorganic filler may be a known inorganic filler, and the insulating resin may be a known epoxy resin or the like. However, inorganic fillers and insulating resins are not limited to this.

The second connection member 140 may be configured to rewire the connection pad 122 of the semiconductor wafer 120 to the fan-in area or the fan-out area. Tens to hundreds of connection pads 122 having various functions can be re-wired by the second connection member 140, and can be physically connected or electrically connected through the connection terminals 170 to be described below according to the functions To external source. The second connection member 140 may include: an insulating layer 141; a redistribution layer 142 disposed on the insulating layer 141; and a via layer 143 penetrating through the insulating layer 141 and connecting the redistribution layers 142 to each other.

An insulating material may be used as the material of each of the insulating layers 141. In this case, a photosensitive insulating material such as a photosensitive imaging dielectric resin may also be used as the insulating material. In this case, the insulating layer 141 can be formed to have a smaller thickness, and the fine pitch of the through holes of the through hole layer 143 can be more easily achieved. If necessary, the materials of the insulating layers 141 may be the same as each other or may be different from each other. The insulating layers 141 may be integrated with each other according to the manufacturing process, so that the boundary between the insulating layers 141 may not be obvious.

The redistribution layer 142 may be substantially used to reroute the connection pad 122, and may use, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni) Conductive materials such as lead (Pb), titanium (Ti), or their alloys are used as the material of each of the redistribution layers 142. The redistribution layer 142 may perform various functions according to the design of its corresponding layer. For example, the redistribution layer 142 may include a ground (GND) pattern, a power supply (PWR) pattern, a signal (S) pattern, and so on. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power supply (PWR) pattern, etc., such as a data signal. In addition, the redistribution layer 142 may include via pads, connection terminal pads, and the like. If necessary, a surface treatment layer may be further formed on the exposed portion of the redistribution layer 142.

The via layer 143 may electrically connect the redistribution layer 142, the connection pad 122, and the like formed on different layers, thereby generating an electrical path in the fan-out semiconductor package 100A. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys can be used as The material of each of the hole layers 143. The via layer 143 may also be completely filled with conductive material, or the conductive material may be formed along the wall of each via. In addition, the via layer 143 may have all shapes known in the related art, for example, tapered, cylindrical, and the like.

The figure illustrates the case where the second connection member 140 has one of the insulating layers 141 and has one of the redistribution layer 142 and one of the via layers 143 according to the one insulating layer 141, but the second connection The member 140 is not limited to this. That is, the second connection member 140 may include a larger number of insulating layers according to its design, and thus include a larger number of redistribution layers and via layers. That is, the second connection member 140 may also be formed of multiple layers.

The thickness of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c of the first connection member 110 may be greater than the thickness of the redistribution layer 142 of the second connection member 140. Since the first connection member 110 may have a thickness equal to or greater than the thickness of the semiconductor wafer 120, according to the specifications of the first connection member 110, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c Can be formed to be relatively large. On the other hand, the redistribution layer 142 of the second connection member 140 may be formed to be relatively small to achieve thinning. Similarly, the thickness of the first coil pattern layer 112a-i, the second coil pattern layer 112b-i, and the third coil pattern layer 112c-i of the first connection member 110 may be greater than that of the redistribution layer 142 of the second connection member 140 thickness.

If necessary, a protective layer 150 may be introduced, and the protective layer 150 may be configured to protect the second connection member 140 from external physical damage or chemical damage. The protective layer 150 may have an opening 151, and the opening 151 exposes at least a portion of the redistribution layer 142 of the second connection member 140 (ie, at least some of the connection terminal pads). The number of openings 151 formed in the protective layer 150 may be tens to thousands.

The material of the protective layer 150 is not particularly limited, but may be a photosensitive insulating material such as a photosensitive imaging dielectric resin. Alternatively, solder resist may be used as the material of the protective layer 150. Alternatively, as the material of the protective layer 150, an insulating material including filler and resin but not glass cloth, such as an Ajinomoto constituent film, may be used. The surface roughness of the protective layer 150 may be lower than normal. When the surface roughness is low as described above, several side effects (such as stains on the surface, difficulty in implementing fine circuits, etc.) that may occur in the circuit formation process can be improved.

If necessary, the under bump metal layer 160 may be introduced, and the connection reliability of the connection terminal 170 to be described below may be improved, thereby further improving the reliability of the fan-out semiconductor package. The under bump metal layer 160 may be formed on the insulating layer 141 or the opening 151 of the protective layer 150 to connect to the exposed portion of the redistribution layer 142. The under-bump metal layer 160 may include a seed layer and a conductor layer formed on the seed layer. The seed layer and the conductor layer may include known conductive materials, preferably, electroless copper and electrolytic copper, respectively. The seed layer may have a thickness smaller than that of the conductor layer.

The connection terminal 170 may be configured to physically or electrically connect the fan-out semiconductor package 100A externally. For example, the fan-out semiconductor package 100A according to the exemplary embodiment may be directly mounted on the motherboard of the electronic device via the connection terminal 170. Each of the connection terminals 170 may be formed of a conductive material such as solder. However, this is only an example, and the material of each of the connection terminals 170 is not limited to this.

Each of the connection terminals 170 may be a land, a ball, a pin, or the like. The connection terminal 170 may be formed of multiple layers or a single layer. When the connection terminal 170 is formed of multiple layers, the connection terminal 170 may include copper pillars and solder. When the connection terminal 17 is formed of a single layer, the connection terminal 170 may include tin-silver solder or copper. However, this is only an example, and the connection terminal 170 is not limited to this. The number, interval, arrangement form, etc. of the connection terminals 170 are not particularly limited, and can be sufficiently modified by those skilled in the art according to design details. For example, according to the number of the connection pads 122 of the semiconductor chip 120, the connection terminals 170 may be set to a number of tens to thousands, but not limited to this, and may be set to tens to thousands or more The number or the number of tens to thousands or less.

At least one of the connection terminals 170 may be disposed in the fan-out area. The fan-out area is an area other than the area where the semiconductor wafer 120 is arranged. That is, the fan-out type semiconductor package 100A according to the exemplary embodiment may be a fan-out type package. Compared with the fan-in package, the fan-out package can have excellent reliability, the fan-out package can implement multiple input / output (I / O) terminals, and can facilitate three-dimensional 3D interconnection. In addition, compared to a ball grid array (BGA) package, a land grid array (LGA) package, etc., the fan-out package can be installed in an electronic device without a separate circuit board on. Therefore, the fan-out package can be manufactured to have a small thickness and can be competitively priced.

Although not shown in the figure, if necessary, a separate metal layer may be further disposed on the inner side wall of the through hole 110H of the first connection member 110 to dissipate heat and block electromagnetic waves. In addition, if necessary, a plurality of semiconductor wafers may be arranged in the through holes 110H of the first connection member 110, and the number of the through holes 110H of the first connection member 110 may be plural, and the semiconductor wafers may be respectively arranged in the Through the hole. In addition, a separate passive component such as a capacitor may be encapsulated in the through hole 110H together with the semiconductor wafer. In addition, a surface mount technology (SMT) component can be mounted on the protective layer 150.

11A and 11B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention.

Referring to the drawings, in the fan-out semiconductor package 100B according to the present exemplary embodiment, all the first coil pattern layers 112a-i, the second coil pattern layers 112b-i, and the third coil pattern layers 112c-i Each may include a coil pattern, and the coil patterns may each form a coil whose center axis corresponds to the stacking direction of the first coil pattern layer 112a-i, the second coil pattern layer 112b-i, and the third coil pattern layer 112c-i, respectively 180b. That is, the first connection member 110 may include a plurality of coils 180b each stacked in the vertical direction and having a planar coil shape. In some cases, the plurality of coils 180b may be connected to each other in parallel in respective layers to reduce the DC resistance (Rdc) of the inductor. Meanwhile, the number of coil pattern layers does not necessarily depend on the number of redistribution layers. That is, in some cases, the number of redistribution layers may be greater than the number of coil pattern layers. That is, even in the case where the number of rewiring layers is three or more, the number of coil pattern layers each forming a coil may be only one or only two. The configuration that duplicates the configuration described earlier will not be repeated.

12A and 12B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention.

Referring to the drawings, in the fan-out semiconductor package 100C according to the present exemplary embodiment, the first connection member 110 may include a first redistribution layer 112a, a second redistribution layer 112b, and a third redistribution layer 112c. However, the first connection member 110 may include only the first coil pattern layers 112a-i and the second coil pattern layers 112b-i. The coil patterns included in the first coil pattern layers 112a-i and the second coil pattern layers 112b-i may be electrically connected to each other via the through holes 183a-i to form a center axis corresponding to the first coil pattern layers 112a-i And the coil 180c in the stacking direction of the second coil pattern layers 112b-i. That is, the number of redistribution layers and the number of coil pattern layers are not necessarily the same as each other. The configuration that duplicates the configuration described earlier will not be repeated.

13A and 13B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention.

Referring to the drawings, in the fan-out semiconductor package 100D according to the present exemplary embodiment, the first connection member 110 may include a first redistribution layer 112a, a second redistribution layer 112b, and a third redistribution layer 112c. However, the first connection member 110 may include only the second coil pattern layer 112b-i and the third coil pattern layer 112c-i. The coil patterns included in the second coil pattern layer 112b-i and the third coil pattern layer 112c-i may be electrically connected to each other via the through hole 183b-i to form a center axis corresponding to the second coil pattern layer 112b-i And the coil 180d in the stacking direction of the third coil pattern layers 112c-i. That is, the number of redistribution layers and the number of coil pattern layers are not necessarily the same as each other. The configuration that duplicates the configuration described earlier will not be repeated.

14A and 14B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention.

Referring to the drawings, in the fan-out semiconductor package 100E according to the present exemplary embodiment, each of the first coil pattern layers 112a-i and the second coil pattern layers 112b-i may include a plurality of coil patterns And the plurality of coil patterns can be electrically connected to each other via a plurality of through holes 183a-i to form a center axis corresponding to the direction perpendicular to the stacking direction of the first coil pattern layers 112a-i and the second coil pattern layers 112b-i The direction of the coil 180e. The plurality of coil patterns formed in each of the first coil pattern layers 112a-i and the second coil pattern layers 112b-i may be disconnected from each other on the same layer. The coil 180e may have a spiral path that rotates based on the central axis while alternately passing through each of the coil pattern layers 182a-i and the coil pattern layers 182b-i through the plurality of through holes 183a-i Coil pattern. The configuration that duplicates the configuration described earlier will not be repeated.

15A and 15B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention.

Referring to the drawing, in the fan-out semiconductor package 100F according to the present exemplary embodiment, each of the second coil pattern layer 112b-i and the third coil pattern layer 112c-i may include a plurality of coil patterns , And the plurality of coil patterns can be electrically connected to each other through a plurality of through holes 183b-i to form a center axis corresponding to the direction perpendicular to the stacking direction of the second coil pattern layer 112b-i and the third coil pattern layer 112c-i The direction of the coil 180f. The plurality of coil patterns formed in each of the second coil pattern layer 112b-i and the third coil pattern layer 112c-i may be disconnected from each other on the same layer. The coil 180f may have a spiral path that rotates based on the central axis while passing through each of the coil pattern layer 182b-i and the coil pattern layer 182c-i alternately through the plurality of through holes 183b-i Coil patterned. The configuration that duplicates the configuration described earlier will not be repeated.

16A and 16B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention.

17A to 17C are schematic cross-sectional views illustrating various modifications of the coil formed in the fan-out type semiconductor package shown in FIG. 16A.

Referring to the drawing, in the fan-out semiconductor package 100G according to the present exemplary embodiment, the first connection member 110 and the second connection member 140 may include a coil pattern layer electrically connected to the connection pad 122 of the semiconductor chip 120 182a1-i, 182a2-i, 182b1-i and 182b2-i. The coil pattern layers 182a1-i, 182a2-i, 182b1-i, and 182b2-i included in each of the first connection member 110 and the second connection member 140 are electrically connected to each other to form a coil 180g. In more detail, the first connection member 110 may include a plurality of first coil pattern layers 182a1-i, 182b1-i, and 182b2-i, and the second connection member 140 may include at least one second coil pattern layer 182a2-i. A plurality of coil patterns included in each of the plurality of first coil pattern layers 182a1-i, 182b1-i, and 182b2-i and each of the at least one second coil pattern layer 182a2-i The plurality of coil patterns included in one is electrically connected to each other through a plurality of through holes 183a1-i, 183a2-i, 183b1-i, and 183b2-i formed in the first connection member 110 and the second connection member 140, to A coil 180g having a central axis corresponding to a direction perpendicular to the stacking direction of the plurality of first coil pattern layers 182a1-i, 182b1-i, and 182b2-i and the at least one second coil pattern layer 182a2-i is formed. In this case, it is possible to have a large number of turns in a limited space, thereby effectively improving the inductance characteristics.

Meanwhile, as illustrated in FIG. 17A, the coil 180g may include a plurality of first coil pattern layers 182a1-i, 182a2-i, and 182b1-i, and a plurality of outer layers 182a1-i and 182a2 of at least one second coil pattern layer 182b2-i. -i, the plurality of first coil pattern layers 182a1-i, 182a2-i, and 182b1-i and the plurality of inner layers 182b1-i and 182b2-i of the at least one second coil pattern layer 182b2-i, so The plurality of outer layers 182a1-i and 182a2-i are composed of layers arranged on the outermost layer and the lowest layer based on the stacking direction, and the plurality of inner layers 182b1-i and 182b2-i are composed of the plurality of outer layers Consists of layers between 182a1-i and 182a2-i. The coil 180g may have a spiral path that rotates based on the central axis while passing through the plurality of outer layers 182a1-i and alternately through the plurality of through holes 183a1-i, 183a2-i, 183b1-i, and 183b2-i. 182a2-i and the plurality of inner layers 182b1-i and 182b2-i. More specifically, the spiral path of the coil 180g can be moved from the first outer layer 182a1-i to the second outer layer 182a2-i through the first outer layer through hole 183a1-i, and then to the second outer layer through hole 183a2-i to The first inner layer 182b1-i can then move to the second inner layer 182b2-i through the first inner layer via 183b1-i, and can move to the first outer layer 182a1- again through the second inner layer via 183b2-i i. Therefore, the spiral path is rotated by repeating the above path. In this case, it is possible to have a large number of turns in a limited space, thereby effectively improving the inductance characteristics.

In addition, as illustrated in FIG. 17B, a larger number of second coil pattern layers 182a2-i, 182b2-i, and 182c2-i may be formed in the second connection member 140. In this case, among the multiple inner layers 182b1-i, 182b2-i, 182c1-i, and 182c2-i of the coil 180g ¢, except the third inner layer 182c1-i and the fourth inner layer 182c2-i The first inner layer 182b1-i and the second inner layer 182b2-i are connected to each other through a plurality of through holes 183b1-i, 183b2-i, 183c1-i, and 183c2-i similar to the above to form a spiral path, the spiral The path rotates based on the central axis while passing through the plurality of through holes 183b1-i, 183b2-i, 183c1-i, and 183c2-i alternately through the third inner layer 182c1-i and the fourth inner layer 182c2-i The outer first inner layer 182b1-i and the second inner layer 182b2-i. More specifically, the spiral path of the coil 180g ¢ can be moved from the first outer layer 182a1-i through the first outer layer through hole 183a1-i to the second outer layer 182a2-i, and then can be moved through the second outer layer through hole 183a2-i To the first inner layer 182b1-i, then move to the second inner layer 182b2-i via the first inner layer via 183b1-i, and then move to the third inner layer 182c1 via the second inner layer via 183b2-i -i, then it can move to the fourth inner layer 182c2-i through the third inner layer via 183c1-i, and can move to the first outer layer 182a1-i again through the fourth inner layer via 183c2-i. Therefore, the spiral path is rotated by repeating the above path. In this case, it is possible to have a larger number of turns in a limited space, thereby effectively improving the inductance characteristics.

In addition, as illustrated in FIG. 17C, in the coil 180g ¢ illustrated in FIG. 17B, a coil pattern may not be formed between the plurality of inner layers 182b1-i and 182b2-i, and a layer where the coil pattern is not formed may be formed as necessary. The magnetic layer 188 can be formed. The magnetic layer 188 may include magnetic materials known in the art. When a film layer in which a coil pattern is not formed between the plurality of inner layers 182b1-i and 182b2-i is introduced, the inductance characteristics can be improved by ensuring the air core of the inductor. In addition, when the magnetic layer 188 is formed in the film layer where the coil pattern is not formed, the inductance characteristic of the coil 180g ¢¢ can be further improved due to the magnetic properties of the magnetic layer 188. Meanwhile, the spiral path of the coil 180g ¢¢ can be moved from the first outer layer 182a1-i to the second outer layer 182a2-i through the first outer layer through hole 183a1-i, and then to the second outer layer through the second outer layer through hole 183a2-i An inner layer 182b1-i, which can then be moved to the second inner layer 182b2-i through the first inner layer via 183b1-i, and can be moved to the first outer layer 182a1-i again through the second inner layer via 183b2-i . Therefore, the spiral path is rotated by repeating the above path.

18A and 18B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention.

Referring to the drawings, in the fan-out semiconductor package 100H according to the present exemplary embodiment, the first connection member 110 may include: a first insulating layer 111a; a first redistribution layer 112a and a second redistribution layer 112b, They are respectively arranged on the two surfaces of the first insulating layer 111a; the second insulating layer 111b is arranged on the first insulating layer 111a and covers the first redistribution layer 112a; the third redistribution layer 112c is arranged on the second insulating layer On 111b; the third insulating layer 111c is disposed on the first insulating layer 111a and covers the second rewiring layer 112b; and the fourth rewiring layer 112d is disposed on the third insulating layer 111c. The first rewiring layer 112a, the second rewiring layer 112b, the third rewiring layer 112c, and the fourth rewiring layer 112d can pass through the first insulating layer 111a, the second insulating layer 111b, and the third insulating layer 111c. A via layer 113a, a second via layer 113b, and a third via layer 113c are electrically connected to each other.

In addition, the first connection member 110 may include a first redistribution layer 112a and a second redistribution layer 112b respectively disposed on both surfaces of the first insulating layer 111a, and a third redistribution layer disposed on the second insulating layer 111b The layer 112c and the fourth redistribution layer 112d disposed on the third insulating layer 111c. The first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may pass through the first via layer 113a, the second via layer 113b, and the third via layer 113c Electrically connected to form a coil 180h whose central axis corresponds to the stacking direction of the first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d. In some cases, the first connection member 110 may include a smaller number of coil pattern layers, and the coil pattern layers may each form a corresponding coil. In addition, some coil pattern layers may include a plurality of coil patterns, and the plurality of coil patterns may be electrically connected to each other via a plurality of through holes to form a coil whose center axis is perpendicular to the stacking direction of the plurality of coil pattern layers . That is, the various forms of the coil described above can also be applied to the fan-out semiconductor package 100G.

The first insulating layer 111a may have a thickness greater than that of the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be substantially thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of redistribution layers 112c and redistribution layers 112d. The first insulating layer 111a may include an insulating material different from that of the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including glass cloth, inorganic filler and insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be Ajinomoto including inorganic filler and insulating resin Constitute a film or photosensitive insulating film. However, the materials of the first insulating layer 111a and the materials of the second insulating layer 111b and the third insulating layer 111c are not limited thereto.

The lower surface of the third redistribution layer 112c of the first connection member 110 may be arranged at a lower level than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the second connection member 140 and the third redistribution layer 112c of the first connection member 110 may be smaller than the distance between the redistribution layer 142 of the second connection member 140 and the connection pad 122 of the semiconductor wafer 120 The distance between. The reason is that the third redistribution layer 112c may be disposed on the second insulating layer 111b in a protruding manner so as to contact the second connection member 140. Similarly, the lower surface of the third coil pattern layer 112c-i of the first connection member 110 may be disposed at a lower level than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the second connection member 140 and the third coil pattern layer 112c-i of the first connection member 110 may be smaller than the connection pad of the redistribution layer 142 of the second connection member 140 and the semiconductor wafer 120 The distance between 122.

The first redistribution layer 112 a and the second redistribution layer 112 b of the first connection member 110 may be arranged at the level between the active surface and the passive surface of the semiconductor wafer 120. The first connection member 110 may be formed with a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the first redistribution layer 112 a and the second redistribution layer 112 b formed in the first connection member 110 can be arranged at the level between the active surface and the passive surface of the semiconductor wafer 120. Similarly, the first redistribution layer 112a and the second redistribution layer 112b of the first connection member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120.

The thickness of the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d of the first connection member 110 may be greater than the thickness of the redistribution layer 142 of the second connection member 140. Since the first connection member 110 may have a thickness equal to or greater than the thickness of the semiconductor wafer 120, the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d may also be formed Is relatively large. On the other hand, the redistribution layer 142 of the second connection member 140 may be formed to be relatively small to achieve thinning. Similarly, the thickness of the first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d of the first connection member 110 may be greater than the redistribution layer 142 of the second connection member 140 thickness of. The configuration that duplicates the configuration described earlier will not be repeated.

19A and 19B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention.

Referring to the drawings, in the fan-out semiconductor package 100I according to the present exemplary embodiment, the first connection member 110 may include a plurality of coil pattern layers 182a1-i electrically connected to the connection pads 122 of the semiconductor wafer 120, 182a2-i, 182b1-i and 182b2-i. The plurality of coil patterns included in each of the plurality of coil pattern layers 182a1-i, 182a2-i, 182b1-i, and 182b2-i pass through the plurality of through holes 183a1 formed in the first connection member 110 -i, 183a2-i, 183b1-i, and 183b2-i are electrically connected to each other to form a stack whose center axis corresponds to the plurality of coil pattern layers 182a1-i, 182a2-i, 182b1-i, and 182b2-i The direction is perpendicular to the coil 180i. The coil 180i may include a plurality of outer layers 182a1-i and 182a2-i of the plurality of coil pattern layers 182a1-i, 182a2-i, 182b1-i, and 182b2-i and the plurality of coil pattern layers 182a1-i, 182a2- A plurality of inner layers 182b1-i and 182b2-i of i, 182b1-i and 182b2-i, the plurality of outer layers 182a1-i and 182a2-i are layers arranged on the outermost layer and the lowest layer based on the stacking direction As a result, the plurality of inner layers 182b1-i and 182b2-i are composed of layers disposed between the plurality of outer layers 182a1-i and 182a2-i. The coil 180i may have a spiral path that rotates based on the central axis while alternately passing through the plurality of outer layers 182a1- via the plurality of through holes 183a1-i, 183a2-i, 183b1-i, and 183b2-i i and 182a2-i and the plurality of inner layers 182b1-i and 182b2-i. The configuration that duplicates the configuration previously explained will not be repeated.

20A and 20B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention.

Referring to the drawings, in the fan-out semiconductor package 100J according to the present exemplary embodiment, the first connection member 110 and the second connection member 140 may include a coil pattern layer electrically connected to the connection pad 122 of the semiconductor wafer 120 182a1-i, 182a2-i, 182b1-i and 182b2-i. The coil pattern layers 182a1-i, 182a2-i, 182b1-i, and 182b2-i included in each of the first connection member 110 and the second connection member 140 are electrically connected to each other to form a coil 180j. In more detail, the first connection member 110 may include a plurality of first coil pattern layers 182a1-i, 182b1-i, and 182b2-i, and the second connection member 140 may include at least one second coil pattern layer 182a2-i. A plurality of coil patterns included in each of the plurality of first coil pattern layers 182a1-i, 182b1-i, and 182b2-i and each of the at least one second coil pattern layer 182a2-i The plurality of coil patterns included in one is electrically connected to each other through a plurality of through holes 183a1-i, 183a2-i, 183b1-i, and 183b2-i formed in the first connection member 110 and the second connection member 140, to A coil 180j having a central axis corresponding to a direction perpendicular to the stacking direction of the plurality of first coil pattern layers 182a1-i, 182b1-i, and 182b2-i and the at least one second coil pattern layer 182a2-i is formed. That is, the plurality of coil pattern layers 182a1-i, 182b1-i, and 182b2-i may be formed only in a part of the film layers of the first connection member 110, and the remaining coil pattern layers 182a2-i may be formed in the second connection member 140. Meanwhile, although not shown in the figure, as described above, a larger number of second coil pattern layers may be formed on the second connection member 140. Alternatively, the coil pattern may not be formed between the plurality of inner layers. In this case, a magnetic layer may be formed as needed in the layer in which the coil pattern is not formed. The configuration that duplicates the configuration previously explained will not be repeated.

As mentioned above, according to the exemplary embodiments of the present invention, there is provided a fan-out type semiconductor package which is excellent in power supply efficiency and whose cost can be reduced.

Although the exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and modifications can be made without departing from the scope of the invention defined by the scope of the accompanying patent application transform.

100‧‧‧Semiconductor packaging

100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 2100 ‧‧‧Fan-out semiconductor packages

110‧‧‧First connecting member

110H‧‧‧Through hole

111a‧‧‧First insulation layer

111b‧‧‧Second insulation layer

111c‧‧‧The third insulating layer

112a‧‧‧rewiring layer / first rewiring layer

112b‧‧‧Rewiring layer / second rewiring layer

112c‧‧‧Rewiring layer / third rewiring layer

112d‧‧‧Rewiring layer / Fourth rewiring layer

113a‧‧‧via layer / first via layer

113b‧‧‧via layer / second via layer

113c‧‧‧third via layer

120, 2120, 2220 ‧‧‧ semiconductor chip

121, 1101, 2121, 2221

122, 2122, 2222 ‧‧‧ connection pad

123, 150, 2150, 2223, 2250‧‧‧protection layer

130, 2130‧‧‧ Envelope

140‧‧‧Second connecting member

141, 2141, 2241‧‧‧Insulation

142, 2142‧‧‧ Redistribution layer

143‧‧‧via layer

151, 2251‧‧‧ opening

160, 2160, 2260 ‧‧‧ under bump metal layer

170‧‧‧Connecting terminal

180a, 180b, 180c, 180d, 180e, 180f, 180g, 180g ', 180g' ', 180h, 180i, 180j‧‧‧coil

182a-i‧‧‧ First coil pattern layer / coil pattern layer

182a1-i‧‧‧coil pattern layer / first coil pattern layer / outer layer / first outer layer

182a2-i‧‧‧coil pattern layer / first coil pattern layer / second coil pattern layer / outer layer / second outer layer

182b-i‧‧‧coil pattern layer / inner layer

182b1-i‧‧‧coil pattern layer / first coil pattern layer / inner layer / first inner layer

182b2-i‧‧‧coil pattern layer / first coil pattern layer / second coil pattern layer / inner layer / second inner layer

182c-i‧‧‧coil pattern layer

182c1-i‧‧‧Inner layer / third inner layer

182c2-i‧‧‧second coil pattern layer / inner layer / fourth inner layer

183a-i, 183b-i, 2143, 2243

183a1-i‧‧‧through hole / first outer layer through hole

183a2-i‧‧‧through hole / second outer through hole

183b1-i‧‧‧through hole / first inner layer through hole

183b2-i‧‧‧through hole / second inner through hole

183c1-i‧‧‧through hole / third inner through hole

183c2-i‧‧‧through hole / fourth inner layer through hole

188‧‧‧Magnetic layer

1000‧‧‧Electronic device

1010, 1110, 2500‧‧‧ Motherboard

1020‧‧‧chip related components

1030‧‧‧Network-related components

1040‧‧‧Other components

1050、1130‧‧‧Camera module

1060‧‧‧ Antenna

1070‧‧‧Display device

1080‧‧‧Battery

1090‧‧‧Signal line

1100‧‧‧Smartphone

1120‧‧‧Electronic components

2140, 2240‧‧‧connecting member

2170, 2270‧‧‧ solder balls

2200‧‧‧Fan-in semiconductor package

2242‧‧‧Wiring pattern

2243h‧‧‧Through hole

2280‧‧‧Bottom filling resin

2290‧‧‧Molding material

2301, 2302‧‧‧Intermediate substrate

I-I'‧‧‧cut line

The above and other aspects, features, and advantages of the present invention will be more clearly understood by reading the following detailed description in conjunction with the drawings. In the drawings: FIG. 1 is a schematic block diagram illustrating an example of an electronic device system. 2 is a schematic perspective view illustrating an example of an electronic device. 3A and 3B are schematic cross-sectional views illustrating the state of the fan-in semiconductor package before and after being packaged. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package. 5 is a schematic cross-sectional view illustrating a fan-in type semiconductor package mounted on an interposer substrate and finally mounted on a main board of an electronic device. 6 is a schematic cross-sectional view illustrating a fan-in type semiconductor package embedded in an interposer substrate and finally mounted on a main board of an electronic device. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package. 8 is a schematic cross-sectional view illustrating a fan-out type semiconductor package mounted on a main board of an electronic device. 9A and 9B are schematic diagrams illustrating a fan-out type semiconductor package according to an exemplary embodiment of the present invention. FIG. 10 is a schematic plan view taken along section line II ′ of the fan-out semiconductor package shown in FIG. 9A. 11A and 11B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention. 12A and 12B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention. 13A and 13B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention. 14A and 14B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention. 15A and 15B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention. 16A and 16B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention. 17A to 17C are schematic cross-sectional views illustrating various modifications of the coil formed in the fan-out type semiconductor package shown in FIG. 16A. 18A and 18B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention. 19A and 19B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention. 20A and 20B are schematic diagrams illustrating a fan-out type semiconductor package according to another exemplary embodiment of the present invention.

Claims (13)

A fan-out type semiconductor package includes: a first connection member having a through hole; a semiconductor wafer disposed in the through hole of the first connection member and surrounded by the first connection member, the semiconductor wafer Having an active surface and a passive surface opposite to the active surface, a connection pad is arranged on the active surface; an encapsulation body covering at least part of the passive surface of the first connection member and the semiconductor chip; And a second connection member disposed on the first connection member and the active surface of the semiconductor wafer, wherein the first connection member and the second connection member respectively include a redistribution layer, the heavy The wiring layer is electrically connected to the connection pad of the semiconductor wafer, and the first connection member includes a coil pattern layer, and the coil pattern layer is electrically connected to the connection pad of the semiconductor wafer. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the first connection member includes a plurality of first coil pattern layers, and each of the plurality of first coil pattern layers includes The coils formed by the coil patterns each have a central axis corresponding to the stacking direction of the plurality of first coil pattern layers. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the first connection member includes a plurality of first coil pattern layers, and each of the plurality of first coil pattern layers includes Of the coil patterns are electrically connected to each other via a through hole formed in the first connection member to form a coil, and the central axis of the coil corresponds to the stacking direction of the plurality of first coil pattern layers. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the first connection member includes a plurality of first coil pattern layers, each of which is included in each of the plurality of first coil pattern layers A plurality of coil patterns are electrically connected to each other via a plurality of through holes formed in the first connection member to form a coil, and a central axis of the coil corresponds to a direction perpendicular to the stacking direction of the plurality of first coil pattern layers Direction. The fan-out semiconductor package according to item 4 of the patent application range, wherein the coil includes a plurality of outer layers and a plurality of inner layers, the plurality of outer layers is based on the stack of the plurality of first coil pattern layers The layers are arranged on the outermost layer and the lowest layer in the direction, the plurality of inner layers are composed of the layers of the plurality of first coil pattern layers arranged between the plurality of outer layers, and the coil has a spiral path , The spiral path rotates based on the central axis while alternately passing through the plurality of outer layers and the plurality of inner layers. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the first connection member includes a first region to a fourth region surrounding the semiconductor wafer, and the first coil pattern layer is formed on the In a single area from the first area to the fourth area. The fan-out semiconductor package as described in item 1 of the patent scope, wherein the semiconductor chip includes an application processor (AP) and a power management integrated circuit (PMIC), and the first coil pattern layer forms a power inductor ( PI), and one end and the other end of the power inductor are electrically connected to the application processor and the power management integrated circuit, respectively. The fan-out semiconductor package according to item 1 of the patent application scope, wherein the first connection member includes a first insulating layer, first redistribution layers disposed on both surfaces of the first insulating layer, and A second rewiring layer, a second insulating layer disposed on the first insulating layer and covering the first rewiring layer, and a third rewiring layer disposed on the second insulating layer. The fan-out semiconductor package as described in item 8 of the patent application range, wherein the first connection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and the configuration A fourth rewiring layer on the third insulating layer. The fan-out type semiconductor package as described in item 8 of the patent application range, wherein the first insulating layer has a thickness greater than that of the second insulating layer. The fan-out semiconductor package as described in item 8 of the patent application range, wherein the third redistribution layer has a thickness greater than that of the redistribution layer of the second connection member. The fan-out semiconductor package as described in item 8 of the patent application range, wherein the first redistribution layer is disposed at a level between the active surface and the passive surface of the semiconductor wafer. The fan-out semiconductor package as described in item 8 of the patent application range, wherein the lower surface of the third redistribution layer is disposed at a level lower than the lower surface of the connection pad.