TW201839541A - Phase compensation method for power factor correction circuit - Google Patents
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Description
本案關於一種相位補償方法,尤指一種適用於功率因數校正電路之相位補償方法。The present invention relates to a phase compensation method, and more particularly to a phase compensation method suitable for a power factor correction circuit.
負載對於電源轉換裝置而言,可能表現為電阻性阻抗、電感性阻抗、電容性阻抗或者其組合。當輸入至負載的電流與加到負載的電壓同相時,功率因數接近1。當功率因數小於1時,所傳輸的功率可能因電流和電壓之間的相位不匹配或雜訊的引入而有所損耗。The load may be represented by a resistive impedance, an inductive impedance, a capacitive impedance, or a combination thereof for the power conversion device. When the current input to the load is in phase with the voltage applied to the load, the power factor is close to one. When the power factor is less than 1, the transmitted power may be lost due to phase mismatch between current and voltage or the introduction of noise.
故為了避免功率因數降低而提高效率,習知電源轉換裝置通常具有功率因數校正功能,例如藉由配置主動型的功率因數校正(PFC)電路來實現,該功率因數校正電路可以前饋的方式採樣所接收之交流輸入電壓,進而依據交流輸入電壓調整自身所輸出之輸出電流,以使功率因數校正電路所接收之交流輸入電流追隨交流輸入電壓,藉此得到一個接近正弦波形且同相位的交流輸入電流,以提高功率因數,降低電流諧波。Therefore, in order to avoid the power factor reduction and improve the efficiency, the conventional power conversion device usually has a power factor correction function, for example, by configuring an active power factor correction (PFC) circuit, which can be sampled in a feedforward manner. The received AC input voltage, and then the output current output by the AC input voltage is adjusted, so that the AC input current received by the power factor correction circuit follows the AC input voltage, thereby obtaining an AC input that is close to a sinusoidal waveform and is in phase. Current to increase power factor and reduce current harmonics.
然而,習知功率因數校正電路中多具有橋式整流二極體,而橋式整流二極體之順向壓降,以及設置於橋式整流二極體後之高頻濾波電容,會造成交流輸入電流在交流輸入電壓零點附近發生停頓及其畸變之現象,因而產生零交越失真,使得總諧波失真增加,並導致功率因數降低。However, the conventional power factor correction circuit has a bridge rectifier diode, and the forward voltage drop of the bridge rectifier diode and the high frequency filter capacitor disposed after the bridge rectifier diode cause AC communication. The input current is stalled near the zero point of the AC input voltage and its distortion, resulting in zero-crossing distortion, which increases the total harmonic distortion and leads to a reduction in power factor.
因此,如何發展一種可改善上述習知技術缺失之適用於功率因數校正電路之相位補償方法,實為目前迫切之需求。Therefore, how to develop a phase compensation method suitable for a power factor correction circuit which can improve the above-mentioned conventional techniques is an urgent need.
本案之目的在於提供一種適用於功率因數校正電路之相位補償方法,俾解決習知功率因數校正電路具有零交越失真,使得總諧波失真增加及功率因數降低等缺失。The purpose of the present invention is to provide a phase compensation method suitable for a power factor correction circuit, which solves the problem that the conventional power factor correction circuit has zero crossover distortion, such as total harmonic distortion increase and power factor reduction.
為達上述目的,本案提供一種相位補償方法,適用於功率因數校正電路,功率因數校正電路係接收輸入電壓及輸入電流,且包含開關電路及控制單元,開關電路係藉由控制單元之控制進行導通或截止之運作,使功率因數校正電路輸出輸出電壓及輸出電流,控制單元包含低通濾波器、微分控制器及餘弦乘法器,其中低通濾波器係持續接收反映當下輸入電流之輸入電流採樣信號,相位補償方法包含步驟:(a)依據當下之輸入電流產生對應之輸入電流採樣信號,並利用低通濾波器將輸入電流採樣信號進行濾波;(b)利用微分控制器而依據當下所接收之濾波後之輸入電流採樣信號及前次所接收之濾波後之輸入電流採樣信號,預測當下輸入電流之波形及前次輸入電流之波形,並依據當下輸入電流之波形及前次輸入電流之波形的差異產生電流誤差信號;(c)利用餘弦乘法器對電流誤差信號進行調整,以產生調整信號;(d)將調整信號與前饋信號進行疊加,以產生相位補償信號;(e)將相位補償信號與電流控制信號進行疊加,以產生脈衝寬度調變信號,並利用脈衝寬度調變信號控制開關電路之運作。In order to achieve the above object, the present invention provides a phase compensation method for a power factor correction circuit, the power factor correction circuit receives an input voltage and an input current, and includes a switch circuit and a control unit, and the switch circuit is controlled by the control unit. Or the operation of the cutoff, the power factor correction circuit outputs the output voltage and the output current, and the control unit comprises a low pass filter, a differential controller and a cosine multiplier, wherein the low pass filter continuously receives the input current sampling signal reflecting the current input current. The phase compensation method comprises the steps of: (a) generating a corresponding input current sampling signal according to the current input current, and filtering the input current sampling signal by using a low-pass filter; (b) using the differential controller to receive according to the current The filtered input current sampling signal and the previously received filtered input current sampling signal predict the waveform of the current input current and the waveform of the previous input current, and according to the waveform of the current input current and the waveform of the previous input current Difference produces a current error signal; (c) uses cosine The device adjusts the current error signal to generate an adjustment signal; (d) superimposes the adjustment signal and the feedforward signal to generate a phase compensation signal; (e) superimposes the phase compensation signal and the current control signal to generate a pulse The width modulation signal, and the pulse width modulation signal is used to control the operation of the switching circuit.
體現本案特徵與優點的一些典型實施例將在後段的說明中詳細敘述。應理解的是本案能夠在不同的態樣上具有各種的變化,其皆不脫離本案之範圍,且其中的說明及圖式在本質上當作說明之用,而非架構於限制本案。Some exemplary embodiments embodying the features and advantages of the present invention are described in detail in the following description. It should be understood that the present invention is capable of various modifications in various aspects, and is not intended to limit the scope of the present invention.
請參閱第1圖,其係為本案較佳實施例之功率因數校正電路之電路結構示意圖。如第1圖所示,本案之功率因數校正電路1可應用於一電源轉換裝置(未圖示)中,用以提高電源轉換裝置之功率因數,該功率因數校正電路1係接收一輸入電流Iin及一輸入電壓Vin,並輸出一輸出電流Iout及一輸出電壓Vout,且包含一開關電路10及一控制單元20。開關電路10可進行導通或截止之切換運作,使功率因數校正電路1產生輸出電流Iout及輸出電壓Vout。控制單元20係依據輸入電流Iin、輸入電壓Vin及輸出電壓Vout而輸出對應之一脈衝寬度調變信號D_pwm,以控制開關電路10之運作,藉此調整輸入電流Iin之相位與輸入電壓Vin之相位一致,並消除輸入電流Iin在輸入電壓Vin零點附近所發生之停頓及畸變之現象(零交越失真)。Please refer to FIG. 1 , which is a schematic diagram of the circuit structure of the power factor correction circuit of the preferred embodiment of the present invention. As shown in FIG. 1, the power factor correction circuit 1 of the present invention can be applied to a power conversion device (not shown) for improving the power factor of the power conversion device, and the power factor correction circuit 1 receives an input current Iin. And an input voltage Vin, and output an output current Iout and an output voltage Vout, and include a switch circuit 10 and a control unit 20. The switching circuit 10 can perform an on or off switching operation to cause the power factor correction circuit 1 to generate an output current Iout and an output voltage Vout. The control unit 20 outputs a corresponding pulse width modulation signal D_pwm according to the input current Iin, the input voltage Vin and the output voltage Vout to control the operation of the switching circuit 10, thereby adjusting the phase of the input current Iin and the phase of the input voltage Vin. Consistent, and eliminate the phenomenon of pause and distortion of the input current Iin near the zero point of the input voltage Vin (zero crossover distortion).
請參閱第2圖並配合第1圖,其中第2圖係為第1圖所示之控制單元之運作原理示意圖。如第2圖所示,控制單元20包含一低通濾波器22、一微分控制器23、一餘弦乘法器24、一第一加法運算器25及一第二加法運算器26。Please refer to FIG. 2 and cooperate with FIG. 1 , wherein FIG. 2 is a schematic diagram of the operation principle of the control unit shown in FIG. 1 . As shown in FIG. 2, the control unit 20 includes a low pass filter 22, a differential controller 23, a cosine multiplier 24, a first adder 25, and a second adder 26.
低通濾波器22可持續接收反映功率因數校正電路1當下所接收之輸入電流Iin之一輸入電流採樣信號,並對輸入電流採樣信號進行濾波。The low pass filter 22 can continuously receive an input current sampling signal reflecting one of the input currents Iin received by the power factor correction circuit 1 and filter the input current sampling signal.
微分控制器23電連接於低通濾波器22,其係接收每一次低通濾波器22所傳來之濾波後之輸入電流採樣信號,且具有可用來儲存信號之一暫存器,微分控制器23每一次接收到低通濾波器22所傳來之濾波後之輸入電流採樣信號時,係更新暫存器內的信號為當下所接收到之濾波後之輸入電流採樣信號,此外,在更新暫存器內的信號為當下所接收到之濾波後之輸入電流採樣信號之前,微分控制器23會先依據當下所接收到之濾波後之輸入電流採樣信號而預測當下輸入電流Iin之波形,以及依據暫存器所儲存之信號而預測暫存器所儲存之信號的波形,並比較當下輸入電流Iin之波形及暫存器所儲存之信號的波形,依據兩者波形之差異而對應輸出一電流誤差信號,其中若暫存器尚未儲存信號時,微分控制器23則輸出為零之電流誤差信號。因此於本實施例中,當功率因數校正電路1尚未運作時,微分控制器23之暫存器中實際上並無儲存任何信號,故當功率因數校正電路1開始運作而微分控制器23第一次接收到濾波後之輸入電流採樣信號時,由於此時暫存器中尚未存有任何信號,故微分控制器23輸出為零之電流誤差信號,且微分控制器23接續將此次所接收到之濾波後之輸入電流採樣信號儲存於暫存器內,而當微分控制器23第二次接收到濾波後之輸入電流採樣信號時,微分控制器23先依據第二次所接收到之濾波後之輸入電流採樣信號預測當下輸入電流Iin之波形,以及依據暫存器所儲存之信號而預測第一次所接收到之濾波後之輸入電流採樣信號的波形,並依據兩者波形之差異而對應輸出電流誤差信號,最後,再將第二次所接收到之濾波後之輸入電流採樣信號更新於暫存器中,換言之,微分控制器23實際上會依據當下所接收到之濾波後之輸入電流採樣信號而預測當下輸入電流Iin之波形,以及依據暫存器所儲存之前一次所接收到之濾波後之輸入電流採樣信號而預測前次對應之輸入電流Iin的波形,並依據兩者波形之差異而對應輸出電流誤差信號,且接續將當下所接收到之濾波後之輸入電流採樣信號更新於暫存器中。The differential controller 23 is electrically connected to the low pass filter 22, which receives the filtered input current sampling signal transmitted by each low pass filter 22, and has a register for storing the signal, and the differential controller 23, each time receiving the filtered input current sampling signal transmitted by the low-pass filter 22, updating the signal in the temporary register to the filtered input current sampling signal received at the moment, in addition, in the update Before the signal in the memory is the filtered input current sampling signal received by the current, the differential controller 23 first predicts the waveform of the current input current Iin according to the filtered input current sampling signal received, and according to The signal stored in the register predicts the waveform of the signal stored in the register, compares the waveform of the current input current Iin and the waveform of the signal stored in the register, and outputs a current error according to the difference between the waveforms of the two The signal, wherein the differential controller 23 outputs a zero current error signal if the register has not yet stored the signal. Therefore, in the present embodiment, when the power factor correction circuit 1 is not operating, virtually no signal is stored in the register of the differential controller 23, so when the power factor correction circuit 1 starts operating and the differential controller 23 is first When the filtered input current sampling signal is received, since there is no signal stored in the register at this time, the differential controller 23 outputs a zero current error signal, and the differential controller 23 continues to receive the current time. The filtered input current sampling signal is stored in the temporary register, and when the differential controller 23 receives the filtered input current sampling signal for the second time, the differential controller 23 firstly filters the received signal according to the second time. The input current sampling signal predicts the waveform of the current input current Iin, and predicts the waveform of the filtered input current sampling signal received by the first time according to the signal stored in the register, and correspondingly according to the difference between the waveforms of the two Output current error signal, and finally, update the filtered input current sampling signal received in the second register, in other words, differential control 23 actually predicts the waveform of the current input current Iin according to the filtered input current sampling signal received, and predicts the previous time according to the filtered input current sampling signal received by the temporary storage device. Corresponding to the waveform of the input current Iin, and corresponding to the output current error signal according to the difference between the two waveforms, and subsequently updating the filtered input current sampling signal received in the register to the temporary register.
於上述實施例中,微分控制器23可具有一補償因數,當微分控制器23比較輸入電流Iin之波形及暫存器所儲存之信號的波形後,係將比較結果與為常數值之補償因數進行乘法運算,藉此產生電流誤差信號。其中補償因數可為正數或負數。且補償因數可藉由輸入電流Iin與輸入電壓Vin之相位差預先設定。In the above embodiment, the differential controller 23 can have a compensation factor. When the differential controller 23 compares the waveform of the input current Iin with the waveform of the signal stored in the register, the comparison result is compared with the compensation factor of the constant value. A multiplication operation is performed to generate a current error signal. The compensation factor can be positive or negative. And the compensation factor can be preset by the phase difference between the input current Iin and the input voltage Vin.
餘弦乘法器24電連接於微分控制器23,用以接收微分控制器23所輸出之電流誤差信號,並對電流誤差信號進行調整,以輸出一調整信號,而藉由餘弦乘法器24的調整,可降低電流誤差信號之波形在峰值時的變化程度,並增加電流誤差信號之波形在零點時的變化程度。The cosine multiplier 24 is electrically connected to the differential controller 23 for receiving the current error signal output by the differential controller 23, and adjusting the current error signal to output an adjustment signal, which is adjusted by the cosine multiplier 24. It can reduce the degree of change of the waveform of the current error signal at the peak value and increase the degree of change of the waveform of the current error signal at the zero point.
第一加法運算器25電連接於餘弦乘法器24,其係可將所接收到的信號進行疊加,即將前饋信號D_ff及餘弦乘法器24所輸出之調整信號進行疊加,以對應輸出一相位補償信號D_comp,其中前饋信號D_ff主要是用來使功率因數校正電路1所輸出之輸出電流Iout可依據輸入電壓Vin進行調整,藉此使輸入電流Iin之相位與輸入電壓Vin之相位一致,且前饋信號D_ff實際上係依據輸入電壓Vin及輸出電壓Vout而產生,而前饋信號D_ff的推算方法如下式(1): D_ff = 1 – ( Vin / Vout ) (1) 另外,當微分控制器23輸出為零之電流誤差信號時,餘弦乘法器24所輸出之調整信號亦對應為零,故此時第一加法運算器25所輸出之相位補償信號D_comp實際上等於前饋信號D_ff。反之,當微分控制器23輸出非零之電流誤差信號時,第一加法運算器25所接收到之信號則包含餘弦乘法器24所輸出之調整信號及前饋信號D_ff,故第一加法運算器25所輸出之相位補償信號D_comp實際上等於調整信號與前饋信號D_ff之疊加。The first adder 25 is electrically connected to the cosine multiplier 24, which superimposes the received signals, that is, the feedforward signal D_ff and the adjustment signal output by the cosine multiplier 24 are superimposed to correspond to the output one phase compensation. The signal D_comp, wherein the feedforward signal D_ff is mainly used to adjust the output current Iout outputted by the power factor correction circuit 1 according to the input voltage Vin, thereby making the phase of the input current Iin coincide with the phase of the input voltage Vin, and before The feed signal D_ff is actually generated according to the input voltage Vin and the output voltage Vout, and the feedforward signal D_ff is estimated by the following equation (1): D_ff = 1 - (Vin / Vout) (1) In addition, when the differential controller 23 When the current error signal of zero is output, the adjustment signal output by the cosine multiplier 24 also corresponds to zero, so that the phase compensation signal D_comp output by the first adder 25 is substantially equal to the feedforward signal D_ff. On the other hand, when the differential controller 23 outputs a non-zero current error signal, the signal received by the first adder 25 includes the adjustment signal output by the cosine multiplier 24 and the feedforward signal D_ff, so the first adder The output phase compensation signal D_comp of 25 is actually equal to the superposition of the adjustment signal and the feedforward signal D_ff.
第二加法運算器26電連接於第一加法運算器25,其係接收第一加法運算器25所輸出之相位補償信號D_comp及一電流控制信號D_curr_ctrl,並將相位補償信號D_comp與電流控制信號D_curr_ctrl進行疊加,以產生脈衝寬度調變信號D_pwm。其中,電流控制信號D_curr_ctrl乃是依據輸出電流Iout的一電流回授值與一預設電流的比較結果而對應產生,其係用來使功率因數校正電路1所輸出之輸出電流Iout可符合預設電流而對應進行調整。The second adder 26 is electrically connected to the first adder 25, which receives the phase compensation signal D_comp and a current control signal D_curr_ctrl output by the first adder 25, and the phase compensation signal D_comp and the current control signal D_curr_ctrl The superposition is performed to generate a pulse width modulation signal D_pwm. The current control signal D_curr_ctrl is correspondingly generated according to a comparison result of a current feedback value of the output current Iout and a preset current, and is used to make the output current Iout output by the power factor correction circuit 1 conform to the preset. The current is adjusted accordingly.
請參閱第3圖並配合第1、2圖,其中第3圖係為本案較佳實施例之適用於第1圖所示之功率因數校正電路之相位補償方法的流程圖。本案較佳實施例之相位補償方法係包含下列步驟:Please refer to FIG. 3 and cooperate with the first and second figures. FIG. 3 is a flow chart of the phase compensation method applicable to the power factor correction circuit shown in FIG. 1 in the preferred embodiment of the present invention. The phase compensation method of the preferred embodiment of the present invention comprises the following steps:
首先,依據當下之輸入電流Iin產生對應之輸入電流採樣信號,並利用低通濾波器22對輸入電流採樣信號進行濾波 (如步驟S301所示)。First, a corresponding input current sampling signal is generated according to the current input current Iin, and the input current sampling signal is filtered by the low pass filter 22 (as shown in step S301).
接著利用微分控制器23依據當下所接收之濾波後之輸入電流採樣信號及前次所接收之濾波後之輸入電流採樣信號,預測當下輸入電流Iin之波形與前次輸入電流Iin之波形,並比較兩者波形之差異,以根據比較結果產生電流誤差信號 (如步驟S302所示)。Then, the differential controller 23 is used to predict the waveform of the current input current Iin and the waveform of the previous input current Iin according to the currently received filtered input current sampling signal and the previously received filtered input current sampling signal, and compare and compare The difference between the two waveforms is to generate a current error signal based on the comparison result (as shown in step S302).
接著,利用餘弦乘法器24對電流誤差信號進行調整,以產生調整信號 (如步驟S303所示)。Next, the current error signal is adjusted using the cosine multiplier 24 to generate an adjustment signal (as shown in step S303).
然後,利用第一加法運算器25將依據輸入電壓Vin及輸出電壓Vout所產生之前饋信號D_ff與調整信號進行疊加,以產生相位補償信號D_comp (如步驟S304所示)。Then, the feedforward signal D_ff generated according to the input voltage Vin and the output voltage Vout is superimposed with the adjustment signal by the first adder 25 to generate the phase compensation signal D_comp (as shown in step S304).
最後,利用第二加法運算器26將依據輸出電流Iout之電流回授值與預設電流的比較結果所產生之電流控制信號D_curr_ctrl與相位補償信號D_comp進行疊加,以產生脈衝寬度調變信號D_pwm來控制開關電路10,以調整輸出電流Iout之相位(如步驟S305)。而在步驟S305中,因輸出電流Iout之相位可依據脈衝寬度調變信號D_pwm之調整而對應於輸入電壓Vin之相位,又因輸入電流之相位會與輸出電流之相位相同,故調整輸出電流Iout的相位即可調整輸入電流Iin之相位,使輸入電流Iin之相位與輸入電壓Vin之相位為一致,此外,藉由低通濾波器22、微分控制器23及餘弦乘法器24的設置,即採用上述之步驟S301~S303,便可使本案之功率因數校正電路1有效降低零交越失真,降低總諧波失真,進而提升功率傳輸之效率。Finally, the second adder 26 superimposes the current control signal D_curr_ctrl and the phase compensation signal D_comp generated according to the comparison result of the current feedback value of the output current Iout with the preset current to generate the pulse width modulation signal D_pwm. The switching circuit 10 is controlled to adjust the phase of the output current Iout (step S305). In step S305, since the phase of the output current Iout can correspond to the phase of the input voltage Vin according to the adjustment of the pulse width modulation signal D_pwm, and the phase of the input current is the same as the phase of the output current, the output current Iout is adjusted. The phase of the input current Iin can be adjusted so that the phase of the input current Iin coincides with the phase of the input voltage Vin, and the setting of the low pass filter 22, the differential controller 23, and the cosine multiplier 24 is adopted. In the above steps S301~S303, the power factor correction circuit 1 of the present invention can effectively reduce the zero-crossover distortion and reduce the total harmonic distortion, thereby improving the efficiency of power transmission.
其中,在步驟S302中,若因功率因數校正電路1剛啟動而使微分控制器23初次接收到濾波後之輸入電流採樣信號,則如前所述,微分控制器23係輸出為零之電流誤差信號,故於步驟S304中,相位補償信號D_comp實際上等於前饋信號D_ff,而於步驟S305中,疊加電流控制信號D_curr_ctrl與相位補償信號D_comp所產生之脈衝寬度調變信號D_pwm則僅用來控制開關電路10,使輸入電流Iin之相位與輸入電壓Vin之相位為一致。In step S302, if the differential controller 23 first receives the filtered input current sampling signal due to the power factor correction circuit 1 being activated, the differential controller 23 outputs a zero current error as described above. The signal, so in step S304, the phase compensation signal D_comp is substantially equal to the feedforward signal D_ff, and in step S305, the pulse width modulation signal D_pwm generated by the superimposed current control signal D_curr_ctrl and the phase compensation signal D_comp is only used to control The switching circuit 10 makes the phase of the input current Iin coincide with the phase of the input voltage Vin.
請參閱第4圖及第5圖,其中第4圖係為未使用本案之相位補償方法之習知功率因數校正電路所接收之輸入電流之波形圖,第5圖係為使用本案第3圖所示之相位補償方法之功率因數校正電路所接收之輸入電流之波形圖。如第4圖所示,習知功率因數校正電路所接收之輸入電流在輸入電壓處於零點時,即時間T1及時間T2時,會因功率因數校正電路所包含之橋式整流二極體及高頻濾波電容而造成停頓及其畸變之現象,因而產生零交越失真,使得總諧波失真增加。而如第5圖所示,本案之功率因數校正電路所接收之輸入電流Iin在輸入電壓處於零點時,即時間T3及時間T4時,會因使用本案之相位補償方法,使得停頓及其畸變之現象大幅減少,故零交越失真明顯較小。因此,比較第4圖及第5圖可知,相較於利用習知功率因數校正電路進行功率因數校正後之輸入電流,使用本案第3圖所示之相位補償方法之功率因數校正電路所接收之輸入電流Iin的零交越失真大幅降低,有效降低總諧波失真,進而提升功率傳輸之效率。Please refer to FIG. 4 and FIG. 5 , wherein FIG. 4 is a waveform diagram of input current received by a conventional power factor correction circuit that does not use the phase compensation method of the present invention, and FIG. 5 is a diagram used in FIG. 3 of the present application. A waveform diagram of the input current received by the power factor correction circuit of the phase compensation method. As shown in FIG. 4, the input current received by the conventional power factor correction circuit is due to the bridge rectifier diode and the high voltage included in the power factor correction circuit when the input voltage is at zero, that is, time T1 and time T2. The frequency filter capacitor causes a phenomenon of pause and distortion, thereby generating zero-crossing distortion, resulting in an increase in total harmonic distortion. As shown in Fig. 5, the input current Iin received by the power factor correction circuit of the present case causes the pause and its distortion due to the use of the phase compensation method of the present case when the input voltage is at zero, that is, time T3 and time T4. The phenomenon is greatly reduced, so the distortion of zero crossover is significantly smaller. Therefore, comparing FIGS. 4 and 5, it can be seen that the input current after power factor correction using the conventional power factor correction circuit is received by the power factor correction circuit of the phase compensation method shown in FIG. 3 of the present invention. The zero-crossover distortion of the input current Iin is greatly reduced, effectively reducing the total harmonic distortion, thereby improving the efficiency of power transmission.
綜上所述,本案之適用於功率因數校正電路之相位補償方法藉由微分控制器依據當下所接收之濾波後之輸入電流採樣信號及前次所接收之濾波後之輸入電流採樣信號,預測當下輸入電流之波形與前次輸入電流之波形,並根據波形之差異產生電流誤差信號,接著利用餘弦乘法器對電流誤差信號進行調整以產生調整信號,而後將調整信號與前饋信號進行疊加以產生相位補償信號,最後藉由相位補償信號與電流控制信號疊加所產生之脈衝寬度調變信號來控制開關電路,如此一來,不僅調整輸入電流之相位與輸入電壓之相位為一致,更能有效降低零交越失真,降低總諧波失真,進而提升功率傳輸之效率。此外,本案之適用於功率因數校正電路之相位補償方法藉由餘弦乘法器對電流誤差信號之調整,降低電流誤差信號之波形在峰值時的變化程度,並增加電流誤差信號之波形在零點時的變化程度,使利用本案之相位補償方法之功率因數校正電路得以提升穩定裕度。In summary, the phase compensation method applicable to the power factor correction circuit of the present invention predicts the current state by the differential controller according to the currently received filtered input current sampling signal and the previously received filtered input current sampling signal. The waveform of the input current and the waveform of the previous input current, and the current error signal is generated according to the difference of the waveform, and then the current error signal is adjusted by the cosine multiplier to generate an adjustment signal, and then the adjustment signal is superimposed with the feedforward signal to generate The phase compensation signal finally controls the switching circuit by the pulse width modulation signal generated by superimposing the phase compensation signal and the current control signal, so that not only the phase of the input current is matched with the phase of the input voltage, but also the effective reduction can be effectively reduced. Zero crossover distortion reduces total harmonic distortion, which in turn increases the efficiency of power transfer. In addition, the phase compensation method applicable to the power factor correction circuit of the present invention adjusts the current error signal by the cosine multiplier, reduces the degree of change of the waveform of the current error signal at the peak value, and increases the waveform of the current error signal at the zero point. The degree of change enables the power factor correction circuit using the phase compensation method of the present invention to increase the stability margin.
須注意,上述僅是為說明本案而提出之較佳實施例,本案不限於所述之實施例,本案之範圍由如附專利申請範圍決定。且本案得由熟習此技術之人士任施匠思而為諸般修飾,然皆不脫如附專利申請範圍所欲保護者。It should be noted that the above is only a preferred embodiment for the purpose of illustrating the present invention, and the present invention is not limited to the embodiments described above, and the scope of the present invention is determined by the scope of the patent application. Moreover, the case may be modified by those who are familiar with the technology, but it is not intended to be protected by the scope of the patent application.
1‧‧‧功率因數校正電路1‧‧‧Power Factor Correction Circuit
10‧‧‧開關電路10‧‧‧Switch circuit
20‧‧‧控制單元20‧‧‧Control unit
22‧‧‧低通濾波器22‧‧‧Low-pass filter
23‧‧‧微分控制器23‧‧‧Differential controller
24‧‧‧餘弦乘法器24‧‧‧ Cosine Multiplier
25‧‧‧第一加法運算器25‧‧‧First Adder
26‧‧‧第二加法運算器26‧‧‧Second Adder
Iin‧‧‧輸入電流Iin‧‧‧ input current
Vin‧‧‧輸入電壓Vin‧‧‧Input voltage
Iout‧‧‧輸出電流Iout‧‧‧Output current
Vout‧‧‧輸出電壓Vout‧‧‧ output voltage
D_ff‧‧‧前饋信號D_ff‧‧‧ feedforward signal
D_comp‧‧‧相位補償信號D_comp‧‧‧ phase compensation signal
D_curr_ctrl‧‧‧電流控制信號D_curr_ctrl‧‧‧ current control signal
D_pwm‧‧‧脈衝寬度調變信號D_pwm‧‧‧ pulse width modulation signal
S301~S305‧‧‧相位補償方法的步驟Steps of S301~S305‧‧‧ phase compensation method
T1、T2、T3、T4‧‧‧時間T1, T2, T3, T4‧‧‧ time
第1圖係為本案較佳實施例之功率因數校正電路之電路結構示意圖。FIG. 1 is a schematic diagram showing the circuit structure of a power factor correction circuit according to a preferred embodiment of the present invention.
第2圖係為第1圖所示之控制單元之運作原理示意圖。Figure 2 is a schematic diagram showing the operation principle of the control unit shown in Figure 1.
第3圖係為本案較佳實施例之適用於第1圖所示之功率因數校正電路之相位補償方法的流程圖。Figure 3 is a flow chart of a phase compensation method applicable to the power factor correction circuit shown in Figure 1 of the preferred embodiment of the present invention.
第4圖係為未使用本案之相位補償方法之習知功率因數校正電路所接收之輸入電流之波形圖。Figure 4 is a waveform diagram of the input current received by a conventional power factor correction circuit that does not use the phase compensation method of the present invention.
第5圖係為使用本案第3圖所示之相位補償之功率因數校正電路所接收之輸入電流之波形圖。Figure 5 is a waveform diagram of the input current received by the power factor correction circuit of the phase compensation shown in Fig. 3 of the present invention.
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