TW201836091A - Semiconductor device and method of controlling warpage in reconstituted wafer - Google Patents

Abstract

A semiconductor device has a substrate with a plurality of active semiconductor die disposed over a first portion of the substrate and a plurality of non-functional semiconductor die disposed over a second portion of the substrate while leaving a predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die. The predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die includes a central area, checkerboard pattern, linear, or diagonal area of the substrate. The substrate can be a circular shape or rectangular shape. An encapsulant is deposited over the active semiconductor die, non-functional semiconductor die, and substrate. An interconnect structure is formed over the semiconductor die. The absence of active semiconductor die and non-functional semiconductor die from the predetermined areas of the substrate reduces bending stress in that area of the substrate.

Description

 Semiconductor device and method of controlling warpage in reconstructed wafer  

The present invention relates generally to semiconductor devices and, more particularly, to a semiconductor device and method for controlling warpage in a reconstructed wafer by reducing the number of crystal grains to leave a temporary substrate The open area is free of semiconductor grains.

Domestic priority claim

This application is a continuation-in-part of U.S. Patent Application Serial No. 14/036, the entire disclosure of which is incorporated herein by reference.

Semiconductor devices are common in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices typically comprise one type of electrical component, such as a light emitting diode (LED), a small signal transistor, a resistor, a capacitor, an inductor, and a power metal oxide semiconductor field effect transistor (MOSFET). Semiconductor devices that are concentrated typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, and various signal processing circuits.

Semiconductor devices perform a wide range of functions, such as signal processing, high speed computing, transmitting and receiving electromagnetic signals, controlling electronics, converting sunlight into electricity, and producing visual images for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networking, computers, and consumer products. Semiconductor devices are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

Semiconductor devices utilize the electrical properties of semiconductor materials. The structure of the semiconductor material allows the conductivity of the material to be manipulated by the application of an electric or base current or through a doping process. The doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

A semiconductor device includes an active and passive electrical structure. An active structure comprising a bi-carrier and a field effect transistor controls the flow of current. By varying the degree of doping and the application of an electric or base current, the transistor does not lift, or limit, the flow of current. A passive structure comprising resistors, capacitors, and inductors creates a relationship between voltage and current that is necessary to perform various electrical functions. The passive and active structures are electrically connected to form a circuit that enables the semiconductor device to perform high speed operations and other useful functions.

Semiconductor devices are typically fabricated using two complex processes, namely front-end manufacturing and back-end manufacturing, each of which potentially involves hundreds of steps. Front-end fabrication involves the formation of a plurality of dies on the surface of a semiconductor wafer. Each of the semiconductor dies is generally identical and includes circuitry formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor dies from completed wafers and packaging the dies to provide structural support, electrical interconnection, and environmental isolation. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and thus can refer to both a single semiconductor device and a plurality of semiconductor devices.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume lower power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint that is desirable for smaller end products. Smaller semiconductor grain sizes can be achieved by improvements in the front end process of producing semiconductor dies having smaller and higher density active and passive components. The backend process can produce semiconductor device packages with smaller footprints by improvements in electrical interconnects and packaging materials.

In the fabrication of a semiconductor package, a plurality of semiconductor dies can be mounted to a temporary substrate. A sealant is deposited over the semiconductor dies and the substrate. The temporary substrate system is then removed. Due to the difference in the CTE of the semiconductor dies and the encapsulant, the reconstituted wafer is susceptible to warpage or bending after removal of the substrate. The warpage of the reconstructed wafer is caused by defects and handling during subsequent fabrication steps, such as an interconnect structure over the semiconductor die and formation of the encapsulant.

According to a feature of the present application, there is provided a method of fabricating a semiconductor device, comprising: providing a substrate comprising a plurality of die attach locations arranged in rows and columns across the substrate, each The die attach location has a predetermined uniform region; a plurality of active semiconductor die are disposed over a first number of die attach locations on the substrate; and a second amount on the substrate a plurality of non-functional semiconductor dies are disposed over the die attaching locations, leaving a third number of die attach locations on the substrate without the active semiconductor die and the non-functional semiconductor die of.

According to another feature of the present application, there is provided a method of fabricating a semiconductor device, the method comprising: providing a substrate including a plurality of die attach locations; and a first number of die on the substrate A plurality of semiconductor dies are disposed over the attachment locations, leaving a second number of die attachment locations on the substrate open and unoccupied, respectively.

According to another feature of the present application, there is provided a semiconductor device comprising: a substrate including a plurality of die attach locations; a plurality of first number of die attaches disposed on the substrate An active semiconductor die above the bonding location; and a plurality of non-functional semiconductor dies disposed over a second number of die attach locations on the substrate, leaving a portion on the substrate The three number of die attach locations are absent from the active semiconductor die and the non-functional semiconductor die.

50‧‧‧Electronic devices

52‧‧‧PCB

54‧‧‧Signal lines

56‧‧‧bonded wire package

58‧‧‧Flip chip

60‧‧‧Pellet Array (BGA)

62‧‧‧Bump wafer substrate (BCC)

66‧‧‧ Platform Grid Array (LGA)

68‧‧‧Multi-chip module (MCM)

70‧‧‧Four-sided flat leadless package (QFN)

72‧‧‧Four-sided flat package

74‧‧‧In-line wafer level grid array (eWLB)

76‧‧‧ Wafer Level Wafer Size Package (WLCSP)

120‧‧‧Semiconductor wafer

122‧‧‧Base substrate material

124‧‧‧Semiconductor grains

126‧‧ ‧ cutting road

128‧‧‧Back surface (non-active surface)

130‧‧‧Active surface

132‧‧‧ Conductive layer

136‧‧‧Test probe head

138‧‧‧ probe

139‧‧‧Computer Test System

140‧‧‧ Temporary substrate

141‧‧‧ saw blade (laser cutting tool)

142‧‧‧Foil layer (interlayer layer, double-sided tape)

144‧‧‧Reconstructed wafer

146‧‧‧Sealant (forming compound)

147‧‧‧Central area

148‧‧‧Central area

150‧‧‧Area

152‧‧‧ area

154‧‧‧ Area

156‧‧‧ Area

158‧‧‧Area

200‧‧‧ die attach area

200a‧‧‧ die attachment area

200b‧‧‧ die attach area

200c‧‧‧ die attach area

202‧‧‧Dummy semiconductor die

206‧‧‧open space (central area)

210‧‧‧ die attach area

210a‧‧‧ die attach area

210b‧‧‧ die attach area

210c‧‧‧ die attach area

212‧‧‧Dummy semiconductor die

216‧‧‧open space (area)

220‧‧‧ die attach area

220a‧‧‧ die attach area

220b‧‧‧ die attachment area

220c‧‧‧ die attachment area

222‧‧‧Dummy semiconductor die

226‧‧‧open space (region)

226a‧‧‧checkerboard pattern

226b‧‧‧ diagonal area

230‧‧‧ die attach area

230a‧‧‧ die attach area

230b‧‧‧ die attach area

230c‧‧‧ die attach area

232‧‧‧Dummy semiconductor die

236‧‧‧open space (area)

236a‧‧‧Central Area

236b‧‧‧ diagonal area

240‧‧‧ die attach area

240a‧‧‧ die attachment area

240b‧‧‧ die attachment area

240c‧‧‧ die attach area

246‧‧‧open space (area)

246a‧‧‧Central area

246b‧‧‧ diagonal area

250‧‧‧ die attach area

250a‧‧‧ die attachment area

250b‧‧‧ die attach area

250c‧‧‧ die attach area

256‧‧‧open space (area)

256a‧‧‧Central area

256b‧‧‧ diagonal area

260‧‧‧ die attachment area

260a‧‧‧ die attach area

260b‧‧‧ die attach area

260c‧‧‧ die attach area

266‧‧‧open space (area)

266a‧‧‧Central Area

266b‧‧‧Line (diagonal) area

270‧‧‧ die attach area

270a‧‧‧ die attach area

270b‧‧‧ die attach area

270c‧‧‧ die attach area

276‧‧‧open space (area)

276a‧‧‧Central Area

276b‧‧‧Linear (diagonal) area

280‧‧‧Stacked interconnect structures

282‧‧‧ Conductive layer (redistribution layer)

284‧‧‧Insulation (passivation) layer

286‧‧‧Bumps

288‧‧‧ saw blade (laser cutting tool)

290‧‧‧eWLB

Figure 1 depicts a printed circuit board (PCB) in which different types of packages are mounted to a surface of the PCB; Figures 2a-2d depict a semiconductor wafer in which a plurality of semiconductor dies are formed by dicing streets Separate; Figures 3a-3h depict a process for forming a reconstructed wafer with reduced warpage by leaving an open region of a substrate without the semiconductor die; Figure 4 is depicted in Figure 4 A semiconductor package after the singulation of the reconstructed wafer; FIGS. 5a-5b depict a circular reconstructed wafer in which a semiconductor die is not present in a center; FIGS. 6a-6b depict a a circular reconstructed wafer in which a plurality of semiconductor dies are not present in a center; FIGS. 7a-7c depict a circular reconstructed wafer in which a plurality of open regions on the substrate are absent Figure 8 is a rectangular reconstructed wafer having a position where the gap is open on the substrate; Figure 9 is a diagram showing another rectangular reconstructed wafer having the substrate on the substrate The position where the gap is open; Figure 10 depicts another rectangular reconstructed crystal , which has a position where the gap on the substrate is open; FIG. 11 depicts another rectangular reconstructed wafer having a position where the gap on the substrate is open; FIGS. 12a-12c depict a reconstructed crystal a circle having semiconductor grains and a central open region without semiconductor grains; FIGS. 13a-13b depict a reconstructed wafer having semiconductor grains and a checkerboard pattern of open regions without semiconductor grains Figure 14 depicts a reconstructed wafer having semiconductor grains and a checkerboard pattern and diagonal open areas without semiconductor grains; Figures 15a-15b depict a reconstructed wafer with semiconductor crystals Particles and a central region and a diagonal region without semiconductor grains; FIG. 16 depicts another reconstructed wafer having semiconductor grains and a central region and a diagonal region without semiconductor grains; Another reconstructed wafer is depicted having a semiconductor die and a central region and a diagonal region without the semiconductor die; FIG. 18 depicts a reconstructed wafer having a semiconductor die and a There are no central regions of the semiconductor grains and straight and diagonal regions; and Figure 19 depicts another reconstructed wafer having semiconductor grains and a central region without semiconductor grains and straight and diagonal regions.

The invention is described in one or more embodiments in the following description of the drawings, wherein the same reference numerals represent the same or similar elements. Although the present invention has been described in terms of the best mode for the purpose of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to be The accompanying claims, and the equivalents, modifications and equivalents

Semiconductor devices are typically fabricated using two complex processes: front-end manufacturing and back-end manufacturing. Front-end fabrication involves the formation of a plurality of dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. For example, the active electrical components of the transistor and the diode have the ability to control the flow of current. For example, passive electrical components of capacitors, inductors, and resistors produce a relationship between the voltage and current necessary to perform circuit functions.

The passive and active components are formed on the surface of the semiconductor wafer by a series of processing steps including doping, deposition, lithography, etching, and planarization. Doping is carried into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the conductivity of the semiconductor material in the active device by dynamically changing the conductivity of the semiconductor material in response to an electric field or base current. The electro-crystalline system comprises regions of different types and degrees of doping that are configured to enable the transistor to increase or limit the flow of current when an electric field or base current is applied.

Active and passive components are formed by layers of materials having different electrical properties. The layers can be formed by a variety of deposition techniques, some of which are determined by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is typically patterned to form an active member, a passive member, or a portion of an electrical connection between the members.

Back end fabrication refers to cutting or singulation of a finished wafer into individual semiconductor dies, and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor die, the wafer is scribed and truncated along non-functional areas of the wafer, referred to as scribe lines or scribe lines. The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are mounted to a package substrate that includes pins or contact pads for interconnecting with other system components. A contact pad formed over the semiconductor die is then attached to the contact pads within the package. The electrical connections can be made using conductive layers, bumps, stud bumps, conductive paste, or wire bonds. A sealant or other forming material is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system and the functionality of the semiconductor device is made available to other system components.

1 depicts an electronic device 50 having a wafer carrier substrate or PCB 52, wherein a plurality of semiconductor packages are mounted over a surface of PCB 52. Depending on the application, electronic device 50 can have one type of semiconductor package, or multiple types of semiconductor packages. Different types of semiconductor packages are shown in Figure 1 for purposes of illustration.

Electronic device 50 can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 50 can be a sub-component of a larger system. For example, the electronic device 50 can be part of a tablet, a mobile phone, a digital camera, or other electronic device. Alternatively, the electronic device 50 can be a display card, a network interface card or other signal processing card that can be inserted into a computer. The semiconductor package can include a microprocessor, a memory, an application specific integrated circuit (ASIC), a logic circuit, an analog circuit, a radio frequency (RF) circuit, a discrete device, or other semiconductor die or electrical component. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices can be shortened to achieve higher densities.

In FIG. 1, PCB 52 provides a general substrate for structural support and electrical interconnection of a semiconductor package mounted on the PCB. The electrically conductive signal lines 54 are formed over a surface of the PCB 52 or within the layers by evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal line 54 provides electrical communication between each of the semiconductor package, the mounted components, and other external system components. Line 54 also provides power and ground connections to each semiconductor package.

In some embodiments, a semiconductor device has two package levels. The first level of packaging is a technique for mechanically and electrically attaching semiconductor dies to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, a semiconductor device may have only the package of the first level, wherein the die is directly mechanically and electrically mounted to the PCB.

For purposes of illustration, a plurality of types of first level packages including bond wire packages 56 and flip chips 58 are shown on PCB 52. In addition, it includes a ball grid array (BGA) 60, a bump wafer substrate (BCC) 62, a platform grid array (LGA) 66, a multi-chip module (MCM) 68, a quad flat no-lead package (QFN) 70, and four sides. Several types of second level packages of flat package 72, in-line wafer level ball grid array (eWLB) 74, and wafer level wafer size package (WLCSP) 76 are shown mounted on PCB 52. In one embodiment, the eWLB 74 is a fan-out level package (Fo-WLP) and the WLCSP 76 is a fan-in-wafer level package (Fi-WLP). Depending on the needs of the system, any combination of semiconductor packages and other electronic components configured in any combination of package types of the first and second levels can be connected to the PCB 52. In some embodiments, electronic device 50 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Since semiconductor packages include complex functions, electronic devices can be fabricated using less expensive components and streamlined processes. The resulting device is less likely to fail and is less expensive to manufacture, resulting in lower costs for the consumer.

2a shows a semiconductor wafer 120 having a base substrate material 122 such as tantalum, niobium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, tantalum carbide, or Other base semiconductor materials for structural support. A plurality of semiconductor dies or features 124 are formed on wafer 120 as described above, separated by an inactive inter-die wafer region or scribe line 126. The scribe line 126 provides a dicing area to singulate the semiconductor wafer 120 into individual semiconductor dies 124. In one embodiment, semiconductor wafer 120 has a width or diameter of 100-450 millimeters (mm).

2b is a cross-sectional view showing a portion of a semiconductor wafer 120. Each of the semiconductor dies 124 has a back surface or an inactive surface 128, and an active surface 130 including an analog or digital circuit implemented as an active device, a passive device, a conductive layer, and a dielectric A layer, which is formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit can include one or more transistors, diodes, and other circuit components formed within active surface 130 to implement analog circuits or digital circuits, such as digital signal processors (DSPs), ASICs, Memory, or other signal processing circuits. Semiconductor die 124 may also include an integrated passive device (IPD) such as an inductor, capacitor, and resistor for RF signal processing.

A conductive layer 132 is formed over the active surface 130 by PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. Conductive layer 132 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer 132 operates as a contact pad that is electrically coupled to circuitry on active surface 130. As shown in FIG. 2b, the conductive layer 132 can be formed as a contact pad that is disposed side by side with a first distance apart from the edge of the semiconductor die 124. Alternatively, the conductive layer 132 can be formed as a contact pad that is biased in a plurality of columns such that a contact pad of a first column is disposed a first distance from the edge of the die, and The contact pads of the second column of alternating first columns are disposed a second distance from the edge of the die.

The semiconductor wafer 120 is electrically tested and inspected as part of a quality control process. Inspection of the artificial vision and automated optical systems are used to perform inspections on the semiconductor wafer 120. The software can be utilized in automated optical analysis of the semiconductor wafer 120. The visual inspection method can utilize, for example, a scanning electron microscope, high intensity or ultraviolet light, or a metallographic microscope. The semiconductor wafer 120 is inspected for structural features including warpage, thickness variations, surface particles, irregularities, cracks, delamination, and discoloration.

The active and passive components within the semiconductor die 124 are tested at the wafer level for electrical performance and circuit function. As shown in Figure 2c, each semiconductor die 124 is tested for functional and electrical parameters using a test probe head 136 comprising a plurality of probes or test leads 138, or other test device. . Probe 138 is used to make electrical contact between the nodes or conductive layers 132 on each of the semiconductor dies 124 and to provide electrical stimulation to the components on the active surface 130. The semiconductor die 124 is responsive to the electrical stimuli, which are measured by a computer test system 139 and tested for the function of the semiconductor die as compared to an expected response. These electrical tests may include circuit function, lead integrity, resistivity, continuity, reliability, junction depth, ESD, RF performance, drive current, critical current, leakage current, and specific operating parameters of the component type. . Inspection and electrical testing of the semiconductor wafer 120 enables the passed semiconductor die 124 to be identified as a well-known die (KGD) for use in a semiconductor package.

In FIG. 2d, semiconductor wafer 120 is singulated into individual semiconductor dies 124 by a saw blade or laser cutting tool 141 through dicing streets 126. The individual semiconductor dies 124 can be inspected and electrically tested for identification of KGD after singulation.

3a-3h depict, in relation to FIG. 1, a process for forming a reconstructed wafer having reduced warpage, by which the number of crystal grains is reduced to leave an open region of the temporary substrate without semiconductor crystals. Granular. Figure 3a is a cross-sectional view showing a portion of a temporary substrate 140 comprising a sacrificial substrate material such as germanium, polymer, tantalum oxide, glass, or other suitable low cost for structural support. Rigid material. A foil layer 142 is laminated to the substrate 140. The foil layer 142 can be copper or other reinforcing material to reduce the warping effect. Alternatively, an interfacial layer or double-sided tape 142 is formed over the substrate 140 as a temporary adhesive bonding film, etch stop layer, or heat release layer.

Substrate 140 can be a circular or rectangular panel (greater than 300 mm) having a capacity for a plurality of semiconductor dies 124. Substrate 140 can have a surface area that is greater than the surface area of semiconductor wafer 120. A larger substrate reduces the manufacturing cost of the semiconductor package because more semiconductor dies can be processed on the larger substrate, thereby reducing the cost per unit. Semiconductor packaging and processing equipment is designed and configured for the size of the wafer or substrate being processed.

In order to further reduce the manufacturing cost, the size of the substrate 140 is selected independently of the size of the semiconductor die 124 or the size of the semiconductor wafer 120. In other words, the substrate 140 has a fixed or standardized size that can accommodate semiconductor dies 124 of various sizes that are singulated from one or more semiconductor wafers 120. In one embodiment, substrate 140 is circular having a diameter of 330 mm. In another embodiment, the substrate 140 is a rectangle having a width of 560 mm and a length of 600 mm. The semiconductor die 124 may have a size of 10 mm by 10 mm, which is disposed on the standardized substrate 140. Alternatively, the semiconductor die 124 may have a size of 20 mm by 20 mm, which is disposed on the same standardized substrate 140. Thus, the standardized substrate 140 can process semiconductor dies 124 of any size, which allows subsequent semiconductor processing equipment to be standardized to a common substrate, i.e., regardless of die size or incoming wafer size. Semiconductor package devices can be designed and configured for a standard substrate using a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized substrate 140 reduces manufacturing costs and capital risk by reducing or eliminating the need for a dedicated semiconductor production line based on die size or incoming wafer size. A flexible manufacturing line can be implemented by selecting a predetermined substrate size for use with semiconductor dies of any size from all semiconductor wafers.

In Figure 3b, the semiconductor die 124 from Figure 2d is mounted to the substrate 140 and the foil layer 142, for example, by a pick and place operation, wherein the active surface 130 is oriented toward the substrate. 3c shows the semiconductor die 124 mounted to the foil layer 142 of the substrate 140 as a reconstructed or reconfigured wafer 144 having a width or diameter of 330 mm.

Reconstructed wafer 144 can be processed into many types of semiconductor packages, including in-line wafer level ball grid array (eWLB), fan-in wafer level wafer size package (WLCSP), rebuild or in-line wafer level Wafer size package (eWLCSP), fan-out WLCSP, flip chip package, such as a stacked package (PoP) three-dimensional (3D) package, or other semiconductor package. The reconstructed wafer 144 is configured according to the specifications of the resulting semiconductor package. In one embodiment, the semiconductor die 124 is disposed on the substrate 140 in a high density configuration (i.e., 300 micrometers (μm) or less) for processing the fan-in device. In another embodiment, the semiconductor dies 124 are separated by a distance of 50 [mu]m on the substrate 140. The distance between the semiconductor dies 124 on the substrate 140 is optimized for fabricating the semiconductor packages at the lowest unit cost. The larger the surface area of the substrate 140, the more semiconductor wafers 124 are accommodated and the manufacturing cost is reduced because each of the reconstructed wafers 144 processes more of the semiconductor die 124. The number of semiconductor dies 124 mounted to the substrate 140 may be greater than the number of semiconductor dies 124 that are singulated from the semiconductor wafer 120. Substrate 140 and reconstituted wafer 144 provide resiliency to utilize different sized semiconductor dies 124 from different sized semiconductor wafers 120 to fabricate many different types of semiconductor packages.

In Figure 3d, a sealant or molding compound 146 is deposited using a paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicator. Above the semiconductor die 124 and the substrate 140. In particular, the encapsulant 146 covers the four side surfaces and the back surface 128 of the semiconductor die 124 at a thickness of 470 μm. The encapsulant 146 can be a polymer composite such as an epoxy with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. Encapsulant 146 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. Encapsulant 146 also protects semiconductor die 124 from degradation due to exposure to light.

In Figure 3e, substrate 140 and foil layer 142 are by chemical etching, mechanical stripping, chemical mechanical planarization (CMP), mechanical polishing, thermal baking, UV light, laser scanning, or wet stripping. It is removed to expose the active surface 130 and the conductive layer 132. The back surface 128 of the semiconductor die 124 and the sides of the semiconductor die remain covered by the encapsulant 146 to serve as a protective panel to increase yield, particularly when the semiconductor die is surface mounted.

As shown in FIG. 3f, after removal of the substrate 140 and the foil layer 142, the wafer 144 is reconstructed because of differences in the CTE of the semiconductor die 124 and the encapsulant 146, as well as the chemical cure shrinkage effect of the encapsulant. , and easily suffer from warping or bending. For a circular substrate 140 having a diameter of 305 mm, the reconstructed wafer 144 may exhibit a warp or bend of -2.0 mm.

Under consideration of this warpage problem, Figure 5a is returned to the state of the reconstructed wafer 144 prior to removal of the substrate 140 and foil layer 142. In particular, Figure 5a shows a plan view of a circular reconstructed wafer 144 in which semiconductor die 124 is mounted to foil layer 142 and substrate 140 and is covered by encapsulant 146, i.e., in accordance with Figure 3d. The substrate 140 is of sufficient size to accommodate a plurality of semiconductor dies 124 arranged in rows and columns across the substrate.

A conventional layout of substrate 140 would suggest that a maximum number of semiconductor dies 124 should be placed on substrate 140, i.e., all available substrate space should be utilized. The layout of the semiconductor die should use all of the available space of the substrate to achieve the maximum die throughput for each substrate. However, in order to reduce the warpage of the reconstructed wafer 144, certain regions of the substrate 140 are reduced by the semiconductor die 124 to leave an open space, i.e., no preset and selected semiconductor die 124 are mounted to the substrate 140. Area. In the case of FIG. 5a, no semiconductor die 124 is mounted to the central region 147 of the substrate 140. In other words, although the central region 147 can originally accommodate at least one semiconductor die 124, the central region of the substrate 140 is free of the possible semiconductor die 124. 5b shows a cross-sectional view of the reconstructed wafer 144 taken along line 5b-5b of FIG. 5a with no semiconductor die 124 mounted to the central region 147 of the substrate 140.

In another embodiment, FIG. 6a shows a plan view of a circular reconstructed wafer 144 prior to removal of the substrate 140, wherein the semiconductor die 124 is mounted to the foil layer 142 and the substrate 140 and is sealed by the encapsulant 146. cover. In order to reduce warpage of the reconstructed wafer 144 after removal of the substrate 140, the central region 148 is reduced by the semiconductor die 124 to leave an open space, i.e., no semiconductor die 124 is mounted to the central region 148 of the substrate 140. . Although the central region 148 may otherwise accommodate a plurality of semiconductor dies 124 in one or more portions of the columns and rows of available space, the central region of the substrate 140 is devoid of those possible semiconductor dies 124. In particular, as shown in Figure 6a, the region 148 without the semiconductor die 124 has a "+" shape. 6b shows a cross-sectional view of the reconstructed wafer 144 taken along line 6b-6b of FIG. 6a with no semiconductor die 124 mounted in the central region 148 of the substrate 140.

In another embodiment, FIG. 7a shows a plan view of a circular reconstructed wafer 144 prior to removal of the substrate 140, wherein the semiconductor die 124 is mounted to the foil layer 142 and the substrate 140 and is sealed by the encapsulant 146. cover. To reduce warpage of the reconstructed wafer 144 after removal of the substrate 140, the region 150 is reduced by the semiconductor die 124 to leave an open space, i.e., no semiconductor die 124 is mounted to the region 150 of the substrate 140. Although region 150 may otherwise accommodate multiple semiconductor dies 124 in the available space of columns and rows of one or more portions, region 150 of substrate 140 does not have those possible semiconductor dies 124. In particular, as shown in FIG. 7a, the region 150 without the semiconductor die 124 includes a central region of the substrate 140 and a trench location within the column and row of semiconductor die 124. For example, the leftmost row of semiconductor dies 124 in substrate 140 does not have an open position. The leftmost second row of semiconductor dies 124 in substrate 140 has an open gap position between the upper two semiconductor dies 124 and the lower two semiconductor dies 124. The leftmost third row of semiconductor die 124 in substrate 140 has two open cell gap locations. The centerline of semiconductor die 124 in substrate 140 has three open cell gap locations alternating between semiconductor die 124. The rightmost row of semiconductor die 124 in substrate 140 does not have an open position. The second row on the far right of the semiconductor die 124 in the substrate 140 has an open gap position between the upper two semiconductor dies 124 and the lower two semiconductor dies 124. The third line of the rightmost side of the semiconductor die 124 in the substrate 140 has two open cell gap locations. 7b shows a cross-sectional view of the reconstructed wafer 144 taken along line 7b-7b of FIG. 7a with no semiconductor die 124 mounted in region 150 of substrate 140. Figure 7c shows a cross-sectional view of the reconstructed wafer 144 taken along line 7c-7c of Figure 7a with no semiconductor die 124 mounted in region 150 of substrate 140.

The absence of semiconductor die 124 in selected regions 147-148 or 150 of substrate 140 reduces the bending stress in that region of the substrate. The CTE of the semiconductor die 124 on the reconstructed wafer 144 after removal of the substrate 140 and the CTE of the encapsulant 146 by leaving the selected regions 147-148 or 150 of the substrate 140 without the semiconductor die 124 Any mismatched warping effect between them is reduced. In the case of the circular substrate 140, reducing the semiconductor die 124 from the central region 147-148 or region 150 of the substrate 140 has a significant effect on the off-plane deformation. Below the semiconductor die 124 in the central region 147-148 or region 150, the CTE mismatch and the modulus are reduced because the deflection point is removed from the center of the substrate. Any warpage in the peripheral region of the substrate 140 should become dominant after the removal of the substrate. Maintaining the semiconductor die 124 near a perimeter of the substrate 140 helps maintain the rigidity of the structure for ease of processing. Alternatively, non-functional (dummy) dies or other reinforced support members are disposed adjacent a perimeter of substrate 140 for structural rigidity and ease of handling.

The number and location of regions 147-148 or 150 of substrate 140 in which semiconductor die 124 are absent is a function of the size and shape of the substrate. For a circular substrate 140 having a diameter of 305 mm, and given that five to ten semiconductor dies 124 are not present in a "+" shaped region 148, the substrate is moved in a 14 x 14 eWLB package. The warp after the removal was reduced to about -1.4 mm. The reduction in warpage increases the yield of subsequent processes by, for example, the formation of the interconnect structure of Figure 3g, without significant loss of overall throughput, even though the given actual condition is that each substrate 140 is only The same is true for the small semiconductor die 124. The yield loss due to the absence of certain semiconductor grains 124 in the substrate 140 is partially mitigated by the lower failure rate of the semiconductor die during formation of the interconnect structure in subsequent processes. .

Moreover, the absence of semiconductor die 124 in central region 147-148 or region 150 reduces the stiffness of reconstructed wafer 144. Depending on the structure of the device, some of the reconstructed wafers exhibit a sudden change in warpage, for example, directly from -2.0 mm to +2.0 mm. By selectively removing the semiconductor die 124 from the central region 147-148 or region 150, the reconstructed wafer 144 is slack and the warp can be adjusted to an acceptable range.

8 is a plan view showing a rectangular reconstructed wafer 144 prior to removal of the substrate 140, wherein the semiconductor die 124 is mounted to the foil layer 142 and the substrate 140 and is covered by a sealant 146. To reduce warpage of the reconstructed wafer 144 after removal of the substrate 140, the region 152 is reduced by the semiconductor die 124 to leave an open space, i.e., no semiconductor die 124 is mounted to the region 152 of the substrate 140. Although region 152 may otherwise accommodate multiple semiconductor dies 124 in the available space of columns and rows of one or more portions, region 152 of substrate 140 does not have those possible semiconductor dies 124. In particular, as shown in FIG. 8, region 152 without semiconductor die 124 includes a central region of substrate 140 and a gap position within the columns and rows of semiconductor die 124. The leftmost row of semiconductor dies 124 in substrate 140 does not have an open position. The leftmost second row of semiconductor dies 124 in substrate 140 has two open cell gap locations. The leftmost third row of semiconductor dies 124 in substrate 140 has an open cell gap location. The centerline of the semiconductor die 124 in the substrate 140 has three open and coherent gap locations. The rightmost row of semiconductor die 124 in substrate 140 does not have an open position. The second row on the far right of the semiconductor die 124 in the substrate 140 has two open cell gap locations. The third row of the rightmost side of the semiconductor die 124 in the substrate 140 has an open gap position.

9 is a plan view showing another embodiment of a rectangular reconstructed wafer 144 prior to removal of the substrate 140, wherein the semiconductor die 124 is mounted to the foil layer 142 and the substrate 140 and is covered by a sealant 146. To reduce warpage of the reconstructed wafer 144 after removal of the substrate 140, the region 154 is reduced by the semiconductor die 124 to leave an open space, i.e., no semiconductor die 124 is mounted to the region 154 of the substrate 140. Although region 154 may otherwise accommodate multiple semiconductor dies 124 in the available space of columns and rows of one or more portions, region 154 of substrate 140 does not have those possible semiconductor dies 124. In particular, as shown in FIG. 9, region 154 without semiconductor die 124 includes a central region of substrate 140 and a trench location within semiconductor columns 124 of the columns and rows. The leftmost row of semiconductor dies 124 in substrate 140 does not have an open position. The leftmost second row of semiconductor dies 124 in substrate 140 has two open cell gap locations. The leftmost third row of semiconductor die 124 in substrate 140 has two open cell gap locations. The centerline of the semiconductor die 124 in the substrate 140 has an open cell gap location. The rightmost row of semiconductor die 124 in substrate 140 does not have an open position. The second row on the far right of the semiconductor die 124 in the substrate 140 has two open cell gap locations. The third line of the rightmost side of the semiconductor die 124 in the substrate 140 has two open cell gap locations.

10 is a plan view showing another embodiment of a rectangular reconstructed wafer 144 prior to removal of the substrate 140, wherein the semiconductor die 124 is mounted to the foil layer 142 and the substrate 140 and is covered by a sealant 146. To reduce warpage of the reconstructed wafer 144 after removal of the substrate 140, the region 156 is reduced by the semiconductor die 124 to leave an open space, i.e., no semiconductor die 124 is mounted to the region 156 of the substrate 140. Although region 156 may otherwise accommodate multiple semiconductor dies 124 in the available space of columns and rows of one or more portions, region 156 of substrate 140 does not have those possible semiconductor dies 124. In particular, as shown in FIG. 10, the region 156 without the semiconductor die 124 includes a central region of the substrate 140 and a trench location within the column and row of semiconductor die 124.

11 is a plan view showing another embodiment of a rectangular reconstructed wafer 144 prior to removal of the substrate 140, wherein the semiconductor die 124 is mounted to the foil layer 142 and the substrate 140 and is covered by a sealant 146. To reduce warpage of the reconstructed wafer 144 after removal of the substrate 140, the region 158 is reduced by the semiconductor die 124 to leave an open space, i.e., no semiconductor die 124 is mounted to the region 158 of the substrate 140. Although region 158 may otherwise accommodate multiple semiconductor dies 124 in the available space of columns and rows of one or more portions, region 158 of substrate 140 does not have those possible semiconductor dies 124. In particular, as shown in FIG. 11, region 158 without semiconductor die 124 includes a central region of substrate 140 and a trench location within semiconductor columns 124 of the columns and rows.

Figure 12a shows a plan view of a circular reconstructed wafer 144 having a die attach area 200 on a substrate 140. The active semiconductor die 124 and the non-functional dummy semiconductor die 202 are mounted to the foil layer 142 and the substrate 140 in the die attach region 200. Active semiconductor die 124 and dummy semiconductor die 202 are covered by encapsulant 146, i.e., in accordance with Figure 3d. The substrate 140 is of sufficient size to accommodate a plurality of semiconductor dies 124 and dummy semiconductor dies 202 arranged in rows and columns across the substrate. In particular, the active semiconductor die 124 is mounted to the die attach region 200a in an interior region of the substrate 140. The inner die attach region 200a includes a cluster of a plurality of active semiconductor dies 124, such as four or more active semiconductor dies 124 per cluster. Active semiconductor die 124 and/or dummy semiconductor die 202 are also mounted to die attach regions 200b near a perimeter of substrate 140. The peripheral die attach regions 200b are a ring of active semiconductor die 124 and/or dummy semiconductor die 202. For example, one or more active semiconductor die 124 are disposed across a width of the ring. The dummy semiconductor die 202 and/or the dummy semiconductor die 202 are disposed in the die attach region 200c between the die attach regions 200a-200b. Alternatively, active semiconductor die 124 is disposed in die attach region 200b.

In order to reduce warpage of the reconstructed wafer 144, certain regions of the substrate 140 are reduced by the semiconductor die 124 and the dummy semiconductor die 202 to leave an open space 206 that is shown as a solid black region, i.e., without a semiconductor crystal. The particles are disposed in a predetermined and selected region 206 of the substrate 140. In the case of FIG. 12a, no semiconductor die 124 or dummy semiconductor die 202 is disposed in the central region 206 of the substrate 140. In other words, although the central region 206 can originally accommodate one or more semiconductor dies 124 or dummy semiconductor dies 202, the central region 206 of the substrate 140 does not have the possible semiconductor dies. The central region 206 without the semiconductor die 124 or the dummy semiconductor die 202 comprises a "+" shape, such as four solid black locations on each of the sides around a central solid black location. Figure 12b shows a focused view of a region 206 having solid black without semiconductor dies 124 and 202, and die attach regions 200a and 200c having active semiconductor dies 124 and dummy semiconductor dies 202. Figure 12c shows a focused view of die attach regions 200b and 200c having active semiconductor die 124 and dummy semiconductor die 202.

FIG. 13a is a plan view showing a circular reconstructed wafer 144 having a die attach area 210 on a substrate 140. The active semiconductor die 124 and the non-functional dummy semiconductor die 212 are mounted to the foil layer 142 and the substrate 140 in the die attach region 210. Active semiconductor die 124 and dummy semiconductor die 212 are covered by encapsulant 146, i.e., in accordance with Figure 3d. The substrate 140 is of sufficient size to accommodate a plurality of semiconductor dies 124 and dummy semiconductor dies 212 arranged in rows and columns across the substrate. In particular, active semiconductor die 124 is mounted to die attach region 210a in an interior region of substrate 140. The inner die attach regions 210a comprise a plurality of clusters of active semiconductor die 124, such as four or more active semiconductor die 124 per cluster. Active semiconductor die 124 and/or dummy semiconductor die 212 are also mounted to die attach regions 210b near a perimeter of substrate 140. The peripheral die attach regions 210b are a ring of active semiconductor die 124 and/or dummy semiconductor die 212. For example, one or more active semiconductor die 124 and/or dummy semiconductor die 212 are spanning the ring. One width is set. The dummy semiconductor die 212 is disposed in the die attach region 210c between the die attach regions 210a-210b. Alternatively, active semiconductor die 124 is disposed in die attach region 210b.

In order to reduce warpage of the reconstructed wafer 144, certain regions of the substrate 140 are reduced by the semiconductor die 124 and the dummy semiconductor die 212 to leave an open space 216 that is shown as a solid black region, i.e., without a semiconductor crystal. The particles are disposed in a predetermined and selected region 216 of the substrate 140. In the case of Figure 13a, no semiconductor die 124 or dummy semiconductor die 212 is disposed in region 216 of substrate 140. In other words, although region 216 may otherwise accommodate one or more semiconductor dies 124 or dummy semiconductor dies 212, region 216 of substrate 140 does not have the possible semiconductor dies. The region 216 without the semiconductor die 124 or the dummy semiconductor die 212 comprises a checkerboard pattern shown in solid black, wherein the semiconductor die 124 or the dummy semiconductor die 212 are disposed within the checkerboard pattern. Figure 13b shows a solid black without semiconductor die 124 and 212 and a region 216 having semiconductor die 124 or dummy semiconductor die 212 disposed within the checkerboard pattern, and having active semiconductor die 124 and dummy semiconductor A focused view of the die attach regions 210a and 210c of the die 212.

14 is a plan view showing a circular reconstructed wafer 144 having a die attach region 220 on a substrate 140. The active semiconductor die 124 and the non-functional dummy semiconductor die 222 are mounted to the foil layer 142 and the substrate 140 in the die attach region 220. Active semiconductor die 124 and dummy semiconductor die 222 are covered by encapsulant 146, i.e., consistent with Figure 3d. The substrate 140 is of sufficient size to accommodate a plurality of semiconductor dies 124 and dummy semiconductor dies 222 arranged in rows and columns across the substrate. In particular, the active semiconductor die 124 is mounted to the die attach region 220a in an interior region of the substrate 140. The inner die attach regions 220a comprise a plurality of clusters of active semiconductor die 124, such as four or more active semiconductor die 124 per cluster. Active semiconductor die 124 and/or dummy semiconductor die 222 are also mounted to die attach regions 220b near a perimeter of substrate 140. The peripheral die attach regions 220b are a ring of active semiconductor die 124 and/or dummy semiconductor die 222. For example, one or more active semiconductor die 124 and/or dummy semiconductor die 222 are across the ring. One width is set. The dummy semiconductor die 222 is disposed in the die attach region 220c between the die attach regions 220a-220b. Alternatively, active semiconductor die 124 is disposed in die attach region 220b.

In order to reduce warpage of the reconstructed wafer 144, certain regions of the substrate 140 are reduced by the semiconductor die 124 and the dummy semiconductor die 222 to leave an open space 226 that is shown as a solid black region, i.e., without a semiconductor crystal. The particles are disposed in a predetermined and selected region 226 of the substrate 140. In the case of FIG. 14, no semiconductor die 124 or dummy semiconductor die 222 is disposed in region 226 of substrate 140. In other words, although region 226 could otherwise accommodate one or more semiconductor dies 124 or dummy semiconductor dies 222, region 226 of substrate 140 does not have the possible semiconductor dies. The region 226 without the semiconductor die 124 or the dummy semiconductor die 222 includes a checkerboard pattern 226a having a solid black color, wherein the semiconductor die 124 or the dummy semiconductor die 222 are disposed within the checkerboard pattern and have The solid black extends from the checkerboard pattern across the substrate 140 to the diagonal region 226b of the die attach region 220b.

Figure 15a shows a plan view of a circular reconstructed wafer 144 having a die attach area 230 on a substrate 140. The active semiconductor die 124 and the non-functional dummy semiconductor die 232 are mounted to the foil layer 142 and the substrate 140 in the die attach region 230. Active semiconductor die 124 and dummy semiconductor die 232 are covered by encapsulant 146, i.e., consistent with Figure 3d. The substrate 140 is of sufficient size to accommodate a plurality of semiconductor dies 124 and dummy semiconductor dies 232 arranged in rows and columns across the substrate. In particular, active semiconductor die 124 is mounted to die attach region 230a in an interior region of substrate 140. The inner die attach regions 230a comprise a plurality of clusters of active semiconductor die 124, such as four or more active semiconductor die 124 per cluster. Active semiconductor die 124 and/or dummy semiconductor die 232 are also mounted to die attach regions 230b near a perimeter of substrate 140. The peripheral die attach regions 230b are a ring of active semiconductor die 124 and/or dummy semiconductor die 232. For example, one or more active semiconductor die 124 and/or dummy semiconductor die 232 are across the ring. One width is set. The dummy semiconductor die 232 is disposed in the die attach region 230c between the die attach regions 230a-230b. Alternatively, active semiconductor die 124 is disposed in die attach region 230b.

In order to reduce the warpage of the reconstructed wafer 144, certain regions of the substrate 140 are reduced by the semiconductor die 124 and the dummy semiconductor die 232 to leave an open space 236 that is shown as a solid black region, i.e., without a semiconductor crystal. The particles are disposed in a predetermined and selected region 236 of the substrate 140. In the case of FIG. 15a, no semiconductor die 124 or dummy semiconductor die 232 is disposed in region 236 of substrate 140. In other words, although region 236 may otherwise accommodate one or more semiconductor dies 124 or dummy semiconductor dies 232, region 236 of substrate 140 does not have the possible semiconductor dies. Region 236 without semiconductor die 124 or dummy semiconductor die 232 includes a central region 236a having a solid black color and a diagonal region 236b. The diagonal region 236b extends diagonally across the substrate 140 from the central region 236a to the die attach region 230b. Figure 15b shows a central region 236a and a portion of a diagonal region 236b without solid semiconductor dies 124 and 232 having solid black, and a die attach region 230a having active semiconductor die 124 and dummy semiconductor die 232 and A focused view of the 230c.

16 is a plan view showing a circular reconstructed wafer 144 having a die attach area 240 on a substrate 140. Similar to FIG. 15b, active semiconductor die 124 and non-functional dummy semiconductor die are mounted to foil layer 142 and substrate 140 in die attach region 240. The active semiconductor die 124 and the dummy semiconductor die are covered by a sealant 146, i.e., consistent with Figure 3d. The substrate 140 is of sufficient size to accommodate a plurality of semiconductor dies 124 and dummy semiconductor dies arranged in rows and columns across the substrate. In particular, the active semiconductor die 124 is mounted to the die attach region 240a in an interior region of the substrate 140. The inner die attach regions 240a comprise a plurality of clusters of active semiconductor die 124, such as four or more active semiconductor die 124 per cluster. Active semiconductor die 124 and/or dummy semiconductor die are also mounted to die attach regions 240b near a perimeter of substrate 140. The peripheral die attach regions 240b are a ring of active semiconductor die 124 and/or dummy semiconductor die, for example, one or more active semiconductor die 124 and/or dummy semiconductor die across the ring. Width is set. The dummy semiconductor die is disposed in the die attach region 240c between the die attach regions 240a-240b. Alternatively, active semiconductor die 124 is disposed in die attach region 240b.

In order to reduce the warpage of the reconstructed wafer 144, certain regions of the substrate 140 are reduced by the semiconductor die 124 and the dummy semiconductor die to leave an open space 246 that is shown as a solid black region, i.e., without a semiconductor die. It is disposed in the preset and selected area 246 of the substrate 140. In the case of FIG. 16, no semiconductor die 124 or dummy semiconductor die is disposed in region 246 of substrate 140. In other words, although region 246 may otherwise accommodate one or more semiconductor dies 124 or dummy semiconductor dies, region 246 of substrate 140 does not have the possible semiconductor dies. Region 246 without semiconductor die 124 or dummy semiconductor die includes a central region 246a having a solid black and a diagonal region 246b extending from the central region across substrate 140.

17 is a plan view showing a circular reconstructed wafer 144 having a die attach area 250 on a substrate 140. Similar to FIG. 15b, the active semiconductor die 124 and the non-functional dummy semiconductor die are mounted to the foil layer 142 and the substrate 140 in the die attach region 250. The active semiconductor die 124 and the dummy semiconductor die are covered by a sealant 146, i.e., consistent with Figure 3d. The substrate 140 is of sufficient size to accommodate a plurality of semiconductor dies 124 and dummy semiconductor dies arranged in rows and columns across the substrate. In particular, the active semiconductor die 124 is mounted to the die attach region 250a in an interior region of the substrate 140. The inner die attach regions 250a comprise a plurality of clusters of active semiconductor die 124, such as four or more active semiconductor die 124 per cluster. Active semiconductor die 124 and/or dummy semiconductor die are also mounted to die attach regions 250b near a perimeter of substrate 140. The peripheral die attach regions 250b are a ring of active semiconductor die 124 and/or dummy semiconductor die, for example, one or more active semiconductor die 124 and/or dummy semiconductor die across the ring. Width is set. The dummy semiconductor die is disposed in the die attach region 250c between the die attach regions 250a-250b. Alternatively, active semiconductor die 124 is disposed in die attach region 250b.

In order to reduce the warpage of the reconstructed wafer 144, certain regions of the substrate 140 are reduced by the semiconductor die 124 and the dummy semiconductor die to leave an open space 256 that is shown as a solid black region, i.e., without a semiconductor die. It is disposed in the preset and selected area 256 of the substrate 140. In the case of FIG. 17, no semiconductor die 124 or dummy semiconductor die is disposed in region 256 of substrate 140. In other words, although region 256 could originally accommodate one or more semiconductor dies 124 or dummy semiconductor dies, region 256 of substrate 140 does not have the possible semiconductor dies. The region 256 without the semiconductor die 124 or the dummy semiconductor die includes a central region 256a having a solid black and a diagonal region 256b extending across the substrate 140.

FIG. 18 is a plan view showing a circular reconstructed wafer 144 having a die attach region 260 on a substrate 140. The active semiconductor die 124 and the non-functional dummy semiconductor die are mounted to the foil layer 142 and the substrate 140 in the die attach region 260. The active semiconductor die 124 and the dummy semiconductor die are covered by a sealant 146, i.e., consistent with Figure 3d. The substrate 140 is of sufficient size to accommodate a plurality of semiconductor dies 124 and dummy semiconductor dies arranged in rows and columns across the substrate. In particular, active semiconductor die 124 is mounted to die attach regions 260a in an interior region of substrate 140. The inner die attach regions 260a comprise a plurality of clusters of active semiconductor die 124, such as four or more active semiconductor die 124 per cluster. Active semiconductor die 124 and/or dummy semiconductor die are also mounted to die attach regions 260b near a perimeter of substrate 140. The peripheral die attach regions 260b are a ring of active semiconductor die 124 and/or dummy semiconductor die, for example, one or more active semiconductor die 124 and/or dummy semiconductor die across the ring. Width is set. The dummy semiconductor die is disposed in the die attach region 260c between the die attach regions 260a-260b. Alternatively, active semiconductor die 124 is disposed in die attach region 260b.

In order to reduce the warpage of the reconstructed wafer 144, certain regions of the substrate 140 are reduced by the semiconductor die 124 and the dummy semiconductor die to leave an open space 266 that is shown as a solid black region, i.e., without a semiconductor die. It is disposed in the preset and selected region 266 of the substrate 140. In the case of Fig. 18, no semiconductor die 124 or dummy semiconductor die is disposed in region 266 of substrate 140. In other words, although region 266 may otherwise accommodate one or more semiconductor dies 124 or dummy semiconductor dies, region 266 of substrate 140 does not have the possible semiconductor dies. The region 266 without the semiconductor die 124 or the dummy semiconductor die includes a central region 266a having a solid black and a straight or diagonal region 266b extending across the substrate 140.

19 is a plan view showing a circular reconstructed wafer 144 having die attach regions 270 on substrate 140. The active semiconductor die 124 and the non-functional dummy semiconductor die are mounted to the foil layer 142 and the substrate 140 in the die attach region 270. The active semiconductor die 124 and the dummy semiconductor die are covered by a sealant 146, i.e., consistent with Figure 3d. The substrate 140 is of sufficient size to accommodate a plurality of semiconductor dies 124 and dummy semiconductor dies arranged in rows and columns across the substrate. In particular, active semiconductor die 124 is mounted to die attach region 270a in an interior region of substrate 140. The inner die attach regions 270a comprise a plurality of clusters of active semiconductor die 124, such as four or more active semiconductor die 124 per cluster. Active semiconductor die 124 and/or dummy semiconductor die are also mounted to die attach regions 270b near a perimeter of substrate 140. The peripheral die attach regions 270b are a ring of active semiconductor die 124 and/or dummy semiconductor die, for example, one or more active semiconductor die 124 are disposed across a width of the ring. The dummy semiconductor die and/or dummy semiconductor die are disposed in die attach regions 270c between die attach regions 270a-270b. Alternatively, active semiconductor die 124 is disposed in die attach region 270b.

In order to reduce the warpage of the reconstructed wafer 144, certain regions of the substrate 140 are reduced by the semiconductor die 124 and the dummy semiconductor die to leave an open space 276 that is shown as a solid black region, i.e., without a semiconductor die. It is disposed in a preset and selected area of the substrate 140. In the case of FIG. 19, no semiconductor die 124 or dummy semiconductor die is disposed in region 276 of substrate 140. In other words, although region 276 could otherwise accommodate one or more semiconductor dies 124 or dummy semiconductor dies, region 276 of substrate 140 does not have the possible semiconductor dies. Region 276 without semiconductor die 124 or dummy semiconductor die includes a central region 276a and a plurality of linear or diagonal regions 276b extending across substrate 140 to die attach region 270b.

The absence of semiconductor die 124 in selected regions 152-158, 206, 216, 226, 236, 246, 256, 266, and 276 of substrate 140 in Figures 8-19 reduces bending in this region of the substrate stress. By leaving the selected regions 152-158, 206, 216, 226, 236, 246, 256, 266, and 276 of the substrate 140 without the semiconductor die 124, the reconstructed wafer 144 after removal of the substrate 140 Any mismatched warping effect between the CTE of the semiconductor die 124 and the CTE of the encapsulant 146 is reduced. In the case of a rectangular substrate 140, reducing the semiconductor die 124 from the regions 152-158, 206, 216, 226, 236, 246, 256, 266, and 276 of the substrate 140 has a significant effect on the off-plane deformation. In the regions 152-158, 206, 216, 226, 236, 246, 256, 266, and 276, there is no semiconductor die 124 underneath, the CTE is mismatched, and the modulus is reduced because the deflection point is from the center of the substrate. Was removed. Any warpage in the peripheral region of the substrate 140 should become dominant after the removal of the substrate. Maintaining the semiconductor die 124 near a perimeter of the substrate 140 helps maintain the rigidity of the structure to facilitate processing of the process.

The reduction in warpage increases the yield of subsequent processes by, for example, the formation of the interconnect structure of Figure 3g, without significant loss of overall throughput, even though the given actual condition is that each substrate 140 is only The same is true for the small semiconductor die 124. The yield loss due to the absence of certain semiconductor grains 124 in the substrate 140 is partially mitigated by the lower failure rate of the semiconductor die during formation of the interconnect structure in subsequent processes. .

Moreover, the absence of semiconductor die 124 in regions 152-158, 206, 216, 226, 236, 246, 256, 266, and 276 reduces the stiffness of reconstructed wafer 144. Depending on the structure of the device, some of the reconstructed wafers exhibit a sudden change in warpage, for example, directly from -2.0 mm to +2.0 mm. By selectively removing the semiconductor die 124 from regions 152-158, 206, 216, 226, 236, 246, 256, 266, and 276, the reconstructed wafer 144 is relaxed and the warp can be adjusted to The scope of acceptance.

Returning to FIG. 3g and also after removal of substrate 140, a stacked interconnect structure 280 is formed over semiconductor die 124 and encapsulant 146. The stacked interconnect structure 280 includes a conductive layer or redistribution layer (RDL) 282 that is formed using a patterning and metal deposition process such as sputtering, electrolytic plating, or electroless plating. Conductive layer 282 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. A portion of the conductive layer 282 is electrically connected to the conductive layer 132. Other portions of conductive layer 282 may be electrically or electrically isolated depending on the design and function of semiconductor die 124.

An insulating or passivation layer 284 is formed around and between the conductive layer 282 by PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 284 comprises one or more layers of cerium oxide (SiO2), cerium nitride (Si3N4), cerium oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or the like. Materials that are similar in nature to insulation and structure. A portion of insulating layer 284 is removed by an etch process or laser directed ablation (LDA) to expose conductive layer 282.

A conductive bump material is deposited over conductive layer 282 by a vapor deposition, electrolytic plating, electroless plating, ball dropping, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof with an optional fluxing solvent. For example, the bump material can be eutectic Sn/Pb, high lead solder, or lead free solder. The bump material is bonded to conductive layer 282 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a ball or bump 286. In some applications, bumps 286 are reflowed a second time to improve electrical contact to conductive layer 282. In one embodiment, bumps 286 are formed over a sub-bump metallization (UBM) layer. The bumps 286 can also be compression bonded or thermocompression bonded to the conductive layer 282. Bumps 286 represent a type of interconnect structure that can be formed over conductive layer 282. The interconnect structure can also use bond wires, conductive pastes, stud bumps, microbumps, or other electrical interconnects.

In FIG. 3h, semiconductor die 124 is singulated into individual eWLBs 290 by a saw blade or laser cutting tool 288 through sealant 146. Figure 4 is a graph showing eWLB 290 after singulation. The semiconductor die 124 is electrically connected to the conductive layer 282 and the bumps 286 for external interconnection. The eWLB 290 can be electrically tested before or after singulation. The absence of semiconductor die 124 in selected regions of substrate 140 reduces the bending stress in that region of the substrate. By leaving the selected area of the substrate 140 without the semiconductor die 124, any CTE between the CTE of the semiconductor die 124 on the reconstructed wafer 144 after removal of the substrate 140 and the CTE of the encapsulant 146 The matching warping effect is reduced. The reduction in warpage increases the yield of subsequent processes by using standard semiconductor processing tools without significant loss of overall throughput, even though the actual situation is that there are fewer semiconductor crystals per substrate 140. The same is true for the pellet 124.

Although one or more embodiments of the present invention have been described in detail, those skilled in the art will recognize that modifications and adaptations to those embodiments can be made without departing from the scope as set forth in the following claims. This is done within the scope of the invention.

Claims (15)

 A method of fabricating a semiconductor device, comprising: providing a substrate comprising a plurality of die attach locations arranged in rows and columns across the substrate, each die attach location having a predetermined uniformity a region; a plurality of active semiconductor dies are disposed over a first number of die attach locations on the substrate; and a plurality of non-displacement locations are disposed over a second number of die attach locations on the substrate The functional semiconductor die, while leaving a third number of die attach locations on the substrate without the active semiconductor die and the non-functional semiconductor die.    The method of claim 1, wherein the third number of die attachment locations are disposed on the substrate in a checkerboard pattern.    The method of claim 1, wherein the third number of die attachment locations are disposed in a straight or diagonal region of the substrate.    The method of claim 1, wherein the substrate comprises a circular shape or a rectangular shape.    The method of claim 1 further comprising depositing a sealant over the active semiconductor die, the non-functional semiconductor die, and the substrate.    A method of fabricating a semiconductor device, comprising: providing a substrate comprising a plurality of die attach locations; and providing a plurality of semiconductor dies over a first number of die attach locations on the substrate A second number of die attachment locations left on the substrate are open and unoccupied, respectively.    The method of claim 6, wherein the second number of die attachment locations are disposed on the substrate in a checkerboard pattern.    The method of claim 6 wherein the second number of die attachment locations are disposed in a straight or diagonal region of the substrate.    The method of claim 6 further comprising depositing a sealant over the semiconductor die and the substrate.    The method of claim 6, wherein the semiconductor dies comprise a plurality of active semiconductor dies disposed over the first number of die attachment locations on the substrate, and a plurality of semiconductor dies are disposed A third number of die attach locations on the substrate are non-functional semiconductor grains above the location.    A semiconductor device comprising: a substrate comprising a plurality of die attach locations; a plurality of active semiconductor die disposed over a first number of die attach locations on the substrate And a plurality of non-functional semiconductor dies disposed over a second number of die attach locations on the substrate leaving a third number of die attaches on the substrate The position is absent from the active semiconductor die and the non-functional semiconductor die.    The semiconductor device of claim 11, wherein the third number of die attachment locations are disposed on the substrate in a checkerboard pattern.    The semiconductor device of claim 11, wherein the third number of die attach locations are disposed in a straight or diagonal region of the substrate.    The semiconductor device of claim 11, wherein the substrate comprises a circular shape or a rectangular shape.    The semiconductor device of claim 11, further comprising a sealant deposited on the active semiconductor die, the non-functional semiconductor die, and the substrate.