TW201834278A - Fbar devices including highly crystalline metal nitride films - Google Patents

Abstract

Methods and devices are described that use highly crystalline III-Nitride materials to improve the performance of a film bulk acoustic resonator (FBAR). The III-Nitride materials can be epitaxially grown on a substrate having an appropriate lattice structure. These highly crystalline materials can be used with FBARs that use, for example, air gaps or Bragg reflectors for acoustic isolation. The resulting FBAR exhibits a high Q value that provides for improved bandwidth performance.

Description

 FBAR device containing highly crystalline metal nitride film  

The present invention relates to a film bulk acoustic resonator device. More particularly, the present invention relates to a film bulk acoustic resonator device comprising a highly crystalline metal nitride film.

In the field of electronic communication and power management, solid state devices including, for example, transistors and capacitors are used to implement a wide variety of components. For example, these solid state devices can be formed on integrated circuits and used in radio frequency (RF) communication applications, such as RF front end applications. Thin film bulk acoustic resonators (FBARs) provide RF filters that enable narrow bandwidth discrimination and minimize insertion loss. A typical RF front-end technology using second-generation (2G), third-generation (3G), fourth-generation (4G), and long-range evolution (LTE) wireless standards uses multiple RF filters, each with one or more Multi-composed FBAR.

102‧‧‧Base

104‧‧‧ Air gap

106‧‧‧Piezo III-N layer

108‧‧‧electrode layer

110‧‧‧electrode layer

112‧‧‧ Conductive layer

152‧‧‧ Conductive layer

154‧‧‧ points

200‧‧‧ structure

202‧‧‧body base

204‧‧‧Sonic isolation zone

300‧‧‧ device

1000‧‧‧Computation System

Figure 1 shows an embodiment of an FBAR device.

Figure 2 shows an embodiment of an epitaxial layer grown on a substrate.

Figure 3 shows an embodiment of a conductive layer formed on the embodiment of Figure 2.

Figure 4 shows an embodiment of an acoustic isolation region.

Figure 5 shows the embodiment of Figure 3 located in the acoustic isolation region to be joined to Figure 5.

Figure 6 shows an embodiment of a device formed by joining the devices of Figures 4 and 5.

Figure 7 shows an embodiment of the apparatus of Figure 6 after removal of the substrate layer.

Figure 8 shows an embodiment comprising a conductive layer formed on top of the epitaxial layer of the embodiment shown in Figure 7.

Figure 9 shows an embodiment of an FBAR device containing air pockets in an acoustic isolation zone.

Figure 10 shows another embodiment of an FBAR device that includes air pockets in the acoustic isolation region.

Figure 11 shows a process embodiment in which an acoustic isolation region is formed in the crucible substrate of the FBAR device.

Figure 12 shows a process embodiment in which an acoustic isolation region is formed in the substrate and conductive layer of the FBAR device.

Figure 13 shows a process embodiment of a FBAR device in which an acoustic isolation region is formed in an intermediate layer between the substrate and the piezoelectric layer of the FBAR device.

Figure 14 shows a process embodiment of a FBAR device in which selectively etchable material is removed from a hole in the substrate to form an acoustic isolation region.

Figure 15 shows a process embodiment in which an acoustic isolation region is formed in a layer adhered to the piezoelectric layer.

16 shows a computing system in accordance with an embodiment of the present disclosure implemented by an integrated circuit structure or device formed using the techniques disclosed herein.

These and other features of the embodiments of the present invention will be better understood from the description of the appended claims. In the drawings, identical or nearly identical components shown in different figures may be represented by like reference numerals. For the sake of brevity, not every component will be labeled in every figure. In addition, as the following will be understood, the drawings are not necessarily to scale. For example, while some of the figures generally show straight lines, right angles, and smooth surfaces, the actual implementation of the disclosed techniques may have less perfect straight and right angles, and certain features may have surface extensions or non-smoothness. The real world limit of a given process. In short, the graphics are only used to show the structure of the illustration.

 SUMMARY OF THE INVENTION AND EMBODIMENT  

A fabrication technique for an integrated circuit comprising one or more film bulk acoustic resonator (FBAR) devices is disclosed. According to some embodiments, a given FBAR device comprises a height of epitaxial piezoelectric material such as aluminum nitride (AlN), gallium nitride (GaN), and any or a combination of these and other III-N semiconductor materials. Crystal structure. According to certain embodiments, the formation of an epitaxial layer via an epitaxial deposition process allows for precise control of film crystallinity and thickness. For example, the epitaxial layer exhibits an XRD FWHM of less than 0.5 degrees compared to a sputtered III-N semiconductor material typically having an XRD FWHM of 1 to 4 degrees. Many of the FBAR embodiments disclosed herein can provide RF filters that achieve superior performance in a wide variety of communication devices. These devices include devices that receive or transmit RF signals, such as mobile phones, computers, vehicles, aircraft, and radio. In one aspect, the disclosed resonators provide a more enhanced performance using highly crystalline epitaxial films than FBARs using polycrystalline materials such as those formed using sputtering techniques. For example, these improvements include increased bandwidth, lower insertion loss, and higher Q values. Numerous configurations and variations will be apparent in light of this disclosure.

 Overview  

Thin film bulk acoustic resonators (FBARs) have been used in RF filters and offer advantages over surface acoustic wave (SAW) filters. These advantages include reduced interference from nearby radio bands and reduced insertion loss. It is most effective when the RF filter passes the selected frequency band and reduces or eliminates the passage of adjacent unnecessary frequencies. This results in high signal strength and minimal interference, which increases communication and reduces power requirements. The Group III nitride (III-N) FBAR devices currently in use rely on III-N materials that cause sputtering of polycrystalline layers containing high concentrations of crystal defects. The sputtered layer also exhibited inconsistent thicknesses and thicker surfaces. The methods disclosed herein use higher crystallity III-N materials, even single crystal materials, to provide a low defect, highly crystalline piezoelectric layer, resulting in RF that allows more useful energy to pass through and minimizes lower energy losses. filter. This results in a higher Q value, providing for example longer battery life and more receiving strips. In one set of embodiments, these highly crystalline III-N materials are formed on a suitable substrate by epitaxial growth, such as a 300 mm germanium wafer.

The piezoelectric layer can be used in a wide variety of FBAR architectures, including those with air gaps, stacked crystal filters, and coupled co-filter filters. For example, the FBAR topologies of different embodiments include trapezoidal, bridge, and hybrid types. In some cases, the use of the techniques disclosed herein can result in a III-N semiconductor structure, including a higher quality piezoelectric layer that provides higher electromechanical coupling and Q factor RF devices. Considering the above, it will be appreciated that these improvements will then increase the bandwidth, reduce the signal loss, and increase the ability of the main RF filter to reject signals outside the band. In some cases, FBAR devices fabricated via the disclosed techniques can be used, inter alia, with second generation (2G), third generation (3G), fourth generation (4G), fifth generation (5G), or long range evolution. RF filters and other RF devices in any or a combination of (LTE) wireless standards. In some cases, the use of these devices can achieve lower loss and higher signal integrity, and the primary wireless communication platform can benefit from this.

In accordance with certain embodiments, the various configurations provided herein can be configured for use in, for example, RF front-end modules in computing devices, mobile devices, and the like, as well as in a wide variety of communication systems, but review the description. Various other applications will be apparent. According to certain embodiments, the various configurations provided herein may be configured for use in, for example, a base station, a cellular communication tower, and the like. X-ray diffraction (XRD), scanning electron microscopy (SEM), penetration of a given IC or other semiconductor structure having a plurality of resonators configured as diversely illustrated herein, in accordance with certain embodiments. Any combination or combination of electron microscopy (TEM), chemical composition analysis, X-ray energy dispersive analyzer (EDX), electrical characteristics, and secondary ion mass spectrometry (SIMS) can detect the use of the disclosed techniques and devices. As used herein, the highly crystalline III-N material is a III-N material that exhibits an XRD FWHM of less than 1.0 degrees.

 Architecture and methodology  

1 provides a cross-sectional view of an embodiment of an FBAR device fabricated using one or more of the methods disclosed herein. The semiconductor substrate 102 includes an acoustic isolation region 204, as shown, the acoustic isolation region 204 includes an air gap 104 that is etched or otherwise formed in the substrate. The upper surface of the substrate 102 and the air gap 104 are covered by the electrode layer 108, which is a conductive material such as metal. The second electrode layer 110 may have the same material as the electrode layer 108. The highly crystalline piezoelectric III-N layer 106 is between the second electrode layer 110 and the electrode layer 108, but another conductive layer, the layer 112 is between the highly crystalline piezoelectric material 106 and the electrode layer 108. As can be clearly seen in the description below, the conductive layer 112 can have the same or a different material than the electrode 108.

As shown, Figures 2-9 illustrate the process flow for various embodiments of forming FBARs in accordance with the present disclosure. For example, in accordance with certain embodiments, this process flow can be used to fabricate an integrated circuit comprising one or more FBAR devices including one or more highly crystalline piezoelectric III-N semiconductor materials. For example, these III-N materials include epitaxially grown gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN). , aluminum indium nitride (AlInN), and aluminum indium gallium nitride (AlInGaN). In various embodiments, for example, the epitaxially grown III-N material exhibits an XRD FWHM of less than 3 degrees, less than 2 degrees, less than 1 degree, less than 0.5 degrees, less than 0.4 degrees.

The process begins in Figure 2, which shows a cross-sectional view of an embodiment of an epitaxial layer 106 of AlN grown on a crystalline donor substrate 202. Different embodiments include any other III-N materials and combinations thereof. The crystalline substrate 202 can be a donor substrate selected for its crystal lattice and can be, for example, tantalum or tantalum carbide. Different crystal faces can be used as the surface for growth, and include, for example, the [111], [100] or [110] direction. In the illustrated embodiment, a highly crystalline layer of aluminum nitride is epitaxially grown on a ruthenium [111] substrate. It will be apparent from consideration of this disclosure that the III-N semiconductor layer 106 can be formed by any suitable standard, customized, or proprietary technique. The process can be any method that results in a highly crystalline (less than 1.0 degree FWHM) semiconductor layer. These processes include processes for growing highly crystalline materials via epitaxial growth and deposition methods. For example, epitaxial growth and deposition methods include chemical vapor deposition (CVD) such as metal organic CVD (MOCVD), molecular beam epitaxy. (MBE), atomic layer deposition (ALD), or a combination thereof. In many embodiments, the highly crystalline III-N layer 106 is a piezoelectric material and exhibits a wurtzite crystalline structure. The thickness (z) of the highly crystalline layer 106 can be controlled to any thickness suitable for the final device, for example between 0.3 and 6.0 μm, between 0.5 and 5.0 μm, between 1.0 and 4.0 μm. In the same and other embodiments, the thickness may be less than 5.0 μm, less than 4.0 μm, less than 3.0 μm, or less than 2.0 μm. In the same or other embodiments, the thickness may be greater than 0.1 μm, greater than 0.3 μm, greater than 0.5 μm, or greater than 1.0 μm. Compared to sputtered III-N materials, highly crystalline materials have a smoother surface, less tissue and typically do not require polishing or planarization prior to IC fabrication.

The process continues in FIG. 3, which shows conductive electrode layer 112 formed on highly crystalline AlN layer 106. Electrode layer 112 includes any of a wide range of electrically conductive materials. For example, in some cases, electrode layer 112 includes any or any combination of electrically conductive refractory materials including oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO), such as tungsten. (W), metals such as molybdenum (Mo) and titanium (Ti), and nitrides such as tantalum nitride (TaN), titanium nitride (TiN), or any alloy thereof, and the above are only some of the materials listed. In some cases, electrode layer 112 comprises a dopant.

As will be apparent upon consideration of this disclosure, electrode layer 112 can be formed via any suitable standard, custom, or proprietary technique. According to certain embodiments, any or any combination of physical vapor deposition (PVD) processes (eg, sputtering), chemical vapor deposition (CVD) processes, and atomic layer deposition (ALD) processes may be formed. Electrode layer 112. The size of the electrode layer 112 (e.g., the z-thickness in the z-direction) can be customized according to the needs of a given target application or terminal use. In some cases, electrode layer 112 can have a range of about 200 nm or less (eg, about 150 nm or less, about 100 nm or less, about 50 nm or less, or about 200 or less). The z thickness of any other subrange in the range). In other embodiments, electrode layer 112 can have a z-thickness of, for example, 50 to 300 nm, 100 to 250 nm, or 100 to 200 nm. Other suitable materials, forming techniques, and dimensions for electrode layer 112 will depend on the particular application and will be apparent upon consideration of the present disclosure.

As seen in Figure 4, device 300 includes a semiconductor substrate 102 having any of a wide range of configurations. For example, the semiconductor substrate 102 can be configured as a bulk semiconductor substrate, a germanium-on-insulator (SOI) structure, or other semiconductor-on-insulator structure (XOI, where X represents a semiconductor material, such as germanium, germanium, germanium-rich germanium). , or the like, any one or combination of semiconductor wafers, and multilayer semiconductor structures. In some cases, the semiconductor substrate 102 can be configured as a structure on a sapphire (SOS).

Semiconductor substrate 102 includes any of a wide range of semiconductor materials. For example, in some cases, semiconductor substrate 102 includes any one or combination of Group IV semiconductor materials such as germanium (Si), germanium (Ge), or germanium (SiGe). In some cases, semiconductor substrate 102 includes Si having a [111], [110], or [100] crystal orientation, optionally having a 1-10° (eg, about 1-4°, about 4-7) The edge toward [110] in the range of °, about 7-10°, or any other subrange in the range of about 1-10°. In some other instances, semiconductor substrate 102 includes any one or combination of III-V compound semiconductor materials, particularly such as gallium arsenide (GaAs) or indium phosphide (InP). In still other cases, the semiconductor substrate 102 comprises tantalum carbide (SiC) or sapphire (a-Al ₂ O ₃ ). As described herein, in certain instances, the particular material composition of the semiconductor substrate 102 can be selected based, at least in part, on a target resistivity range suitable for one or more resonator devices formed thereon. In some cases, the semiconductor substrate 102 has a thickness of about 1,000 ohms. A resistivity of cm or greater (e.g., about 1,200 Ω.cm or more, about 1,500 Ω.cm or more, etc.).

It should be appreciated that the semiconductor substrate 102 is not limited to the configuration and implementation of a substrate as a given primary architecture. According to certain other embodiments, the semiconductor substrate 102 can be configured or implemented as an intermediate layer disposed in a given primary architecture. . Other suitable materials, configurations, and resistivity ranges. Other suitable materials, configurations, and resistivities for the semiconductor substrate 102 will depend on the given application and will be apparent upon consideration of the present disclosure.

Apparatus 300 includes one or more acoustic isolation regions 204. According to an embodiment illustrated in FIG. 4, acoustic isolation region 204 includes a dielectric Bragg reflector 132, a metal Bragg reflector 134, a dielectric Bragg reflector 136, And a metal Bragg reflector 138. Any suitable acoustic isolation region can be used, including, for example, separate pockets, stacked crystals, coupled resonators, and reflectors including Bragg reflectors. As shown, device 300 includes two pairs of metal/dielectric Bragg reflectors. In various embodiments, one, two, three or more pairs of reflectors can be used. The reflector provides acoustic isolation of the FBAR from the substrate by creating boundary conditions that result in constructive and destructive dry shots. In many cases, metal and dielectric materials have a large proportion of separate acoustic impedance. For example, the ratio can be greater than 5:1, 10:1, or 20:1. In some embodiments, the reflector can withstand high temperatures, exhibit low interfacial roughness, and exhibit good adhesion. In one set of embodiments, the metal/dielectric Bragg reflector is tungsten and yttrium oxide (W/SiO ₂ ) which has been found to provide a broad useful reflection band. Other materials may be used for the Bragg reflector, for example, including Al, Ti, Au, Mo, Nb, Ni, Pt, Ta, W, SiO ₂ , AlN, HfO ₂ , MgO, TiO ₂ and Si ₃ N ₄ .

In some embodiments, Bragg reflectors 132, 134, 136, and 138 are formed using thin film deposition techniques. For example, these techniques include physical vapor deposition (PVD) (eg, sputtering) and chemical vapor deposition (CVD). In some embodiments, the Bragg reflector can be a quarter wave layer, and in other embodiments, the layers can be formed with a predetermined nominal thickness selected to provide acoustic isolation at the selected wavelength. The electrode layer 108 includes a conductive material such as a metal or an oxide, and is the same or different material as the material of the electrode layer 112 described above. It does not need to have a composition and size similar to that of the electrode layer 112. It can also be fabricated using the same technique as described above for the electrode layer 112.

In FIG. 5, donor substrate 202, AlN layer 106, and electrode layer 112 are flipped in preparation for mating with device 300. The donor substrate 202 is selectively removed prior to pairing with the device 300. The substrate can be removed via grinding or etching, and any remaining portions left behind can be selectively etched. For example, in accordance with certain embodiments, if the donor substrate 202 is a tantalum-on-insulator (SOI) or Si substrate on a sapphire (SOS) substrate, then when the Si material is removed from the epitaxial AlN 106, An etchant comprising potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) ((CH ₃ ) ₄ NOH) can be used. For example, the surface of the exposed electrode layer 112 can be modified using chemical mechanical planarization (CMP) techniques to remove defects.

In some embodiments, a highly crystalline epitaxial layer 106 can be bonded to device 300 as shown in FIGS. 6A and 6B. As described above, the donor substrate 202 can be removed before or after bonding the electrode layer 112 to the electrode layer 108. One or both of layers 112 and 108 are cleaned and/or planarized prior to bonding using, for example, solvent or CMP. Recall that layers 112 and 108 comprise the same or different electrically conductive materials and can be, for example, metals or oxides. In various embodiments, the electrode layers can have the same or different shapes in the xy plane. The exposed surfaces of layers 112 and 108 in Figure 6A are brought together and bonded via, for example, van der Waals. In some embodiments, such as shown in Figure 6B, steps can be taken to further secure the layers together. For example, these steps include CVD oxide processing, particularly when layer 108 is an oxide and is not a metal. The embodiment of Figure 6B includes an added layer, oxide layer 116. Layer 116 may be applied after deposition of oxide electrode 108a, which facilitates bonding electrode layer 108a to electrode layer 112. In other embodiments, oxide layer 116 is applied to electrode layer 112 on structure 200 prior to bonding structures 200 and 300. In other embodiments, layer 108 may be the oxide layer itself, which facilitates adhesion of electrode 112 to substrate 102 or a stack of Bragg reflectors 300. In certain embodiments, the material is annealed to promote bonding of adjacent layers. For example, in one embodiment, after the oxide layer 116 is formed, annealing can push SiO ₂ on the surface with wafer free. In some embodiments, layer 112, layer 108, or both can be connected to a conductive trace. In spite of the fact that the donor substrate 202 has not been removed as shown in FIG. 6, in some embodiments, it is removed from the epitaxial layer 106 using, for example, grinding, polishing, and/or etching. Figure 7 shows an embodiment of the device after removal of the donor substrate 202.

As shown in FIG. 8, the embodiment includes an additive electrode layer 114. The electrode layer 114 includes a conductive material such as a metal and a material including the same or different from the electrode layers 112 and 108. Electrode layer 114 can be formed using the methods described herein, including deposition processes, such as chemical and physical deposition techniques. These include, for example, physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes. The electrode layer 114 has the same material as, similar to, or different from the electrode layers 108 and 112. The electrode layer 114 can be refined using a post deposition process. For example, grinding, etching, and planarization techniques can be used to reduce the thickness of the layer and remove surface defects. The electrode layer 114 can be electrically conductively bonded to other components using, for example, conductive traces.

Figure 9 shows an alternate embodiment of an FBAR comprising an independent cavity and not including the Bragg reflector of the embodiment of Figure 8. Unlike the FBAR of Figure 1, the individual holes are not formed in the substrate, but in the conductive layer 152 comprising one or more metals. The composition of the conductive layer 152 may be the same as, but not necessarily the same as, any of the electrode layers 114, 112, and 108. For example, in certain embodiments, it can be a metal such as tungsten or molybdenum. In one set of embodiments, a hole 154 is formed prior to deposition of the electrode layer 108. In a particular embodiment, conductive layer 152 is deposited on substrate 202 using physical or chemical deposition methods. From the conductive layer 152, the holes 154 are selectively etched. The etch includes either dry or wet etch techniques or both, and the etch can be selected to remove portions of conductive layer 152 without attacking substrate 202. As shown, the pockets 154 extend throughout the z-thickness of the layer 152, but in some embodiments, the pockets extend partially through the conductive layer 152. In other embodiments, the pockets 154 are formed by selectively masking or depositing the sacrificial material in the region of the pockets 154. In some embodiments, the electrode layer 108 is formed on the conductive layer 152, after which the sacrificial material is removed to form the pockets 154. Then, for example, layers 112 and 106 are added to the stack using the techniques described above with reference to Figures 6 and 7. In a further embodiment, electrode layer 114 is formed as described above with reference to FIG.

In another set of embodiments, the FBAR of FIG. 10 is formed using a method similar to that of FIG. 9, but without the electrode layer 108. For example, after forming the pockets 154, the electrode layer 112 and the highly crystalline layer 106 (and the optional donor substrate 202) can be bonded directly to the conductive layer 152. For example, the facing surfaces of the conductive layer 152 and the electrode layer 112 are treated by planarization to make them easier to bond. These surfaces are then joined together and adhered via van der Waals or other bonding techniques. In some embodiments, the device is annealed to further ensure adhesion of layers 112 and 152. In a further embodiment, electrode layer 114 is deposited on highly crystalline piezoelectric layer 106 to form a top electrode. The result is an air gap FBAR having a gap formed in a metal or other conductive layer, as opposed to being formed in the substrate as shown in FIG.

Figure 11 shows a process embodiment in which an air gap FBAR is formed by forming an acoustic isolation region 204 directly in the substrate 102. Process 11a includes forming a pocket 154 in substrate 102 using methods such as dry or wet etching. In some cases, the oxide layer 160 is allowed to be naturally formed on the upper surface of the substrate 102. In other cases, oxide layer 160 is deposited on the surface using methods such as CVD. Process 11b includes a structure that adheres substrate 102 to structure 200 similar to that of FIG. 3, and includes a highly crystalline layer 106, a donor substrate 202, and electrodes 108. In the case where the electrode 108 includes a conductive oxide, the oxide layer 160 helps to adhere the structure 200 to the substrate 102. An optional annealing process can drive the formation of SiO ₂ to further adhere the substrate 102 to the electrode 108. The process 11c includes removing the donor layer 202 and the deposited electrode layer 114 to produce an FBAR 1100 that includes an acoustic isolation region 204. Note that in other cases, the donor layer 202 is removed prior to attaching the highly crystalline layer 106 to the substrate 102. Similarly, electrode layer 114 is deposited prior to attaching highly crystalline layer 106 to substrate 102. In various embodiments, the acoustic isolation region 204 is a reflector stack such as a Bragg reflector or an air gap.

Figure 12 shows a process embodiment in which an air gap FBAR is fabricated by forming a pocket 154 in both the substrate 102 and the conductive layer 170. The process begins with structure 1200a, which includes a conductive layer 170 that has been deposited on planar substrate 102. For example, conductive layer 170 is a metal, oxide, or metal layer on an oxide layer, and is deposited by using methods such as CVD or PVD. Process 12a includes forming a pocket in substrate 102 and conductive layer 170 to create structure 1200b. Conductive layer 170 and substrate 102 may be wet or dry etched to create pockets 154. In the process, part of the conductive layer material and part of the base material are removed. In some embodiments, the individual materials in these materials are removed with the same or different etchants and procedures. In the process 12b, a structure including the highly crystalline material 106, the conductive layer 108, and the donor substrate 202 is provided as in the example of FIG. 3 described above. This structure is combined with structure 1200b to create structure 1200c. In various embodiments, conductive layers 108 and 170 are adhered using metal bonding or oxide bonding. In process 12c, for example, donor substrate 202 is removed by etching and depositing a conductive layer on the exposed surface of highly crystalline material 106 (in this case, epitaxial AlN) to fabricate FBAR 1200d.

Figure 13 shows a process embodiment in which the acoustic isolation regions are not formed in the substrate 102 (Si) but are formed in the conductive layer 172, which is a metal such as a metal, oxide or oxide. Conductive layer 172 is deposited or attached to substrate 102 using methods such as CVD or PVD as described herein to form structure 1300a. Process 13a includes forming a pocket 154 in conductive layer 172 to create structure 1300b. The holes 154 may be uniquely in the conductive layer 172 and extend through the thickness of all or a portion of the conductive layer 172. In the illustrated embodiment, the pockets 154 are not expanded into the substrate 102. For example, a wet or dry etch process can be used to form the pockets 154. In the present embodiment, process 13b includes adhering epitaxial AlN layer 106 to structure 1300b to create structure 1300c. Conductive layers 108 and 172 are joined together using, for example, metal-to-metal bonding or oxide bonding to form structure 1300c. Although not the case in all embodiments, as shown, the pockets 154 may be completely surrounded by conductive material such as layer 172 or layer 108. Process 13c includes removing donor substrate 202 and adding electrode layer 114 to produce FBAR 1300d. Note that in other embodiments, acoustic isolation region 204 includes other isolation structures, such as Bragg reflectors.

Figure 14 shows a process embodiment in which a pocket 154 is filled with a selectively etchable material 144. For example, the selectively etchable material 144 is SiO ₂ . This process can be combined with any of the other processes described herein to provide an alternative process for protecting the cavity during manufacture. Material such as Si is removed from the substrate 102 to create a pocket 154. 14a comprises a process, for example a material such as SiO ₂ is selectively etched to fill the hole. For example, SiO ₂ or other selectively etchable materials are deposited using plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or ion beam deposition (IBD). For example, other selectively etchable materials include nitrides including SiN, SiCN, or the like, or amorphous materials such as amorphous germanium, organic polymers, and thermally decomposable polymers.

After the etchable material 144 is deposited in the pockets 154, for example, the upper surface of the substrate 102 and the etchable material 144 are prepared by CMP. Next, in process 14c, a conductive electrode layer 108 is deposited over both the etchable material 144 and the substrate 102. Alternatively, a highly crystalline layer such as an epitaxial AlN layer 106 is adhered to the substrate together with the conductive electrode layer 108 using, for example, an oxide bonding or the like. A cross-section and a plan (bottom) view of the structure 1400d are provided. Looking at the plan view 1400d, the highly crystalline epitaxial material 106 is on top of the conductive electrode 108, and the conductive electrode 108 is then placed on the substrate 102 (Si in this case). Dashed line 154 represents the position of the hole 154 that is now covered by the selectively etchable material 144 (in this case, SiO ₂ ). Release holes 156a and 156b are formed in conductive electrode layer 108 and provide communication with etchable material 144. In some embodiments, a wet or dry etchant is provided and the etchable material is accessed via release apertures 156a and 156b to remove etchable material 144 from pockets 154. Other removal techniques include, for example, vaporization or combustion, depending on the particular etchable material. This removal process can cause the pockets 154 to be depleted or mostly depleted, as well as provide an air gap for the FBAR. An increased conductive electrode layer can be deposited on the highly crystalline material 106 before or after the etchable material 144 is removed.

Figure 15 shows a process embodiment in which the FBAR is constructed by forming an acoustic isolation region on a highly crystalline piezoelectric layer in contrast to other embodiments for forming acoustic isolation regions on substrates such as germanium wafers. Structure 1500a in FIG. 15 includes piezoelectric layer 106 epitaxially grown on donor substrate 202. Conductive layer 108 is deposited as an electrode on piezoelectric layer 106 using methods such as those described herein, including PVD and CVD. The acoustic isolation layer 303 is deposited on the conductive layer 108 and includes, for example, a metal or an insulator. In certain embodiments, layers 303 and 108 are the same material and can be deposited as a single layer. An embodiment similar or identical to structure 1500b is fabricated by etching layer 303 to create pockets 154. Structure 1500b is then rotated 180[deg.] so that cavity 154 faces downward, and structure 1500b is bonded to structure 1500c or the like to create structure 1500d with air gap 154 trapped between layers 108 and 112. The structures 1500b and 1500c are bonded to each other using, for example, metal-to-metal bonding or oxide bonding techniques. Structure 1500e shows the FBAR device with donor substrate 202 removed and replaced by conductive electrode layer 114. In an alternate embodiment, this removal/substitution can occur prior to joining the structures 1500b and 1500c together.

As described herein, a wide variety of constituent layers of IC 100 can have any thickness in a range of widths (eg, z-thickness in the z-direction, x-direction, depending on the desired target application or end-use requirements). The thickness of x, or other specified thickness). In some cases, a given layer can be placed as a single layer on the underlying terrain. For example, in some cases, for a given FBAR device configured as described herein, a given constituent layer may have a substantially uniform thickness on the underlying terrain. In some cases, a given constituent layer can be placed as a substantially conformal layer on the underlying topography. In other cases, a given constituent layer may have a non-uniform or varying thickness on the underlying topography. For example, in some cases, a first portion of a given layer has a thickness in a first range and a second portion has a thickness in a second, different range. In some cases, a given layer can have first and second portions, the first and second portions having an average thickness that differs from each other by about 20% or less, about 15% or less, and about 10%. Or less, or about 5% or less. Numerous configurations and variations will be apparent in light of this disclosure.

Furthermore, as described herein, various constituent layers of the FBAR device can be deposited on one or more other constituent layers. In some cases, the first constituent layer may be directly disposed on the second constituent layer without other layers interposed therebetween. In some other cases, one or more interposer layers may be disposed between the first constituent layer and the lower second constituent layer. More generally, in accordance with certain embodiments, a given constituent layer can be configured to be capped on another given constituent layer, optionally with one or more intervening layers.

 Illustrated system  

16 shows a computing system 1000 implemented in accordance with an exemplary embodiment of an integrated circuit structure or device formed using the techniques disclosed herein. As can be seen, computing system 1000 houses motherboard 1002. The motherboard 1002 includes a plurality of components including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which is physically and electrically coupled to the motherboard 1002, or integrated therein. As will be appreciated, for example, whether it is a motherboard, a daughter board on a motherboard, or a unique board of system 1000, etc., motherboard 1002 can be any printed circuit board. Depending on its application, computing system 1000 includes one or more other components that are physically and electrically coupled or uncoupled to motherboard 1002. These other components include, but are not limited to, electrical memory (eg, DRAM), non-electrical memory (eg, ROM), graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, Touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and a large number Storage devices (such as hard drives, compact discs (CDs), digital multi-format discs (DVDs), etc.). Any of the components included in computing system 1000 can include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with the illustrated embodiments. In some embodiments, numerous functions may be integrated into one or more of the wafers (e.g., communication chip 1006 may be part of or integrated into processor 1004).

Communication chip 1006 is capable of wireless communication for communicating data with computing system 1000. The term "wireless" and its derivatives are used to describe circuits, devices, systems, methods, techniques, communication channels, and the like that transmit data via the use of modulated electromagnetic radiation through a non-solid medium. The term does not mean that the associated devices do not contain any wiring, however, in some embodiments they may not contain any wiring. The communication chip 1006 can implement any wireless standard or communication protocol, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Range Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless communication protocols marked with 3G, 4G, 5G, and newer generations. Computing system 1000 includes a plurality of communication chips 1006. For example, the first communication chip 1006 can be dedicated to a shorter range of wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip 1006 can be dedicated to a longer range of wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and so on.

Processor 1004 of computing system 1000 includes integrated circuit dies that are packaged within processor 1004. In some embodiments, the integrated circuit die of the processor includes on-board circuitry implemented by one or more integrated circuit structures or devices formed using the various techniques disclosed herein. The term "processor" means any device or device that processes, for example, electronic data from a register and/or memory to convert electronic data into other electronic data stored in a register and/or memory. Part.

The communication chip 1006 also includes integrated circuit dies that are packaged within the communication chip 1006. In accordance with certain such illustrated embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the techniques disclosed herein. With the disclosure in mind, it will be appreciated that multi-standard wireless capabilities can be directly integrated into processor 1004 (eg, the functionality of any of the wafers 1006 is integrated into processor 1004, rather than having separate wafers). Additionally, processor 1004 can be a chipset having this wireless capability. In short, any number of processors 1004 and/or communication chips 1006 can be used. Similarly, any wafer or wafer set can have multiple functions integrated therein.

In various implementations, computing system 1000 can be a laptop computer that processes data using one or more integrated circuit structures or devices formed by the various disclosed techniques disclosed herein, and saves power, Notebook, smart phone, tablet, personal digital assistant (PDA), ultra-thin mobile PC, mobile phone, transceiver, desktop computer, server, printer, scanner, monitor, set-top box , entertainment control unit, digital camera, portable music player, digital camera, or any other electronic device.

 Further illustrated embodiment  

The following examples are directed to additional embodiments from which numerous variations and configurations will be apparent.

Example 1 is a film bulk acoustic resonator (FBAR) device comprising a first electrically conductive layer, a second electrically conductive layer, having less than 1.0 degrees of diffraction between the first electrical and second electrically conductive layers by x-rays A highly crystalline piezoelectric layer of crystallinity of FWHM, and an acoustic isolation region separated from the piezoelectric layer by at least a first electrically conductive layer.

Example 2 contains the subject matter of Example 1, wherein the highly crystalline piezoelectric layer comprises a III-nitride material.

Example 3 includes the subject matter of Example 1 or 2, wherein the highly crystalline piezoelectric layer comprises at least one material selected from the group consisting of AlN, GaN, and InN.

Example 4 comprises the subject matter of any of the preceding examples, wherein the highly crystalline piezoelectric layer comprises AlN.

Example 5 comprises the subject matter of any of the preceding examples, wherein the highly crystalline piezoelectric layer has an XRD FWHM peak of less than 0.5 degrees.

Example 6 comprises the subject matter of any of the preceding examples, wherein the highly crystalline piezoelectric layer has an XRD FWHM peak of less than 0.4 degrees.

Example 7 comprises the subject matter of any of the preceding examples, wherein the highly crystalline piezoelectric layer comprises a single crystal.

Example 8 comprises the subject matter of any of the preceding examples, wherein the highly crystalline piezoelectric layer is formed by epitaxial growth.

Example 9 includes the subject matter of any of the preceding examples, wherein at least one of the first and second electrically conductive layers comprises a metal.

Example 10 comprises the subject matter of any of the preceding examples, further comprising a bulk germanium substrate.

Example 11 includes the subject matter of any of the preceding examples, wherein the acoustic isolation region comprises an air gap or a Bragg reflector.

Example 12 includes the subject matter of any of the preceding examples, wherein the acoustic isolation region comprises a plurality of Bragg reflectors.

Example 13 includes the subject matter of any of the preceding examples, wherein the acoustic isolation region is defined by a conductive layer.

Example 14 comprises the subject matter of any of the preceding examples, wherein the highly crystalline piezoelectric layer exhibits a wurtzite structure.

Example 15 includes the subject matter of any of the preceding examples, wherein the acoustic isolation region is defined by a non-conductive layer.

Example 16 includes the subject matter of any of the preceding examples, wherein the acoustic isolation region is defined by at least two layers comprising an electrode layer and a substrate layer.

Example 17 includes the subject matter of any of the preceding examples, comprising a third electrically conductive layer in contact with the crucible substrate, wherein the third electrically conductive layer defines an air gap.

Example 18 is a radio frequency (RF) filter device comprising the film bulk acoustic resonator device of any of the foregoing examples.

Example 19 is a computing system comprising a film bulk acoustic resonator device of any of the preceding examples.

Example 20 is a mobile telephone comprising a film bulk acoustic resonator device of any of the foregoing examples.

Example 21 is a method for fabricating a film bulk acoustic resonator (FBAR), the method comprising: epitaxially growing a III-nitride piezoelectric layer on a first substrate, forming a first conductive layer, and forming a III-nitride piezoelectric layer A surface is bonded to the second substrate via the first conductive layer to form an acoustic isolation region, the first conductive layer being between the III-nitride piezoelectric layer and the second substrate, and, in the III-nitride piezoelectric layer A second conductive layer is formed on the two surfaces.

Example 22 contains the subject matter of Example 21, wherein the acoustic isolation region comprises a stack of Bragg reflectors.

Example 23 includes the subject matter of Example 21, further comprising forming an acoustic isolation region by forming an air gap or Bragg reflector in the second substrate, in the insulating layer, or in the first conductive layer.

Example 24 includes the subject matter of any of Examples 21-23, wherein the first conductive layer is formed on one of the III-nitride piezoelectric layer and the second substrate.

Example 25 includes the subject matter of any of Examples 21-24, wherein the selectively etchable material is etched from a hole in the second substrate to form an acoustic isolation region.

Example 26 includes the subject matter of any of Examples 21-25, wherein the III-nitride piezoelectric layer comprises AlN or GaN.

Example 27 includes the subject matter of any of Examples 21-26, wherein the first conductive layer is formed on the surface of the III-nitride piezoelectric layer upon growth without first polishing or planarizing the III-nitride piezoelectric layer s surface.

Example 28 includes the subject matter of any of Examples 21-27, wherein the first and second conductive layers each comprise a metal or an oxide.

Example 29 includes the subject matter of any of Examples 21-28, wherein the III-nitride piezoelectric layer exhibits an x-ray diffraction FWHM of less than 1.0 degrees, less than 0.5 degrees, or less than 0.4 degrees.

Example 30 includes the subject matter of any of Examples 21-29, wherein at least one of the first and second substrates comprises tantalum or tantalum carbide.

Example 31, comprising the subject matter of any of Examples 21-30, further comprising: bonding the first surface of the III-nitride piezoelectric layer to the second substrate prior to moving the first substrate away from the piezoelectric layer.

Example 32, comprising the subject matter of any of Examples 21-30, further comprising: bonding the first surface of the III-nitride piezoelectric layer to the second substrate after moving the first substrate away from the piezoelectric layer.

Example 33 includes the subject matter of any of Examples 21-30, wherein at least one of the first and second substrates has a [111], [100], or [110] crystal orientation. In some such cases, the first substrate has a [111], [100], or [110] crystal orientation.

Example 34 includes the subject matter of any of Examples 21-33, wherein the first conductive layer is formed on a surface of the III-nitride piezoelectric layer.

Example 35 includes the subject matter of any of Examples 21-33, wherein the first conductive layer is formed on the second substrate.

Example 36 includes the subject matter of any of Examples 21-35, wherein the first conductive layer is bonded to the second conductive layer.

Example 37, comprising the subject matter of any of Examples 21-36, further comprising etching a pocket in the second substrate.

Example 38 includes the subject matter of any of Examples 21-37, wherein the acoustic isolation region comprises a pocket, a stacked crystal, a coupled resonator, or a Bragg reflector.

Example 39, comprising the subject matter of any of Examples 21-38, further comprising depositing a layer of interleaved metal and dielectric material to form a Bragg reflector series.

Example 40 includes the subject matter of Example 39, wherein the metal layer comprises tungsten and the dielectric layer comprises yttrium oxide.

Example 41 includes the subject matter of any of Examples 21-39, wherein bonding the first surface of the III-nitride piezoelectric layer to the second substrate via the first conductive layer comprises using a metal/metal bond or an oxide bond.

The illustrated examples of the foregoing description are presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. The scope of the present disclosure is not limited by the detailed description, but is defined by the scope of the appended claims. In the future, the application of the priority of the present invention may be claimed in a different manner, and generally encompasses any collection of one or more of the limitations as disclosed herein.

Claims (25)

 A film bulk acoustic resonator (FBAR) device comprising: a first electrically conductive layer; a second electrically conductive layer; a highly crystalline piezoelectric layer between the first and the second electrically conductive layer, the piezoelectric layer a crystallinity having a FWHM of less than 1.0 degrees by x-ray diffraction; and an acoustic isolation region separated from the piezoelectric layer by at least the first electrically conductive layer.    The film bulk acoustic resonator device of claim 1, wherein the highly crystalline piezoelectric layer comprises a III-nitride material.    The film bulk acoustic resonator device of claim 1, wherein the highly crystalline piezoelectric layer comprises at least one material selected from the group consisting of AlN, GaN, and InN.    The film bulk acoustic resonator device of claim 1, wherein the highly crystalline piezoelectric layer comprises AlN.    The film bulk acoustic resonator device of any one of claims 1-4, wherein the highly crystalline piezoelectric layer has an XRD FWHM peak of less than 0.5 degrees.    The film bulk acoustic resonator device of any one of claims 1-4, wherein the highly crystalline piezoelectric layer has an XRD FWHM peak of less than 0.4 degrees.    The film bulk acoustic resonator device of any one of claims 1-4, wherein the highly crystalline piezoelectric layer comprises a single crystal.    The film bulk acoustic resonator device of any one of claims 1-4, wherein the highly crystalline piezoelectric layer is formed by epitaxial growth.    The film bulk acoustic resonator device of any one of claims 1-4, wherein at least one of the first and second electrically conductive layers comprises a metal.    The film bulk acoustic resonator device of any one of claims 1-4, further comprising a bulk crucible substrate.    The film bulk acoustic resonator device of any one of claims 1-4, wherein the acoustic isolation region comprises an air gap or a Bragg reflector.    The film bulk acoustic resonator device of any one of claims 1-4, wherein the acoustic isolation region comprises a plurality of Bragg reflectors.    The film bulk acoustic resonator device of any one of claims 1-4, wherein the acoustic isolation region is defined by a conductive layer.    The film bulk acoustic resonator device of any one of claims 1-4, comprising a third electrically conductive layer in contact with the crucible substrate, wherein the third electrically conductive layer defines an air gap .    A radio frequency (RF) filter device comprising the film bulk acoustic resonator device of any one of claims 1-4.    A computing system comprising the film bulk acoustic resonator device of any one of claims 1-4.    A method for fabricating a film bulk acoustic resonator (FBAR), the method comprising: epitaxially growing a III-nitride piezoelectric layer on a first substrate; forming a first conductive layer; and forming the III-nitride piezoelectric layer a surface is bonded to the second substrate via the first conductive layer to form an acoustic isolation region, the first conductive layer being between the III-nitride piezoelectric layer and the second substrate; and, in the III-nitride A second conductive layer is formed on the second surface of the piezoelectric layer.    The method of claim 17, wherein the acoustic isolation region comprises a stack of Bragg reflectors.    The method of claim 17, comprising: forming the acoustic isolation region by forming an air gap or a Bragg reflector in the second substrate, in the insulating layer, or in the first conductive layer.    The method of any one of claims 17 to 19, wherein the first conductive layer is formed on one of the III-nitride piezoelectric layer and the second substrate.    The method of any one of claims 17 to 19, wherein the selectively etchable material is etched from a hole in the second substrate to form the acoustic isolation region.    The method of any one of claims 17 to 19, wherein the III-nitride piezoelectric layer comprises AlN or GaN.    The method of any one of claims 17 to 19, wherein the first conductive layer is formed on the surface of the III-nitride piezoelectric layer upon growth without first polishing or planarizing the III- The surface of the nitride piezoelectric layer.    The method of any one of claims 17 to 19, wherein the first and second conductive layers each comprise a metal or an oxide.    The method of any one of claims 17-19, wherein the III-nitride piezoelectric layer exhibits an x-ray diffraction FWHM of less than 1.0 degrees, less than 0.5 degrees, or less than 0.4 degrees.