TW201830579A - Semiconductor device structure - Google Patents

Abstract

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer. The semiconductor device structure also includes a gate stack structure in the dielectric layer. The semiconductor device structure further includes a semiconductor wire partially surrounded by the gate stack structure. In addition, the semiconductor device structure includes a contact electrode in the dielectric layer and electrically connected to the semiconductor wire. The contact electrode and the gate stack structure extend from the semiconductor wire in opposite directions.

Description

   Semiconductor device structure   

The embodiments of the present invention relate to the structure of a semiconductor device, and more particularly to the relative positions of the semiconductor lines, contact electrodes, and gate stack structures.

The semiconductor integrated circuit industry has experienced rapid growth. The technological advances in integrated circuit materials and design have produced generations of integrated circuits. Each generation of integrated circuits has smaller and more complex circuits than the previous generation.

In the evolution of integrated circuits, functional density (such as the number of interconnect devices per chip area) generally increases as the geometric size (the smallest component or line that can be formed by the process) shrinks. The reduction in the size of the process usually helps to increase production capacity and reduce related costs.

The reduction in size also increases the complexity of the integrated circuit process. To achieve these advances, similar developments are needed in the integrated circuit process. For example, a three-dimensional transistor such as a semiconductor device having a nanowire may be used instead of a planar transistor. These newer types of semiconductor integrated circuit devices face process challenges and are not fully applicable in all aspects.

A semiconductor device structure provided by an embodiment of the present invention includes: a first dielectric layer; a gate stack structure located in the first dielectric layer; a semiconductor line, and a portion of the semiconductor line surrounding the gate stack structure; An electrode is located in the first dielectric layer and is electrically connected to the semiconductor line. The contact electrode and the gate stack structure extend from the semiconductor line in opposite directions.

D ₁ , D ₂ , D ₃ , D ₄ ‧‧‧ distance

I-I ’, II-II’‧‧‧ line segments

S ₁ , S ₁ ′, S ₂ , S ₃ , S ₄ , S ₅ , S ₆ , S ₇ , S ₇ ′, S ₈ ‧‧‧ surface

X ₁ , X ₂ ‧‧‧ direction

100‧‧‧ semiconductor substrate

100A, 100B‧‧‧ area

110, 150, 170, 210, 280‧‧‧ dielectric layers

110A, 120A, 121, 122‧‧‧ parts

120‧‧‧Semiconductor layer

125, 125’‧‧‧Semiconductor line

125A‧‧‧Channel area

125B‧‧‧Source / Drain Region

130, 160, 175, 220, 220 ’, 245‧‧‧ groove

140‧‧‧ Adhesive layer

142‧‧‧side surface

152‧‧‧ patterned mask layer

154, 290‧‧‧ opening

180, 250, 252, 252’‧‧‧ gate stacked structure

185‧‧‧spacer unit

190, 260‧‧‧Gate dielectric layer

200‧‧‧Gate

205‧‧‧Sag

225‧‧‧ extra steps

230‧‧‧ silicide structure

240, 240’‧‧‧ contact structure

270‧‧‧metal gate

272‧‧‧Barrier layer

274‧‧‧Work function layer

276‧‧‧Adhesive layer

278‧‧‧ metal filling layer

292‧‧‧ conductive material

294‧‧‧ conductive via

Units 300, 301, 310, 311, 320‧‧‧

400A, 400B, 400C‧‧‧ Structure

1A to 1Q are perspective views of various stages of a process for forming a semiconductor device structure in some embodiments.

FIG. 2 is a perspective view of various stages of a process for forming a semiconductor device structure in some embodiments.

3A and 3B are cross-sectional views of a semiconductor device structure in some embodiments.

FIG. 4 is a perspective view of a semiconductor device structure in some embodiments.

FIG. 5 is a perspective view of a semiconductor device structure in some embodiments.

FIG. 6 is a perspective view of a semiconductor device structure in some embodiments.

FIG. 7 is a perspective view of a semiconductor device structure in some embodiments.

FIG. 8 is a top view of a semiconductor device structure in some embodiments.

FIG. 9 is a perspective view of a semiconductor device structure in some embodiments.

The different embodiments or examples provided below can implement different structures of the present invention. The embodiments of specific components and arrangements are used to simplify the present invention and not to limit the present invention. For example, the description of forming the first component on the second component includes direct contact between the two, or there are other additional components instead of direct contact between the two. In addition, in various examples of the present invention, reference numerals may be repeated, but these repetitions are only for simplification and clear description, and do not represent that the units with the same reference numerals in different embodiments and / or settings have the same correspondence relationship.

In addition, spatial relative terms such as "below", "below", "below", "above", "above", or similar terms can be used to simplify the description of one component and another component in the illustration. Relative relationship. Spatial relative terms can be extended to components used in other directions, not limited to the illustrated directions. The element can also be rotated 90 ° or other angles, so the directional term is used to describe the direction in the illustration.

In order to make the structure of the semiconductor device easier to understand, the figure provides X-Y-Z coordinates. The X-axis generally runs along the substrate surface of the semiconductor device structure and extends in a lateral direction. The Y axis is usually along the substrate surface and is perpendicular to the X axis. The Z axis is usually perpendicular to the X-Y plane.

Some embodiments of the invention are explained below. 1A to 1N are perspective views of various stages of a process for forming a semiconductor device structure in some embodiments. Additional steps may be performed before, during, and / or after the stages in Figures 1A to 1N. In other embodiments, some stages may be replaced or omitted. The semiconductor device structure may add additional structures. In other embodiments, some structures described below may be replaced or omitted.

As shown in FIG. 1A, a semiconductor substrate 100 is provided. In some embodiments, the semiconductor substrate 100 is a base semiconductor substrate such as a semiconductor wafer. For example, the semiconductor substrate 100 is a silicon wafer. The semiconductor substrate 100 may include silicon or another semiconductor element such as germanium. In some other embodiments, the semiconductor substrate 100 includes a semiconductor compound. The semiconductor compound may include germanium tin, silicon germanium tin, gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable semiconductor compound, or a combination thereof.

In some embodiments, the semiconductor substrate 100 includes a semiconductor substrate on an insulating layer. The manufacturing method of the semiconductor substrate on the insulating layer may adopt a wafer bonding process, a silicon film transfer process, a separation and oxygen implantation process, another feasible method, or a combination thereof.

In some embodiments, a plurality of regions 100A and 100B are defined on the semiconductor substrate 100. One of the regions 100A and one of the regions 100B are illustrated in FIG. 1A. In some embodiments, the gate stack and the contact structure are arranged to be formed in the region 100A and the region 100B, respectively. The gate stack and contact structure will be detailed below. The region 100A may be referred to as a gate region, and the region 100B may be referred to as a contact region.

In some embodiments shown in FIG. 1A, a stacked layer is deposited on the semiconductor substrate 100 in the regions 100A and 100B. The stacked layer includes a plurality of dielectric layers 110 and semiconductor layers 120 that are alternately deposited. The dielectric layer 110 and the semiconductor layer 120 are stacked at different levels in the vertical direction. In some embodiments, the bottommost semiconductor layer 120 covers the bottommost dielectric layer 110. In some embodiments, the topmost dielectric layer 110 covers the topmost semiconductor layer 120.

Although the thickness of the dielectric layer 110 and the semiconductor layer 120 along the Z axis in FIG. 1A is substantially the same, the embodiment of the present invention is not limited thereto. In some embodiments, the thickness of the dielectric layer 110 and the semiconductor layer 120 along the Z axis are different. The dielectric layer 110 may be thicker or thinner than the semiconductor layer 120.

The embodiments of the present invention may have various changes and / or adjustments. In some other embodiments, a plurality of dielectric layers 110 and a semiconductor layer 120 are vertically stacked on the semiconductor substrate 100. The conductive layer 120 is sandwiched between the dielectric layers 110.

In some embodiments, the dielectric layer 110 includes an oxide, a nitride, another suitable material, or a combination thereof. For example, the dielectric layer 110 may include aluminum oxide, silicon oxide, silicon nitride, silicon nitride carbide, silicon oxycarbide, or another suitable dielectric material. In some embodiments, the dielectric layer 110 can be deposited by a chemical vapor deposition process, a spray coating process, a spin coating process, an atomic layer deposition process, a physical vapor deposition process, another feasible process, or a combination thereof.

In some embodiments, the semiconductor layer 120 includes silicon, germanium, silicon germanium, germanium tin, silicon germanium tin, or another suitable semiconductor material. In some embodiments, the semiconductor layer 120 may be deposited by an epitaxial growth process. The deposition method of each semiconductor layer 120 may be a selective epitaxial growth process, a chemical vapor deposition process (such as a gaseous epitaxial process, a low pressure chemical vapor deposition process, and / or an ultra-high vacuum chemical vapor deposition process), a molecule Beam epitaxy process, another feasible process, or a combination of the above.

As shown in FIG. 1B, some of the dielectric layer 110 and the semiconductor layer 120 in the region 100B are removed. In this way, a plurality of trenches (or depressions) 130 can be formed in the dielectric layer 110 and the semiconductor layer 120 in the region 100B. One of the grooves 130 is shown in FIG. 1B. In some embodiments, the trench 130 passes through the dielectric layer 110 and the semiconductor layer 120 and exposes the semiconductor substrate 100 in the region 100B.

In some embodiments, multiple photolithographic processes and etching processes are performed to form the trenches 130. In some embodiments, the etching process includes a wet etching process, a dry etching process, or another suitable etching process. In some embodiments, a patterned masking layer (not shown) is formed on the topmost dielectric layer 110 to help form the trench 130. For example, the patterned mask layer covers the area 100A and exposes a part of the area 100B to define the position of the trench 130.

As shown in FIG. 1C, the adhesive layer 140 is deposited in the trenches 130 in the region 100B. In some embodiments, the adhesive layer 140 is compliantly deposited on the sidewall and the lower surface of the trench 130. In some embodiments, the adhesive layer 140 is in contact with the lateral surfaces of the dielectric layer 110 and the semiconductor layer 120 exposed by the trench 130. In some embodiments, the adhesive layer 140 covers an exposed portion of the semiconductor substrate 100.

In some embodiments, the adhesion layer 140 includes an oxide such as silicon oxide, nitride, another suitable adhesion material, or a combination thereof. In some embodiments, the adhesive layer 140 has a multilayer structure. For example, the adhesion layer 140 may include a nitride layer and an oxide layer. The oxide layer is sandwiched between the nitride layer and the semiconductor layer 120, and is sandwiched between the nitride layer and the dielectric layer 110. In some embodiments, the adhesion layer 140 can be deposited by a chemical vapor deposition process, a spray process, a spin coating process, another feasible process, or a combination thereof.

As in some embodiments shown in FIG. 1C, a dielectric layer 150 is deposited in a trench in the region 100B. In this way, the adhesive layer 140 fills the trench 130 together with the dielectric layer 150. In some embodiments, the dielectric layer 110 and the semiconductor layer 120 surround the adhesive layer 140 and the dielectric layer 150. In some embodiments, a portion of the adhesive layer 140 is sandwiched between the dielectric layer 110 and the dielectric layer 150. In some embodiments, a portion of the adhesive layer 140 is sandwiched between the semiconductor layer 120 and the dielectric layer 150.

In some embodiments, the dielectric layer 150 includes an oxide, a nitride, another suitable material, or a combination thereof. For example, the dielectric layer 150 may include aluminum oxide, silicon oxide, silicon nitride, silicon nitride carbide, silicon oxycarbide, or another suitable dielectric material. In some embodiments, the materials of the dielectric layer 150 and the dielectric layer 110 are different.

In some embodiments, the dielectric layer 150 can be deposited by a chemical vapor deposition process, a spray coating process, a spin coating process, an atomic layer deposition process, a physical vapor deposition process, another feasible process, or a combination thereof. In some embodiments, the deposited adhesive layer 140 and the deposited dielectric layer 150 cover the topmost dielectric layer 110 (not shown) in the regions 100A and 100B. A planarization process is then performed to thin the deposited adhesive layer 140 and the deposited dielectric layer 150 downward until the topmost dielectric layer 110 is exposed. The planarization process may include a chemical mechanical polishing process, a polishing process, an etching process, another feasible process, or a combination thereof.

As in some embodiments shown in FIG. 1D, a patterned masking layer 152 is formed on the topmost dielectric layer 110. The patterned masking layer 152 covers the area 100B, and has an opening 154 to expose a part of the area 100A. One of the openings 154 is shown in FIG. 1D.

Then, the dielectric layer 110 and the semiconductor layer 120 in the area 100A exposed by the opening 154 are removed. As a result, a part of the semiconductor substrate 100 is exposed. Each dielectric layer 110 has a reserved portion 110A in the region 100A, and each semiconductor layer 120 has a reserved portion 120A in the region 100A. The boundary between the region 100A and the region 100B is indicated by a dotted line to facilitate understanding of the structure. In some embodiments, an etching process is used to remove a portion of the dielectric layer 110 and a portion of the semiconductor layer 120 in the region 100A. After the etching process, the patterned masking layer 152 is removed.

In some embodiments shown in FIG. 1E, a portion 110A of the dielectric layer 110 in the region 100A is removed. As such, a plurality of trenches (or depressions) 160 are formed in the region 100A. One of the trenches 160 is shown in FIG. 1E. A space is formed after the trench 160 is used to form a dielectric layer. In some embodiments, the trench 160 passes through the dielectric layer 110 and the semiconductor layer 120 and exposes the semiconductor substrate 100 in the region 100A.

In some embodiments, a portion 110A of the dielectric layer 110 in the region 100A is removed by an etching process. In some embodiments, removing the etched portion of the portion 110A of the dielectric layer 110 has high etching selectivity to the portion 120A of the dielectric layer 110 and the portion of the semiconductor layer 120. As a result, the etching rate of part 110A is much higher than the etching rate of part 120A. In summary, this etching process can easily remove a portion of the 110A without remaining, and the semiconductor layer 120 is not damaged.

In some embodiments described above, the material of the dielectric layer 150 is different from the material of the dielectric layer 110. In some embodiments, the etched product used in the etching process for forming the trench 160 has sufficiently high etch selectivity for the dielectric layer 110 and the dielectric layer 150. As such, in the etching process for forming the trench 160, the etching rate of the dielectric layer 110 is much higher than the etching rate of the dielectric layer 150. For example, some embodiments remove the dielectric layer 110 in the region 100A to form the trench 160 and substantially do not remove the dielectric layer 150 in the region 100B. The trench 160 may be formed at a specific position to correspond to the dielectric layer 150 in the region 100B. As such, the trench 160 is located in the region 100A and is not formed in the region 100B. In summary, the highly selective etching process can generate self-aligned trenches 160, and can achieve precise alignment between the trenches 160 and the area 100A.

In some embodiments shown in FIG. 1E, the dielectric layer 110 and a portion 110A of the semiconductor layer 120 and a portion 120A thereof are removed from the region 100A. In some embodiments, substantially no dielectric layer 110 remains in the region 100A, so a portion 120A of the semiconductor layer 120 is not supported in the region 100A. A portion 120A of the semiconductor layer 120 is suspended in the area 100A, as shown in FIG. 1E. In some embodiments, a portion 120A of the semiconductor layer 120 passes through the adhesive layer 140 to adhere to and fix the dielectric layer 150 in the region 100B. In this way, part 120A of the semiconductor layer 120 can be free from offset and bending in subsequent processes, and these mechanisms will be further detailed below.

As in some embodiments shown in FIG. 1F, a dielectric layer 170 is deposited on the semiconductor substrate 100 in the region 100A. The dielectric layer 170 fills the trench 160. As such, a portion 120A of the semiconductor layer 120 in the region 100A will be buried in the dielectric layer 170. In some embodiments, the dielectric layer 170 partially covers a portion 120A of the semiconductor layer 120. For example, the dielectric layer 170 covers three surfaces of a portion 120A of the semiconductor layer 120, and the adhesive layer 140 and the dielectric layer 150 cover one surface of a portion 120A of the semiconductor layer 120.

In some embodiments, the dielectric layer 170 comprises an oxide, a nitride, another suitable material, or a combination thereof. For example, the dielectric layer 170 may include aluminum oxide, silicon oxide, silicon nitride, silicon nitride carbide, silicon oxycarbide, or another suitable dielectric material. In some embodiments, the materials of the dielectric layer 170 and the dielectric layer 110 are different. In some embodiments, the materials of the dielectric layer 170 and the dielectric layer 150 are different. In some embodiments, the material selection of the dielectric layer 110, the dielectric layer 150, and the dielectric layer 170 needs to have sufficient selectivity in the subsequent etching process, and this mechanism will be further detailed later.

In some embodiments, the dielectric layer 170 can be deposited by a chemical vapor deposition process, a spray coating process, a spin coating process, an atomic layer deposition process, a physical vapor deposition process, another feasible process, or a combination thereof. As described above, a portion 120A of the semiconductor layer 120 is bonded to the dielectric layer 150 via the adhesive layer 140. In summary, when the dielectric layer 170 is deposited, the portion 120A of the semiconductor layer 120 is not shifted or bent.

In some embodiments, a plurality of trenches (or depressions) 175 are then formed within the dielectric layer 170 in the region 100A. In this way, space can be created for the subsequent formation of the gate stack. One of the grooves 175 is shown in FIG. 1G.

In some embodiments, the trench 175 penetrates the dielectric layer 170 and exposes the semiconductor substrate 100 in the region 100A. In some embodiments, the trench 175 exposes a portion 120A of the semiconductor layer 120. In some embodiments, the trench 175 exposes a portion 120A of the semiconductor layer 120. In some embodiments, the trench 175 exposes a portion of the adhesive layer 140 in the area 100B. In some embodiments, the width of one of the trenches 175 is substantially the same as the width of one of the trenches 130 in FIG. 1B. The width of the trench 175 can be measured along a direction substantially parallel to the Y axis (or the boundary between the dielectric layer 170 in the region 100A and the dielectric layer 110 in the region 100B) in FIG. The width of the trench 130 shown in FIG. 1B can be measured along a direction substantially parallel to the Y axis (or the boundary between the region 100A and the region 100B) in FIG. B.

The dimensions of the trenches 175 and 130 can be changed as required. For example, in some embodiments, the width of one of the trenches 130 shown in FIG. 1B may be greater than the width of one of the trenches 175. As such, the dielectric layer 150 formed in one of the trenches 130 is wider than the gate stack subsequently formed in one of the trenches 175. The wider dielectric layer 150 can further provide electrical insulation between the gate stack formed later and the contact structure formed later. The contact structure will be further detailed later.

In some embodiments, a photolithography and etching process is performed to form the trenches 175. In some embodiments, a patterned masking layer (not shown) is used to help form the trench 175. For example, the patterned mask layer covers the area 100B and exposes a part of the area 100A to define the position of the trench 175.

As described above, in some embodiments, the material of the dielectric layer 170 is different from the materials of the dielectric layer 110 and the dielectric layer 150. In some embodiments, the etching process used to form the trench 175 has an etching product that has a sufficiently high etching selectivity for the dielectric layer 170 and the dielectric layer 110. In some embodiments, the etching process used to form the trenches 175 has a sufficiently high etching selectivity for the dielectric layer 170 and the dielectric layer 150. As such, in the etching process for forming the trench 175, the etching rate of the dielectric layer 170 is greater than the etching rates of the dielectric layer 100 and the dielectric layer 150.

For example, some embodiments remove a portion of the dielectric layer 170 in the region 110A to form a trench 175, and substantially do not remove the dielectric layer 110 and the dielectric layer 150 in the region 110B. The trench 175 may be formed at a specific position to correspond to the dielectric layer 110 and the dielectric layer 150. As such, the trench 175 is located in the region 100A, but not in the region 100B. In summary, the highly selective etching process can form a self-aligned trench 175. The highly selective etching process does not require additional alignment of the trench 175 to the area 100A, and precise alignment between the trench 175 and the area 100A can be achieved.

In some embodiments, a patterned mask layer (not shown) having an opening in the region 100A can be used to define the position of the trench 175. The patterned masking layer covers the dielectric layer 110 and the dielectric layer 150 in the area 100B. The opening of the patterned masking layer exposes the dielectric layer 170 in the area 100A. If the patterned mask layer is offset, the opening may expose a portion of the dielectric layer 110 and / or the dielectric layer 150 in the area 100B. Since the etching process for forming the trench 175 does not substantially remove the dielectric layer 110 and the dielectric layer 150, the trench 175 may be formed at a specific position in the region 100A. In this way, even if the patterned masking layer defining the trenches 175 produces an unwanted offset, it is still ensured that the trenches 175 are accurately located in the region 100A.

In some embodiments, multiple sacrificial (or dummy) gate stack structures 180 are then formed in the trenches 175 of the dielectric layer 170. One of the gate stack structures 180 is shown in FIG. 1H. The gate stack structure 180 can be replaced with other gate stacks, and this mechanism will be further detailed later.

In some embodiments, the gate stack structure 180 partially surrounds the exposed portion 120A of the semiconductor layer 120. For example, the gate stack structure 180 covers three surfaces of the portion 120A, and the adhesive layer 140 and the dielectric layer 150 cover one surface of the portion 120A. In some embodiments, the gate stack structure 180 is in contact with the adhesive layer 140 in the region 100B.

As shown in some embodiments in FIG. 1H, one of the gate stack structures 180 includes a sacrificial (or dummy) gate dielectric layer 190 and a sacrificial (or dummy) gate 200. The gate dielectric layer 190 fills the trench 175 of the dielectric layer 170 together with the gate 200. In some embodiments, a portion of the gate dielectric layer 190 is sandwiched between the gate 200 and the adhesive layer 140. In some embodiments, a portion of the gate dielectric layer 190 is sandwiched between the gate 200 and the exposed portion 120A of the semiconductor layer 120.

In some embodiments, the composition of the gate dielectric layer 190 is a dielectric material. For example, the composition of the gate dielectric layer 190 is silicon oxide or another suitable material. In some embodiments, the method for depositing the gate dielectric layer 190 may be a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, a spin coating process, another feasible process, or a combination thereof. In some embodiments, the composition of the gate 200 is polycrystalline silicon or another suitable material. In some embodiments, the deposition method of the gate electrode 200 may be a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, another feasible process, or a combination thereof.

In some embodiments shown in FIG. 11, the dielectric layer 170 in the region 100A and the dielectric layer 110 and the semiconductor layer 120 in the region 100B are removed. In this way, a depression 205 can be formed. The recess 205 exposes the semiconductor substrate 100 in the regions 100A and 100B. In some embodiments, multiple photolithography processes and etching processes may be performed to form the recesses 205.

In some embodiments as described above, the semiconductor layer 120 may be patterned multiple times. A portion of the semiconductor layer 120 in the region 100A can be removed to form a trench 160, as shown in FIG. 1D. Then, the semiconductor layer 120 in the region 100B can be removed to form a recess 205, as shown in FIG. 11. After the trench 160 and the recess 205 are formed, a portion 120 of the semiconductor layer 120 will remain in the region 100A. In this way, a plurality of semiconductor lines 125 can be formed in the region 100A after the semiconductor layer 120 is patterned multiple times. The semiconductor line 125 may also be referred to as a nanowire.

As shown in FIG. 11, each semiconductor line 125 has portions 121 and 122. The gate stack structure 180 covers a portion 121 and the recess 205 exposes a portion 122. The portion 121 of the semiconductor line 125 can be used as a channel region of a field effect transistor. The portion 122 of the semiconductor line 125 can be used as a source / drain region of a field effect transistor. The source / drain region can provide stress to the channel region. In some embodiments, the portion 122 of the semiconductor line 125 is unsupported, so it will hang in the area 100A.

In some embodiments, the gate stack structure 180 in the region 100A and the dielectric layer 150 in the region 100B are located on opposite sides of the semiconductor line 125. Unlike the dielectric layer 150, the gate stack 180 surrounds the semiconductor line 125. In this way, the gate stack structure 180 surrounds a portion of the semiconductor lines 125. The gate stack structure 180 may cover multiple surfaces of the semiconductor line 125. In some embodiments, the gate stack structure 180 covers three surfaces of the semiconductor line 125. In some embodiments, the dielectric layer 150 covers a surface of the semiconductor line 125, and this surface directly contacts the adhesive layer 140.

In some embodiments shown in FIG. 11, a spacer unit 185 is formed on a sidewall of the gate stack structure 180. The spacer unit 185 surrounds a portion of the semiconductor line 125. In some embodiments, a portion of the semiconductor line 125 may be exposed when the spacer unit 185 is formed.

In some embodiments, the spacer unit 185 is composed of a dielectric material. The dielectric material may include silicon nitride, silicon oxynitride, silicon nitride carbide, silicon carbide, another suitable dielectric material, or a combination thereof. In some embodiments, the method for depositing the dielectric material may be a chemical vapor deposition process, a physical vapor deposition process, a spin coating process, another feasible process, or a combination thereof.

As shown in FIG. 1J, the dielectric layer 210 is deposited on the semiconductor substrate 100 in the regions 100A and 100B. The dielectric layer 210 fills the recess 205. As such, the dielectric layer 210 surrounds the semiconductor line 125, the gate stack structure 180, and the dielectric layer 150. The dielectric layer 210 may serve as an interlayer dielectric layer of an interconnect structure. The material of the interlayer dielectric layer can be selected to minimize the size, transmission delay, and crosstalk between nearby conductive structures.

In some embodiments, the dielectric layer 210 includes an oxide, a nitride, another suitable material, or a combination thereof. For example, the dielectric layer 210 may include aluminum oxide, silicon oxide, silicon nitride, silicon nitride carbide, silicon oxycarbide, or another suitable dielectric material. In some embodiments, the materials of the dielectric layer 210 and the dielectric layer 150 are different. The material of the dielectric layer 210 may be the same as or different from the material of the dielectric layer 110.

In some embodiments, the method for depositing the dielectric layer 210 may be a chemical vapor deposition process, a spray coating process, a spin coating process, an atomic layer deposition process, a physical vapor deposition process, another feasible process, or a combination thereof. In some embodiments, the deposited dielectric layer 210 covers the gate stack structure 180 and the dielectric layer 150 (not shown). A planarization process may then be performed to thin the deposited dielectric layer 210 downward until the gate stack structure 180 and the dielectric layer 150 are exposed. The planarization process may include a chemical mechanical polishing process, a polishing process, an etching process, another feasible process, or a combination thereof.

In some embodiments shown in FIG. 1K, a portion of the dielectric layer 210 in the region 100B is removed. In this way, a plurality of trenches (or depressions) 220 can be formed in the dielectric layer 210 in the region 100B to generate a space for a contact electrode to be formed later. The contact electrode is coupled to a source / drain region of the field effect transistor. In some embodiments, the trench 220 exposes a side surface of the semiconductor line 125. In some embodiments, the trenches 220 are located on opposite sides of the dielectric layer 150 and expose the side surface 142 of the adhesive layer 140.

In some embodiments, a photolithography and etching process may be performed to form the trench 220. In some embodiments, a patterned masking layer (not shown) is formed to help form the trench 220. For example, the patterned mask layer covers the area 100A and exposes a part of the area 100B to define the position of the trench 220.

As described above, the materials of the dielectric layer 210 and the dielectric layer 150 are different in some embodiments. In some embodiments, the etched product used in the etching process for forming the trench 220 has a sufficiently high etching selectivity for the dielectric layer 210 and the dielectric layer 150. As such, in the etching process for forming the trench 20, the etching rate of the dielectric layer 210 is much higher than the etching rate of the dielectric layer 150.

For example, some embodiments remove the dielectric layer 210 in the region 100B to form the trench 220 without substantially removing the dielectric layer 150. The trench 220 may be formed at a specific position to correspond to the dielectric layer 150. As such, the trenches may be located on opposite sides of the dielectric layer 150. In summary, the highly selective etch process produces self-aligned trenches 220. The highly selective etching process does not require additional alignment of the trenches 220 to be formed on opposite sides of the dielectric layer 150.

In some embodiments, a patterned masking layer (not shown) having an opening in the region 100B is used to define the position of the trench 220. The patterned masking layer covers the dielectric layer in the region 100B and the region 100A. The opening of the patterned masking layer may expose the dielectric layer 210 in the region 100B. If the patterned mask layer is offset, the opening will expose a portion of the dielectric layer 150 in the area 100B. Since the etching process used to form the trench 220 does not substantially remove the dielectric layer 150, the trench 220 will be formed at a specific position to correspond to the dielectric layer 150. As such, the trenches 220 can be accurately located on opposite sides of the dielectric layer 150. Even if the patterned masking layer defining the position of the trench 220 has an unwanted offset, it is still ensured that the trench 220 is accurately formed at a predetermined position.

One or more additional steps 225 may be performed after the trench 220 is formed. In some embodiments, the additional step 225 includes an epitaxial growth process. In some embodiments, an epitaxial growth process is performed on the structure shown in FIG. 1K. In this way, the source / drain region of the field effect transistor after the epitaxial growth process can be enlarged. The epitaxial growth process may include a selective epitaxial growth process, a chemical vapor deposition process (such as a vapor epitaxial process, a low pressure chemical vapor deposition process, and / or an ultra-high vacuum chemical vapor deposition process), and a molecular beam epitaxial process. Process, another feasible process, or a combination of the above.

For example, during epitaxial growth, a cladding layer may be deposited on a portion of the semiconductor line 125 exposed by the trench 220. In this way, the semiconductor line 125 and the cladding layer thereon can form a source / drain region of the field effect transistor together. In some embodiments, the cladding layer comprises silicon, germanium, silicon germanium, germanium tin, silicon germanium tin, or another suitable semiconductor material. The cladding layer and the semiconductor line 125 may include different or the same materials.

Although the semiconductor line 125 shown in FIG. 1K has a rectangular or square cross-sectional profile, the embodiment of the present invention is not limited thereto. In some other embodiments, the cross-sectional profile of the semiconductor wire 125 is rounded, or may be circular, diamond-shaped, or another shape.

In some embodiments, the additional step 225 includes heat treatment. For example, a heat treatment such as a tempering process is performed on the structure shown in FIG. 1K to change the shape of the semiconductor wire 125. During the heat treatment, the atoms in the semiconductor wire 125 may be rearranged. In some embodiments, the rearrangement of atoms causes the corners of the semiconductor line 125 to be rounded. As such, the semiconductor line 125 may have an arc-shaped surface.

In some embodiments, the additional step 225 includes performing an epitaxial growth process and heat treatment on the structure shown in FIG. 1K. Embodiments of the invention may have many variations and / or adjustments. Different embodiments may replace or omit some of the additional steps 225 described above.

As shown in FIG. 1L, a plurality of silicide structures 230 are formed in the trench 220. The silicide structure 230 covers the exposed surface of the semiconductor line 125. The silicide structure 230 can reduce the contact resistance and increase the conductivity of the source / drain regions of the field effect transistor. In this way, a suitable contact area can be formed for electrical connection.

In some embodiments, the silicide structure 230 includes a metal material. The metallic material may include titanium, nickel, cobalt, or another suitable material. In some embodiments, the silicide structure 230 includes a combination of a metal material and a semiconductor material of the semiconductor line 125. For example, the silicide structure 230 may include titanium silicon, nickel silicon, or cobalt silicon. In some embodiments, the metal material deposition method may be a physical vapor deposition process, a chemical vapor deposition process, another available process, or a combination thereof.

In some embodiments, the silicide structure 230 is formed by a self-aligned silicide process. For example, the metal material may be deposited in the trench 220 compliantly. Tempering may then be performed to diffuse the metal material to the semiconductor lines 125. As such, the silicide structure 230 is formed on the exposed surface of the semiconductor line 125. The tempering process does not cause the metal material to diffuse to the dielectric layer (such as the dielectric layer 210), so no silicide is formed on the dielectric layer. After the tempering process, a cleaning process may be performed to remove undiffused portions of the metal material. The remaining silicide structure 230 will self-align the exposed surface of the semiconductor line 125. The silicide structure 230 may be referred to as a self-aligned silicide structure.

The silicidation process does not require additional alignment of the silicide structure 230 and the semiconductor line 125, so that spontaneous alignment can be achieved between the silicide structure 230 and the semiconductor line 125. In some embodiments, the method of forming the silicide structure 230 does not require a lithographic patterning process.

As shown in FIG. 1M, a plurality of contact structures 240 are formed in the trench 220. The contact structure 240 fills the trench 220. In this way, the silicide structure 230 and the contact structure 240 together form a contact electrode to be coupled to the source / drain region of the field effect transistor.

In some embodiments, the silicide structure 230 is sandwiched between the contact structure 240 and the semiconductor line 125. Each contact structure 240 is electrically connected to the semiconductor line 125 through the silicide structure 230. In some embodiments, the contact structure 240 directly contacts the spacer unit 185. In some embodiments, the contact structure 240 directly contacts the adhesive layer 140. In some embodiments, the dielectric layer 150 extends from the adhesive layer 140 along the contact structure 240.

In some embodiments, the contact structure 240 comprises a conductive material, such as tungsten, copper, aluminum, or another suitable conductive material. In some embodiments, the method for depositing the conductive material may be an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, an electroplating process, an electroless plating process, another feasible process, or a combination thereof. In some embodiments, the deposited conductive material extends beyond the trench 220 and covers the dielectric layer 210. Then, a planarization process may be performed until the dielectric layer 210 is exposed, that is, excess conductive material is removed. In this way, a portion of the conductive material remaining in the trench 220 forms the contact structure 240. The planarization process may include a chemical mechanical polishing process, a polishing process, an etching process, another feasible process, or a combination thereof.

As shown in FIG. 1N, the gate stack structure 250 is replaced with the gate stack structure 250. In some embodiments, the method for removing the gate stack structure 180 may be a wet etching process, a dry etching process, another feasible process, or a combination thereof. As a result, the trenches 245 in the dielectric layer 210 in the area 100A are hollowed out. A gate stack structure 250 including a gate dielectric layer 260 and a metal gate 270 may be formed in the trench 245 afterwards. The gate dielectric layer 260 and the metal gate 270 will be further detailed later. The spacer unit 185 is connected to a sidewall of the gate stack structure 250. The gate stack structure 250 may be referred to as a metal gate stack structure.

In some embodiments, the gate stack structure 250 is electrically connected to the semiconductor line 125. In some embodiments, an adhesion layer 140 is provided between the gate stack structure 250 and the dielectric layer 150. In some embodiments, the gate dielectric layer 260 is sandwiched between the metal gate 270 and the dielectric layer 210, and is sandwiched between the metal gate 270 and the adhesive layer 140. In some embodiments, the interface between the gate stack structure 250 and the adhesive layer 140 and the interface between the dielectric layer 210 and the contact structure 240 are substantially coplanar, as shown in FIG. 1N.

As shown in FIG. 1N, some embodiments extend from the boundary between the region 100A and the region 100B along the X-axis to the contact structure 240, the adhesive layer 140, and the dielectric layer 150 in the region 100B. As shown. The contact structure 240 is located on opposite sides of the dielectric layer 150 and overlaps the dielectric layer 150. The gate stack structure 250 extends from the adhesive layer 140 in the area 100A along the X axis. Since the gate stack structure 250 does not extend in the region 100B, the gate stack structure 250 in the region 100A does not overlap with the contact structure 240 in the region 100B.

In some embodiments, the gate dielectric layer 260 includes a high dielectric constant dielectric layer. The composition of the high-k dielectric layer can be hafnium oxide, zirconia, alumina, silicon oxynitride, hafnium oxide-aluminum oxide, hafnium oxide, hafnium oxide, hafnium oxide, tantalum oxide, titanium oxide, hafnium oxide Zirconium, another suitable high dielectric constant material, or a combination thereof. In some embodiments, the deposition method of the gate dielectric layer 260 may be an atomic layer deposition process, a chemical vapor deposition process, a spin coating process, another feasible process, or a combination thereof. In some embodiments, a high temperature tempering step may be performed to reduce or eliminate defects in the gate dielectric layer 260.

In some embodiments, the gate dielectric layer 260 includes an interface layer (not shown), which is adjacent to the semiconductor line 125. The interface layer can be used to reduce the stress between the high dielectric constant material layer and the semiconductor line 125. In some embodiments, the interface layer is composed of silicon oxide. In some embodiments, the method for forming the interface layer may be an atomic layer deposition process, a thermal oxidation process, another feasible process, or a combination thereof. In some other embodiments, the gate dielectric layer 260 does not include an interface layer. In some embodiments, the gate dielectric layer 260 directly contacts the semiconductor line 125.

The gate 270 of the gate stacked structure 250 may include a metal gate stacked layer on the gate dielectric layer 260. In some embodiments, the metal gate 270 may include one or more work function layers and one or more metal filling layers. For example, the metal gate 270 of some embodiments includes a barrier layer 272, a work function layer 274, a bonding layer 276, and a metal filling layer 278, as shown in FIG. 1N. Different embodiments may replace or omit some metal gate stacks. The metal gate 270 of the metal gate stack 250 may have additional layers.

In some embodiments shown in FIG. 1N, the barrier layer 272 is located between the gate dielectric layer 260 and the work function layer 274. The barrier layer 272 can prevent diffusion between the gate dielectric layer 260 and the work function layer 274. In some embodiments, the barrier layer 272 includes titanium nitride, tantalum nitride, another suitable material, or a combination thereof.

The work function layer 274 can provide a work function required by the transistor to improve device performance, such as improving its threshold voltage. In an embodiment in which an n-type transistor is formed, the work function layer 274 may be an n-type metal layer, which may provide a work function suitable for a device. The work function value may be substantially equal to or less than about 4.5 eV. The n-type metal layer may include a metal, a metal carbide, a metal nitride, other suitable materials, or a combination thereof. For example, the n-type metal layer includes titanium nitride, tantalum, tantalum nitride, another suitable material, or a combination thereof.

On the other hand, in an embodiment in which a p-type transistor is formed, the work function layer 274 may be a p-type metal layer, which may provide a work function suitable for a device. The work function value may be substantially equal to or greater than about 4.8 eV. The p-type metal layer may include a metal, a metal carbide, a metal nitride, other suitable materials, or a combination thereof. For example, the p-type metal layer includes tantalum nitride, tungsten nitride, titanium, titanium nitride, other suitable materials, or a combination thereof.

The embodiments of the present invention may have various changes and / or adjustments. In some other embodiments, the work function layer 274 includes hafnium, zirconium, aluminum, metal carbides (such as hafnium carbide, zirconium carbide, titanium carbide, or aluminum carbide), ruthenium, palladium, platinum, cobalt, nickel, or the foregoing combination. The thickness and / or composition of the work function layer 274 may be fine-tuned to adjust the work function level.

In some embodiments shown in FIG. 1N, the bonding layer 276 is located between the work function layer 274 and the metal filling layer 278. The bonding layer 276 can increase the bonding force between the work function layer 274 and the metal filling layer 278. In this way, peeling or delamination of the metal filling layer 278 can be avoided. In some embodiments, the bonding layer 276 includes tantalum nitride, titanium nitride, another suitable material, or a combination thereof.

The metal filling layer 278 provides an electrical connection between the work function layer 274 and a conductive via formed later. The conductive via is coupled to the metal filling layer 278. In some embodiments, the metal filling layer 278 includes aluminum, tungsten, copper, gold, platinum, cobalt, another suitable metal material, or a combination thereof.

In some embodiments, the deposition method of these metal gate stacked layers (such as the barrier layer 272, the work function layer 274, the adhesive layer 276, and the metal filling layer 278) may be an atomic layer deposition process, a physical vapor deposition process, Chemical vapor deposition process, electroplating process, electroless plating process, another feasible process, or a combination thereof. The deposited gate dielectric layer 260 fills the trench 245 together with the deposited metal gate stack. After that, a part of the gate dielectric layer 260 and the metal gate stacked layer (not shown) beyond the trench 245 can be removed. The metal gate stacked layer in the trench 245 forms a metal gate 270. In this way, the gate dielectric layer 260 remaining in the trench 245 forms a gate stack structure 250 together with the metal gate 270. A planarization process may be performed to remove a portion of the gate layer 260 and the metal gate stacked layer beyond the trench 245. The planarization process may include a chemical mechanical polishing process, a polishing process, an etching process, another feasible process, or a combination thereof.

As shown in FIG. 10, a dielectric layer 280 is deposited on the dielectric layer 210 in the regions 100A and 100B. The dielectric layer 280 covers the contact structure 240 and the gate stack structure 250. The dielectric layer 280 may function as an intermetallic dielectric layer of an interconnect structure.

In some embodiments, the composition of the dielectric layer 280 may be silicon oxide, silicon oxynitride, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, fluorinated silicate glass, low dielectric Constant material, hole-shaped dielectric material, another suitable dielectric material, or a combination thereof. The material of the dielectric layer 280 can be selected to minimize the size, transmission delay, and crosstalk between nearby conductive structures. In some embodiments, the method for depositing the dielectric layer 280 may be a chemical vapor deposition process, a spin coating process, a spray process, an atomic layer deposition process, a physical vapor deposition process, another feasible process, or a combination thereof.

As in some embodiments shown in FIG. 10, a plurality of openings 290 are formed in the dielectric layer 280. The openings 290 in the regions 100A and 100B may expose the contact structure 240 and the gate stack structure 250, respectively. In some embodiments, a photolithography and etching process is performed to form the opening 290.

Thereafter, as shown in FIG. 1P, a conductive material 292 is deposited on the dielectric layer 280 to fill the opening 290. In some embodiments, the conductive material 292 comprises copper, aluminum, tungsten, titanium, nickel, gold, platinum, another suitable material, or a combination thereof. In some embodiments, the method for depositing the conductive material 292 may be a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, another feasible process, or a combination thereof.

A planarization process may then be performed to remove a portion of the conductive material 292 beyond the opening 290. As a result, a portion of the conductive material 292 remaining in the opening 290 forms a plurality of conductive vias 294 in the dielectric layer 280, as shown in FIG. 1Q. The conductive via 294 passes through the dielectric layer 280. Some conductive vias 294 are electrically connected to the contact structure 240. Some conductive vias 294 are electrically connected to the gate stack structure 250.

One or more dielectric layers and conductive structures may then be formed on the dielectric layer 280 and the conductive vias 294 to continue forming interconnect structures. The conductive structure may include conductive lines, conductive vias, and / or other suitable conductive structures. Various device units, such as field effect transistors, can be interconnected with each other via an interconnect structure to form an integrated circuit device.

Embodiments of the invention may have many variations and / or adjustments. For example, the trenches used to form the contact electrodes are not limited to the trenches 220 shown in FIG. 1K. In some other embodiments, a portion of the dielectric layer 210 in the regions 100A and 100B is removed. As such, the trench 220 'is formed in the dielectric layer 210 in the region 100B and extends into the region 100A, as shown in FIG. 2. In some embodiments, the trench 220 'exposes multiple surfaces of the semiconductor line 125. For example, the dielectric layer 210 between the semiconductor lines 125 and on top of the semiconductor lines 125 may be removed. In this way, the trench 220 'exposes the side surface, the upper surface, and the lower surface of the semiconductor line 125, as shown in FIG.

3A and 3B are cross-sectional views of a semiconductor device structure in some embodiments. In some embodiments, FIG. 3A is a cross-sectional view of the semiconductor device structure along line I-I 'in FIG. 1Q. In some embodiments, FIG. 3B is a cross-sectional view of the semiconductor device structure along line II-II 'in FIG. 1Q. As shown in FIGS. 3A and 3B, each semiconductor line 125 in the region 100A includes a channel region 125A and a source / drain region 125B.

As shown in FIG. 3A, the gate stack structure 250 in the region 100A covers a portion of the channel region 125A. As shown in FIG. 3A, the adhesive layer 140 in the region 100B is sandwiched between the channel region 125A in the region 100A and the dielectric layer 150 in the region 100B in the X-Z plane.

In some embodiments, the gate stack structure 250 surrounds a portion of the channel region 125A. In some embodiments, the gate stack structure 250 covers multiple surfaces of the channel region 125A, and the adhesive layer 140 and the dielectric layer 150 cover one surface of the channel region 125A. Taking FIG. 3A as an example, the adhesive layer 140 covers one surface S _{1 of the} channel region 125A, and the gate stack structure 250 covers three surfaces S ₂ , S ₃ , and S _{4 of the} channel region 125A. As such, the adhesive layer 140 in the XZ plane cuts off the interface between the gate stack structure 250 and the channel region 125A. In some embodiments, one of the gate stack structures 250 in the XZ plane, the adhesive layer 140, and the dielectric layer 150 surround the channel region 125A. As shown in Figure 3A.

In some embodiments, the dielectric layer 210 in the region 100A covers the source / drain region 125B, as shown in FIG. 3B. In some embodiments, one of the silicide structures 230 in the XZ plane is sandwiched between the source / drain region 125B in the region 100A and the contact structure 240 in the region 100B, as shown in FIG. 3B .

In some embodiments, the contact electrode includes a silicide structure 230 and a contact structure 240, which are in contact with the source / drain region 125B but do not surround the source / drain region 125B, as shown in FIG. 3B. In some embodiments, the silicide structure 230 and the contact structure 240 cover one surface of the source / drain region 125B, and the dielectric layer 210 covers multiple surfaces of the source / drain region 125B. Taking FIG. 3B as an example, the dielectric layer 210 covers three surfaces S ₆ , S ₇ , and S _{8 of the} source / drain region 125B, but does not cover the surface S _{5 of the} source / drain region 125B. In some embodiments, the dielectric layer 210, the silicide structure 230, and the contact structure 240 surround the source / drain region 125B in the XZ plane, as shown in FIG. 3B.

FIG. 4 is a perspective view of a semiconductor device structure in some embodiments. The structure 400A shown in Fig. 4 is the same as the structures shown in Figs. 1Q, 3A, and 3B. In FIG. 4, some structures of the structure 400A are indicated by dashed lines, and the barrier layer 272, the work function layer 274, the adhesive layer 276, and the metal filling layer 278 are omitted. The structure 400A may be referred to as a transistor structure.

As shown in some embodiments in FIG. 4, the gate stack structure 250 and the contact structure 240 extend from the semiconductor line 125 along the X axis in opposite directions. In some embodiments, the gate stack structure 250 extends in the region 100A along the direction X ₁ and does not cross the boundary between the region 100A and the region 100B. In some embodiments, the contact structure 240 extends in the area 100B along the direction X ₂ and does not cross the boundary between the area 100A and the area 100B. The direction X _{1 is} opposite to the direction X ₂ . In this way, the gate stack structure 250 and the contact structure 240 are substantially parallel to the X axis and do not overlap each other laterally. In some embodiments, the gate stack structure 250 is interleaved with the contact structure 240.

In some embodiments, the gate stack structure 250 surrounds a portion of the semiconductor lines 125. For example, the gate stack structure 250 surrounds three surfaces of the semiconductor line 125. In some embodiments, the contact structure 240 covers the source / drain region 125B of the semiconductor line 125. In some embodiments, the surface of the semiconductor line 125 covered by the contact structure 240 is not coplanar with the surface of the semiconductor line 125 covered by the gate stack structure 250. In some embodiments, the surface of the semiconductor line 125 covered by the contact structure 240 is opposite to the surface of the semiconductor line 125 covered by the gate stack structure 250.

The embodiment of the present invention has many variations and / or adjustments. FIG. 5 is a perspective view of a semiconductor device structure in some embodiments. FIG. 5 is a perspective view of a semiconductor device structure in some embodiments. In the structure 400B shown in FIG. 5 and the structure 400C shown in FIG. 6, some structures are indicated by dashed lines to facilitate understanding. In some embodiments, the materials and / or formation methods of the semiconductor device structures shown in FIGS. 1A to 1Q, 3A, and 3B can also be used in the embodiments shown in FIGS. 5 and 6, and therefore the description is not repeated. The structures 400B and 400C are similar to the structure 400A shown in FIG. 4.

As in some embodiments shown in FIG. 5, the contact structure 240 extending in the area 100B traverses the boundary between the area 100A and the area 100B. For example, the contact structure 240 surrounds a portion of the semiconductor line 125. In some embodiments, the contact structure 240 surrounds three surfaces of the semiconductor line 125. In this way, the gate stack structure 250 and the contact structure 240 extend along the X axis and are parallel to each other, and overlap each other in a small amount laterally. In some embodiments, the surface of the semiconductor line 125 not covered by the contact structure 240 is opposite to the surface of the semiconductor line 125 not covered by the gate stack structure 250 and is not coplanar.

In some embodiments, the silicide structure 230 extends across the boundary between the region 100A and the region 100B and surrounds a portion of the semiconductor line 125. In some embodiments, the silicide structure 230 is discontinuous or disconnected from the source / drain region 125B of the semiconductor line 125.

In some embodiments shown in FIG. 6, the contact structure 240 extends across the boundary between the region 100A and the region 100B and continuously surrounds the semiconductor line 125. In some embodiments, the contact structure 240 does not extend along the gate stack structure 250. In this way, the gate stack structure 250 and the contact structure 240 extend along the X axis and are substantially parallel to each other, and overlap each other in a small amount laterally.

In some embodiments, the silicide structure 230 extends across the boundary between the region 100A and the region 100B and continuously surrounds the semiconductor line 125. In some embodiments, the silicide structure 230 and the source / drain region 125B of the semiconductor line 125 are continuous interfaces.

In the embodiment shown in FIGS. 5 and 6, a portion of the contact structure 240 extending from the region 100B to the region 100A overlaps the gate stack structure 250 in the region 100A laterally. In this way, the parasitic capacitance between the gate stack structure 250 and the contact structure 240 can be greatly reduced.

On the other hand, in the embodiment shown in FIG. 4, the gate stack structure 250 and the contact structure do not overlap each other laterally. In this way, the parasitic capacitance between the gate stack structure 250 and the contact structure 240 in the regions 100A and 100B can be substantially eliminated. In summary, the parasitic capacitance from the gate to the contact in the semiconductor device structure can be suppressed. In this way, the power required by the semiconductor device structure can be reduced, and the operating speed of the semiconductor device structure can be further improved.

In some embodiments, the semiconductor device structure includes an array of a plurality of cells, and the cells include one or more transistor structures. Each transistor structure includes a channel region, a source / drain region, a gate stack structure, and a contact electrode. FIG. 7 is a perspective view of a semiconductor device structure in some embodiments. In order to simplify and explain clearly, FIG. 7 uses one of the units (such as unit 300) as an example. The boundary of the unit 300 is marked with a dashed line to facilitate understanding of its structure.

As in some embodiments shown in FIG. 7, the plurality of semiconductor lines 125 and 125 'in the cell 300 are arranged in a line along the X axis. In some embodiments, the gate stack structure 250 is configured in a line along the Y-axis. In some embodiments, the plurality of gate structures 252 and 252 'are located between the semiconductor lines 125 and 125' and on both sides of the line of the gate stack structure 250.

Each gate stack structure 250 surrounds a portion of the semiconductor lines 125 and 125 '. Gate stack structure 250, 252 and 252 'of each line of the semiconductor surface S ₁ 125 and 125 of each semiconductor lines uncovered' surfaces S ₁ '. In some embodiments, the surface S ₁ of the semiconductor line 125 and the surface S ₁ ′ of the semiconductor line 125 ′ are disposed opposite to each other and away from each other, as shown in FIG. 7.

In some embodiments, the plurality of contact structures 240 and 240 'are arranged in a line along the Y axis. Each contact structure 240 covers the semiconductor line 125 but does not surround the semiconductor line 125. Each contact structure 240 'covers the semiconductor line 125', but does not surround the semiconductor line 125 '. However, the embodiment of the present invention is not limited thereto. The contact structures 240 and 240 'may surround the semiconductor lines 125 and 125', respectively.

In some embodiments, the contact structures 240 and 240 'are staggered with the gate stack structures 250, 252, and 252'. In some embodiments, the gate stack structures 250, 252, and 252 'extend along the X axis and are substantially parallel to the contact structures 240 and 240', but do not overlap with the contact structures 240 and 240 '. In some embodiments, the contact structure 240 extends along the direction X ₁ in the X axis, that is, the contact structure 240 extends away from the gate stack structures 250, 252, and 252 ′ and the semiconductor line 125, as shown in FIG. 7. . The contact structure 240 ′ extends along a direction X ₂ in the X axis, that is, a direction away from the gate stack structures 250, 252, and 252 ′ and the semiconductor line 125 ′. The direction X _{2 is} opposite to the direction X ₁ . As such, the contact structure 240 does not cover the surface S _{7 of the} semiconductor line 125, the contact structure 240 ′ does not cover the surface S ₇ ′ of the semiconductor line 125 ′, and the surface S ₇ faces the surface S ₇ ′.

In some embodiments, the contact structures 240 and 240 'are separated by a distance D ₁ . There is a distance D ₂ between the semiconductor lines 125 and 125 ′. As in some embodiments shown in FIG. 7, the distance D _{1 is} greater than the distance D ₂ . In some embodiments, the distance D1 is substantially the same as the length of one of the gate stack structures 250 extending between the semiconductor lines 125 and 125 '. The embodiments of the present invention are not limited thereto. In some embodiments, the distance D _{1 is} less than or substantially equal to the distance D ₂ .

In some embodiments, no contact structure extends between the gate stack structures 250. In this way, the size of the gate stack structure 250 can be increased to meet requirements. For example, the width of the gate stack structure 250 may be defined along the Y-axis. Since the width of the gate stack structure 250 is increased, the gate stack structure 250 may cover more areas of the semiconductor 125. In this way, a wider channel region can be provided (such as the channel region 125A shown in FIG. 3A).

In some embodiments, no gate stack structure 250 extends between two contact structures 240 or 240 '. In this way, the size of the contact structure 240 or 240 'can be increased to meet requirements. For example, the width of the contact structure 240 or 240 'may be defined along the Y-axis. As the width of the contact structure 240 or 240 'increases, the trench (such as the trench 220 shown in FIG. 1K) may have a lower aspect ratio. The above-mentioned trenches can create spaces in the dielectric layer 210 and can be used later to form the contact structures 240 or 240 '. In summary, it is easier to form the contact structure 240 or 240 '.

In other embodiments, the number of gate stack structures 250, contact structures 240 and 240 ', and semiconductor lines 125 and 125' can be increased to meet requirements. For example, the number of gate stack structures 250, contact structures 240 and 240 ', and semiconductor lines 125 and 125' can be increased to form more transistors in the semiconductor device structure.

In some embodiments, a plurality of n-type field effect transistors or p-type field effect transistors are disposed to be formed in the cell 300. Taking FIG. 7 as an example, the unit 300 includes a plurality of structures 400A shown in FIG. 4. However, the embodiment of the present invention is not limited thereto. In some other embodiments, the unit 300 includes a plurality of structures 400B shown in FIG. 5, a plurality of structures 400C shown in FIG. 6, or other suitable transistor structures. Materials and / or formation methods of the semiconductor device structure shown in FIGS. 1A to 1Q can also be used in the embodiment shown in FIG. 7, and therefore description thereof will not be repeated. Some structures of the semiconductor device structure are not shown in FIG. 7 to facilitate understanding of the structure.

FIG. 7 shows a plurality of structures 400A. Generally, each structure 400A includes a semiconductor line 125 or 125 ', a gate stack structure 250, and two contact structures 240 or 240'. However, in some embodiments, the two structures 400A on the left side of FIG. 7 share the same source / drain region of the semiconductor line 125 and the same contact structure 240. In summary, three contact structures 240 (rather than four contact structures 240) are located on the left side of FIG. 7. The two structures 400A on the left side of FIG. 7 partially overlap each other.

Also in some embodiments, the two structures 400A on the right side of FIG. 7 share the same source / drain region of the semiconductor line 125 ', and the same contact structure 240'. In summary, three contact structures 240 '(instead of four contact structures 240') are located on the right side of FIG. The two structures 400A on the right side of FIG. 7 partially overlap each other.

As in some embodiments shown in FIG. 7, four structures 400A and four gate stacked structures 252 and 252 'form a unit 300. The gate stack structures 252 and 252 '(indicated in bold) in the unit 300 are physically and electrically connected to the semiconductor lines 125 and 125', respectively. The gate stack structures 252 and 252 'are separated from each other. The separate gate stack structures 252 and 252 'can be used to define the boundary of the cell 300 (indicated by dashed lines).

Although FIG. 7 shows a structure 400A in which the unit 300 includes four transistors, the embodiment of the present invention is not limited thereto. In some other embodiments, the semiconductor device structure may include cells having less than four or more than four transistor structures.

Question 8 is a perspective view of the structure of a semiconductor device in some embodiments. As shown in FIG. 8, the cells 300, 310, and 320 form a 1 × 3 array. The boundaries of the units 300, 310, and 320 are marked with dashed lines to facilitate understanding of the structure. In some embodiments, a plurality of complementary field effect transistors (including n-type and p-type field effect transistors) are provided to be formed in the cells 300, 310, and 320. In some other embodiments, only n-type field effect transistors or p-type field effect transistors are provided to be formed in cells 300, 310, and 320.

The settings of the units 310 and 320 are similar to or substantially the same as the settings of the aforementioned unit 300, and thus the description is not repeated. As in some embodiments shown in FIG. 8, the units 300, 310, and 320 are arranged along the X axis. Unit 310 is located between units 300 and 320. In some embodiments, one of the contact structures 240 'in the unit 300 and one of the contact structures 240 in the unit 310 are connected to each other (indicated by bold lines in FIG. 8). One of the contact structures 240 'in the unit 310 and one of the contact structures 240 in the unit 320 are connected to each other (indicated by a bold line in FIG. 8). However, the embodiment of the present invention is not limited thereto. In some other embodiments, the contact structure 240 'in the unit 310 is separate from the contact structure 240 in the unit 320.

As shown in some embodiments in FIG. 8, the gate stack structure 250 in the cell 310 does not extend into the cells 300 and 320. In this way, the gate stack structure 250 in the cells 310 is separated from the gate stack structure 250 in the cells 300 and 320. As shown in some embodiments in FIG. 8, the gate stack structure 250 in the unit 300 and the gate stack structure 250 in the unit 310 are separated by a distance D ₃ . The plurality of contact structures 240 and 240 ′ in some embodiments are disposed between the semiconductor line 125 ′ in the cell 300 and the semiconductor line 125 in the cell 310. The distance between the contact structure 240 ′ in the unit 300 and the contact structure 240 in the unit 310 is D ₄ , as shown in FIG. 8. In some embodiments, in some embodiments, the distance D _{3 is} greater than the distance D ₄ . In some embodiments, the distance D ₃ is substantially the same as the distance between the semiconductor line 125 ′ in the cell 300 and the semiconductor line 125 in the cell 310.

Although FIG. 8 shows a 1 × 3 array of cells, the present invention is not limited thereto. In some other embodiments, the semiconductor device structure may include any suitable array of cells. For example, unit 320 is not provided in some other embodiments. In this way, the semiconductor device structure includes a 1 × 2 array of cells 300 and 310. In some other embodiments, the fourth cell may be formed outside the cell 320 to form a 1 × 4 array of cells. The fourth unit may be substantially the same as the units 300, 310, and 320. The contact structure in the fourth unit may or may not be connected to the contact structure 240 'in the unit 320.

Embodiments of the invention may have many variations and / or adjustments. For example, although FIG. 8 shows a column of cells 300, 310, and 320, other embodiments of the present invention may include multiple columns of cells. FIG. 9 is a perspective view of a semiconductor device structure in some embodiments. Taking FIG. 9 as an example, the cells 300, 301, 310, and 311 form a 2 × 2 array. In some embodiments, the settings of the units 301 and 311 are similar to or substantially the same as the settings of the units 300 and 310, respectively. In this way, the settings of the units 301 and 311 have been described in the embodiments of FIGS. 7 and 8, and therefore will not be described repeatedly.

In some embodiments shown in FIG. 9, the units 300 and 310 are arranged in a row along the X axis, and the units 301 and 311 are arranged in another row along the X axis. In some embodiments, a common semiconductor line 125 is located in the cells 300 and 301. More specifically, the semiconductor lines 125 in the cells 300 and 301 are connected to the gate stack structure 252 (labeled in bold on the left side of FIG. 9), and the gate stack structure 252 covers the semiconductor lines 125. The cells 300 and 301 share the same semiconductor line 125.

Similarly, the cells 300 and 301 share the same semiconductor line 215 '. The semiconductor lines 125 'in the cells 300 and 301 are connected to the gate stack structure 252' (labeled in bold on the left side of FIG. 9), and the gate stack structure 252 'covers the semiconductor line 125'. In some embodiments, the connection between the units 310 and 311 is similar or substantially the same as the connection between the units 300 and 301. In this way, the connection between the units 310 and 311 has been described as above, so the description is not repeated.

In some embodiments, the two gate stack structures 252 and 252 '(shown in bold on the left side of FIG. 9) are separated from each other. The separate gate stack structures 252 and 252 'extend along the boundary between the cells 310 and 311. The above boundary is indicated by a dotted line in FIG. 9. The separate gate stack structures 252 and 252 'may define a boundary between the cells 300 and 301. Similarly, the two gate stack structures 252 and 252 '(shown in bold on the right side of FIG. 9) are separated from each other. The separate gate stack structures 252 and 252 'extend along the boundary between the cells 310 and 311. The separate gate stack structures 252 and 252 'may define a boundary between the cells 310 and 311.

Embodiments of the invention may have many variations and / or adjustments. For example, although the semiconductor device structures shown in FIGS. 1A to 1Q, 2, 3A, 3B, and 4 to 9 have nanowires and metal gate stacks, the embodiments of the present invention are not limited thereto. Some other embodiments of the present invention include semiconductor device structures having nanowires and polycrystalline silicon gate stacks, or another suitable semiconductor device structure.

Embodiments of the present invention form a semiconductor device structure having a nanowire. The semiconductor device structure includes a gate stack structure and a contact electrode electrically connected to the nanowire. The gate stack structure surrounds a portion of the nanowire. The contact electrode and gate electrode stack structure extends in the opposite direction from the nanowire, so the overlapping area between the gate electrode stack structure and the contact electrode electrode can be reduced or substantially eliminated. In this way, the parasitic capacitance between the gate stack structure and the contact electrodes can be alleviated. In addition, the gate-to-contact parasitic capacitance in the semiconductor device structure can be greatly reduced. Therefore, the power required by the semiconductor device structure can be reduced, and the efficiency of the semiconductor device structure can be improved. The embodiments of the present invention can be applied to small-sized low-power devices.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first dielectric layer. The semiconductor device structure also includes a gate stack structure in the first dielectric layer. The semiconductor device structure further includes semiconductor lines, and the gate stack structure surrounds a portion of the semiconductor lines. In addition, the semiconductor device structure includes a contact electrode in the first dielectric layer, and the contact electrode is electrically connected to the semiconductor line. The contact electrode and the gate stack structure extend from the semiconductor line in opposite directions.

In some embodiments, the semiconductor device structure further includes an adhesive layer, which is connected to the gate stack structure and the semiconductor line; and a second dielectric layer, the self-adhesive layer extends along the contact electrode.

In some embodiments, the interface between the gate stack structure and the adhesive layer of the semiconductor device structure is substantially coplanar with the interface between the first dielectric layer and the contact electrode.

In some embodiments, the adhesive layer of the semiconductor device structure extends between the second dielectric layer and the contact electrode, and the adhesive layer is also connected to the contact electrode.

In some embodiments, the semiconductor device structure further includes a spacer unit in the first dielectric layer, wherein the spacer unit covers a sidewall of the gate stack structure and is connected to the contact electrode.

In some embodiments, a portion of the semiconductor line is surrounded by the contact electrodes of the semiconductor device structure.

In some embodiments, the gate stack structure of the semiconductor device structure is substantially parallel to the contact electrodes and does not overlap the contact electrodes.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor line. The semiconductor device structure also includes a second semiconductor line. The semiconductor device structure also includes a gate stack structure extending between the first semiconductor line and the second semiconductor line. The first semiconductor line and the second semiconductor line of the gate stack structure surround a part. In addition, the semiconductor device structure includes a first contact electrode, which is electrically connected to the first semiconductor line. The semiconductor device structure also includes a second contact electrode, which is electrically connected to the second semiconductor line. The first contact electrode and the second contact electrode extend in opposite directions away from each other.

In some embodiments, the gate stack structure of the semiconductor device structure is intersected with the first contact electrode and the second contact electrode.

In some embodiments, the distance between the first contact electrode and the second contact electrode of the semiconductor device structure is greater than the distance between the first semiconductor line and the second semiconductor line.

In some embodiments, the above-mentioned semiconductor device structure further includes a third semiconductor line; a fourth semiconductor line, wherein the third semiconductor line is located between the fourth semiconductor line and the second semiconductor line; and a second gate stack structure extends from the first semiconductor line Between the third semiconductor line and the fourth semiconductor line; and a third contact electrode extending from the third semiconductor line toward the second semiconductor line, wherein the distance between the gate stack structure and the second gate stack structure is greater than the second The distance between the contact electrode and the third contact electrode.

In some embodiments, the distance between the gate stack structure of the semiconductor device structure and the second gate stack structure is substantially the same as the distance between the second semiconductor line and the third semiconductor line.

In some embodiments, a method of forming a semiconductor device structure is provided. The method includes forming a stacked layer including a first dielectric layer and a semiconductor layer that are alternately deposited. The method also includes removing a portion of the stacked layers to form a first trench. The method also includes filling a second dielectric layer into the first trench. In addition, the method includes removing the first dielectric layer and patterning the semiconductor layer to form a semiconductor line. The semiconductor line is bonded to the second dielectric layer. The method also includes forming a third dielectric layer including a second trench; and forming a gate stack structure in the second trench. The gate stack structure surrounds a portion of the semiconductor lines. The method also includes forming a contact electrode to be electrically connected to the semiconductor line.

In some embodiments, the method further includes forming an adhesive layer in the first trench before forming the second dielectric layer, wherein the semiconductor line is bonded to the second dielectric layer through the adhesive layer.

In some embodiments, the method further includes etching the third dielectric layer to form a second trench, wherein in the step of etching the third dielectric layer, the etching rate of the third dielectric layer is greater than that of the second dielectric layer. Etch rate; and after forming the gate stack structure, removing the third dielectric layer.

In some embodiments, the method further includes removing the third dielectric layer after forming the gate stack structure; forming a fourth dielectric layer, wherein the gate stack structure, the semiconductor line, and the second dielectric layer are located at the first Four dielectric layers; and etching the fourth dielectric layer to form a third trench to expose the semiconductor lines, wherein when the fourth dielectric layer is etched, the etching rate of the fourth dielectric layer is greater than the etching rate of the second dielectric layer .

In some embodiments, the method further includes performing an epitaxial growth process on the semiconductor line after etching the fourth dielectric layer.

In some embodiments, the method further includes tempering the semiconductor line after etching the fourth dielectric layer.

In some embodiments, the method of patterning a semiconductor to form a semiconductor line is later than the step of forming a gate stack structure.

In some embodiments, the method further includes forming a spacer unit on a sidewall of the gate stack structure, wherein the semiconductor line is adhered to the second dielectric layer when the spacer unit is formed.

The features of the above-mentioned embodiments are beneficial to those skilled in the art to understand the present invention. Those of ordinary skill in the art should understand that the present invention can be used as a basis for designing and changing other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those with ordinary knowledge in the technical field should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and can be changed, replaced, or changed without departing from the spirit and scope of the patent scope of the present invention. .

Claims (1)

    A semiconductor device structure includes: a first dielectric layer; a gate stack structure located in the first dielectric layer; a semiconductor line and a portion of the semiconductor line surrounding the gate stack structure; and a connection A point electrode is located in the first dielectric layer and is electrically connected to the semiconductor line. The contact electrode and the gate stack structure extend from the semiconductor line in opposite directions.