TW201828419A - Electronic package and method for fabricating the same - Google Patents

Abstract

An electronic package is provided, including a packaging member having a first electronic component, a second electronic component and a conductive post disposed on the packaging member, an encapsulating layer encapsulating the second electronic component and the conductive post, and a second circuit structure disposed on the encapsulating layer, wherein the second electronic component is stacked on the first electronic component. Therefore, the electronic package has a planer area reduced. A method for fabricating the electronic package is also provided.

Description

 Electronic package and its manufacturing method  

The present invention relates to a semiconductor packaging technology, and more particularly to an electronic package and a method of fabricating the same.

With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements of miniaturization of electronic packages, a technology of Chip Scale Package (CSP) has been developed.

1A to 1E are schematic cross-sectional views showing a manufacturing method of a conventional semiconductor package 1.

As shown in FIG. 1A, a thermal release tape 100 is formed on a carrier 10.

Next, a plurality of semiconductor wafers 11 are disposed on the thermalized release layer 100. The semiconductor wafers 11 have opposite active and non-active surfaces 11a, each of which has a plurality of electrode pads 110 thereon. Each of the active surfaces 11a is adhered to the heated release layer 100.

As shown in FIG. 1B, an encapsulant 14 is formed on the thermal release layer 100 to coat the semiconductor wafer 11.

As shown in FIG. 1C, the encapsulant 14 is baked to harden the thermal release layer 100 to remove the thermal release layer 100 and the carrier 10, so that the active surface 11a of the semiconductor wafer 11 is exposed. .

As shown in FIG. 1D, a wiring structure 16 is formed on the encapsulating body 14 and the active surface 11a of the semiconductor wafer 11, so that the wiring structure 16 is electrically connected to the electrode pad 110. Next, an insulating protective layer 18 is formed on the wiring structure 16, and the insulating protective layer 18 exposes a portion of the surface of the wiring structure 16 for bonding the conductive elements 17 such as solder balls.

As shown in FIG. 1E, a singulation process is performed along the dicing path L as shown in FIG. 1D to obtain a plurality of CSP package structure semiconductor packages 1 which are electrically connected to a Motherboard.

However, in order to meet the versatility and high efficiency requirements of the terminal product, the conventional semiconductor package 1 is formed by forming a plurality of semiconductor wafers 11 on the same plane during the singulation process (as shown in FIG. 1E). The planar area of the overall package structure is too large, so it is difficult to reduce the volume of the end product.

Therefore, how to reduce the volume of a conventional multi-chip semiconductor package has become a problem to be solved.

In view of the above-mentioned prior art, the present invention provides an electronic package comprising: a first line structure having opposite first and second sides; and a plurality of conductive columns formed in the first line structure The first circuit structure is electrically connected to the first circuit structure; the first electronic component is disposed on the first side of the first circuit structure; the encapsulation layer is coated with the first electronic component; and the second electronic component is The second layer is disposed on the second side of the first circuit structure; the cladding layer covers the second electronic component and the conductive pillar; and the second circuit structure is formed on the cladding layer and electrically connected to the conductive layer a post and the second electronic component.

The invention also provides a method for manufacturing an electronic package, comprising: providing a package member, comprising a first line structure having a first side and a second side opposite to each other, disposed on a first side of the first line structure a first electronic component and an encapsulation layer encapsulating the first electronic component; a second electronic component is disposed on the second side of the first circuit structure, and a plurality of electrically conductive columns electrically connected to the first circuit structure are formed; Coating a second electronic component and the conductive pillar; and forming a second wiring structure electrically connected to the conductive pillar and the second electronic component on the cladding layer.

The invention further provides a method for manufacturing an electronic package, comprising: providing a package member, comprising a first line structure having a first side and a second side opposite to each other, disposed on a first side of the first line structure a first electronic component and an encapsulation layer encapsulating the first electronic component; a second electronic component disposed on the second side of the first circuit structure; and forming a cladding covering the second electronic component and having a plurality of perforations a conductive pillar electrically connected to the first wiring structure is formed in the through hole; and a second wiring structure electrically connecting the conductive pillar and the second electronic component is formed on the cladding layer.

In the foregoing electronic package and method of manufacturing the same, the first circuit structure includes a conductive blind via to electrically connect the first electronic component.

In the foregoing electronic package and method of manufacturing the same, the first electronic component is an active component, a passive component, or a combination thereof.

In the above electronic package and method of manufacturing the same, one of the surfaces of the first electronic component is exposed to the encapsulation layer.

In the above electronic package and the method of manufacturing the same, the first electronic component and the second electronic component have opposite active and non-active surfaces, and the active surface of the first electronic component and the active surface of the second electronic component The same direction.

In the foregoing electronic package and method of manufacturing the same, the second electronic component is an active component, a passive component, or a combination thereof.

In the above electronic package and method of manufacturing the same, the second circuit structure includes a conductive via hole for electrically connecting the second electronic component and the conductive pillar.

In the foregoing electronic package and method of manufacturing the same, the method further comprises forming a plurality of conductive elements on the second line structure.

It can be seen that the electronic package of the present invention and the method for manufacturing the same are mainly provided with a first electronic component and a second electronic component on the first side and the second side of the first circuit structure to form a three-dimensional stacked design. Therefore, compared with the design of the multi-wafer plane layout of the conventional semiconductor package, the invention can greatly reduce the planar area of the electronic package and meet the requirements of multifunctionality and high efficiency.

1‧‧‧Semiconductor package

10‧‧‧ Carrier

100‧‧‧heating release layer

11‧‧‧Semiconductor wafer

11a, 21a, 22a‧‧‧ action surface

11b, 21b, 22b‧‧‧ non-active surface

110,210,210',220‧‧‧electrode pads

14‧‧‧Package colloid

16‧‧‧Line structure

17,27‧‧‧Conducting components

18,28‧‧‧Insulating protective layer

2‧‧‧Electronic package

2a‧‧‧Package components

20‧‧‧First line structure

20a‧‧‧ first side

20b‧‧‧ second side

200‧‧‧First insulation

201‧‧‧First line redistribution

202‧‧‧First conductive blind hole

21, 21' ‧ ‧ first electronic components

22‧‧‧Second electronic components

221‧‧‧bonding layer

222‧‧‧Electrical conductor

23‧‧‧conductive column

24,24’‧‧‧Encapsulation layer

25‧‧‧Cladding

250‧‧‧Perforation

251‧‧ ‧ blind holes

26‧‧‧Second line structure

260,260'‧‧‧Second insulation

261,261’‧‧‧Second line redistribution

262‧‧‧Second conductive blind hole

270‧‧‧ Metal layer under the bump

280‧‧‧ openings

L, S‧‧‧ cutting path

1A to 1E are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package; 2A to 2E are schematic cross-sectional views showing a method of fabricating the electronic package of the present invention; and FIG. 2C' is another embodiment of FIG. 2C A schematic cross-sectional view of an example; and a 2E' diagram is a schematic cross-sectional view of another embodiment of FIG. 2E.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2A to 2E are schematic cross-sectional views showing the manufacturing method of the electronic package 2 of the present invention.

As shown in Fig. 2A, a package member 2a is provided which includes a first wiring structure 20, at least one first electronic component 21, 21' and an encapsulation layer 24.

In the present embodiment, the method of fabricating the package member 2a can be referred to the method as shown in FIGS. 1A to 1E, but is not limited thereto.

The first line structure 20 has a first side 20a and a second side 20b opposite to each other. In this embodiment, the first circuit structure 20 includes at least one first insulating layer 200, a first redistribution layer (RDL) 201 disposed on the first insulating layer 200, and a plurality of The first conductive blind hole 202 is electrically connected to the first conductive layer 200 and electrically connected to the first conductive blind via 201. For example, the material forming the first circuit redistribution layer 201 and the first conductive blind via 202 is copper, and the material forming the first insulating layer 200 is, for example, polybenzoxazole (PBO). A dielectric material such as polyimide (PI) or prepreg (PP).

Furthermore, an insulating protective layer 28 such as a solder resist layer is selectively formed on the second side 20b of the first wiring structure 20, and a plurality of openings 280 are formed in the insulating protective layer 28.

The first electronic component 21, 21' is bonded to the first side 20a of the first line structure 20. In this embodiment, the first electronic component 21, 21' is an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, if the first electronic component 21 is a semiconductor wafer, it has an opposite active surface 21a and an inactive surface 21b. The active surface 21a has a plurality of electrode pads 210 for electrically connecting the first conductive blind vias 202. If the first electronic component 21' is a passive component, it has a plurality of electrode pads 210' to electrically connect the first conductive vias 202.

The encapsulation layer 24 is formed on the first side 20a of the first line structure 20 to cover the first electronic components 21, 21'. In this embodiment, the encapsulation layer 24 is an insulating material, such as a polyimide (PI), a dry film, an epoxy resin encapsulant or an encapsulant ( A molding compound, which may be formed on the first side 20a of the first wiring structure 20 by lamination or molding.

As shown in FIG. 2B, the second electronic component 22 is disposed on the second side 20b (or the insulating protective layer 28) of the first line structure 20 of the package member 2a by using the package member 2a as a support structure, and A plurality of conductive posts 23 electrically connected to the first line structure 20 are formed on the second side 20b of the first line structure 20.

In this embodiment, the conductive pillars 23 are disposed on the first circuit redistribution layer 201 in the opening 280 and electrically connected to the first circuit redistribution layer 201, and the material of the conductive pillars 23 is Such as copper metal or solder.

Furthermore, the second electronic component 22 is an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the second electronic component 22 is a semiconductor wafer having an opposite active surface 22a and an inactive surface 22b. The second electronic component 22 is adhered to the non-active surface 22b by a bonding layer 221. On the second side 20b of the circuit structure 20, the active surface 22a has a plurality of electrode pads 220, and the electrode pads 220 are bonded and electrically connected to the plurality of electrical conductors 222. Specifically, the conductor 222 is in the shape of a ball of a solder ball, or a columnar shape of a metal material such as a copper post or a solder bump, or a stud made by a wire bonding machine, but is not limited thereto.

Moreover, the electrical conductors 222 can be fabricated or separately fabricated together with the conductive pillars 23 as needed.

As shown in FIG. 2C, a cladding layer 25 is formed on the second side 20b (or the insulating protective layer 28) of the first wiring structure 20, so that the cladding layer 25 covers the second electronic component 22. The conductive body 222 and the conductive pillars 23 are further flattened so that the upper surface of the cladding layer 25 is flush with the end faces of the conductive pillars 23 and the upper surfaces of the conductive bodies 222. The cladding layer 25 is exposed on the end surfaces of the conductive pillars 23 and the upper surfaces of the conductors 222.

In this embodiment, the cladding layer 25 is an insulating material, such as a polyimide (PI), a dry film, an epoxy resin, or an encapsulant. (molding compound), which may be formed on the second side 20b of the first circuit structure 20 by lamination or molding, and the material of the cladding layer 25 and the material of the encapsulation layer 24 may be Same or different.

Moreover, the leveling process removes part of the material of the cladding layer 25 by grinding (the conductive pillar 23 or even part of the conductor 222 may be removed as needed).

It should be understood that, as shown in FIG. 2C', the cladding layer 25 may be formed on the second side 20b of the first circuit structure 20, and the plurality of vias 250 and the plurality of vias 250 may be formed in the cladding layer 25. The blind hole 251 is formed such that a part of the surface of the first circuit redistribution layer 201 of the second side 20b is exposed to the through holes 250, and the electrode pads 220 are exposed to the blind holes 251, and then, for example, by electroplating or In the deposition mode, the conductive pillar 23 is formed in the through hole 250, and the conductive body 222 is formed in the blind hole 251 to form a structure as shown in FIG. 2C.

As shown in FIG. 2D, a second line structure 26 is formed on the cladding layer 25, and the second line structure 26 is electrically connected to the conductive pillars 23 and the conductors 222.

In this embodiment, the second circuit structure 26 includes a plurality of second insulating layers 260, 260', a plurality of second line redistribution layers (RDL) 261, 261' disposed on the second insulating layer 260, 260', and a plurality of The second conductive layer 260, 260' is electrically connected to the second conductive via 262 of the second circuit redistribution layer 261, 261', and the conductive pillars 23 are electrically connected to the second conductive via 262. The conductor 222, and the outermost second insulating layer 260' can serve as a solder resist layer to expose a portion of the surface of the outermost second line redistribution layer 261' to the solder resist layer. Alternatively, the second line structure 26 may also include only a single second insulating layer 260 and a single second line redistribution layer 261.

Furthermore, the second circuit redistribution layer 261, 261' and the second conductive blind via 262 are made of copper, and the second insulating layer 260, 260' is made of, for example, poly-p-oxazobenzene (PBO). Polyimide (PI), prepreg (PP) dielectric material.

As shown in FIG. 2E, a singulation process is performed along the dicing path S as shown in FIG. 2D, and a plurality of conductive elements 27 such as solder balls are formed on the second line redistribution layer 261' of the outermost layer for subsequent use. Attached to other structures (such as package structures, boards or wafers).

In this embodiment, an under bump metallurgy (UBM) 270 may be formed on the outermost second line redistribution layer 261' to facilitate bonding of the conductive element 27.

In another embodiment, as shown in FIG. 2E', the surface of the encapsulation layer 24' can be flushed with the non-active surface 21b of the first electronic component 21 by a leveling process (such as a polishing method). The inactive surface 21b of the first electronic component 21 exposes the encapsulation layer 24'.

Therefore, the electronic package of the present invention is formed by the first electronic component 21, 21' and the second electronic component 22 on the first side 20a and the second side 20b of the first circuit structure 20, respectively. Compared with the multi-wafer plane layout design of the conventional semiconductor package, the method of the present invention can greatly reduce the planar area of the electronic package 2 and meet the requirements of multifunctionality and high efficiency.

The invention also provides an electronic package 2 comprising: a first circuit structure 20, at least one first electronic component 21, 21', an encapsulation layer 24, 24', at least a second electronic component 22, a cladding Layer 25 and a second line structure 26.

The first circuit structure 20 has a first side 20a and a second side 20b opposite to each other, and the second side 20b is formed with a plurality of conductive posts 23 electrically connected to the first line structure 20.

The first electronic component 21, 21' is bonded to the first side 20a of the first line structure 20.

The encapsulation layers 24, 24' are formed on the first side 20a of the first wiring structure 20 such that the encapsulation layers 24, 24' envelop the first electronic components 21, 21'.

The second electronic component 22 is disposed on the second side 20b of the first line structure 20.

The cover layer 25 is formed on the second side 20b of the first circuit structure 20 to cover the second electronic component 22 and the conductive pillars 23, and expose the end surface of the conductive pillar 23 to the Coating layer 25.

The second circuit structure 26 is formed on the cladding layer 25, and the second circuit structure 26 is electrically connected to the conductive pillar 23 and the second electronic component 22 (or the conductor 222).

In one embodiment, the first circuit structure 20 includes a plurality of first conductive vias 202 for electrically connecting the first electronic components 21, 21'.

In one embodiment, the first electronic component 21, 21' is an active component, a passive component, or a combination thereof.

In one embodiment, the inactive surface 21b of the first electronic component 21 exposes the encapsulation layer 24'.

In an embodiment, the active surface 21a of the first electronic component 21 and the active surface 22a of the second electronic component 22 are oriented in the same direction.

In an embodiment, the second electronic component 22 is an active component, a passive component, or a combination thereof.

In an embodiment, the second circuit structure 26 includes a plurality of second conductive vias 262 for electrically connecting the second electronic component 22 and the conductive pillars 23 .

In one embodiment, the electronic package 2 includes a plurality of conductive elements 27 formed on the second line structure 26 and electrically connected to the second line structure 26 .

In summary, the electronic package of the present invention is formed by first and second electronic components on the first side and the second side of the first circuit structure to form a three-dimensional stack. The design can greatly reduce the planar area of the electronic package and meet the requirements of versatility and high efficiency.

The above-described embodiments are intended to illustrate the principles of the invention and its advantages, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

Claims (19)

 An electronic package includes: a first circuit structure having opposite first and second sides; and a plurality of conductive pillars formed on a second side of the first circuit structure and electrically connected to the first line a first electronic component disposed on a first side of the first circuit structure; an encapsulation layer encapsulating the first electronic component; and a second electronic component disposed on a second side of the first circuit structure a cladding layer covering the second electronic component and the conductive pillar; and a second wiring structure formed on the cladding layer and electrically connecting the conductive pillar and the second electronic component.    The electronic package of claim 1, wherein the first circuit structure comprises a plurality of conductive blind holes electrically connected to the first electronic component.    The electronic package of claim 1, wherein the first electronic component is an active component, a passive component, or a combination thereof.    The electronic package of claim 1, wherein the surface of one of the first electronic components exposes the encapsulation layer.    The electronic package of claim 1, wherein the first electronic component and the second electronic component have opposite active and non-active surfaces, and the active surface of the first electronic component and the second The active surfaces of the electronic components are oriented in the same direction.    The electronic package of claim 1, wherein the second electronic component is an active component, a passive component, or a combination thereof.    The electronic package of claim 1, wherein the second circuit structure comprises a plurality of conductive blind holes electrically connected to the second electronic component.    The electronic package of claim 1, wherein the second circuit structure comprises a plurality of conductive blind holes electrically connected to the conductive pillar.    The electronic package of claim 1, further comprising a plurality of conductive elements formed on the second line structure.    An electronic package manufacturing method includes: providing a package member, comprising a first line structure having a first side and a second side opposite to each other, and a first electron disposed on a first side of the first line structure An element and an encapsulation layer encapsulating the first electronic component; a second electronic component is disposed on the second side of the first circuit structure; and a plurality of conductive pillars electrically connected to the first circuit structure are formed; The second electronic component and the conductive pillar; and a second wiring structure electrically connected to the conductive pillar and the second electronic component is formed on the cladding layer.    An electronic package manufacturing method includes: providing a package member, comprising a first line structure having a first side and a second side opposite to each other, and a first electron disposed on a first side of the first line structure An element and an encapsulation layer encapsulating the first electronic component; a second electronic component disposed on a second side of the first circuit structure; and a second electronic component is formed on the second side of the first circuit structure a plurality of perforated cladding layers; forming a conductive pillar electrically connected to the first wiring structure; and forming a second wiring structure electrically connected to the conductive pillar and the second electronic component on the cladding layer.    The method of manufacturing the electronic package of claim 10, wherein the first circuit structure comprises a plurality of conductive blind holes electrically connected to the first electronic component.    The method of manufacturing an electronic package according to claim 10, wherein the first electronic component is an active component, a passive component, or a combination thereof.    The method of manufacturing an electronic package according to claim 10, wherein the surface of one of the first electronic components exposes the encapsulation layer.    The method of manufacturing the electronic package of claim 10 or 11, wherein the first electronic component and the second electronic component have opposite active and non-active surfaces, and the active surface of the first electronic component The acting surfaces of the second electronic component are oriented in the same direction.    The method of manufacturing an electronic package according to claim 10, wherein the second electronic component is an active component, a passive component, or a combination thereof.    The method of manufacturing the electronic package of claim 10, wherein the second circuit structure comprises a plurality of conductive blind holes electrically connected to the second electronic component.    The method of manufacturing the electronic package of claim 10, wherein the second circuit structure comprises a plurality of conductive blind holes electrically connected to the conductive pillar.    The method of manufacturing an electronic package according to claim 10 or 11, further comprising forming a plurality of conductive elements on the second line structure.