TW201828305A - Memory device and power control circuit thereof - Google Patents

Abstract

A memory device comprises a power control circuit and a non volatile memory circuit. The power control circuit is used to receive a mode switching signal and generate a power supply voltage value accordingly. When the memory device is operated in a power down mode, the power supply voltage value is a sum of a threshold voltage of a first transistor and a source/drain cross voltage of a second transistor. The non volatile memory circuit is electrically coupled to the power control circuit to store a plurality of data and receive the power supply voltage value.

Description

Memory device and its power control circuit

The present invention relates to a memory device, and more particularly to a memory device including a power supply control circuit and capable of reducing leakage current.

Flash memory is a non-volatile memory that allows it to be erased or written multiple times during operation. It has the advantages of fast transmission speed, low power consumption and long service life, and is widely used in various electronic applications. Products such as cell phones, lithographs, digital cameras, etc. Modern people rely heavily on mobile devices, so the endurance of mobile devices is becoming more and more important. However, as the flash memory system process becomes more complicated due to the demand, the corresponding leakage current increases relatively. Therefore, how to effectively reduce the flash The leakage current of the memory has become an issue that researchers in the field have paid attention to.

In order to solve the above drawbacks, the present invention provides a memory device capable of reducing leakage current thereof.

The memory device provided by the present invention includes a power control circuit and a non-volatile memory circuit. The power control circuit is configured to receive the mode switching signal, and generate a power voltage value according to the mode switching signal. When the memory device operates in a deep power saving mode, the power voltage value is a threshold voltage of the first transistor and a source of the second transistor. / The sum of the bungee cross pressure. The non-volatile memory circuit is electrically coupled to the power control circuit for storing a plurality of data, the non-volatile memory circuit and receiving the power voltage value.

In an embodiment, the power control circuit includes a signal generating unit, a third transistor, a fourth transistor, a fifth transistor, a voltage dividing impedance, and a switching unit in addition to the first transistor and the second transistor. . The signal generating unit is configured to receive the mode switching signal, and generate the first control signal, the second control signal, and the third control signal according to the mode switching signal. The third transistor has a first end, a control end and a second end. The first end of the third transistor is configured to receive an external power supply voltage value, and the control end of the third transistor is electrically coupled to the signal generating unit and received The first control signal, the second end of the third transistor is used to output a power voltage value. The fourth transistor has a first end, a control end and a second end. The first end of the fourth transistor receives an external power supply voltage value, and the control end of the fourth transistor is electrically coupled to the signal generating unit and receives the second Control signal. The voltage dividing impedance has a first end and a second end, and the first end of the voltage dividing impedance is electrically coupled to the second end of the fourth transistor. The switch unit has a first end, a control end and a second end. The first end of the switch unit is electrically coupled to the second end of the voltage dividing impedance, and the control end of the switch unit is electrically coupled to the signal generating unit for receiving A third control signal. The fifth transistor has a first end, a control end and a second end. The first end of the fifth transistor is electrically coupled to the first end of the voltage dividing impedance, and the control end of the fifth transistor and the second end of the switch unit The second end of the fifth transistor is electrically coupled to the second end of the third transistor. The first transistor has a first end, and the control end has a second end. The first end of the first transistor is electrically coupled to the second end of the switch unit, and the control end of the first transistor is coupled to the first transistor. The second end is electrically coupled. The second transistor has a first end, a control end and a second end. The first end of the second transistor is electrically coupled to the second end of the first transistor, and the control end of the second transistor and the fifth transistor The second end of the second transistor is electrically coupled to the low voltage level.

The solution to the above problem is to provide a lower power supply voltage value to the non-volatile memory circuit when the memory device is operated in the deep power saving mode, and the power supply voltage value at this time is the same. The sum of the threshold voltage of a transistor and the source/drain voltage across the second transistor, so the non-volatile memory circuit can have a lower leakage current corresponding to the supply voltage value.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Please refer to FIG. 1. FIG. 1 is a schematic diagram of an embodiment of a memory device 10 according to the present invention. The memory device 10 includes a power control circuit 11 and a non-volatile memory circuit 12. The power control circuit 11 is used to provide non-volatile memory. The supply voltage value V _D2 required by the circuit 12 is such that the non-volatile memory can operate normally according to the supply voltage value V _D2 .

The non-volatile memory circuit 12 is operative to receive the fixed supply voltage value V _DD and the supply voltage value V _D2 described above to provide the desired voltage value to the internal components. The non-volatile memory circuit 12 may include the control unit 121, the logic unit 122, the memory cell unit 123, and the temporary storage unit 124, but is not limited thereto. The control unit 121 is configured to receive a plurality of control signals S _C , data signals S _D and a plurality of address signals S _A , and the control signals S _{C are,} for example, read/write operation signals of the non-volatile memory circuit 12 and mode switching signals. A control signal such as S _{M for} controlling the operation of the non-volatile memory circuit 12. The data signal S _D can be a data signal to be written into the non-volatile memory circuit 12 or read by the non-volatile memory circuit 12, and the address signal S _A can be stored in the non-volatile memory circuit 12 Or an address signal read by the non-volatile memory circuit 12. The logic unit 122 is electrically coupled to the control unit 121. The logic unit 122 is configured to control the physical address in the memory cell unit 123. The control unit 121 can decode the 123 in the logic unit 122 according to the received logical address. Corresponding memory cell unit. The temporary storage unit 124 is electrically coupled to the control unit 121 and can be used to store circuit setting parameters and related data required for the operation of the non-volatile memory circuit 12, such as memory cell read, write, and erase related voltage settings. For the value and timing control set value, etc., the control unit 121 can read the above-mentioned circuit setting parameters by the temporary storage unit 124 to make the non-volatile memory circuit 12 operate normally.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of an embodiment of a power supply control circuit 11. The power supply control circuit 11 receives a fixed power supply voltage value V _DD , an external power supply voltage value V _{D1 ,} and the above mode switching signal S _M , which is fixed in this embodiment. The voltage value of the power supply voltage value V _DD is greater than the external power supply voltage value V _D1 . The power control circuit 11 further includes a signal generating unit 111, a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a voltage dividing resistor R1, and a switching unit SW.

The signal generating unit 111 is configured to receive the fixed power voltage value V _DD and the mode switching signal S _M , wherein the fixed power voltage value V _DD is an operating voltage of the signal generating unit 111, and the signal generating unit 111 switches the signal according to the mode. _M generates a control signal S ₁ , a control signal S _{2 ,} and a control signal S ₃ . The transistor T1 has a first end, a second end and a control end. The first end of the transistor T1 is for receiving an external power supply voltage value V _D1 , and the control end of the transistor T1 is for receiving the control signal S ₁ , the transistor T1 The second end is configured to output the above-mentioned power supply voltage value V _D2 . The transistor T2 has a first end, a second end and a control end. The first end of the transistor T2 is for receiving an external power supply voltage value V _D1 , and the control end of the transistor T2 is for receiving the control signal S ₂ , the transistor T2 The second end is electrically coupled to the voltage dividing resistor R1. The voltage dividing resistor R1 has a first end and a second end. The first end of the voltage dividing resistor R1 is electrically coupled to the second end of the transistor T2, and the second end of the voltage dividing resistor R1 is electrically connected to the switching unit SW. The coupling, wherein the voltage dividing impedance R1 can be implemented by a single or a plurality of resistive elements or P-type transistors, such as a series of resistive elements or P-type transistors, but not limited thereto.

The switch unit SW has a first end, a control end and a second end. The first end of the switch unit SW is electrically coupled to the second end of the voltage dividing resistor R1, and the control end of the switch unit SW is electrically coupled to the signal generating unit 111. Connected to receive the control signal S ₃ , the second end of the switch unit SW is electrically coupled to the transistor T3 and the transistor T4, and the switch unit SW is configured to determine whether to turn on the first end according to the control signal S ₃ and The two ends, wherein the switch unit SW can be implemented by a transmission gate or a P-type transistor to conduct an electronic component having a lower voltage across the second step, so as to prevent the voltage of the second terminal from being too low when the switch unit SW is turned on. The transistor T3 has a first end, a control end and a second end. The first end of the transistor T3 is electrically coupled to the first end of the voltage dividing resistor R1, and the control end of the transistor T3 and the second end of the switch unit SW The second end of the transistor T3 is electrically coupled to the second end of the transistor T1, wherein the transistor T3 can be a native transistor. The transistor T4 has a first end, a control end and a second end. The first end of the transistor T4 is electrically coupled to the second end of the switch unit SW, and the control end of the transistor T4 is electrically connected to the second end of the transistor T4. Sexual coupling. The transistor T5 has a first end, a control end and a second end. The first end of the transistor T5 is electrically coupled to the second end of the transistor T4, and the control end of the transistor T5 is electrically connected to the second end of the transistor T3. coupled, transistor T5 and a second level V _SS terminal is electrically coupled to a low voltage, the low voltage level V _SS is lower than the voltage level of the fixed power supply voltage V _DD of, for example, ground. In this embodiment, the transistor T1, the transistor T2, and the transistor T4 may be P-type transistors, and the transistor T5 may be an N-type transistor. In other embodiments, the power control circuit 11 further includes an impedance R2 having a first end and a second end, the first end of the impedance R2 being electrically coupled to the control end of the transistor T5, and the second end of the impedance R2 The terminal is electrically coupled to the second end of the transistor T3, and the impedance R2 can be used to adjust the voltage level of the control terminal of the transistor T5. The impedance R2 can be implemented by a single or multiple resistor elements or a P-type transistor, such as a resistor. A string of components or P-type transistors, but not limited to this.

Next, the operation of the memory device 10 of the present invention will be further described with reference to FIG. When the memory device 10 operates in the normal mode, that is, the operation mode in which the memory device 10 normally performs reading and writing of data. The signal generating unit 111 and the control unit 121 of FIG. 2 determine that the current mode of operation is in the normal mode according to the mode switching signal S _{M. The} signal generating unit 111 enables the control signal S ₁ to be enabled, and the control signal S ₂ and the control signal S ₃ are disabled. Therefore, the transistor T2 and the switching unit SW are turned off, the transistor T1 is turned on, and the first terminal and the second terminal of the external power source voltage value V _{D1 being} turned on through the transistor T1 are outputted as the power source voltage value V _D2 .

When the memory device 10 operates in the deep power saving mode, that is, the memory device 10 does not perform reading and writing of data, and maintains the power consumption of the internal electronic components to the lowest mode. The signal generating unit 111 and the control unit 121 of FIG. 2 determine that the current operating mode is in the deep power saving mode according to the mode switching signal S _{M. The} signal generating unit 111 disables the control signal S ₁ , and the control signal S ₂ and the control signal S ₃ are Therefore, the transistor T1 is turned off, and the second terminal of the transistor T1 does not output the power supply voltage value V _D2 . At the same time, the transistor T2 is turned on by the control signal S ₂ , and the external power supply voltage value V _{D1 is} transmitted through the transistor T2 to the voltage dividing impedance R1 and the first end of the transistor T3, and the switching unit SW is turned on by the control signal S ₃ , the transistor T3 is thus turned on. At this time, the transistor T5 is turned on because of the voltage level of its control terminal, thereby maintaining the first end of the transistor T5 at a low voltage level, and the transistor T4 is accordingly turned on, and the voltage level of the first end of the transistor T4 is thus The threshold voltage across transistor T5 is maintained plus the sum of the voltages across the first end of the transistor T4 (one of the source/drain) and the second end (the other of the source/drain). At the same time, since the transistor T3 is a primary transistor, the voltage level of the second terminal can be equal to the voltage level of its control terminal. Therefore, the voltage value of the power supply voltage value V _D2 at this time will be the threshold voltage of the transistor T5 plus the transistor T4. The sum of the voltage across the first end (one of the source/drain) and the second end (the other of the source/drain).

Therefore, according to the above, when the memory device 10 is in the deep power saving mode, the voltage value of the power supply voltage value V _D2 received by the non-volatile memory circuit 12 is converted from the external power supply voltage value V _D1 to the threshold voltage of the transistor T5. The sum of the voltage across the first end (one of the source/drain) and the second end (the other of the source/drain) of the transistor T4, that is, the power supply voltage value V _D2 in the depth province In the electrical mode, the voltage is converted to a relatively low voltage value. Therefore, when the electronic components inside the non-volatile memory circuit 12 generate a leakage current, the leakage current thereof is greatly reduced according to the decrease of the power supply voltage value V _D2 . In addition, in some embodiments, when the temporary storage unit 124 operates in the deep power saving mode, the temporary storage unit 124 needs to additionally receive the mode switching signal S _M , and the temporary storage unit 124 needs to delete the stored data. Operating in the deep power saving mode, and when the memory device 10 is again operating in the normal mode, the temporary storage unit 124 needs to read the required parameters or data again to facilitate the normal operation of the memory device 10. And the memory device of the present invention the body 10, the temporary storage unit 124 when it is operating in deep power saving mode, without receiving the above-described mode switching signal S _M need not delete stored data, and by providing a lower depth in the power saving mode when The power supply voltage value V _D2 can not only effectively reduce the leakage current of the temporary storage unit 124, but also maintain the temporary storage unit 124 in the current storage state. Therefore, when the memory device 10 operates in the normal mode again, the temporary storage unit 124 immediately The parameters and information required for the operation can be provided to accelerate the execution speed of the memory device 10.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10‧‧‧ memory device

11‧‧‧Power Control Circuit

111‧‧‧Signal generating unit

12‧‧‧Non-volatile memory circuits

121‧‧‧Control unit

122‧‧‧Logical unit

123‧‧‧ memory cell unit

124‧‧‧Scratch unit

V _DD ‧‧‧fixed power supply voltage value

V _D1 ‧‧‧External power supply voltage value

V _D2 ‧‧‧Power supply voltage value

Mode switch signal S _M ‧‧‧

S _C ‧‧‧Control signal

S _D ‧‧‧Information Signal

S _A ‧‧‧ address signal

S ₁ , S ₂ , S ₃ ‧‧‧ control signals

T1, T2, T3, T4, T5‧‧‧ transistors

R1‧‧‧voltage impedance

R2‧‧‧ impedance

SW‧‧‧Switch unit

V _SS ‧‧‧low voltage level

1 is a schematic diagram of an embodiment of a memory device of the present invention. 2 is a schematic diagram of an embodiment of a power control circuit of the present invention.

Claims (7)

A memory device includes: a power control circuit for receiving a mode switching signal, and generating a power voltage value according to the mode switching signal, when the memory device operates in a deep power saving mode, the power voltage value a sum of a threshold voltage of a first transistor and a source/drain voltage of a second transistor; and a non-volatile memory circuit electrically coupled to the power control circuit for Storing a plurality of materials, the non-volatile memory circuit and receiving the power voltage value. The memory device of claim 1, wherein the power control circuit comprises: a signal generating unit configured to receive the mode switching signal, and generate a first control signal, a second according to the mode switching signal a control signal and a third control signal; a third transistor having a first end, a control end and a second end, the first end of the third transistor receiving an external power supply voltage value, The control terminal of the third transistor is electrically coupled to the signal generating unit and receives the first control signal, the second end of the third transistor is configured to output the power voltage value; a fourth transistor The first end of the fourth transistor receives the external power supply voltage value, and the control end of the fourth transistor and the signal generating unit are electrically connected. The first control signal is coupled to the second control signal Connected; a switch unit having a The first end of the switch unit is electrically coupled to the second end of the voltage dividing impedance, and the control end of the switch unit is electrically coupled to the signal generating unit Receiving the third control signal; a fifth transistor having a first end, a control end, and a second end, the first end of the fifth transistor and the first end of the voltage dividing impedance The second end of the fifth transistor is electrically coupled to the second end of the fifth transistor, and the second end of the fifth transistor and the second end of the third transistor are electrically coupled Electrically coupled; the first transistor has a first end, a control end, and a second end, the first end of the first transistor is electrically coupled to the second end of the switch unit, The control end of the first transistor is electrically coupled to the second end of the first transistor; and the second transistor has a first end, a control end, and a second end. The first end of the second transistor is electrically coupled to the second end of the first transistor, and the control end of the second transistor The second end of the five transistor coupled to the second terminal of the second transistor and a low level voltage is electrically coupled. The memory device of claim 2, wherein the switching unit is a transmission gate or a P-type transistor. The memory device of claim 2, wherein the fifth transistor is a native transistor. The memory device of claim 2, wherein when the memory device operates in the deep power saving mode, the third transistor is turned off according to the first control signal, and the fourth transistor is The second control signal is turned on, and the switch unit is turned on according to a third control signal. The memory device of claim 2, wherein when the memory device operates in a general mode, the third transistor is turned on according to the first control signal, and the fourth transistor is in accordance with a second control The signal is turned off, and the switch unit is turned off according to a third control signal. The memory device of claim 1, wherein the voltage dividing impedance is a series of resistive elements or P-type transistors.