TW201822468A - Two-terminal integrated circuits with time-varying voltage-current characteristics including phased-locked power supplies - Google Patents

Abstract

A two-terminal IC chip and method thereof. For example, a two-terminal IC chip includes a first chip terminal, a second chip terminal, a first switch configured to receive a control signal, a first capacitor coupled to the first switch, a second switch configured to receive the control signal, a second capacitor coupled to the second switch, a third switch configured to receive the control signal, and a third capacitor coupled to the third switch. A first terminal voltage is a voltage of the first chip terminal, a second terminal voltage is a voltage of the second chip terminal, and a chip voltage is equal to a difference between the first terminal voltage and the second terminal voltage.

Description

   Two-terminal integrated circuit with time-varying voltage-current characteristics   

The invention provides an integrated circuit, in particular to a two-terminal integrated circuit having a voltage-current characteristic that changes with time.

Certain embodiments of the invention relate to integrated circuits. More specifically, some embodiments of the present invention provide a two-terminal integrated circuit including a phase-locked power supply having a voltage-current characteristic that varies with time. By way of example only, some embodiments of the present invention have been applied to drivers for Light Emitting Diodes (LEDs). However, it will be recognized that the present invention has a wider range of applications.

A single conventional integrated circuit typically includes one or more electronic circuits on one or more semiconductor materials (e.g., silicon). A single conventional integrated circuit is often referred to as an IC, chip, and / or IC chip. In addition, a single conventional integrated circuit can typically be made smaller than a discrete circuit with one or more discrete components (eg, discrete resistors, discrete diodes, and / or discrete transistors).

Generally, a conventional IC chip includes three or more terminals that can provide interconnection between one or more internal circuits of the chip and the external environment. Generally, a conventional IC chip uses one terminal to receive a power supply voltage, another terminal to provide a ground for a current loop, and a third terminal to provide input and / or output control.

For example, conventional LED drivers include conventional IC chips that operate in a switching power supply mode. A conventional IC chip includes three or more terminals (for example, pins), and these terminals are used to support normal operation. These terminals include a pin receiving rectified AC power input, another pin receiving IC power, and a third pin providing input / output control and / or providing a chip ground. The magnitude of the input rectified AC power source (eg, rectified AC voltage) typically becomes zero periodically with respect to the wafer. In another example, a pin of the rectified AC power source for input is connected to a terminal of an external capacitor, and another terminal of the external capacitor is connected to a pin for a chip ground. When the size of the input rectified AC power (eg, rectified AC voltage) periodically becomes zero relative to the wafer, an external capacitor is usually required to provide power to a conventional IC chip. In yet another example, a conventional IC chip uses three or more terminals to work with one or more external components (e.g., inductive coils) external to the chip, and converts the rectified AC power of the received input into DC power supply for LED lamps to provide constant LED current under some control mechanism. The use of an external capacitor and / or one or more additional pins of the IC chip generally increases the bill of material (BOM) cost of the LED driver.

Therefore, it is highly desirable to improve the technology of, for example, an integrated circuit that can be used for LED driving.

Certain embodiments of the invention relate to integrated circuits. More specifically, some embodiments of the present invention provide a two-terminal integrated circuit including a phase-locked power supply having a voltage-current characteristic that varies with time. By way of example only, some embodiments of the present invention have been applied to drivers for light emitting diodes. However, it will be recognized that the present invention has a wider range of applications.

According to one embodiment, a two-terminal IC wafer includes a first wafer terminal and a second wafer terminal. The first terminal voltage is the voltage of the first wafer terminal, the second terminal voltage is the voltage of the second wafer terminal, and the wafer voltage is equal to the difference between the first terminal voltage and the second terminal voltage. The wafer is configured to allow a wafer current to flow into the wafer at the first wafer terminal and flow out of the wafer at the second wafer terminal, or flow into the wafer at the second wafer terminal and flow out of the wafer at the first wafer terminal. The magnitude of the chip current is greater than or equal to zero. The wafer is also configured to change the relationship between wafer voltage and wafer current with respect to time. The wafer is an integrated circuit, and the wafer does not include any additional terminals other than the first wafer terminal and the second wafer terminal.

According to another embodiment, a two-terminal IC chip includes a first chip terminal, a second chip terminal, and a first switch. The wafer is configured to allow a wafer current to flow into the wafer at the first wafer terminal and flow out of the wafer at the second wafer terminal, or flow into the wafer at the second wafer terminal and flow out of the wafer at the first wafer terminal. The magnitude of the chip current is greater than or equal to zero. The first switch is configured to receive a driving signal and is opened or closed in response to the driving signal. The chip is further configured to change the magnitude of the chip current from greater than zero to equal to zero in response to the first switch being opened, and change the magnitude of the chip current from equal to zero to greater than zero in response to the first switch being closed. The wafer is an integrated circuit, and the wafer does not include any additional wafer terminals other than the first wafer terminal and the second wafer terminal.

According to yet another embodiment, a two-terminal IC chip includes a first chip terminal, a second chip terminal, a first switch configured to receive a first signal, and a first power source coupled to the first switch. The first switch is configured to be in a closed state during a first duration in response to the first signal and to be in an open state during a second duration in response to the first signal. The first power supply is configured to receive the first power through the first switch and store the received first power during the first duration in response to the first switch being in the closed state, and No additional power is stored during the second duration and the stored power is not allowed to leak through the first switch. The first power source is further configured to output a second power during a first duration and a second duration. The first terminal voltage is the voltage of the first wafer terminal, the second terminal voltage is the voltage of the second wafer terminal, and the wafer voltage is equal to the difference between the first wafer terminal and the second wafer terminal. The wafer is configured to allow current to flow into the wafer at the first wafer terminal and flow out of the wafer at the second wafer terminal, or flow into the wafer at the second wafer terminal and flow out of the wafer at the first wafer terminal. The magnitude of the chip current is greater than or equal to zero. The wafer is further configured to generate at least one selected from the group consisting of a wafer voltage and a wafer current based at least in part on the second power. The wafer is an integrated circuit, and the wafer does not include any additional wafer terminals other than the first wafer terminal and the second wafer terminal.

According to yet another embodiment, a two-terminal IC wafer includes a first wafer terminal and a second wafer terminal. The first wafer terminal is coupled to the first coil terminal of the inductor coil and the first diode terminal of the diode. The induction coil further includes a second coil terminal, and the diode further includes a second diode terminal. A series of one or more light emitting diodes are coupled to the second coil terminal and the second diode terminal. The second coil terminal and the second diode terminal are configured to receive a rectified AC voltage. The wafer is configured to receive an input voltage at a first wafer terminal and generate a wafer current based at least in part on the input voltage, the magnitude of the wafer current being greater than or equal to zero. In addition, the wafer is also configured to allow a wafer current to flow into the wafer at the first wafer terminal and flow out of the wafer at the second wafer terminal, or flow into the wafer at the second wafer terminal and flow out of the wafer at the first wafer terminal, and even when the input voltage is at When the range is changed and the wafer temperature is changed within the temperature range, the wafer current is changed with respect to time so that the light emitting diode current is kept constant with respect to time. The wafer is an integrated circuit, and the wafer does not include any additional wafer terminals other than the first wafer terminal and the second wafer terminal.

According to yet another embodiment, a two-terminal IC wafer for an electronic system includes a first wafer terminal and a second wafer terminal. The first wafer terminal is coupled to one or more components of the electronic system. The electronic system is configured to receive the first signal and generate a second signal based at least on information associated with the first signal. The wafer is configured to receive an input voltage at a first wafer terminal and generate a wafer current based at least in part on the input voltage. The current of new products is greater than or equal to zero. In addition, the wafer is configured to allow a wafer current to flow into the wafer at the first wafer terminal and flow out of the wafer at the second wafer terminal, or flow into the wafer at the second wafer terminal and flow out of the wafer at the first wafer terminal, and change at the first signal. The wafer current is changed relative to time in order to keep the electronic system operating normally. The wafer is an integrated circuit, and the wafer does not include any additional wafer terminals other than the first wafer terminal and the second wafer terminal.

In one embodiment, the two-terminal IC chip includes a first chip terminal, a second chip terminal, a first switch configured to receive a control signal, a first capacitor coupled to the first switch, and a first capacitor configured to receive a control signal. Two switches, a second capacitor coupled to the second switch, a third switch configured to receive a control signal, and a third capacitor coupled to the third switch. The first terminal voltage is the voltage of the first wafer terminal, the second terminal voltage is the voltage of the second wafer terminal, and the wafer voltage is equal to the difference between the first terminal voltage and the second terminal voltage. The wafer is configured to allow a wafer current to flow into the wafer at the first wafer terminal and flow out of the wafer at the second wafer terminal, or flow into the wafer at the second wafer terminal and flow out of the wafer at the first wafer terminal, and the magnitude of the wafer current is greater than or equal to zero. The first switch is further configured to be in a closed state during a first duration in response to the control signal and to be in an open state during a second duration in response to the control signal. The first capacitor is configured to receive the first power voltage through the first switch during the first duration in response to the first switch being in the closed state; in response to the first switch being in the off state, not to store any additional power and not Allowing the first stored power to leak through the first switch during the second duration; and outputting the first output voltage during the first duration and the second duration. The second switch is further configured to be in a closed state during the first duration in response to the control signal and to be in an open state during the second duration in response to the control signal. The second capacitor is configured to: in response to the second switch being closed, receive the first power supply voltage through the second switch during the first duration; in response to the second switch being open, not storing during the second duration Any additional power and does not allow the second stored power to leak through the second switch; and output a second output voltage during the first duration and the second duration. The third switch is further configured to be in a closed state during the first duration in response to the control signal and to be in an open state during the second duration in response to the control signal. The third capacitor is configured to: in response to the third switch being closed, receive the second power supply voltage through the third switch during the first duration; in response to the third switch being open, not storing during the second duration Any additional power and does not allow the second stored power to leak through the third switch; and output a third output voltage during the first duration and the second duration. The wafer is an integrated circuit, and the wafer does not include any additional wafer terminals other than the first wafer terminal and the second wafer terminal.

In another embodiment, a two-terminal IC chip includes a first chip terminal, a second chip terminal, a first switch configured to receive a control signal, a first capacitor coupled to the first switch, and configured to receive a control signal A second switch, a second capacitor coupled to the second switch, and a voltage generator configured to receive the first terminal voltage and generate a power supply voltage. The first terminal voltage is the voltage of the first wafer terminal, the second terminal voltage is the voltage of the second wafer terminal, and the wafer voltage is equal to the difference between the first terminal voltage and the second terminal voltage. The wafer is configured to allow a wafer current to flow into the wafer at the first wafer terminal and flow out of the wafer at the second wafer terminal, or to flow into the wafer at the second wafer terminal and flow out of the wafer at the first wafer terminal. The first switch is also configured to be in a closed state during a first duration in response to a control signal and to be in an open state during a second duration in response to the control signal. The first capacitor is configured to: in response to the first switch being in the closed state, receive the power supply voltage through the first switch during the first duration; in response to the first switch being in the open state, not storing any extras during the second duration And does not allow the first stored power to leak through the first switch; and outputs a first output voltage during a first duration and a second duration. The second switch is further configured to be in a closed state during the first duration in response to the control signal and to be in an open state during the second duration in response to the control signal. The second capacitor is configured to receive the power supply voltage through the second switch during the first duration in response to the second switch being closed; in response to the second switch being open, not to store any additional during the second duration And does not allow the second stored power to leak through the second switch; and output a second output voltage during the first duration and the second duration. The wafer is an integrated circuit, and the wafer does not include any additional wafer terminals other than the first wafer terminal and the second wafer terminal.

Depending on the embodiment, one or more of these benefits can be achieved. These beneficial effects and various additional objects, features, and advantages of the present invention can be fully understood with reference to the following detailed description and drawings.

100, 300, 400‧‧‧ IC chips

371, 471‧‧‧ reference voltage and / or current

120‧‧‧ Internal Power

373, 473‧‧‧ Demagnetization signal

130‧‧‧phase control block

361, 461‧‧‧Control signal

150, 152, 154‧‧‧ Power

363, 463‧‧‧ drive signal

200‧‧‧LED driver

390, 490‧‧‧‧ terminal

210‧‧‧Inductive coil

392, 492‧‧‧Gate terminal

212, 214‧‧‧ Terminals for Inductive Coils

Terminals for 394, 494‧‧‧transistors

320, 420‧‧‧‧low dropout regulator

464, 466, 468‧‧‧ switches

330‧‧‧Phase Controller

460‧‧‧ Comparator

360‧‧‧on time controller

484、486‧‧‧NOR Gate

370, 470‧‧‧ reference voltage generator

446, 448‧‧‧NOT gate

372, 472‧‧‧ Demagnetization sensor

438‧‧‧ Delay control element

380, 480‧‧‧ switch (transistor)

445‧‧‧threshold voltage

382, 482‧‧‧ resistors

447, 485‧‧‧ signal

383, 483‧‧‧Current sensing voltage

362, 462‧‧‧Logic control and gate driving elements

140, 142, 144, 149‧‧‧ controlled switch blocks

160, 162, 164, 170‧‧‧ function blocks

Terminals for 396, 398, 496, 498‧‧‧ resistors

602, 604, 606, 608‧‧‧ Comparator terminals

562, 564, 572, 574‧‧‧ Power supply voltage

240, 450, 452, 454‧‧‧ capacitors

254, 296, 316, 416‧‧‧ current

250, 252, 256, 314, 414‧‧‧ voltage

132, 134, 136, 331, 431‧‧‧ phase control signals

340, 342, 440, 442, 444‧‧‧ Controlled switches and power supplies

Terminals for 110, 112, 310, 312, 410, 412‧‧‧ IC chips

220, 230, 232, 234, 236, 290‧‧‧ diodes

Terminals for 231, 237, 222, 224, 292, 294‧‧‧diodes

122, 322, 341, 343, 422, 441, 443‧‧‧ supply voltage and / or current

510, 520, 530, 540, 550, 560, 570, 580, 590‧‧‧ waveform

114, 116, 124, 126, 141, 143, 145, 151, 153, 155, 161, 163, 165, 175, 181, 183, 185‧‧‧ current and / or voltage

FIG. 1 is a simplified schematic diagram showing an IC chip according to an embodiment of the present invention.

FIG. 2 is a simplified schematic diagram showing an LED driver including the IC chip shown in FIG. 1 according to an embodiment of the present invention.

FIG. 3 is a simplified schematic diagram showing an IC chip according to another embodiment of the present invention.

FIG. 4 is a simplified schematic diagram showing an IC chip according to still another embodiment of the present invention.

FIG. 5 shows a timing chart of an IC chip used as an IC chip in the LED driver shown in FIG. 2 according to an embodiment of the present invention.

Certain embodiments of the invention relate to integrated circuits. More specifically, some embodiments of the present invention provide a two-terminal integrated circuit including a phase-locked power supply having a voltage-current characteristic that varies with time. By way of example only, some embodiments of the invention have been applied to drivers for light emitting diodes (LEDs). However, it will be recognized that the present invention has a wider range of applications.

According to some embodiments, for IC chips, the terminals that provide control for input and / or output are combined with terminals that receive power, or with terminals that provide ground for the current loop. For example, the IC chip includes at most two terminals such as a power terminal and a ground terminal. In another example, these two terminals of the IC chip not only provide a current loop and / or current, but also automatically control the entire electronic system. In yet another example, an IC chip is used as a single input terminal-single output terminal system.

FIG. 1 is a simplified schematic diagram showing an IC chip according to an embodiment of the present invention. This illustration is only an example and should not unduly limit the scope of patent applications. Those skilled in the art will recognize many variations, substitutions, and modifications. The IC chip 100 includes terminals 110 and 112, an internal power source 120, a phase control block 130, controlled switch blocks 140, 142, and 144, power sources 150, 152, and 154, and function blocks 160, 162, 164, and 170. For example, each of the terminals 110 and 112 is a pin. In another example, the phase control block 130 is a phase controller. In yet another embodiment, each of the controlled switch blocks 140, 142, and 144 is a switch (eg, a controlled switch). In yet another example, each of the functional blocks 160, 162, 164, and 170 is an element configured to perform one or more functions.

In one embodiment, the terminal 110 receives the current and / or voltage 114 from outside the IC chip 100 and provides the received current and / or voltage 114 to one or more components in the IC chip 100; the terminal 112 is from the IC chip 100 One or more of the elements receive the current and / or voltage 124 and / or the current and / or voltage 116 and provide the received current and / or voltage 124 and / or the received current and / or to the outside of the IC chip 100. Voltage 126. In another embodiment, the terminal 110 receives the current and / or voltage 114 from one or more elements in the IC chip 100 and provides the received current and / or voltage 114 to the outside of the IC chip 100; the terminal 112 is from the IC chip 100 externally receives current and / or voltage 114 and / or current and / or voltage 116 and provides the received current and / or voltage 124 and / or the received current and / Or voltage 116. In yet another embodiment, at one time, the terminal 110 receives the current and / or voltage 114 from outside the IC chip 100 and provides the received current and / or voltage 114 to the one or more components in the IC chip 100. The terminal 112 receives current and / or voltage 124 and / or current and / or voltage 116 from one or more elements in IC chip 100 and provides the received current and / or voltage 124 and / or received to IC chip 100 outside Current and / or voltage 116; at another time, the terminal 110 receives the current and / or voltage 114 from one or more components in the IC chip 100 and provides the received current and / or voltage 114 to the outside of the IC chip 100 The terminal 112 receives the current and / or voltage 124 and / or the current and / or voltage 116 from outside the IC chip 100 and provides the received current and / or voltage 124 and / or to one or more components in the IC chip 100. Received current and / or voltage 116.

As shown in FIG. 1, according to some embodiments, the terminal 110 receives current and / or voltage 114 from outside the IC chip 100 during a certain duration, provides the received current and / or voltage 114 to the internal power source 120, and The functional blocks 160, 162, 164, and 170 are provided with the received current and / or voltage 114 during another duration.

In one embodiment, the internal power source 120 receives the current and / or voltage 114 and in response outputs the power supply voltage and / or current 122 to the phase control block 130, the controlled switching blocks 140, 142, and 144, and the function block 170. For example, the phase control block 130 receives the power supply voltage and / or current 122 and generates phase control signals 132, 134, and 136 in response. In another example, the phase control block 130 also generates a current and / or a voltage 124. In another embodiment, the controlled switch block 140 receives the power supply voltage and / or current 122 and the phase control signal 132, the controlled switch block 142 receives the power supply voltage and / or current 122 and the phase control signal 134, and the controlled switch block 144 receives a power supply voltage and / or current 122 and a phase control signal 136.

According to one embodiment, the controlled switch block 140 is responsive to the phase control signal 132, is closed (e.g., turned on) during a certain duration, and is opened (e.g., turned off) during another duration. For example, during the duration when the controlled switch block 140 is closed, the controlled switch block 140 uses the power supply voltage and / or current 122 to generate the voltage and / or current 141 and outputs the voltage and / or current 141 to the power supply 150. . In another example, the power source 150 receives power by receiving voltage and / or current 141, and stores the received power while supplying power (eg, voltage and / or current 151) to the functional block 160. In yet another example, during another duration when the controlled switch block 140 is in the off state, the power source 150 does not receive any power from the controlled switch block 140 and the energy stored by the power source 150 is trapped in the power source 150 ( In addition to the power source 150 still providing power to the functional block 160 (eg, voltage and / or current 151). In yet another example, during another duration when the controlled switch block 140 is in the off state, the power source 150 does not receive any power from the controlled switch block 140 and the energy stored by the power source 150 is prevented from passing through the controlled switch block 140 leaks, even though the power source 150 still provides power to the functional block 160 (eg, voltage and / or current 151).

According to another embodiment, the power supply 150 is phase-locked (for example, by the phase control signal 132 of the controlled switch block 149) and is self-sustaining (for example, by preventing the stored energy from leaking through the controlled switch block 140). For example, when the controlled switch block 140 is in the closed state during the duration determined by the phase control signal 132, the power source 150 receives and stores additional energy while supplying power to the function block 160. In another example, when the controlled switch block 140 is in an off state during another duration determined by the phase control signal 132, the power source 150 does not store additional energy, and the energy stored by the power source 150 is prevented from passing through the controlled The switching block 140 leaks, but the power source 150 still supplies power (eg, voltage and / or current 151) to the functional block 160.

In one embodiment, the controlled switch block 142 is responsive to the phase control signal 134, is in a closed (eg, on) state during a certain duration, and is in an open (eg, off) state during another duration. For example, during the duration when the controlled switch block 142 is closed, the controlled switch block 142 uses the power supply voltage and / or current 122 to generate a voltage and / or current 143 and outputs the enable voltage and / or current 143 to the power supply 152. . In another example, the power source 152 receives power by receiving voltage and / or current 143, and stores the received power while supplying power (e.g., voltage and / or current 153) to the function block 162. In another example, during another duration when the controlled switch block 142 is in the off state, the power source 152 does not receive any power from the controlled switch block 142, and the energy stored by the power source 152 is trapped in the power source 152, In addition to the power source 152 still providing power (eg, voltage and / or current 153) to the functional block 162. In yet another example, during another duration when the controlled switch block 142 is in the off state, the power source 152 does not receive any power from the controlled switch block 142 and the energy stored by the power source 152 is prevented from passing through the controlled switch block 142 leaks even though the power source 152 still provides power (eg, voltage and / or current 153) to the functional block 162.

In another embodiment, the power source 152 is phase locked (eg, by the phase control signal 134 of the controlled switch block 134) and is self-sustaining (eg, by preventing the stored energy from leaking through the controlled switch block 142). For example, when the controlled switch block 142 is closed during the duration determined by the phase control signal 134, the power source 152 receives and stores additional energy while supplying power to the function block 162. In another example, when the controlled switch block 142 is in an off state during another duration determined by the phase control signal 134, the power source 152 does not store additional energy and the energy stored by the power source 152 is prevented from passing through the controlled switch Block 142 leaks, but the power source 152 still provides power (eg, voltage and / or current 153) to the functional block 162.

According to one embodiment, the controlled switch block 144 is responsive to the phase control signal 136, is in a closed (eg, on) state during a certain duration and is in an open (eg, off) state during another duration. For example, during the duration when the controlled switch block 144 is in the closed state, the controlled switch block 144 generates a voltage and / or current 145 using the power supply voltage and / or current 122 and outputs the voltage and / or current 145 to the power supply 154. . In another example, the power source 154 receives power by receiving voltage and / or current 145 and stores the received power while providing power (eg, voltage and / or current 155) to the function block 164. In yet another example, during another duration when the controlled switch block 144 is in the off state, the power source 154 does not receive any power from the controlled switch block 144, and the energy stored by the power source 154 is trapped in the power source 154, In addition to the power source 154 still providing power (eg, voltage and / or current 155) to the functional block 164. In yet another example, during another duration when the controlled switch block 144 is in the off state, the power source 154 does not receive any power from the controlled switch block 144 and the energy stored by the power source 154 is prevented from passing through the controlled switch block 144 leaks, even though the power source 154 still provides power to the functional block 164 (eg, voltage and / or current 155).

According to another example, the power source 154 is phase locked (eg, by the phase control signal 136 of the controlled switch block 144) and is self-sustaining (eg, by preventing the stored energy from leaking through the controlled switch block 144). For example, when the controlled switch block 144 is in the closed state during the duration determined by the phase control signal 136, the power source 154 receives and stores additional energy while supplying power to the function block 164. In another example, when the controlled switch block 144 is in an off state during another duration determined by the phase control signal 136, the power source 154 does not store additional energy, and the energy stored by the power source 154 is prevented from passing through the controlled The switching block 144 leaks, but the power source 154 still supplies power (eg, voltage and / or current 155) to the functional block 164.

In one embodiment, the function block 160 receives power (e.g., voltage and / or current 151) from the power source 150, and signals (e.g., current and / or voltage 114) from the terminal 110, and performs a signal (Or voltage 114) performs a function and generates a current and / or voltage 161 based on the function based at least in part on a signal (eg, current and / or voltage 114). For example, the current and / or voltage 161 is part of the current and / or voltage 116.

In another embodiment, the function block 162 receives power (e.g., voltage and / or current 153) from the power source 152, and signals (e.g., current and / or voltage 114) from the terminal 110, and responds to signals (e.g., current And / or voltage 114) perform a function and generate a current and / or voltage 163 based on the function based at least in part on a signal (eg, current and / or voltage 114). For example, the current and / or voltage 163 is part of the current and / or voltage 116. In another example, the current and / or voltage 163 is different from the current and / or voltage 161.

In another embodiment, the function block 164 receives power (e.g., voltage and / or current 155) from the power source 154, and signals (e.g., current and / or voltage 114) from the terminal 110, and responds to signals (e.g., current And / or voltage 114) perform a function and generate a current and / or voltage 165 based on the function based at least in part on a signal (eg, current and / or voltage 114). For example, the current and / or voltage 165 is part of the current and / or voltage 116. In another example, the current and / or voltage 165 is different from the voltage and / or current 161 and the current and / or voltage 163 and the current and / or voltage 163 is different from the current and / or voltage 161.

In yet another embodiment, the functional block 170 receives power (e.g., power supply voltage and / or current 122) from the internal power source 120, and signals (e.g., current and / or voltage 114) from the terminal 110, and responds to signals (e.g., , Current and / or voltage 114) perform a function, and generate current and / or voltage 175 based on the function based at least in part on a signal (eg, current and / or voltage 114). For example, the functions performed by the function block 160, the functions performed by the function block 162, the functions performed by the function block 164, and the functions performed by the function block 170 are different. In yet another example, the current and / or voltage 116 is a combination of current and / or voltage 161, current and / or voltage 163, current and / or voltage 165, and current and / or voltage 175.

As shown in FIG. 1, according to some embodiments, the power source 150 also generates a current and / or voltage 181, the power source 152 also generates a current and / or voltage 183, and the power source 154 also generates a current and / or voltage 185. For example, current and / or voltage 181, current and / or voltage 183, and current and / or voltage 185 are part of current and / or voltage 116. In yet another example, the current and / or voltage 116 is current and / or voltage 161, current and / or voltage 163, current and / or voltage 165, current and / or voltage 175, current and / or voltage 181, current and And / or a combination of voltage 183 and current and / or voltage 185.

In one embodiment, the switch blocks 140, 142, and 144 are controlled to be turned on or off according to their respective timing arrangements. For example, when the switch block 140, the switch block 142, and / or the switch block 144 are turned off, the energy stored in the power source 150, the power source 152, and / or the power source 154 is prevented from passing through the controlled switch block 140, the controlled switch block, respectively. 142, and / or the controlled switching block 144 leaks, even if the power source 150, the power source 152, and / or the power source 154 still provide power to the function block 160, the function block 162, and / or the function block 164, respectively. In another example, the energy trapped in power source 150, power source 152, and / or power source 154 is used to provide power to different functional blocks to maintain proper control, even if the power source (e.g., current and / or voltage 114 and / or current and / or voltage 122) become very weak or even absent during a certain period of time.

As discussed above and further emphasized here, Figure 1 is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. In one embodiment, the IC chip 100 includes more than two functional blocks 170. For example, each of the two or more functional blocks 170 receives power (e.g., power supply voltage and / or current 122) from the internal power source 120 and signals from the terminal 110 (e.g., current and / or voltage 114), and The signal (e.g., current and / or voltage 114) performs a function, and the current and / or voltage is generated based on the function based at least in part on the signal (e.g., current and / or voltage 114). In another example, two or more functions performed by two or more function blocks 170, respectively, are different. In another embodiment, the IC chip 100 includes one or more additional components not explicitly shown in FIG. 1.

FIG. 2 is a simplified schematic diagram showing an LED driver including the IC chip 100 shown in FIG. 1 according to an embodiment of the present invention. This illustration is only an example and should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, the LED driver 200 includes an IC chip 100, an inductance coil 210, a diode 220, diodes 230, 232, 234, and 236, and a capacitor 240. In another example, the LED driver 200 is configured to drive one or more light emitting diodes (LEDs) 290. In yet another example, the LED driver 200 operates in a switching power mode.

In one embodiment, the terminal 231 of the diode 230 and the terminal 237 of the diode 236 receive the AC voltage 250, and in response, the diodes 230, 232, 234, and 236 and the capacitor 240 generate a rectified voltage 252 ( (Eg to provide rectified AC power). In another embodiment, the inductive coil 210 includes terminals 212 and 214, and the diode 220 includes terminals 222 and 224. For example, the rectified voltage 252 is received by the terminal 222 of the diode 220, and the terminal 224 of the diode 220 is connected to the terminal 212 of the inductor 210 and the terminal 110 of the IC chip 100. In another example, one or more light emitting diodes (LEDs) 290 form a series including terminals 292 and 294. In yet another example, the terminal 292 is connected to the terminal 222 and the terminal 294 is connected to the terminal 214.

In yet another embodiment, the terminal 110 of the IC chip 100 receives a voltage 256 from the terminals 224 and 212, and in response, the IC chip 100 generates a current 254. For example, voltage 256 is received as voltage 114 by terminal 110 and current 254 is output as current 116 by terminal 112. In another example, the terminal 112 of the IC chip 100 is biased by a predetermined voltage (eg, a ground voltage).

In yet another embodiment, the IC chip 100 is biased between the voltage of the terminal 110 (eg, the voltage 256) and the voltage of the terminal 112, and in response, the IC chip 100 flows into the IC chip 100 through the terminal 110 and flows out of the IC through the terminal 112 Current of wafer 100 (eg, current 254). For example, the IC chip 100 is a current-voltage having a voltage Vchip (for example, the voltage of the terminal 110 minus the voltage of the terminal 112) across the IC chip 100 and a current Ichip (for example, a current 254) flowing through the IC chip 100. Characteristic two-terminal device. In another example, the current-voltage characteristics of the IC chip 100 are represented by the effective resistance Rchip of the IC chip 100 as follows:

Here, Rchip indicates the effective resistance of the IC chip 100. In addition, Vchip represents a voltage across the IC chip 100 (for example, the voltage of the terminal 110 minus the voltage of the terminal 112), and Ichip represents a current (for example, a current 254) flowing through the IC chip 100.

In yet another embodiment, the current-voltage characteristics of the IC chip 100 change over time. For example, the current-voltage characteristics of the IC chip 100 change periodically over time. In another example, the current-voltage characteristics change over time during each cycle. In another embodiment, the effective resistance Rchip of the IC chip 100 changes over time. For example, the effective resistance Rchip of the IC chip 100 changes periodically over time. In yet another example, the effective resistance Rchip of the IC chip 100 changes with time in each cycle.

According to one embodiment, the voltage 256 is received by the IC chip 100, and in response, the IC chip 100 generates a current 254. For example, the current 254 changes over time. In another example, the current 254 changes periodically over time, and within each cycle, the current 254 changes over time. In yet another example, the current 254 changes over time such that the current 296 flowing through a series of one or more light emitting diodes 290 remains constant with respect to time.

According to another embodiment, the IC chip 100 of the LED driver 200 does not need to rely on an external capacitor to supply power to the IC chip 100. According to another embodiment, the IC chip 100 of the LED driver 200 provides the LED driver 200 with a two-function pin solution, which reduces the bill of materials (BOM) cost but still maintains the cost for one or more light emitting diodes ( LED) 290 for effective constant current control. For example, the IC chip 100 does not include any terminals (for example, pins) other than the terminals (for example, pins) 110 and 112. In another example, the IC chip 100 may reduce the size and / or cost of the entire system (eg, the LED driver 200), and the IC chip 100 may be used in various consumer electronics products.

According to yet another embodiment, the IC chip 100 is configured to keep the current 296 constant with respect to time even if the voltage 256 is changed within a certain voltage range and the temperature of the IC chip 100 is changed within a certain temperature range. For example, the IC chip 100 is also configured to periodically change the current 254 with respect to time, and within each cycle, change the current 254 with respect to time so that the current 296 remains constant with respect to time (even at a voltage of 256 at the above voltage Range, and the temperature of the IC chip 100 also changes within the above-mentioned temperature range). In another example, the temperature range includes an upper temperature limit of 150 ° C and a lower temperature limit of -40 ° C. In another example, the voltage range includes a voltage upper limit of 370V and a voltage lower limit of 126V.

According to yet another embodiment, the IC chip 100 is a controller for the LED driver 200. For example, the LED driver 200 is configured to receive an AC voltage 250 and generate a current 296 based at least on information associated with the AC voltage 250. In another example, the IC chip 100 is configured to generate a current 254, and / or change the current 254 with respect to time, so that the LED driver 200 can operate normally even when the AC current 250 is changed. In yet another example, the IC chip 100 is further configured to periodically change the current 254 with respect to time, and to change the current 254 with respect to time within each cycle, so that the LED driver 200 changes even when the AC voltage 250 changes Can also operate normally. In yet another example, the LED driver 200 maintains normal operation with the AC voltage 250 changed by keeping the magnitude of the current 296 constant with respect to time when the magnitude of the AC voltage 250 changes.

FIG. 3 is a simplified schematic diagram showing an IC chip according to another embodiment of the present invention. This illustration is only an example and should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The IC chip 300 includes terminals 310 and 312, a low dropout regular 320, a phase controller 330 (for example, a phase logic controller), a controlled switch and power supply 340, a controlled switch and power supply 342, and on-time control A controller 360, a logic control and gate driving element 362 (eg, a driver), a reference voltage generator 370, a demagnetization sensor 372, a switch 380 (eg, a transistor), and a resistor 382.

In one embodiment, the IC wafer 300 is an IC wafer 100. For example, the terminal 310 is the terminal 110 and the terminal 312 is the terminal 112. In another example, the low dropout regulator 320 is an internal power source 120 and the phase controller 330 is a phase control block 130. In yet another example, the controlled switch and power supply 340 is a combination of the controlled switch block 140 and the power supply 150, and the controlled switch and power supply 342 is a combination of the controlled switch block 142 and power supply 152. In yet another example, the on-time controller 360 is a functional block 160 and the logic control and gate driving element 362 is a functional block 162. In yet another example, the reference voltage generator 370 is a functional block 170 and the demagnetization sensor 372 is another functional block 170. In another embodiment, the IC chip 300 is an IC chip 100 used in the LED driver 200 shown in FIG. 2.

In one embodiment, the terminal 310 receives a voltage 314 (eg, current and / or voltage 114, or voltage 256) from outside the IC chip 300, and the terminal 312 outputs a current 316 (eg, current and / or voltage 116) to the outside of the IC chip 300 , Or current 254). For example, the magnitude of the current 316 is greater than or equal to zero. In another example, the voltage 314 is received by the low dropout regulator 320 and the switch 380. In another example, the switch 380 is a transistor (eg, a MOSFET). In another embodiment, the low dropout regulator 320 receives the voltage 314 and responds to the phase controller 330, the controlled switch and power supply 340, the controlled switch and power supply 342, the reference voltage generator 370, and demagnetization sensing. The device 372 outputs a power supply voltage 322.

According to one embodiment, the reference voltage generator 370 outputs the reference voltage and / or the current 371 to the on-time controller 360. According to another embodiment, the demagnetization sensor 372 outputs a demagnetization signal 373 to the logic control and gate driving element 362. For example, the demagnetization signal 373 indicates the start and end of each demagnetization cycle. In another example, the demagnetization period is related to the demagnetization process of the inductive coil 210.

According to yet another embodiment, the phase controller 330 receives the power supply voltage 322 and outputs a phase control signal 331 to the controlled switch and power supply 340 and the controlled switch and power supply 342. For example, the controlled switch and power supply 340 includes a switch, and the controlled switch and power supply 342 also includes a switch. In another example, the phase control signal 331 indicates the start and end of each on-time period. And the beginning and end of each shutdown period. In yet another example, the phase control signal 331 is at a certain logic level (e.g., a logic high level) during each on-time period (e.g., the beginning to the end of each on-time period), and is turned off every The time period (eg, the beginning to the end of each off-time period) is at another logic level (eg, a logic low level).

In one embodiment, during the on-time period indicated by the phase control signal 331, the controlled switch and the switch of the power supply 340 are in a closed (eg, on) state, and during the off-time period indicated by the phase control signal 331, the subject The control switch and the switches of the power supply 340 are in an off (eg, off) state. For example, if the switches of the controlled switch and power supply 340 are closed, the controlled switch and power supply 340 receives power provided by the power supply voltage 322 and stores the received power while the on-time controller 360 provides power (eg, the power supply voltage 341). Of power. In another example, if the switches of the controlled switch and power supply 340 are off, the controlled switch and power supply 340 does not store any additional power provided by the power supply voltage 322, and the energy that the controlled switch and power supply 340 has stored is Trapped in the controlled switch and power supply 340, except that the controlled switch and power supply 340 still provides power to the conduction controller 360 (eg, the power supply voltage 341). In yet another example, if the switches of the controlled switch and power supply 340 are off, the controlled switch and power supply 340 does not store any additional power provided by the power supply voltage 322, and the controlled switch and power supply 340 has stored energy Leakage is prevented through the switches of the controlled switch and the power supply 340, even if the controlled switch and the power supply 340 still provide power to the on-time controller 360 (eg, the power supply voltage 341).

In another embodiment, during the on-time period indicated by the phase control signal 331, the controlled switch and the switch of the power supply 342 are in a closed (eg, on) state, and during the off-time period indicated by the phase control signal 331, The controlled switch and the switch of the power supply 342 are in an off (eg, off) state. For example, if the switches of the controlled switch and the power supply 342 are closed, the controlled switch and the power supply 342 receive power provided by the power supply voltage 322 and are supplying power to the logic control and gate driving element 362 (for example, the power supply voltage 343) While storing the received power. In another example, if the switches of the controlled switch and power supply 342 are off, the controlled switch and power supply 342 does not store any additional power provided by the power supply voltage 322, and the controlled switch and power supply 342 has stored energy Trapped in the controlled switch and power supply 342, except that the controlled switch and power supply 342 still provides power to the logic control and gate drive element 362 (e.g., the power supply voltage 343). In yet another example, if the switches of the controlled switch and power supply 342 are off, the controlled switch and power supply 342 does not store any additional power provided by the power supply voltage 322, and the controlled switch and power supply 342 has stored energy Leakage is prevented through the switches of the controlled switch and power supply 342, although the controlled switch and power supply 342 still provides power to the logic control and gate drive element 362 (e.g., power supply voltage 343).

According to one embodiment, the on-time controller 360 receives the reference voltage and / or the current 372 and the current sensing voltage 383 and generates a control signal 361 in response. For example, the on-time controller 360 compares the current sensing voltage 383 with a predetermined voltage limit corresponding to a predetermined current limit. In another example, the control signal 361 indicates whether the current 316 has reached or exceeded a predetermined current limit. In another example, the control signal 361 is received by a control logic and gate driving element 362, which also receives a demagnetization signal 373 and a power supply voltage 343. In another example, the logic control and gate driving element 362 generates a driving signal 363 that is received by the switch 380 and the demagnetization sensor 372.

According to another embodiment, the demagnetization sensor 372 receives the drive signal 363 and the power supply voltage 322 and generates a demagnetization signal 373 based at least in part on the drive signal 363. For example, the driving signal 363 is coupled to the voltage 314 through a parasitic capacitor (eg, Cgd) between the gate terminal 392 of the transistor 380 and the drain terminal 390 of the transistor 380. In another example, the demagnetization signal 373 indicates the beginning and end of each demagnetization cycle. In another example, the demagnetization period is related to the demagnetization process of the inductive coil 210.

In one embodiment, the switch 380 receives the driving signal 363 and is closed or opened by the driving signal 363. For example, the drive signal 363 is a pulse width modulation (PWM) signal that changes between a logic low level and a logic high level. In another example, a pulse width modulation (PWM) signal remains at a logic high level during the pulse width. In another embodiment, if the driving signal 363 is at a logic high level, the switch 380 is opened and then closed, and if the driving signal 363 is at a logic low level, the switch 380 is closed and then opened.

In another embodiment, the switch 380 (eg, transistor) includes terminals 390, 392, and 394, and the resistor 382 includes terminals 396 and 398. For example, the terminal 390 of the transistor 380 is connected to the terminal 310 of the IC chip 300, and the terminal 392 of the transistor 380 is configured to receive the driving signal 363. In another example, the terminal 394 of the transistor 380 is connected to the terminal 396 of the resistor 382 and the terminal 398 of the resistor 382 is connected to the terminal 312 of the IC chip 300.

As shown in FIG. 3, according to some embodiments, the transistor 380 and the resistor 382 are biased between the voltage of the terminal 310 and the voltage of the terminal 312. For example, if the transistor 380 is turned on, a current 316 flows into the IC wafer 300 at the terminal 310 through the transistor 380 and the resistor 382 and flows out of the IC wafer 300 at the terminal 312. In another example, the current sensing voltage 383 represents the magnitude of the current 316.

According to one embodiment, the on-time controller 360 receives the power supply voltage 341, the reference voltage and / or the current 371, and the current sensing voltage 383, and generates a control signal 361; the demagnetization sensor 372 receives the driving signal 363 and the power supply voltage 322, And a demagnetization signal 373 is generated. For example, the control signal 361 indicates whether the current 316 has reached or exceeded a predetermined current limit, and the demagnetization signal 373 indicates that each demagnetization cycle begins and ends (for example, related to the demagnetization process of the inductor 210). In another example, both the control signal 361 and the demagnetization signal 373 are received by the logic control and gate driving element 362.

According to another embodiment, the logic control and gate driving element 362 uses the control signal 361 and the demagnetization signal 373 to determine the pulse width of the driving signal 363. For example, if the demagnetization signal 373 indicates the end of the demagnetization period (for example, related to the demagnetization process of the inductive coil 210), the pulse width of the drive signal 363 starts and the switch 380 changes from being turned off to being turned on, so that the magnitude of the current 316 is changed from Zero starts to increase. In another example, if the control signal 361 indicates that the current 316 has reached or exceeded a predetermined current limit, the pulse width of the driving signal 363 ends and the switch 380 changes from being turned on to being turned off, so that the magnitude of the current 316 drops to zero .

As discussed above and further emphasized here, Figure 3 is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. For example, the IC chip 300 also includes a band gap circuit (for example, a temperature-independent voltage reference circuit). In another example, the IC chip 300 includes a reference current generator in addition to, or instead of, the reference voltage generator 370.

According to some embodiments, the IC chip 100 (eg, the IC chip 300) is an integrated circuit. For example, the IC chip 100 (for example, the IC chip 300) includes two or more semiconductor devices integrated together, and has a control architecture including a plurality of functional blocks. In another example, the IC wafer 100 (eg, the IC wafer 300) includes no more than two terminals (eg, the terminals 110 and 112). In another example, the IC chip 300 may be used in various electronic systems (for example, the LED driver 200).

According to some embodiments, the IC chip 100 (for example, the IC chip 300) is an integrated circuit including no more than two terminals (for example, pins). For example, the integrated circuit of the IC chip 100 includes two or more active semiconductor devices (eg, one or more diodes and / or one or more transistors) that are integrated together. In another example, the IC chip 100 (e.g., the IC chip 300) generates an internal signal (e.g., the drive signal 363), which is a pulse width modulation (PWM) signal. In yet another example, the IC wafer 100 (eg, the IC wafer 300) has a current-voltage characteristic between a voltage across the IC wafer 100 and a current flowing through the IC wafer 100. In another example, the current-voltage characteristics of the IC chip 300 are periodic with respect to time, and the current-voltage characteristics (e.g., current-voltage analog behavior) change with time in each cycle.

According to some embodiments, the IC chip 100 (eg, the IC chip 300) includes one or more mixed-signal IC architectures, circuits, and / or components. For example, the phase controller 330 and the logic control and gate driving elements 362 are digital circuits. In another example, the low dropout regulator 320, the controlled switch and power supply 340, the controlled switch and power supply 342, and the reference voltage generator 370 are all analog circuits. In yet another example, the on-time controller 360 and the demagnetization sensor 372 each include an analog circuit and a digital circuit.

According to some embodiments, the IC chip 100 (e.g., IC chip 300) includes no more than two terminals and also includes one or more controlled switch blocks (e.g., controlled switch blocks 140, 142, and / or 144). ) And integrated circuits of one or more power sources (eg, power sources 150, 152, and / or 154). For example, the IC chip 100 (for example, the IC chip 300) generates an internal signal (for example, a driving signal 363), which is a pulse width modulation (PWM) signal. In another example, one or more controlled switch blocks (e.g., controlled switch blocks 140, 142, and / or 144) receive one or more corresponding phase control signals (e.g., phase control signals 132, 134, respectively). , And / or 136), and are respectively opened or closed by one or more corresponding phase control signals (eg, phase control signals 132, 134, and / or 136). In yet another example, one or more controlled switch blocks (e.g., controlled switch blocks 140, 142, and / or 144) are opened or closed according to their respective timing (e.g., by one or more The corresponding phase control signal is determined).

In one embodiment, if a controlled switch block (e.g., controlled switch block 140, 142, or 144) is in a closed (e.g., on) state during a certain duration, it is connected to a corresponding power source of the controlled switch block (E.g., power supply 150, 152, or 154) receives power through a controlled switch block, and stores received power while supplying power to a corresponding function block (e.g., function block 160, 162, or 164) connected to the power supply power. In another embodiment, a controlled switch block (e.g., controlled switch block 140, 142, or 144) is connected to the controlled switch if it is in an open (e.g., off) state during another duration The block's corresponding power supply (for example, power supply 150, 152, or 154) does not receive any power from the controlled switch block, and the energy stored in the corresponding power supply is trapped in the power supply summary, except that the power supply is still connected to the power supply The corresponding function block (for example, function block 160, 162, or 164) provides power in addition to power. In yet another embodiment, a controlled switch block (e.g., controlled switch block 140, 142, or 144) is connected to the controlled switch if it is in an open (e.g., off) state during another duration. The block's corresponding power source (e.g., power supply 150, 152, or 154) does not receive any power from the controlled switch block, and the energy stored by the corresponding power source is prevented from leaking through the controlled switch block, although the power source is still connected to A corresponding function block (eg, function block 160, 162, or 164) of the power supply provides power.

According to some embodiments, the IC chip 100 (for example, the IC chip 300) is an integrated circuit including no more than two terminals (for example, pins). In one embodiment, the two-terminal IC chip 100 (eg, the two-terminal IC chip 300) is a controller for an electronic system (eg, an electronic system including an LED driver 200 and one or more LEDs 290). In another embodiment, the two-terminal controller 100 (eg, the two-terminal controller 300) enables the electronic system to perform normal and / or stable operations even if external conditions of the electronic system change. For example, the electronic system includes an LED driver 200 and one or more LEDs 290, and the two-terminal controller 100 (e.g., the two-terminal controller 300) maintains the current 296 flowing through the one or more light emitting diodes 290 with respect to time Constant even if the magnitude of the AC voltage 250 changes (for example, the peak value of the AC voltage 250 changes from 1V to another volt value).

According to some embodiments, the IC chip 100 (e.g., IC chip 300) uses the same terminal (e.g., terminal 110 and / or terminal 310) as an input terminal during a certain duration and as an output terminal during another duration Two-terminal controller. For example, the two-terminal controller 100 (e.g., the two-terminal controller 300) implements a signal processing mechanism (e.g., a signal processing algorithm), and the signal processing mechanism is used to determine the relationship between a certain duration and another duration . In another example, during the pulse width of the pulse width modulation (PWM) signal 363, the two-terminal controller 300 uses the terminal 310 as an output terminal to allow a current 316 greater than zero to flow into the controller 300 at the terminal 310 and at The terminal 312 flows out of the controller 300. In another example, during the pulse width of the pulse width modulation (PWM) signal 363, the two-terminal controller 100 (eg, the two-terminal controller 300) outputs to one or more light emitting diodes (LEDs) 290 as A current greater than zero of the drive current 316. In yet another example, during a demagnetization period (e.g., related to the demagnetization process of the inductor 210) outside the pulse width of the pulse width modulation (PWM) signal 363, the two-terminal controller 300 receives using the terminal 310 as an input terminal Voltage 314, and the received voltage 314 is processed (e.g., sensed and / or sampled) to determine the end of the demagnetization cycle (corresponding to the beginning of the next pulse width). In yet another example, the voltage 314 is coupled to the drive signal 363 through a parasitic capacitor (eg, Cgd) between the gate terminal 392 of the transistor 380 and the drain terminal 390 of the transistor 380.

According to some embodiments, the IC chip 100 (e.g., IC chip 300) is a two-terminal controller capable of responding to changes in its inputs (e.g., current and / or voltage 114, voltage 256, and / or voltage 314) While self-adjusting its output (eg, current and / or voltage 116, current 254, and / or current 316), thereby enabling an electronic system (eg, including LED driver 200, one or more LEDs 290, and two-terminal control The electronic system of the device 100) may perform normal and / or stable operations (eg, keep the current 296 flowing through one or more light emitting diodes 290 stable with respect to time). For example, in response to changes in the magnitude of its inputs (e.g., changes in the peak values of current and / or voltage 114, voltage 256, and / or voltage 314), IC chip 100 (e.g., IC chip 300) passes a control mechanism (e.g., By changing the pulse width and / or duty cycle of the driving signal 363 to change its output (eg, current and / or voltage 116, current 254, and / or current 316) so that one or more light emitting diodes flow through The current 296 of the body 290 remains constant with respect to time.

In another example, if the amplitude of the AC voltage 250 changes (eg, the peak value of the AC voltage 250 changes from one volt to another volt), the current and / or voltage 114, voltage 256, and / or voltage 314 The amplitude (eg, the peak value of the current and / or voltage 114, the voltage 256, and / or the voltage 314) also changes. In yet another example, if the amplitudes of the current and / or voltage 114, voltage 256, and / or voltage 314 become smaller, the pulse width or duty cycle of the driving signal 363 becomes larger, so that one or more light emitting flows The current 296 of the diode 290 remains constant with respect to time.

In another example, the two-terminal controller 100 (eg, the two-terminal controller 300) responds to changes in its inputs (eg, current and / or voltage 114, voltage 256, and / or voltage 314) by changing the controller The relationship between the input and the controller output (e.g., the current-voltage characteristics of the IC chip 100 as shown in Equation 1) comes from me adjusting the output (e.g., current and / or voltage 116, electrical six 254, And / or current 316), so that the current 296 flowing through the one or more light emitting diodes 290 remains constant with respect to time. In another example, the relationship between the controller input and the controller output changes periodically over time without the relationship changing; instead, the controller input and the controller output change when the relationship changes The relationship between them does not change periodically over time.

According to another embodiment, a two-terminal IC wafer (e.g., IC wafer 100 and / or IC wafer 300) includes a first wafer terminal (e.g., terminal 110 and / or terminal 310) and a second wafer terminal (e.g., terminal 112 and / Flexible terminal 312). The first terminal voltage (eg, voltage 256) is the voltage of the first wafer terminal, the second terminal voltage is the voltage of the second wafer terminal, and the wafer voltage (eg, the voltage Vchip across the IC chip 100) is the first terminal voltage and The difference between the second terminal voltages. The wafer is configured to allow a wafer current (eg, current 254) to flow into the wafer at the first wafer terminal and out of the wafer at the second wafer terminal, or to flow into the wafer at the second wafer terminal and out of the wafer at the first wafer terminal. The magnitude of the chip current is equal to or greater than zero. The wafer is also configured to change the relationship between the wafer voltage and the wafer current with respect to time (for example, the current-voltage characteristics of the IC wafer 100 shown in Equation 1). The wafer (e.g., IC wafer 100 and / or IC wafer 300) is an integrated circuit, and the wafer does not include a first wafer terminal (e.g., terminal 110 and / or terminal 310) and a second wafer terminal (e.g., terminal 112 and / or Or terminal 312). For example, a two-terminal IC chip is implemented based on at least FIG. 1, FIG. 2, and / or FIG. 3.

In another example, the two-terminal IC wafer is further configured to periodically change the relationship between the wafer voltage and the wafer current with respect to time (for example, the current-voltage characteristics of the IC wafer shown in Equation 1), and In each cycle, the relationship between the wafer voltage and the wafer current with respect to time is changed. In yet another example, the two-terminal IC chip further includes a switch (eg, switch 380) and a resistor (eg, resistor 382) coupled to the switch. The switch is configured to receive a driving signal (eg, the driving signal 363), and is opened or closed in response to the driving signal. The chip is also configured to change the magnitude of the chip current (e.g., current 254) from greater than zero to equal to zero in response to the switch being turned off, and change the magnitude of the chip current (e.g., current 254) from to zero in response to the switch being closed Change to greater than zero. In yet another example, the chip is further configured to allow chip current to flow through the switch and resistor in response to the switch being closed. The magnitude of the chip current is greater than zero. In yet another example, the driving signal (eg, the driving signal 363) is a pulse width modulation signal corresponding to a pulse width of each modulation period. In yet another example, the two-terminal IC chip further includes a device configured to receive a first signal (e.g., demagnetization signal 373) and a second signal (e.g., control signal 361) and generate a driving signal (e.g., driving signal 363). Drive (for example, drive 362). The driver is further configured to change the drive signal to start a pulse width in response to a first signal (e.g., demagnetization signal 373) indicating the end of the demagnetization period, and in response to indicating that the wafer current (e.g., current 254) has reached or exceeded a predetermined A current-limited second signal (eg, current signal 254) to change the drive signal to end the pulse width. In yet another example, the driver is further configured to respond to the first signal indicating the end of the demagnetization period, change the driving signal to close the switch and increase the magnitude of the chip current (eg, current 254) from zero, and respond to the second The signal indicates that the wafer current has reached or exceeded a predetermined current limit, and the driving signal is changed to open the switch and reduce the magnitude of the wafer current to zero.

In yet another example, a first wafer terminal (e.g., terminal 110 and / or terminal 310) is coupled to a first coil terminal (e.g., terminal 212) and a diode (e.g., terminal 212) of an inductive coil (e.g., inductive coil 210) , A first diode terminal (eg, a terminal 224) of the diode 220). The inductive coil further includes a second coil terminal (for example, terminal 214), and the diode further includes a second diode terminal (for example, terminal 222). A series of one or more light emitting diodes (e.g., one or more LEDs 290) are coupled to the second coil terminal and the second diode terminal. The second coil terminal and the second diode terminal are configured to receive a rectified AC voltage (eg, the rectified voltage 252). In yet another example, the two-terminal IC wafer is further configured to receive a first terminal voltage (e.g., voltage 256) at a first wafer terminal (e.g., terminal 110 and / or terminal 310) and based at least in part on the first terminal The voltage generates a wafer current (eg, current 254). In yet another example, a wafer current (e.g., current 254) is configured to flow between a first wafer terminal and a second wafer terminal to affect a series of one or more light emitting diodes (e.g., one Or a plurality of LEDs 290) of light emitting diode current (eg, current 296). In yet another example, the two-terminal IC wafer is further configured to change the wafer current (eg, current 254) with respect to time to keep the light emitting diode current (eg, current 296) constant with respect to time. In yet another example, a two-terminal IC wafer (e.g., IC wafer 100 and / or IC wafer 300) is further configured to periodically change the wafer current (e.g., current 254) with respect to time, and relative to each cycle The wafer current (eg, current 254) is changed over time so that the light emitting diode current (eg, current 296) remains constant with respect to time.

In yet another example, the two-terminal IC chip (e.g., IC chip 100 and / or IC chip 300) further includes a control signal (e.g., phase control signal 132, phase control signal 134, phase control signal 136, and (Or phase control signal 331) controlled switches (e.g., controlled switch 140, controlled switch 142, and / or controlled switch 144), and a power source (e.g., power supply 150, power supply 152) coupled to the controlled switch , And / or power supply 154). The controlled switch is further configured to be in a closed state during the first duration in response to the control signal and to be in an open state during the second duration in response to the control signal. The power supply is configured to receive first power (e.g., voltage and / or current 141, voltage and / or current 143, and / or voltage and / Or current 145) and stores the received first power and does not store any additional power during the second duration in response to the controlled switch being in the off state and does not allow the stored power to leak through the controlled switch. The power source (e.g., power source 150, power source 152, and / or power source 154) is further configured to output a second power (e.g., voltage and / or current 151, voltage and / or current during a first duration and a second duration). 153, voltage and / or current 155, power supply voltage 341, and / or power supply voltage 343). In yet another example, the wafer voltage (eg, the voltage Vchip across the IC wafer 100) is equal to the first terminal voltage minus the second terminal voltage.

According to yet another embodiment, a two-terminal IC wafer (eg, IC wafer 100 and / or IC wafer 300) includes a first wafer terminal (eg, terminal 110 and / or terminal 130), a second wafer terminal (eg, terminal 112 and (Or terminal 312), and a first switch (e.g., switch 380). The wafer is configured to allow a wafer current (eg, current 254) to flow into the wafer at the first wafer terminal and out of the wafer at the second wafer terminal, or to flow into the wafer at the second wafer terminal and out of the wafer at the first wafer terminal. The magnitude of the chip current is greater than or equal to zero. The first switch is configured to receive a driving signal (eg, the driving signal 363), and is opened or closed in response to the driving signal. The chip is also configured to change the magnitude of the chip current from greater than zero to equal to zero in response to the first switch being opened, and change the chip current from equal to zero to greater than zero in response to the first switch being closed. The wafer is an integrated circuit, and the wafer does not include any additional wafer terminals other than the first wafer terminal (e.g., terminal 110 and / or terminal 310) and the second wafer terminal (e.g., terminal 112 and / or terminal 312). . For example, a two-terminal IC chip is implemented based on at least FIG. 1, FIG. 2, and / or FIG. 3.

In another example, the driving signal (eg, the driving signal 363) is a pulse width modulation signal corresponding to a pulse width of each modulation period. In yet another example, the two-terminal IC chip further includes a driver configured to receive a first signal (e.g., demagnetization signal 373) and a second signal (e.g., control signal 361) and generate a driving signal (e.g., driving signal 363) . The driver is also configured to change the drive signal to turn on the pulse width in response to the first signal (e.g., demagnetization signal 373) indicating the end of the demagnetization cycle, and to indicate the chip current (e.g. The current 254) has reached or exceeded a predetermined current limit to change the driving signal to end the pulse width. In yet another example, the driver is further configured to change the driving signal in response to the first signal indicating the end of the demagnetization period to close the first switch and increase the magnitude of the chip current (eg, current 254) from zero; and respond The driving signal is changed after the second signal indicates that the wafer current has reached or exceeded a predetermined current limit to open the first switch and reduce the magnitude of the wafer current to zero.

In yet another example, a first wafer terminal (e.g., terminal 110 and / or terminal 310) is coupled to a first coil terminal (e.g., terminal 212) and a diode (e.g., terminal 212) of an inductive coil (e.g., inductive coil 210) , A first diode terminal (eg, a terminal 224) of the diode 220). The inductive coil further includes a second coil terminal (for example, terminal 214), and the diode further includes a second diode terminal (for example, terminal 222). A series of one or more light emitting diodes (eg, one or more LEDs 290) are coupled to the second coil terminal and the second diode terminal. The second coil terminal and the second diode terminal are configured to receive a rectified AC voltage (eg, the rectified voltage 252).

In yet another example, the two-terminal IC chip is further configured to receive an input voltage (e.g., voltage 256) at a first chip terminal (e.g., terminal 110 and / or terminal 310), and based at least in part on the received input voltage A wafer current (eg, current 254) is generated. In yet another example, a wafer current (e.g., current 254) is configured to flow between a first wafer terminal and a second wafer terminal to affect a series of one or more light emitting diodes (e.g., one Or a plurality of LEDs 290) of light emitting diode current (eg, current 296). In yet another example, the two-terminal IC wafer is further configured to change the wafer current (eg, current 254) with respect to time to keep the light emitting diode current (eg, current 296) constant with respect to time. In yet another example, a two-terminal IC wafer (e.g., IC wafer 100 and / or IC wafer 300) is also configured to change the wafer current (e.g., current 254) periodically with respect to time, and relative to each cycle The wafer current (eg, current 254) is changed over time so that the light emitting diode current (eg, current 296) remains constant with respect to time.

In yet another example, a two-terminal IC chip (e.g., IC chip 100 and / or IC chip 300) further includes a signal configured to receive a control signal (e.g., phase control signal 132, phase control signal 134, phase control signal 136, and (Or phase control signal 331) a second switch (e.g., switch 140, switch 142, and / or switch 144), and a power source (e.g., power supply 150, power supply 152, and / or power supply 154) coupled to the second switch . The second switch is also configured to be in a closed state during the first duration in response to the control signal and to be in an open state during the second duration in response to the control signal. The power supply is configured to receive the first power (e.g., voltage and / or current 141, voltage and / or current 143, and / or voltage and / or current 145) through the second switch in response to the second switch being in the closed state and store The first power received and not storing any additional power during the second duration in response to the second switch being in the off state does not allow the stored power to leak through the second switch. The power source (e.g., power source 150, power source 152, and / or power source 154) is further configured to output a second power (e.g., voltage and / or current 151, voltage and / or current during a first duration and a second duration). 153, voltage and / or current 155, power supply voltage 341, and / or power supply voltage 343).

According to yet another embodiment, a two-terminal IC wafer (eg, IC wafer 100 and / or IC wafer 300) includes a first wafer terminal (eg, terminal 110 and / or terminal 310), a second wafer terminal (eg, terminal 112 and (Or terminal 312), a first switch (e.g., switch 140, switch) configured to receive a first signal (e.g., phase control signal 132, phase control signal 134, phase control signal 136, and / or phase control signal 331) 142, and / or switch 144), and a first power source (eg, power source 150, power source 152, and / or power source 154) coupled to the first switch. The first switch is configured in response to the first signal being in a closed state during a first duration and in response to the first signal being in an open state during a second duration. The first power source (e.g., power source 150, power source 152, and / or power source 154) is configured to respond to a first switch (e.g., switch 140, switch 142, and / or switch 144) for a first duration of time Receive the first power (eg, voltage and / or current 141, voltage and / or current 143, and / or voltage and / or current 145) through the first switch during the period and store the received first power, and respond to the first The switch is in the off state without storing any additional power during the second duration and does not allow the stored power to leak through the first switch. The first power source (e.g., power source 150, power source 152, and / or power source 154) is also configured to output a second power (e.g., voltage and / or current 151, voltage and / Or current 153, voltage and / or current 155, power supply voltage 341, and / or power supply voltage 343). The first terminal voltage (e.g., voltage 256) is the voltage of the first wafer terminal (e.g., terminal 110 and / or terminal 310), and the second terminal voltage is the voltage of the second wafer terminal (e.g., terminal 112 and / or terminal 312) The voltage, the wafer voltage (eg, the voltage Vchip across the IC wafer 100) is equal to the difference between the first terminal voltage and the second terminal voltage. The wafer is configured to allow a wafer current (eg, current 254) to flow into the wafer at the first wafer terminal and out of the wafer at the second wafer terminal, or to flow into the wafer at the second wafer terminal and out of the wafer at the first wafer terminal. The magnitude of the chip current is greater than or equal to zero. The wafer (eg, IC wafer 100 and / or IC wafer 300) is also configured to be based at least in part on a second power (eg, voltage and / or current 151, voltage and / or current 153, voltage and / or current 155, power source The voltage 341, and / or the power supply voltage 343) generates at least one selected from the group consisting of a wafer voltage (eg, a voltage Vchip across the IC wafer 100) and a wafer current (eg, a current 254). The wafer (e.g., IC wafer 100 and / or IC wafer 300) is an integrated circuit, and the wafer does not include a first wafer terminal (e.g., terminal 110 and / or terminal 310) and a second wafer terminal (e.g., terminal 112 and / or Or terminal 312). For example, a two-terminal IC chip is implemented based on at least FIG. 1, FIG. 2, and / or FIG. 3.

In another example, the two-terminal IC chip further includes a driver configured to receive the second power (e.g., the power supply voltage 343) and generate a driving signal (e.g., the driving signal 363), and a driver configured to receive the driving signal and respond to A second switch (eg, switch 380) whose driving signal two is opened or closed. The chip is also configured to change the magnitude of the chip current (e.g., current 254) from greater than zero to equal to zero in response to the switch being turned off, and change the magnitude of the chip current (e.g., current 254) from to zero in response to the switch being closed Change to greater than zero.

In yet another example, the driving signal (eg, the driving signal 363) is a pulse width modulation signal corresponding to a pulse width of each modulation period. In another example, the two-terminal IC chip further includes a controller (e.g., a phase control signal 132, a phase control signal 134, a phase control signal 136, and / or a phase control signal 331) configured to generate a first signal (Phase controller 130 and / or phase controller 330). The first signal (e.g., phase control signal 132, phase control signal 134, phase control signal 136, and / or phase control signal 331) is at a first logic level during a first duration, and the first signal is at a second duration At the second logical level during time. The second logic level is different from the first logic level.

In yet another example, the two-terminal IC chip (e.g., IC chip 100 and / or IC chip 300) further includes a second power source (e.g., internal power source 120 and / or low dropout regulator 320). The second power source is configured to receive third power (e.g., current and / or voltage 114, voltage 256, and / or voltage 314) from the first wafer terminal (e.g., terminal 110 and / or terminal 310), based at least in part on The third power generates fourth power (e.g., power supply voltage and / or current 122 and / or power supply voltage 322) and outputs the fourth power to a controller (e.g., phase controller 130 and / or phase controller 330) and The first switch (eg, switch 140, switch 142, and / or switch 144). In another example, the first switch (e.g., switch 140, switch 142, and / or switch 144) is further configured to respond to the first switch in a closed state, based at least in part on a fourth power (e.g., a power supply voltage and (Or current 122 and / or power supply voltage 322) output a first power (eg, voltage and / or current 141, voltage and / or current 143, and / or voltage and / or current 145).

In yet another example, a first wafer terminal (e.g., terminal 110 and / or terminal 310) is coupled to a first coil terminal (e.g., terminal 212) and a diode (e.g., terminal 212) of an inductive coil (e.g., inductor 210) , The first diode terminal (terminal 224) of the diode 220). The inductive coil further includes a second coil terminal (for example, terminal 214), and the diode further includes a second diode terminal (for example, terminal 222). A series of one or more light emitting diodes (eg, one or more LEDs 290) are coupled to the second inductive coil and the second diode terminal. The second coil terminal and the second diode terminal are configured to receive a rectified AC voltage (eg, the rectified voltage 252). In yet another example, the wafer voltage (eg, the voltage Vchip across the IC wafer 100) is equal to the first terminal voltage minus the second terminal voltage.

According to yet another embodiment, a two-terminal IC wafer (eg, IC wafer 100 and / or IC wafer 300) includes a first wafer terminal (eg, terminal 110 and / or terminal 310), and a second wafer terminal (eg, terminal 112) And / or terminal 312). The first wafer terminal is coupled to a first coil terminal (e.g., terminal 212) of an inductive coil (e.g., inductive coil 210), and a first diode terminal (e.g., diode 220) Terminal 224). The inductive coil further includes a second coil terminal (for example, terminal 214), and the diode further includes a second diode terminal (for example, terminal 222). A series of one or more light emitting diodes (eg, one or more LEDs 290) are coupled to the second coil terminal and the second diode terminal. The second coil terminal and the second diode terminal are configured to receive a rectified AC voltage (eg, the rectified voltage 252). A wafer (e.g., IC wafer 100 and / or IC wafer 300) is configured to receive an input voltage (e.g., voltage 256) at a first wafer terminal and generate a wafer current (e.g., current 254) based at least in part on the input voltage, the wafer The magnitude of the current is greater than or equal to zero. In addition, the wafer is configured to allow a wafer current to flow into the wafer at the first wafer terminal and flow out of the wafer at the second wafer terminal, or to flow into the wafer at the second wafer terminal and flow out of the wafer at the first wafer terminal, and change the wafer current with respect to time. So that the light emitting diode current (for example, current 296) changes within a certain voltage range even when the input voltage (for example, voltage 256) and the wafer temperature (for example, the temperature of IC chip 100 and / or IC chip 300) is within a certain range. It can also be kept constant over time when changing over temperature. The wafer (eg, the IC wafer 100 and / or the IC wafer 300) is an integrated circuit, and the wafer does not include any additional wafer terminals other than the first wafer terminal and the second wafer terminal. For example, a two-terminal IC chip is implemented based on at least FIG. 1, FIG. 2, and / or FIG. 3.

In another example, the two-terminal IC chip is also configured to periodically change the wafer current with respect to time, and change the wafer current with respect to time in each cycle so that the light emitting diode current is maintained even when the input voltage is above It is also possible to keep constant with respect to time when the voltage range is changed and the wafer temperature is changed within the above temperature range. In yet another example, the temperature range includes an upper temperature limit of 150 ° C and a lower temperature limit of -40 ° C. In another example, the voltage range includes a voltage upper limit of 370V and a voltage lower limit of 126V.

According to yet another embodiment, a two-terminal IC chip (e.g., IC chip 100 and / or IC chip 300) for an electronic system (e.g., LED driver 200) includes a first chip terminal (e.g., terminal 110 and / or terminal 310) ) And a second wafer terminal (eg, terminal 112 and / or terminal 312). The first wafer terminal is coupled to one or more components (eg, the inductor 210 and / or the diode 220) of an electronic system (eg, the LED driver 200). An electrical subsystem (e.g., LED driver 200) is configured to receive a first signal (e.g., AC voltage 250) and generate a second signal (e.g., current 296) based at least on information associated with the first signal. A wafer (e.g., IC wafer 100 and / or IC wafer 300) is configured to receive an input voltage (e.g., voltage 256) at a first wafer terminal (e.g., terminal 110) and generate a wafer current (e.g., based on the input voltage at least in part) , Current 254). The magnitude of the chip current is greater than or equal to zero. In addition, the wafer is configured to allow a wafer current to flow into the wafer at the first wafer terminal and flow out of the wafer at the second wafer terminal, or to flow into the wafer at the second wafer terminal and flow out of the wafer at the first wafer terminal, and change the wafer current with respect to time. In order to enable the electronic system (for example, the LED driver 200) to operate normally even when the first signal (for example, the AC voltage 250) is changed. The wafer is an integrated circuit, and the wafer does not include any additional wafer terminals other than the first wafer terminal and the second wafer terminal. For example, a two-terminal IC chip is implemented based on at least FIG. 1, FIG. 2, and / or FIG. 3.

In another example, a two-terminal IC wafer (eg, IC wafer 100 and / or IC wafer 300) is also configured to periodically change the wafer current with respect to time, and change the wafer current with respect to time in each cycle, So that the electronic system (for example, the LED driver 200) can operate normally even when the first signal is changed. In another example, the first signal is a voltage signal (eg, AC voltage 250) and the second signal is a current signal (eg, current 296). In yet another example, the two-terminal IC chip is also configured to change the chip current with respect to time so that the current signal (e.g., current 296) can be relative to the voltage signal (e.g., AC voltage 250) relative to the magnitude of the change Time remains constant. In yet another example, the two-terminal IC wafer is also configured to periodically change the wafer current with respect to time and change the wafer current with respect to time in each cycle so that the current signal (e.g., current 296) is even at voltage The magnitude of the signal (for example, AC voltage 250) can also be kept constant with respect to time. In yet another example, a two-terminal IC chip (e.g., IC chip 100 and / or IC chip 300) is a controller for an electronic system (e.g., LED driver 200).

FIG. 4 is a simplified schematic diagram showing an IC chip according to still another embodiment of the present invention. This illustration is only an example and should not unduly limit the scope of patent applications. Those skilled in the art will recognize many variations, substitutions, and modifications. IC chip 400 includes terminals 410 and 412, low-dropout regulator 420, capacitors 450, 452, and 454, switches 464, 466, and 468, comparator 460, NOR gates 484 and 486, NOT gates 446 and 448, and delay control elements 438 (eg, a delay controller), a reference voltage generator 470, a demagnetization sensor 472, a switch 480 (eg, a transistor), and a resistor 482.

For example, the NOR gates 484 and 486, the NOT gates 446 and 448, and the delay control element 438 (eg, a delay controller) are parts of the logic control and gate driving element 462 (eg, a logic controller and driver). In another example, capacitor 452 and switch 466 are part of a controlled switch and power supply 440. In yet another example, the capacitor 450 and the switch 464 are part of a controlled switch and power supply 442. In yet another example, capacitor 454 and switch 468 are part of a controlled switch and power supply 444.

According to one embodiment, the IC wafer 400 is an IC wafer 100 and / or an IC wafer 300. For example, the terminal 410 is the terminal 110 and / or the terminal 310 and the terminal 412 is the terminal 112 and / or the terminal 312. In another example, the low-dropout regulator 420 is an internal power source 120 and / or a low-dropout regulator 320. In yet another example, the controlled switch and power supply 440 is a combination of the controlled switch block 140 and the power supply 150, and the controlled switch and power supply 442 is a combination of the controlled switch block 142 and power supply 152. In yet another example, the controlled switch and power supply 440 is a controlled switch and power supply 340 and the controlled switch and power supply 442 is a controlled switch and power supply 342.

In yet another example, the comparator 460 is a function block 160 and / or an on-time controller 360. In yet another example, the logic control and gate driving element 462 (eg, a logic controller and driver) is a logic control and gate driving element 362 and / or a function block 162. In yet another example, the reference voltage generator 470 is a function block 170 and / or a reference voltage generator 370. In yet another example, the demagnetization sensor 472 is another functional block 170 and / or a demagnetization sensor 372.

According to another embodiment, the IC chip 400 is the IC chip 100 used in the LED driver 200 shown in FIG. 2, the terminal 410 is the terminal 110 shown in FIG. 2, and the terminal 412 is shown in FIG. 2 Of the terminal 112. According to another embodiment, the IC chip 400 is an IC chip 300 used in the LED driver 200 shown in FIG. 2.

In one embodiment, the terminal 410 receives a voltage 414 (eg, current and / or voltage 114, voltage 256, or voltage 314) from the outside of the IC chip 400, and the terminal 412 outputs a current 416 (eg, current and // (Or voltage 116, current 254, or current 316). For example, the magnitude of the current 416 is greater than or equal to zero. In another example, the voltage 414 is received by the low dropout regulator 420 and the switch 480. In another example, the switch 480 is a transistor (eg, Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). In another embodiment, the low dropout regulator 420 receives the voltage 414 and outputs a power supply voltage to the controlled switch and power supply 440, the controlled switch and power supply 442, the reference voltage generator 470, and the demagnetization sensor 472 in response. 422.

According to one embodiment, the reference voltage generator 470 outputs a reference voltage and / or current 471 (eg, a reference voltage) to the controlled switch and power supply 442. According to another embodiment, the demagnetization sensor 472 outputs a demagnetization signal 473 to the logic control and gate driving element 462 (eg, a logic controller and driver). For example, the demagnetization signal 473 indicates the start and end of each demagnetization cycle. In another example, the demagnetization period is related to the demagnetization process of the inductive coil 210.

According to another embodiment, the phase control signal 431 is received by the controlled switch and power supply 440, the controlled switch and power supply 442, and the controlled switch and power supply 444. For example, the controlled switch and power supply 440 includes a switch 466 and a capacitor 452. In another example, the controlled switch and power supply 442 includes a switch 464 and a capacitor 450. In yet another example, the controlled switch and power supply voltage 444 include a switch 468 and a capacitor 454.

According to yet another embodiment, the phase control signal 431 indicates the start and end of each on-period, and the start and end of each off-period. For example, the phase control signal 431 is at a certain logic level (e.g., a logic high level) during each on-time period (e.g., from the beginning to the end of each on-time period), and is , From the beginning to the end of each shutdown period) at another logic level (eg, a logic low level).

In one embodiment, during the on-time period indicated by the phase control signal 431, the controlled switch and the switch 466 of the power supply 440 are in a closed (eg, on) state, and during the off-time period indicated by the phase control signal 431, The controlled switch and the switch 466 of the power supply 440 are in an off (eg, off) state. For example, if the switch 466 of the controlled switch and power supply 440 is in the closed state, the capacitor 452 of the controlled switch and power supply 440 receives the power provided by the power supply voltage 422, and supplies power to the comparator 460 (for example, the power supply voltage 441). The received power (eg, charging) is stored at the same time. In another example, if the switch 466 of the controlled switch and power supply 440 is off, the capacitor 452 of the controlled switch and power supply 440 does not store any additional power provided by the power supply voltage 422, and the controlled switch and power supply 440 The energy that the capacitor 452 has stored is trapped in the controlled switch and power supply 440, except that the capacitor 452 of the controlled switch and power supply 440 still supplies power to the comparator 460 (eg, the power supply voltage 441). In another example, if the switch 446 of the controlled switch and power supply 440 is off, the capacitor 452 of the controlled switch and power supply 440 does not store any additional power provided by the power supply voltage 422, and the The energy that capacitor 452 has stored is prevented from leaking through controlled switch and switch 466 of power supply 440, although capacitor 452 of controlled switch and power supply 440 still provides power to comparator 460 (eg, power supply voltage 441).

In another embodiment, during the on-time period indicated by the phase control signal 431, the controlled switch and the switch 464 of the power supply 442 are in a closed (eg, on) state, during the off-time period indicated by the phase control signal 431, The controlled switch and the switch 464 of the power supply 442 are in an off (eg, off) state. For example, if the switch 464 of the controlled switch and power supply 442 is in the closed state, the capacitor 450 of the controlled switch and power supply 442 receives the power provided by the power supply voltage 422 and is supplying the logic control and gate drive element 462 (e.g., logic control Drivers and drivers) while providing power (eg, power supply voltage 443) while storing received power (eg, charging). In another example, if the switch 464 of the controlled switch and power supply 442 is off, the capacitor 450 of the controlled switch and power supply 442 does not store any additional power provided by the power supply voltage 422, and the controlled switch and power supply 442 The energy that the capacitor 450 has stored is trapped in the controlled switch and power supply 442. In addition to the controlled switch and power supply 442, the capacitor 450 still provides power to the logic control and gate drive elements 462 (e.g., logic controllers and drivers) ( (For example, power supply voltage 443). In another example, if the switch 464 of the controlled switch and power supply 442 is off, the capacitor 450 of the controlled switch and power supply 442 does not store any additional power provided by the power supply voltage 422, and the controlled switch and power supply 442 The stored energy of capacitor 450 is prevented from leaking through switch 464 of controlled switch and power supply 442, although capacitor 450 of controlled switch and power supply 442 still provides logic control and gate drive elements 462 (e.g., logic controllers and drivers) Provide power (e.g., power supply voltage 443).

In yet another embodiment, during the on-time period indicated by the phase control signal 431, the controlled switch and the switch 468 of the power supply voltage 444 are in a closed (e.g., on) state, and during the off-time period indicated by the phase control signal 431 During this time, the controlled switch and the switch 468 of the power supply voltage 444 are in an off (eg, off) state. For example, if the controlled switch and the switch 468 of the power supply voltage 444 are in the closed state, the capacitor 454 of the controlled switch and the power supply voltage 444 receives the power provided by the reference voltage and / or the power supply 471 (eg, the reference voltage) and is comparing the The generator 460 provides the threshold voltage 445 while storing the received power (eg, charging). In another example, if the controlled switch and the switch 468 of the power supply voltage 444 are in an open state, the capacitor 454 of the controlled switch and the power supply voltage 444 does not store a reference voltage and / or current 471 (eg, a reference voltage) Any additional power, and the energy already stored in the capacitor 454 of the controlled switch and power supply voltage 444 is trapped in the controlled switch and power supply voltage 444, except that the capacitor 454 of the controlled switch and power supply voltage 444 is still provided to the comparator 460 Outside the threshold voltage 445. In another example, if the controlled switch and the switch 468 of the power supply voltage 444 are in an open state, the capacitor 454 of the controlled switch and the power supply voltage 444 does not store a reference voltage and / or current 471 (eg, a reference voltage) Any additional power, and the energy already stored in the capacitor 454 of the controlled switch and power supply voltage 444 is prevented from leaking through the switch 468 of the controlled switch and power supply voltage 444, although the capacitor 454 of the controlled switch and power supply voltage 444 remains to the comparator 460 provides a threshold voltage 445.

According to one embodiment, the comparator 460 includes terminals 602, 604, 606, and 608. In one embodiment, the terminal 602 is used as a power input, the terminal 604 is used as a non-inverting input, and the terminal 606 is used as an inverting input. For example, the comparator 460 receives the power supply voltage 441 at the terminal 602, the current sensing voltage 483 at the terminal 604, and the threshold voltage 445 at the terminal 606. In another embodiment, the terminal 608 is used as an output. For example, the comparator 460 generates a control signal 461 and outputs the control signal 461 at a terminal 608. In yet another embodiment, the comparator 460 compares the current sense voltage 483 with a threshold voltage 445, which identifies a predetermined voltage limit corresponding to a predetermined current limit. For example, the control signal 461 indicates whether the current 416 has reached or exceeded a predetermined current limit. In another example, the control signal 461 is received by a logic control and gate driving element 462 (eg, a logic controller and driver) that also receives a demagnetization signal 473 and a power supply voltage 443. In yet another example, the logic control and gate drive element 462 (eg, a logic controller and driver) generates a drive signal 463 that is received by the switch 480 and the demagnetization sensor 472.

According to another embodiment, the demagnetization sensor 472 receives the drive signal 463 and the power supply voltage 422 and generates a demagnetization signal 473 based at least in part on the drive signal 463. For example, the drive signal 463 is coupled to the voltage 414 through a parasitic capacitor (eg, Cgd) between the gate terminal 492 of the transistor 480 and the drain terminal 490 of the transistor 489. In another example, the demagnetization signal 473 indicates the beginning and end of each demagnetization cycle. In another example, the demagnetization period is related to the demagnetization process of the inductive coil 210.

In one embodiment, the switch 480 receives the driving signal 463 and is closed or opened by the driving signal 463. For example, the drive signal 463 is a pulse width modulation (PWM) signal that changes between a logic low level and a logic high level. In another example, a pulse width modulation (PWM) signal is held at a logic high level during the pulse width (eg, during the on period of the drive signal 463). In another embodiment, if the driving signal 463 is at a logic high level, the switch 480 is turned on and then turned off, and if the driving signal 463 is at a logic low level, the switch 480 is switched and then turned on.

In yet another embodiment, the switch 480 (eg, a transistor) includes terminals 490, 492, and 494, and the resistor 482 includes terminals 496 and 498. For example, the terminal 490 of the transistor 480 is connected to the terminal 410 of the IC chip 400, and the terminal 492 of the transistor 480 is configured to receive the driving signal 463. In another example, the terminal 494 of the transistor 480 is connected to the terminal 496 of the resistor 482, and the terminal 498 of the resistor 482 is connected to the terminal 412 of the IC chip 400.

As shown in FIG. 4, according to some embodiments, the transistor 480 and the resistor 482 are biased between the voltage of the terminal 410 and the voltage of the terminal 412. For example, if transistor 480 is turned on, current 416 flows into IC chip 400 at terminal 410 through transistor 480 and resistor 482 and flows out of IC chip 400 at terminal 412. In another example, the current sense voltage 483 represents the magnitude of 416.

According to one embodiment, the comparator 360 receives the power supply voltage 441, the threshold voltage 445, and the current sensing voltage 483 and generates a control signal 461, and the demagnetization sensor 472 receives the driving signal 463 and the power supply voltage 422 and generates a demagnetization signal 473. For example, the control signal 461 is at a logic high level when the magnitude of the current sensing voltage 483 is greater than the threshold voltage 445, and the control signal 461 is at a logic low level if the magnitude of the current sensing voltage 483 is less than the threshold voltage 445. In another example, the control signal 361 indicates whether the current 416 has reached or exceeded a predetermined current limit, and the demagnetization signal 473 indicates the beginning and end of each demagnetization cycle (for example, related to the demagnetization process of the inductive coil 210). In yet another example, both the control signal 461 and the demagnetization signal 473 are received by a logic control and gate driving element 462 (eg, a logic controller and driver).

According to another embodiment, the logic control and gate driving element 462 (eg, the logic controller and driver) uses the control signal 461 and the demagnetization signal 473 to determine the pulse width of the driving signal 463 (eg, the on-time period of the driving signal 463) . For example, if the demagnetization signal 473 indicates the end of the demagnetization period (for example, related to the demagnetization process of the inductor coil 210), the pulse width of the drive signal 463 (for example, the on-time period of the drive signal 463) starts, and the switch 480 is turned off Change to ON so that the magnitude of the current 416 increases from zero. In another example, if the control signal 461 indicates that the current 416 has reached or exceeded a predetermined current limit, the pulse width of the drive signal 463 (eg, the on-time period of the drive signal 463) ends, and the switch 493 changes from on to off, And the off period of the driving signal 463 starts. In yet another example, during the off period of the drive signal 463, the magnitude of the current 416 drops to zero.

As discussed above and further emphasized here, Figure 4 is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications, for example, the IC chip 400 includes a bandgap circuit (eg, a temperature-independent voltage reference circuit). In another example, the IC chip 400 includes a reference current generator in addition to or instead of the reference voltage generator 470.

As shown in FIG. 4, according to some embodiments, the control mechanism is performed by a comparator 460, a demagnetization sensor 472, and a logic controller and driver 462. For example, the driving signal 463 generated by the logic controller and the driver 462 is used to turn on or off the transistor 480. In another example, when the transistor 480 is turned on, the current sensing voltage 483 ramps up. In another example, if the current sensing voltage 483 becomes greater than the threshold voltage 445, the comparator 460 switches and forces the control signal 461 to change from a logic high level to a logic low level. In yet another example, if the control signal 461 changes to a logic low level, the driving signal 463 also changes to turn off the transistor 480, ends the on-time period of the driving signal 463 and starts the off-time period of the driving signal 463. In yet another example, if the demagnetization signal 473 indicates the end of the demagnetization period (for example, related to the demagnetization process of the inductive coil 210), the driving signal 463 is changed to a conducting crystal 480, the off period of the driving signal 463 is ended, and the On period of the driving signal 463. In another example, each period of the driving signal 463 includes an on period of the driving signal 463 and an off period of the driving signal 463.

In one embodiment, the controlled switch and power supply 440 includes a switch 466 and a capacitor 452 and is used to store additional charge in the capacitor 452 when the switch 466 is closed, thereby allowing the comparator 460 to operate even on an external AC power source (e.g., AC Voltage 250) can still be powered up and working when it becomes unavailable. In another embodiment, the controlled switch and power supply 442 includes a switch 464 and a capacitor 450 and is used to store additional charge in the capacitor 450 when the switch 464 is closed, thereby allowing the logic controller and driver 462 to operate even on an external AC power source (For example, AC voltage 250) can still be powered on and function normally when it becomes unavailable. In yet another embodiment, the controlled switch and power supply voltage 444 includes a switch 468 and a capacitor 454, and is used to store additional charge in the capacitor 454 when the switch 468 is closed, thereby making the threshold voltage 445 even when external AC power (e.g. , AC voltage 250) can still be provided when it becomes unavailable.

According to one embodiment, in order to properly control the dissipation of the charge stored on the capacitor 452, the comparator 460 can operate at various power supply voltages 441, and the comparator 460 also has low power consumption. For example, by using a large-sized transistor as the switch 480, the Miller plateau impact of the transistor 480 is also reduced.

According to another embodiment, the logic controller and driver 462 includes NOR gates 484 and 486, NOT gates 446 and 448, and a delay control element 438 (eg, a delay controller). In one embodiment, the NOR gate 484 receives a control signal 461 and the NOR gate 486 receives a demagnetization signal 473. For example, the NOR gate 484 outputs a signal 485 to the NOT gate 446, and the NOT gate 446 generates a signal 447 in response. In another example, the signal 447 is received by a NOT gate 448 and a delay controller 438. In another embodiment, the NOT gate 448 receives the signal 447 and generates a driving signal 463 in response. For example, the signal 447 and the driving signal 463 are complementary signals. In another example, if the driving signal 463 is at a logic high level, the signal 447 is at a logic low level; if the driving signal 463 is at a logic low level, the signal 447 is at a logic high level.

According to another embodiment, the delay controller 438 receives the signal 447 and generates a phase control signal 431, where the phase control signal 431 is a signal 447 with a predetermined delay. In one embodiment, if the predetermined delay is equal to zero, the phase control signal 431 is the same as the signal 447. For example, if the predetermined delay is equal to zero, the phase control signal 431 changes from the logic low level to the logic high level while the signal 447 changes from the logic low level to the logic high level, and the phase control signal 431 changes from the logic high level to the signal 447 to The logic low level is changed from the logic high level to the logic low level at the same time.

In another embodiment, the predetermined delay is less than the delay from signal 485 to signal 447. In yet another embodiment, the predetermined delay is greater than zero. For example, if the predetermined delay is greater than zero, the phase control signal 431 changes from logic low to logic high after signal 447 is adapted from logic low to logic high, and the phase control signal 431 changes from logic high to The logic low level is then changed from the logic high level to the logic low level.

As discussed above and further emphasized here, Figure 4 is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, the delay controller 438 is removed and the signal 447 is the phase control signal 431.

FIG. 5 shows some timing charts of the IC chip 400 used as the IC chip 100 in the LED driver 200 shown in FIG. 2 according to an embodiment of the present invention. These illustrations are merely examples and should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. Waveform 510 represents AC voltage 250 as a function of time, waveform 520 represents current sensing voltage 483 as a function of time, waveform 530 represents a drive signal 463 as a function of time, waveform 540 represents a phase control signal 431 as a function of time, and waveform 550 Shows the power supply voltage 422 as a function of time. In addition, a waveform 560 represents a power supply voltage 441 as a function of time, a waveform 580 represents a reference voltage 471 as a function of time, and a waveform 590 represents a threshold voltage 445 as a function of time.

In one embodiment, as shown by waveform 550, power supply voltage 422 drops to 0 volts during at least a portion of the on-time period (eg, Ton) of drive signal 463 when drive signal 463 is at a logic high level as shown by waveform 530. For example, as shown by waveform 580, the power supply voltage 422 drops to 0 volts so that the reference voltage 471 also drops to 0 volts. In another example, as shown by waveform 530, the driving signal 463 is maintained at a logic high level during the on-time period (eg, Ton) of the driving signal 463. In yet another example, as shown by the waveform 530, the on-time period (for example, Ton) of the driving signal 463 starts at time t1 and ends at time t2, and another on-time period (for example, Ton) of the driving signal 463 is at time t3 starts and ends at time t4. In yet another example, as shown by the waveform 530, the drive signal 463 is maintained at a logic low level during the off time period (eg, Toff) of the drive signal 463. In yet another example, the off-time period (eg, Tocc) of the drive signal 463 starts at time t2 and ends at time t3, as shown by waveform 530.

In another embodiment, as shown by waveforms 530 and 540, the on-time period of the driving signal 463 (for example, Ton from time t1 to time t2) and the off-time period of the phase control signal 430 (from time t1 to time tturn-off) of t2); as shown in waveforms 530 and 540, the off-time period of the drive signal 463 (for example, Toff from time t2 to time t3) and the on-time period of the phase control signal 431 (for example, from time (tturn-off) from t2 to time t3).

For example, T _on = T _turn-off (Equation 2)

Among them, Ton indicates the on-time period of the driving signal 463, and Tturn-off indicates the off-time period of the phase control signal 431.

In another example, T _off = T _turn-on (Equation 3)

Among them, Toff indicates an off period of the driving signal 463, and Tturn-off indicates an on period of the phase control signal 431.

In yet another example, a combination of the on period of the driving signal 463 (eg, Ton from time t1 to time t2) and the off period of the driving signal 463 (eg, Toff from time t2 to time t3) represent driving Off period of signal 463. In yet another example, the switching period of the driving signal 463 starts at time t1 and ends at time t3. In yet another example, the pulse width of the driving signal 463 starts at time t1 and ends at time t2. In another example, the pulse width of the driving signal 463 starts at time t3 and ends at time t4.

In another embodiment, the on-time period of the driving signal 463 (for example, Ton from time t1 to time t2) and the off-time period of the phase control signal 431 (for example, Tturn-off from time t1 to time t2) Match, as shown by waveforms 530 and 540; the off time period of the drive signal 463 (for example, Toff from time t2 to time t3) and the on time period of the phase control signal 431 (for example, from time t2 to time t3 Tturn-off matches), as shown by waveforms 530 and 540.

In another embodiment, during the on-time period (eg, Tturn-on) of the phase control signal 431, the controlled switch and the switch 466 of the power supply 440 are in a closed (eg, on) state; During the off time period (eg, Tturn-off), the controlled switch and the switch 466 of the power supply 440 are in an off (eg, off) state. For example, if switch 466 of controlled switch and power supply 440 is off, capacitor 452 of controlled switch and power supply 440 does not store any additional power provided by power supply voltage 422, and capacitor 452 of controlled switch and power supply 440 has been stored Of energy is trapped in the controlled switch and power supply 440, in addition to the capacitor 452 of the controlled switch and power supply 440 still providing power to the comparator 460 (eg, power supply voltage 441).

In another example, the phase control signal at the start of the off-time period (e.g., Tturn-off) 431, the power supply voltage is 441: Avdd _ U 1_ B = Avdd ( Equation 4)

Among them, Avdd_U1_B represents the power supply voltage 441 at the beginning of the off period of the phase control signal 431, and Avdd represents the power supply voltage 422.

In yet another example, at the end of the off period (eg, Tturn-off) of the phase control signal 431, the power supply voltage 441 becomes:

Among them, Avdd_U1_E represents the power supply voltage 441 at the end of the off period of the phase control signal 431, and Avdd represents the power supply voltage 422. In addition, Icomp represents the current consumption of the comparator 460, Tturn-off represents the off period of the phase control signal 431, and C represents the capacitance of the capacitor 452.

In yet another example, based on Equation 2, Equation 5 becomes:

Among them, Avdd_U1_E represents the power supply voltage 441 at the end of the off period of the phase control signal 431, and Avdd represents the power supply voltage 422. In addition, Icomp represents the current consumption of the comparator 460, Ton represents the on-time of the driving signal 463, and C represents the capacitance of the capacitor 452.

As shown by the waveform 560 of FIG. 5, according to some embodiments, the power supply voltage 441 has a magnitude 562 at the beginning of the off period of the phase control signal 431 (for example, at time t1), and the power supply voltage 441 is at the phase control signal 431 At the end of the off-time period (for example, at time t2), it has a size of 564. For example, the size 562 is equal to Avdd_U1_B shown in Equation 4. In another example, the size 564 is equal to Avdd_U1_E shown in Equation 6.

In one embodiment, as long as the power supply voltage 441 remains higher than the minimum amplitude of the power supply voltage 441 required for normal operation of the comparator 460, the comparator 460 can operate normally to compare the threshold voltage 445 with the current sense voltage 483, And a control signal 461 is generated.

In another embodiment, during the on-time period indicated by the phase control signal 431, the controlled switch and the switch 468 of the power supply voltage 444 are in a closed (eg, on) state; during the off-time period indicated by the phase control signal 431 The controlled switch and the switch 468 of the power supply voltage 444 are in an off (eg, off) state. For example, if the controlled switch and the switch 468 of the power supply voltage 444 are off, the capacitor 454 of the controlled switch and the power supply voltage 444 does not store any additional power provided by the reference voltage and / or the current 471 (eg, the reference voltage) And the stored energy of capacitor 454 of controlled switch and power supply voltage 444 is trapped in capacitor 454 of controlled switch and power supply voltage 444, in addition to capacitor 454 of controlled switch and power supply voltage 444 still provides a threshold to comparator 460 Outside voltage 445. In another example, if the controlled switch and the switch 468 of the power supply voltage 444 are in an open state, the capacitor 454 of the controlled switch and the power supply voltage 444 does not store a reference voltage and / or current 471 (eg, a reference voltage) Any additional power, and the energy already stored in the capacitor 454 of the controlled switch and power supply voltage 444 is prevented from leaking through the switch 468 of the controlled switch and power supply voltage 444, although the capacitor 454 of the controlled switch and power supply voltage 444 remains to the comparator 460 provides a threshold voltage 445.

In yet another embodiment, as shown by waveform 580, the reference signal 471 drops to 0 volts during at least a portion of the off-time period of the phase control signal 431 (eg, Tturn-off from time t1 to time t2). For example, during the off period of the phase control signal 431 (eg, Tturn-off from time t1 to time t2), the controlled switch and the switch 468 of the power supply voltage 444 are in an off state, so the controlled switch and the power supply voltage The energy already stored by the capacitor 454 of the capacitor 444 is trapped in the controlled switch and the power supply voltage 444, except that the capacitor 454 of the controlled switch and the power supply voltage 444 still provides the threshold voltage 445 to the comparator 460. In another example, during the off time period of the phase control signal 431 (eg, Tturn-off from time t1 to time t2), the controlled switch and the switch 468 of the power supply voltage 444 are in an off state, so the threshold voltage 445 remains stable even when the reference voltage 471 drops to 0 volts, as shown by waveforms 580 and 590.

In yet another embodiment, during the on-time period indicated by the phase control signal 431, the controlled switch and the switch 464 of the power supply 442 are in a closed (eg, on) state; during the off-time period indicated by the phase control signal 431, The controlled switch and the switch 464 of the power supply 442 are in an off (eg, off) state. For example, if the switch 464 of the controlled switch and power supply 442 is off, the capacitor 450 of the controlled switch and power supply 442 does not store any additional power provided by the power supply voltage 422, and the capacitor 450 of the controlled switch and power supply 442 has been The stored energy is trapped in the controlled switch and power supply 442, in addition to which the capacitor 450 of the controlled switch and power supply 442 still provides power (e.g., power) to the logic control and gate drive elements 462 (e.g., logic controllers and drivers) Voltage 443). In another example, if the switch 464 of the controlled switch and power supply 442 is off, the capacitor 450 of the controlled switch and power supply 442 does not store any additional power provided by the power supply voltage 422, and the controlled switch and power supply 442 The energy that the capacitor 450 has stored is prevented from leaking through the switch 464 of the controlled switch and power supply 442, although the capacitor 450 of the controlled switch and power supply 442 still provides logic control and gate drive elements 462 (e.g., logic controllers and drivers ) To provide power (eg, power supply voltage 443).

In yet another embodiment, when the controlled switch and the switch 464 of the power supply 442 are turned off (for example, at time t1), the power supply voltage 443 changes from a magnitude 572 to another magnitude 574, such as a waveform 570. For example, the change in power supply voltage 443 from magnitude 572 to magnitude 574 is caused by a redistribution of charge between capacitor 450 and one or more parasitic capacitors in logic controller and driver 462. In another example, the decrease in power supply voltage 443 from magnitude 572 to magnitude 574 is also caused by the Miller Plateau effect of transistor 480. In yet another example, after the power supply voltage 443 is reduced from the size 572 to the size 574, the power supply voltage 443 is maintained at a constant level, so that the transistor 480 remains on, as shown by the waveform 570.

According to some embodiments, a phase-locked, self-sustaining power supply is provided for LED lighting. For example, in order to support the combination of one or more power terminals and one or more control terminals, one or more phase-locked, self-sustaining power supplies are used when the AC power becomes very weak or not available in some control phases. Limit and store energy.

According to another embodiment, a two-terminal IC wafer (eg, IC wafer 100, IC wafer 300, and / or IC wafer 400) includes a first wafer terminal (eg, terminal 110, terminal 310, and / or terminal 410). Two wafer terminals (for example, terminal 112, terminal 312, and / or terminal 412), a first switch (for example, switch 464) configured to receive a control signal (for example, phase control signal 431), coupled to the first switch A first capacitor (eg, capacitor 450), a second switch (eg, switch 466) configured to receive a control signal, and a second capacitor (eg, capacitor 452) coupled to the second switch, configured to receive a control signal. A third switch (eg, switch 468), and a third capacitor (eg, capacitor 454) coupled to the third switch. The first terminal voltage (e.g., voltage 256 and / or voltage 414) is the voltage of the first wafer terminal (e.g., terminal 110, terminal 310, and / or terminal 410), and the second terminal voltage is the second wafer terminal (e.g., The voltage of the terminal 112, the terminal 312, and / or the terminal 412), the wafer voltage (for example, the voltage Vchip across the IC chip 100) is equal to the difference between the first terminal voltage and the second terminal voltage. The wafer is configured to allow a wafer current (eg, current 254, current 316, and / or current 416) to flow into the wafer at the first wafer terminal and out of the wafer at the second wafer terminal, or flow into the wafer at the second wafer terminal and at the first The wafer terminal flows out of the wafer, and the magnitude of the wafer current is greater than or equal to zero. The first switch (eg, switch 464) is further configured to be in a closed state during the first duration in response to the control signal and to be in an open state during the second duration in response to the control signal. The first capacitor (eg, capacitor 450) is configured to: in response to the first switch being in a closed state, receive a first power supply voltage (eg, power supply voltage 422) through the first switch during a first duration; in response to the first switch Is in an off state, does not store any additional power during the second duration and does not allow the first stored power to leak through the first switch; and outputs a first output voltage during the first and second durations (eg, Power supply voltage 443). A second switch (eg, switch 466) is configured to be in a closed state during the first duration in response to the control signal and to be in an open state during the second duration in response to the control signal. The second capacitor (for example, capacitor 452) is configured to: in response to the second switch being in the closed state, receive the first power supply voltage through the second switch during the first duration; in response to the second switch being in the open state, in the first No additional power is stored during the second duration and the second stored power is not allowed to leak through the second switch; and a second output voltage (eg, power supply voltage 441) is output during the first duration and the second duration. A third switch (eg, switch 468) is also configured to be in a closed state during a first duration in response to the control signal and to be in an open state during a second duration in response to the control signal. A third capacitor (e.g., capacitor 454) is configured to receive the second power supply voltage (e.g., reference voltage 471) through the third switch during the first duration in response to the third switch being in the closed state, and continue for the second duration Not storing any additional power during time does not allow the second stored power to leak through the third switch; and output a third output voltage (eg, threshold voltage 445) during the first and second durations. The wafer (for example, IC wafer 100, IC wafer 300, and / or IC wafer 400) is an integrated circuit, and the wafer does not include a first wafer terminal (for example, terminal 110, terminal 310, and / or terminal 410) and a first Any additional wafer terminals other than two wafer terminals (eg, terminal 112, terminal 312, and / or terminal 412). For example, a two-terminal IC chip is realized at least according to FIG. 4.

In another example, the two-terminal IC chip further includes a first voltage generator (eg, low-dropout regulator 420) configured to receive a first terminal voltage (eg, voltage 256 and / or voltage) 414) and generate a first power supply voltage (eg, power supply voltage 422). In yet another example, the two-terminal IC chip further includes a second voltage generator (e.g., a reference voltage generator 470) configured to receive the first power supply voltage and generate a second power supply voltage. In yet another example, the two-terminal IC chip further includes a comparator (for example, comparator 460) including a first terminal (for example, terminal 602), a second terminal (for example, terminal 604), and a third terminal (For example, terminal 606). The comparator is configured to receive a second output voltage as a power source at a first terminal, a current sensing voltage (eg, current sensing voltage 483) at a second terminal, and a third output voltage at a third terminal, and at least a portion A ground generates a comparison signal (eg, a control signal 461) based on the current sensing voltage and the third output voltage.

In yet another example, the two-terminal IC chip further includes a logic controller and driver (e.g., logic control and gate driving element 462) configured to receive the first output voltage and the comparison signal, and at least A control signal and a drive signal (eg, drive signal 463) are generated based in part on the comparison signal. In yet another example, the two-terminal IC chip further includes a demagnetization sensor (eg, demagnetization sensor 472) configured to receive a first power supply voltage and a drive signal, and based at least in part on the drive signal A demagnetization signal is generated (eg, a demagnetization signal 473). The demagnetization signal child is the beginning and end of each demagnetization cycle. In yet another example, the logic controller and driver are further configured to receive a demagnetization signal and generate a control signal and a drive signal based at least in part on the comparison signal and the demagnetization signal. In yet another example, the driving signal is a pulse width modulation signal corresponding to a pulse width of each modulation period. In yet another example, the logic controller and driver are further configured to: in response to the demagnetization signal indicating the end of the demagnetization cycle, change the driving signal to start a pulse width; and in response to the comparison signal indicating that the chip current has reached or exceeded a predetermined current limit, Change the drive signal to end the pulse width.

In yet another example, the two-terminal IC chip further includes a fourth switch (for example, transistor 480) configured to receive a driving signal, and a resistor (coupled to the fourth switch and configured to generate a current sensing voltage) (Eg, resistor 482). The fourth switch is configured for each modulation period: in the closed state during the pulse width to change the magnitude of the chip current from zero to greater than zero; and in the open state outside the modulation width to change the magnitude of the chip current The size changes from greater than zero to equal zero. In yet another example, the logic controller and driver are further configured to generate an internal signal (eg, signal 447) based at least in part on the comparison signal and the demagnetization signal, and output a control signal and a drive signal based at least in part on the internal signal. In yet another example, the driving signal and the internal signal are complementary signals. In yet another example, the control signal is an internal signal with a predetermined delay that is greater than zero. In yet another example, the control signal is the same as the internal signal.

In yet another example, the wafer is further configured to change the relationship between the wafer voltage and the wafer current with respect to time. In yet another example, a first wafer terminal is coupled to a first coil terminal (e.g., terminal 212) of an inductive coil (e.g., inductive coil 210) and a first dipole of a diode (e.g., diode 220) Body terminal (for example, terminal 224). The inductive coil further includes a second coil terminal (for example, terminal 214), and the diode further includes a second diode terminal (for example, terminal 222). A series of one or more light emitting diodes (e.g., one or more LEDs 290) are coupled to the second coil terminal and the second diode terminal, and the second diode terminal is configured to receive the rectified AC Voltage (eg, rectified voltage 252).

In another example, the two-terminal IC wafer is also configured to receive a first terminal voltage (eg, voltage 256 and / or voltage 414) at a first wafer terminal (eg, terminal 110, terminal 310, and / or terminal 410). And generate a wafer current (eg, current 254, current 316, and / or current 416) based at least in part on the first terminal voltage. In yet another example, the wafer current (e.g., current 254, current 316, and / or current 416) is configured to connect the first wafer terminal (e.g., terminal 110, terminal 310, and / or terminal 410) with the second wafer Flow between terminals (e.g., terminal 112, terminal 312, and / or terminal 412) to affect light emitting diodes flowing through a series of one or more light emitting diodes (e.g., one or more LEDs 290) Current (eg, current 296). In yet another example, the two-terminal IC wafer is also configured to change the wafer current (eg, current 254, current 316, and / or current 416) with respect to time, such that the light emitting diode current (eg, current 296) is relative to Keep constant over time. In yet another example, the two-terminal IC wafer is also configured to periodically change the wafer current with respect to time, and change the wafer current with respect to time in each cycle so that the light emitting diode current remains constant with respect to time.

According to yet another embodiment, a two-terminal IC chip (e.g., IC chip 100, IC chip 300, and / or IC chip 400) includes a first terminal (e.g., terminal 110, terminal 310, and / or terminal 410), a second A wafer terminal (e.g., terminal 112, terminal 312, and / or terminal 412), a first switch (e.g., switch 464) configured to receive a control signal (e.g., phase control signal 431) is coupled to a first switch (e.g., switch 464) A capacitor (for example, capacitor 450), a second switch (for example, switch 466) configured to receive a control signal, a second capacitor (for example, capacitor 452) coupled to the second switch, and configured to receive a first terminal A voltage generator (eg, low dropout regulator 420) that generates a voltage (eg, voltage 256 and / or voltage 414) and generates a power supply voltage (eg, power supply voltage 422). The first terminal voltage (e.g., voltage 256 and / or voltage 414) is the voltage of the first wafer terminal (e.g., terminal 110, terminal 310, and / or terminal 410), and the second terminal voltage is the second wafer terminal (e.g., The voltage of the terminal 112, the terminal 312, and / or the terminal 412), the wafer voltage (for example, the voltage Vchip across the IC chip 100) is equal to the difference between the first terminal voltage and the second terminal voltage. The wafer is configured to allow a wafer current (eg, current 254, current 316, and / or current 416) to flow into the wafer at the first wafer terminal and out of the wafer at the second wafer terminal, or flow into the wafer at the second wafer terminal and at the first The wafer terminal flows out of the wafer, and the magnitude of the wafer current is greater than or equal to zero. The first switch (eg, switch 464) is also configured to be in a closed state during a first duration in response to the control signal and to be in an open state during a second duration in response to the control signal. The first capacitor (eg, capacitor 450) is configured to: in response to the first switch being closed, receive a power supply voltage (eg, power supply voltage 422) through the first switch during the first duration; in response to the first switch being open ON state, does not store any additional power during the second duration and does not allow the first stored power to leak through the first switch; and outputs a first output voltage (eg, power supply voltage) during the first duration and the second duration 443). The second switch (eg, switch 466) is also configured to be in a closed state during the first duration in response to the control signal and to be in an open state for the second duration in response to the control signal. The second capacitor (eg, the capacitor 452) is configured to receive the power supply voltage through the second switch during the first duration in response to the second switch being in the closed state; No additional power is stored during time and the second stored power is not allowed to leak through the second switch; and a second output voltage (eg, power supply voltage 441) is output during the first duration and the second duration. Wafers (eg, IC wafer 100, IC wafer 300, and / or IC wafer 400) are integrated circuits that do not include a first wafer terminal (eg, terminal 110, terminal 310, and / or terminal 410) and a second Any additional wafer terminals (eg, any additional pins) other than the wafer terminals (eg, terminal 112, terminal 312, and / or terminal 412). For example, a two-terminal IC chip is realized at least according to FIG. 4.

In another example, the two-terminal IC chip further includes a logic controller and driver (eg, logic control and gate driving element 462) configured to receive the first output voltage and generate a control signal and drive Signal (for example, drive signal 463). In another example, the two-terminal IC chip with patent application scope item 22 further includes a demagnetization sensor (eg, demagnetization sensor 472) configured to receive a power supply voltage and a drive signal, and at least A demagnetization signal (eg, a demagnetization signal 473) is generated based in part on the drive signal, the demagnetization signal indicating the beginning and end of each demagnetization cycle. In yet another example, the logic controller and driver are further configured to receive a demagnetization signal and generate a control signal and a drive signal based at least in part on the demagnetization signal.

In yet another example, the driving signal is related to the pulse width of each switching cycle. In yet another example, the two-terminal IC chip further includes a third switch (eg, transistor 480) configured to receive a driving signal. The third switch is also configured for each switching period: in a closed state during the pulse width; and in an open state outside the pulse width. In yet another example, the magnitudes of the second duration and the pulse width are equal. In yet another example, the second duration begins after a predetermined delay after the pulse width. In yet another example, the second duration begins simultaneously with the pulse width.

In yet another example, a first wafer terminal is coupled to a first coil terminal (e.g., terminal 212) of an inductive coil (e.g., inductive coil 210) and a first dipole of a diode (e.g., diode 220) Body terminals (for example, terminal 224), the inductive coil also includes a second coil terminal (for example, terminal 214), the diode also includes a second diode terminal (for example, terminal 222), and a series of one or more lights A diode (e.g., one or more LEDs 290) is coupled to the second coil terminal and the second diode terminal, the second diode terminal being configured to receive a rectified AC voltage (e.g., rectified voltage 252). In yet another example, the wafer current (e.g., current 254, current 316, and / or current 416) is configured to connect the first wafer terminal (e.g., terminal 110, terminal 310, and / or terminal 410) with the second wafer Flow between terminals (e.g., terminal 112, terminal 312, and / or terminal 412) to affect light emitting diodes flowing through a series of one or more light emitting diodes (e.g., one or more LEDs 290) Current (eg, current 296). In yet another example, the two-terminal IC wafer is also configured to change the wafer current (eg, current 254, current 316, and / or current 416) with respect to time, such that the light emitting diode current (eg, current 296) is relative to Keep constant over time.

For example, some or all of the elements of the various embodiments of the present invention are separately and / or combined with at least another element, using one or more software components, one or more hardware components, and / or one of the software and hardware components. Or multiple combinations. In another example, some or all of the elements of various embodiments of the present invention are separately and / or combined with at least another element, using one or more circuits, for example, one or more analog circuits and / or one or Multiple digital circuits are implemented. In yet another example, various embodiments and / or examples of the invention may be combined together.

Although specific embodiments of the invention have been described, those skilled in the art will understand that there are other embodiments that are equivalent to the described embodiments. Therefore, it will be understood that the present invention is not limited to the specifically illustrated embodiments, but is limited only by the scope of the appended patent applications.

Claims (32)

    A two-terminal IC chip includes: a first chip terminal; a second chip terminal; a first switch configured to receive a control signal; a first capacitor coupled to the first switch; and a second switch configured to Receiving the control signal; a second capacitor coupled to the second switch; a third switch configured to receive the control signal; a third capacitor coupled to the third switch; wherein: the first terminal voltage is The voltage of the first wafer terminal; the second terminal voltage is the voltage of the second wafer terminal; and the wafer voltage is equal to the difference between the first terminal voltage and the second terminal voltage; wherein the wafer Configured to allow a wafer current to flow into the wafer at the first wafer terminal and out of the wafer at the second wafer terminal, or to flow into the wafer at the second wafer terminal and at the first wafer terminal Out of the wafer, the magnitude of the wafer current is greater than or equal to zero; wherein the first switch is further configured to: in response to the control signal, when the first duration Is in a closed state during the period; and is in an open state during a second duration in response to the control signal; wherein the first capacitor is configured to: in response to the first switch being in a closed state, in the first Receiving a first power voltage through the first switch during a duration; in response to the first switch being in an off state, no additional power is stored during the second duration and the first stored power is not allowed to pass The first switch leaks; and outputs a first output voltage during the first duration and the second duration; wherein the second switch is further configured to: in response to the control signal, Said first duration is in a closed state; and in response to said control signal, it is in an open state during said second duration; wherein said second capacitor is configured to: in response to said second switch being in In a closed state, receiving the first power supply voltage through the second switch during the first duration; in response to the second switch Off state, does not store any additional power during the second duration and does not allow the second stored power to leak through the second switch; and outputs during the first duration and the second duration A second output voltage; wherein the third switch is further configured to: in response to the control signal, be in a closed state during the first duration; in response to the control signal, during the second duration During the period, the third capacitor is in an open state; in response to the third switch being in a closed state, receiving a second power supply voltage through the third switch during the first duration; in response to The third switch is in an off state, does not store any additional power during the second duration and does not allow the second stored power to leak through the third switch; and during the first duration and the A third output voltage is output during the second duration; wherein: the wafer is an integrated circuit; and the wafer does not include the first wafer terminal and all Any additional wafer terminals other than the second wafer terminal.         The two-terminal IC chip according to item 1 of the scope of patent application, further comprising: a first voltage generator configured to receive the first terminal voltage and generate the first power supply voltage.         The two-terminal IC chip according to item 2 of the patent application scope, further comprising: a second voltage generator configured to receive the first power supply voltage and generate the second power supply voltage.         The two-terminal IC chip according to item 3 of the scope of patent application, further comprising: a comparator including a first terminal, a second terminal, and a third terminal; wherein the comparator is configured to: Receiving the second output voltage as a power source; receiving a current sensing voltage at the second terminal; receiving the third output voltage at the third terminal; and based at least in part on the current sensing voltage and The third output voltage generates a comparison signal.         The two-terminal IC chip according to item 4 of the patent application scope, further comprising: a logic controller and a driver configured to receive the first output voltage and the comparison signal, and generate at least in part based on the comparison signal The control signal and the driving signal.         The two-terminal IC chip according to item 5 of the patent application scope, further comprising: a demagnetization sensor configured to receive the first power supply voltage and the driving signal, and generate a demagnetization based at least in part on the driving signal Signal that indicates the beginning and end of each demagnetization cycle.         The two-terminal IC chip according to item 6 of the patent application scope, wherein the logic controller and driver are further configured to receive the demagnetization signal, and generate an at least one part based on the comparison signal and the demagnetization signal. Said control signal and said driving signal.         The two-terminal IC chip according to item 7 of the scope of patent application, wherein the driving signal is a pulse width modulation signal corresponding to a pulse width of each modulation period.         The two-terminal IC chip according to item 8 of the scope of patent application, wherein the logic controller and driver are further configured to: in response to the demagnetization signal indicating the end of a demagnetization cycle, change the driving signal to turn on the A pulse width; and in response to the comparison signal indicating that the wafer current has reached or exceeded a predetermined current limit, changing the driving signal to end the pulse width.         The two-terminal IC chip according to item 9 of the scope of patent application, further comprising: a fourth switch configured to receive the driving signal; and a resistor coupled to the fourth switch and configured to generate the current Sense the voltage; wherein the fourth switch is configured for each modulation cycle: in a closed state during the pulse width to change the magnitude of the chip current from equal to zero to greater than zero; during the pulse The outside of the width is in an off state to change the magnitude of the wafer current from greater than zero to equal zero.         The two-terminal IC chip according to item 10 of the patent application scope, wherein the logic controller and driver are further configured to: generate an internal signal based at least in part on the comparison signal and the demagnetization signal; and at least in part The ground outputs the control signal and the driving signal based on the internal signal.         The two-terminal IC chip according to item 11 of the scope of patent application, wherein the driving signal and the internal signal are complementary signals.         The two-terminal IC chip according to item 11 of the scope of patent application, wherein the control signal is the internal signal with a predetermined delay, and the predetermined delay is greater than zero.         The two-terminal IC chip according to item 11 of the scope of patent application, wherein the control signal is the same as the internal signal.         The two-terminal IC wafer according to item 1 of the scope of patent application, wherein the wafer is further configured to change a relationship between the wafer voltage and the wafer current with respect to time.         The two-terminal IC chip according to item 1 of the patent application scope, wherein the first chip terminal is coupled to a first coil terminal of an inductance coil and a first diode terminal of a diode, and the inductance coil is further Comprising a second coil terminal, said diode further comprising a second diode terminal, a series of one or more light emitting diodes being coupled to said second coil terminal and said second diode terminal, The second diode terminal is configured to receive a rectified AC voltage.         The two-terminal IC chip according to item 16 of the scope of patent application, further configured to receive the first terminal voltage at the first chip terminal, and generate the chip based at least in part on the first terminal voltage. Current.         The two-terminal IC chip according to item 17 of the scope of patent application, wherein the wafer current is configured to flow between the first wafer terminal and the second wafer terminal to affect the flow through the series The light emitting diode current of one or more light emitting diodes.         The two-terminal IC chip according to item 18 of the scope of patent application is further configured to change the wafer current with respect to time so that the light-emitting diode current remains constant with respect to time.         The two-terminal IC chip according to item 19 of the scope of patent application is further configured to periodically change the wafer current with respect to time in each cycle, and change the wafer current with respect to time, so that the The light-emitting diode current remains constant over time.         A two-terminal IC chip includes: a first chip terminal; a second chip terminal; a first switch configured to receive a control signal; a first capacitor coupled to the first switch; and a second switch configured to Receiving the control signal; a second capacitor coupled to the second switch; a voltage generator configured to receive a first terminal voltage and generate a power supply voltage; wherein the first terminal voltage is a voltage of the first chip terminal ; The second terminal voltage is a voltage of the second wafer terminal; the wafer voltage is equal to a difference between the first terminal voltage and the second terminal voltage; wherein the wafer is configured to allow a wafer current to pass through the A first wafer terminal flows into the wafer and flows out of the wafer through the second wafer terminal, or a second wafer terminal flows into the wafer and flows out of the wafer at the first wafer terminal, the wafer The magnitude of the current is greater than or equal to zero; wherein the first switch is further configured to be in a closed state during a first duration in response to the control signal. And in response to the control signal, being in an open state during a second duration; wherein the first capacitor is configured to: in response to the first switch being in a closed state, during the first duration Receiving the power supply voltage through the first switch; in response to the first switch being in an off state, no additional power is stored during the second duration and the first stored power is not allowed to pass through the first A switch is leaked; and a first output voltage is output during the first duration and the second duration; wherein the second switch is further configured to: in response to the control signal, In a closed state during time; in response to the control signal, in an open state during the second duration; wherein the second capacitor is further configured to: in response to the second switch being in a closed state, in Receiving the power supply voltage through the second switch during the first duration; in response to the second switch being in an off state, in the Does not store any additional power during the second duration and does not allow the second stored power to leak through the second switch; and outputs a second output voltage during the first duration and the second duration; wherein: The wafer is an integrated circuit; and the wafer does not include any additional wafer terminals other than the first wafer terminal and the second wafer terminal.         The two-terminal IC chip according to item 21 of the scope of patent application, further comprising: a logic controller and a driver configured to receive the first output voltage and generate the control signal and the drive signal.         The two-terminal IC chip according to item 22 of the scope of patent application, further comprising: a demagnetization sensor configured to receive the power supply voltage and the drive signal, and generate a demagnetization signal based at least in part on the drive signal, The demagnetization signal indicates the start and end of each demagnetization cycle.         The two-terminal IC chip according to item 23 of the scope of patent application, wherein the logic controller and driver are further configured to receive the demagnetization signal, and generate the control signal and the at least partially based on the demagnetization signal. Mentioned drive signals.         The two-terminal IC chip according to item 24 of the patent application scope, wherein the driving signal is related to a pulse width of each switching cycle.         The two-terminal IC chip according to item 25 of the scope of patent application, further comprising: a third switch configured to receive the driving signal; wherein the third switch is further configured for each switching cycle: The pulse width is in a closed state; and outside the pulse width is in an open state.         The two-terminal IC chip according to item 26 of the scope of patent application, wherein the second duration and the pulse width are equal in size.         The two-terminal IC chip as described in claim 27, wherein the second duration starts after a predetermined delay after the start of the pulse width.         The two-terminal IC chip according to item 27 of the patent application scope, wherein the second duration starts simultaneously with the pulse width.         The two-terminal IC chip according to item 21 of the scope of patent application, wherein the first chip terminal is coupled to a first coil terminal of an inductance coil and a first diode terminal of a diode, and the inductance coil is also Including a second coil terminal, the second polar body further includes a second diode terminal, and a series of one or more light emitting diodes are coupled to the second coil terminal and the second diode terminal The second diode terminal is configured to receive a rectified AC voltage.         The two-terminal IC chip as described in claim 30, wherein the wafer current is configured to flow between the first wafer terminal and the second wafer terminal to affect the flow through the series The light emitting diode current of one or more light emitting diodes.         The two-terminal IC chip according to item 31 of the scope of patent application is further configured to change the wafer current with respect to time so that the light-emitting diode current remains constant with respect to time.