TW201821989A - Test circuit board for NGFF slot testing - Google Patents

Abstract

A test circuit board for NGFF slot testing is provided. The test circuit board is plugged on a NGFF slot of a tested circuit board through a NGFF connection interface to proceed with kinds of testing processes for the tested circuit board. In another embodiment, a plurality of NGFF connection interfaces on a test circuit board may being plugged respectively on NGFF slots of a plurality of tested circuit boards to do kinds of testing processes for the plurality of tested circuit boards through the control of a PCI-E switch chip and a test module. Therefore, the efficiency of reducing testing costand improving testing coverage may be achieved.

Description

Test board for NGFF slots

A test circuit board, in particular, a test circuit board suitable for an NGFF slot through a standard peripheral switching module and a test module for performing various corresponding test processes on the NGFF slot.

The NGFF connection interface is developed to replace the Serial Attached SCSI (SAS) connection interface. The NGFF connection interface is characterized by the use of a Peripheral Component Interconnect Express (PCI-E) connection interface. The Solid State Drive (SSD) is connected directly to the standard peripheral interface of the Fast Peripheral Interconnect.

However, the test process of the NGFF connection interface on the circuit board to be tested needs to be tested by an external solid state hard disk. However, the number of use of the solid state hard disk is limited, and the solid state hard disk is used to treat the test circuit board. The test of the NGFF connection interface is costly and fails to provide high test coverage.

In summary, it can be seen that the existing NGFF connection interface test in the prior art has a problem of high test cost and failure to provide high test coverage. Therefore, it is necessary to propose an improved technical means to solve this problem. .

In view of the prior art existing NGFF connection interface test has the problem of high test cost and failure to provide high test coverage, the present invention discloses a test circuit board system suitable for an NGFF slot and a method thereof, wherein:

A test circuit board suitable for an NGFF slot according to the first embodiment of the present invention includes: a NGFF (Next Generation Form Factor) connection interface and a test module.

The NGFF connection interface is a Peripheral Component Interconnect Express (PCI-E) connection interface for plugging into the NGFF slot of the circuit board to be tested; and the test module is electrically connected to the NGFF connection interface. It is used to test the fast peripheral interconnection standard signal, power supply test, auxiliary signal input interface (Auxiliary, AUX) test and system management bus (SMBus) test in the NGFF slot through the NGFF connection.

The test circuit board applicable to the NGFF slot according to the second embodiment of the present invention comprises: a plurality of NGFF connection interfaces, at least one shortcut peripheral interconnection standard switching (Switch) module, and a test module.

Among them, a plurality of NGFF connection interfaces adopt a Peripheral Component Interconnect Express (PCI-E) connection interface, and each NGF connection interface is respectively inserted into the NGFF slot of the circuit board to be tested; The interconnected standard switch module is divided into two logical units, each of which includes a virtual shortcut peripheral interconnect standard switching module and a non-transparent bridge (NT Bridge) module, and the non-transparent bridge module includes a non-transparent link. (NT Link) module and non-transparent virtual (NT Virtual) module, virtual shortcut peripheral interconnection standard switching module and NGFF connection interface and opaque virtual module are electrically connected, non-transparent connection module and another An NGFF connection interface is electrically connected; and the test module is respectively connected with the NGFF connection interface, the virtual shortcut peripheral interconnection standard exchange module, and the non-transparent virtual electrical connection, for connecting the standard switching module through the NGFF connection interface and the shortcut peripheral interconnection. Fast peripheral interconnection standard signal test, power supply test, auxiliary signal input interface for NGFF slot (Auxil Iary, AUX) testing and System Management Bus (SMBus) testing.

The test circuit board disclosed in the present invention is different from the prior art in that the test circuit board having the NGFF connection interface is directly inserted into the NGFF slot of the circuit board to be tested to perform various corresponding tests on the NGFF slot. The process is performed by inserting a plurality of NGFF connection interfaces into the NGFF slot of the circuit board to be tested, and interconnecting the standard switching module and the test module to perform various test processes on the NGFF slot.

Through the above technical means, the present invention can achieve the technical effect of providing a low-cost NGFF connection interface test and improving test coverage.

The embodiments of the present invention will be described in detail below with reference to the drawings and embodiments, so that the application of the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented.

The following is a description of the test circuit board for the NGFF slot according to the first embodiment of the present invention. Please refer to "1" and "2", and "1" is shown as A schematic diagram of a first embodiment of a test circuit board suitable for use in an NGFF slot is shown in FIG. 2; FIG. 2 is a schematic diagram showing a first embodiment of the test circuit board for testing the NGFF slot.

The test circuit board 10 for the NGFF slot according to the first embodiment of the present invention includes an NGFF (Next Generation Form Factor) connection interface 11 and a test module 12.

The NGFF connection interface 11 of the test circuit board 10 is implemented by using a Peripheral Component Interconnect Express (PCI-E) connection interface. In the first embodiment, each NGFF slot 21 of the circuit board 20 to be tested is tested. A single NGFF connection interface 11 for plugging in a test circuit board 10.

The test module 12 of the test circuit board 10 is electrically connected to the NGFF connection interface 11 of the test circuit board 10. The test module 12 of the test circuit board 10 can pass through the NGFF connection interface 11 of the test circuit board 10 to the corresponding circuit to be tested. The NGFF slot 21 of the board 20 performs the test of the fast peripheral interconnection standard signal, the power supply test, the auxiliary signal input interface (Auxiliary, AUX) test, and the system management bus (SMBus) test, wherein the circuit to be tested The NGFF slot 21 of the board 20 is directly electrically connected to a central processing unit (CPU) 22 of the circuit board 20 to be tested.

In addition, the test circuit board 10 further includes a direct memory access (DMA) controller 13, and the direct memory access controller 13 of the test circuit board 10 is electrically connected to the NGFF of the test circuit board 10. The connection interface 11, the direct memory access controller 13 of the test circuit board 10 is used to test the NGFF slot 21 of the test board 20 for a fast peripheral interconnection standard data stream.

The direct memory access controller 13 of the test circuit board 10 transmits a second base address set on the test circuit board 10 through a first base address register (BAR) 14 disposed on the test circuit board 10. The address data of the memory 15 is sent to the central processing unit 22 of the circuit board 20 to be tested, and the fast peripheral interconnection standard controller of the central processing unit 22 of the circuit board 20 to be tested 20 parses the address data to direct the data into place. The address of the second base register 15 of the test circuit board 10 to which the address data is mapped is transmitted through the above structure, and the direct memory access controller 13 of the test circuit board 10 can be centered with the circuit board 20 to be tested. A read/write model of a loop is formed between the processors 22, and the start and end of the data are controlled by the direct memory access controller 13 of the test circuit board 10, and the NGFF of the circuit board 20 to be tested is realized. A pressure test of a large amount of data transmission on the slot 21 is performed by the NGFF slot 21 of the test board 20 for testing the standard data stream of the fast peripheral interconnection.

The following is a description of the test circuit board for the NGFF slot according to the second embodiment of the present invention. Please refer to "3" and "4", and "3" is shown as A schematic diagram of a second embodiment of a test circuit board suitable for use in an NGFF slot is shown in FIG. 4; FIG. 4 is a schematic diagram showing a second embodiment of the test circuit board for testing the NGFF slot.

The test circuit board 10 applicable to the NGFF slot according to the second embodiment of the present invention comprises: a plurality of NGFF connection interfaces 11, at least one shortcut peripheral interconnection standard switch module 16 and a test module 12 .

The NGFF connection interface 11 of the test circuit board 10 is implemented by using a Peripheral Component Interconnect Express (PCI-E) connection interface. In the second embodiment, the first NGFF slot 211 of the circuit board 20 to be tested is tested. The fourth NGFF slot 214 is inserted into the first NGFF connection interface 111 to the fourth NGFF connection interface 114 of the test circuit board 10, and the first NGFF slot 211 to the fourth NGFF slot of the circuit board 20 to be tested. The number of 214 and the first NGFF connection interface 111 to the fourth NGFF connection interface 114 of the test circuit board 10 are merely illustrative and are not intended to limit the scope of application of the present invention.

The standard peripheral switching module 16 of the test circuit board 10 is divided into a first logic unit 161 and a second logic unit 162. The test circuit board 10 is only illustrated by a single fast peripheral interconnection standard switching module 16 as an example. The name is not limited to this. In fact, the test circuit board 10 can have a plurality of fast peripheral interconnection standard switching modules 16, and each of the fast peripheral interconnection standard switching modules 16 is divided into two logical units, that is, A single fast peripheral interconnect standard switch module 16 can provide the upper four NGFF slots of the test circuit board 20 for testing.

The first logic unit 161 includes a first virtual shortcut peripheral interconnection standard switching module 1611 and a first non-transparent bridge (NT Bridge) module 1612. The first non-transparent bridge module 1612 includes a first non-transparent bridge. The NT Link module 16121 and the first non-transparent virtual (NT Virtual) module 16122 are connected.

The second logic unit 162 includes a second virtual shortcut peripheral interconnection standard switching module 1621 and a second non-transparent bridge module 1622. The second non-transparent bridge module 1622 includes a second opaque connection module 16221 and a second non-transparent Virtual module 16222.

The first virtual open peripheral interconnect standard switch module 1611 is electrically connected to the first NGFF connection interface 111, the first opaque connection module 16121 is electrically connected to the second NGFF connection interface 112, and the second opaque connection module 16221 is electrically connected. The third NGFF connection interface 113 is electrically connected to the third NGFF connection interface, and the second virtual shortcut peripheral interconnection standard exchange module 1621 is electrically connected to the fourth NGFF connection interface 114.

The first virtual shortcut peripheral interconnect standard switch module 1611 is also electrically connected to the first opaque virtual module 16122, and the second virtual shortcut peripheral interconnect standard switch module 1621 is also electrically connected to the second opaque virtual module 16222. connection.

The test module 12 of the test circuit board 10 is electrically connected to the first NGFF connection interface 111 to the fourth NGFF connection interface 114, respectively, and the test module 12 of the test circuit board 10 is interconnected with the first virtual shortcut peripheral standard exchange mode. The group 1611, the first opaque connection module 16121, the second virtual shortcut peripheral interconnection standard switching module 1621, and the second opaque connection module 16221 are electrically connected.

For the central processing unit 22 of the circuit board 20 to be tested, the first virtual shortcut peripheral interconnection standard switching module 1611 and the second virtual shortcut peripheral interconnection standard switching module 1621 are respectively regarded as a standard exchange of fast peripheral interconnection standards. The upstream of the module 16 (PCIe Switch Upstream); and the central processing unit 22 of the circuit board 20 to be tested will respectively regard the first opaque connection module 16121 and the second opaque connection module 16221 as standard devices for fast peripheral interconnection. (PCIe Device).

The test module 12 of the test circuit board 10 can respectively test the first NGFF slot 211 of the circuit board 20 through the first NGFF connection interface 111 to the fourth NGFF connection interface 114 and the shortcut peripheral interconnection standard switching module 16 The four NGFF slots 214 perform standard peripheral signal testing, power supply testing, auxiliary signal input interface (Auxiliary, AUX) testing, and system management bus (SMBus) testing.

The central processing unit 22 of the circuit board 20 to be tested reads data from the memory 23 and sends it to the base address register (BAR) address space corresponding to the first opaque virtual module 16122. The first virtual shortcut peripheral interconnect standard switching module 1611 is directed to the first opaque virtual module 16122. The first opaque virtual module 16122 and the first opaque linking module 16121 direct data to and through the address translation. The first opaque connection module 16121 corresponds to the base address register address space, and the first NGFF slot 211 and the second NGFF slot 212 of the test circuit board 20 are subjected to the first aspect of the fast peripheral interconnection standard. Data flow testing.

The central processing unit 22 of the circuit board 20 to be tested reads data from the memory 23 and sends it to the base address register address space corresponding to the second opaque virtual module 16222, and the data is interconnected through the second virtual shortcut peripheral. The standard switch module 1621 is directed to the second opaque virtual module 16222, and the second opaque virtual module 16222 and the second opaque link module 16221 are forwarded to the second opaque virtual module by address translation. The second base register address space corresponding to the 16222 is used to test the first aspect of the fast peripheral interconnect standard data stream of the third NGFF slot 213 and the fourth NGFF slot 214 of the test circuit board 20.

In addition, the test circuit board 20 further includes a first direct memory access (DMA) controller 131, and the first direct memory access controller 131 is separately exchanged with the first virtual shortcut peripheral interconnect standard. The module 1611 and the first opaque virtual module 16122 are electrically connected to the second NGFF slot 211 and the second NGFF slot 212 of the test circuit board 20 for performing the second aspect of the fast peripheral interconnection standard data stream. Test.

The first direct memory access controller 131 transmits the address data of the base address register corresponding to the first opaque virtual module 16122 to the base to be tested through the base address register corresponding to the first opaque connection module 16121. The circuit board 20, the circuit board 20 to be tested is parsed by the shortcut peripheral interconnect standard controller for the address data, and the data is directed to the address of the base address register to which the address data is mapped, so that the circuit board to be tested is used. The first NGFF slot 211 of the 20 and the second NGFF slot 212 perform a test of the second aspect of the fast peripheral interconnect standard data stream.

The test circuit board 20 further includes a second direct memory access controller 132. The second direct memory access controller 132 interconnects the standard switching module 1621 and the second non-transparent virtual module 16222 with the second virtual shortcut peripheral. The electrical connection is used to test the second NGFF slot 213 and the fourth NGFF slot 214 of the test circuit board 20 for the second aspect of the fast peripheral interconnection standard data stream.

The second direct memory access controller 132 sends the address data of the base address register corresponding to the second opaque virtual module 16222 to the base to be tested through the base address register corresponding to the second opaque connection module 16221. The circuit board 20, the circuit board 20 to be tested is parsed by the shortcut peripheral interconnect standard controller for the address data, and the data is directed to the address of the base address register to which the address data is mapped, so that the circuit board to be tested is used. The third NGFF slot 213 and the fourth NGFF slot 214 of 20 perform the test of the second aspect of the fast peripheral interconnection standard data stream.

In summary, it can be seen that the difference between the present invention and the prior art is that a test circuit board having an NGFF connection interface is directly inserted into the NGFF slot of the circuit board to be tested to perform various corresponding testing processes on the NGFF slot. Alternatively, the NGFF slot is inserted into the NGFF slot of the circuit board to be tested by using a plurality of NGFF connection interfaces, and the standard peripheral switching module and the test module are interconnected to perform various corresponding testing processes on the NGFF slot.

By means of this technical means, the existing NGFF connection interface test existing in the prior art has the problems of high test cost and failure to provide high test coverage, thereby achieving low-cost NGFF connection interface test and improving test coverage. Technical efficacy.

While the embodiments of the present invention have been described above, the above description is not intended to limit the scope of the invention. Any changes in the form and details of the embodiments may be made without departing from the spirit and scope of the invention. The scope of the invention is to be determined by the scope of the appended claims.

10‧‧‧Test circuit board

11‧‧‧NGFF connection interface

111‧‧‧First NGFF connection interface

112‧‧‧Second NGFF connection interface

113‧‧‧ Third NGFF connection interface

114‧‧‧Four NGFF connection interface

12‧‧‧Test module

13‧‧‧Direct Memory Access Controller

131‧‧‧First Direct Memory Access Controller

132‧‧‧Second Direct Memory Access Controller

14‧‧‧First base register

15‧‧‧Second base register

16‧‧‧Quick Peripheral Interconnect Standard Switching Module

161‧‧‧First logical unit

1611‧‧‧The first virtual shortcut peripheral interconnect standard switching module

1612‧‧‧First non-transparent bridge module

16121‧‧‧First non-transparent connection module

16122‧‧‧First non-transparent virtual module

162‧‧‧Second logic unit

1621‧‧‧Second virtual shortcut peripheral interconnection standard switching module

1622‧‧‧Second non-transparent bridge module

16221‧‧‧Second non-transparent connection module

16222‧‧‧Second non-transparent virtual module

20‧‧‧Test board to be tested

21‧‧‧NGFF slot

211‧‧‧First NGFF slot

212‧‧‧Second NGFF slot

213‧‧‧ Third NGFF slot

214‧‧‧Four NGFF slot

22‧‧‧Central processor

23‧‧‧ memory

FIG. 1 is a schematic diagram showing a first embodiment of a test circuit board suitable for use in an NGFF slot according to the present invention. FIG. 2 is a schematic diagram showing the first embodiment of the present invention when testing the test circuit board for the NGFF slot. FIG. 3 is a schematic diagram showing the second embodiment of the test circuit board applicable to the NGFF slot of the present invention. FIG. 4 is a schematic diagram showing a second embodiment of the present invention when the test circuit board for testing the NGFF slot is tested.

Claims (9)

A test circuit board for an NGFF slot, comprising: an NGFF (Next Generation Form Factor) connection interface, using a Peripheral Component Interconnect Express (PCI-E) connection interface for plugging in a An NGFF slot of the circuit board to be tested; and a test module electrically connected to the NGFF connection interface for performing a fast peripheral interconnection standard signal through the NGFF connection interface to the NGFF slot Test, power supply test, auxiliary signal input interface (Auxiliary, AUX) test and system management bus (SMBus) test. The test circuit board for an NGFF slot according to the first aspect of the invention, wherein the test circuit board further comprises a direct memory access (DMA) controller, the direct memory storage The controller is electrically connected to the NGFF connection interface for testing the standard peripheral data of the fast peripheral interconnection of the NGFF slot. The test circuit board for the NGFF slot, as described in claim 2, wherein the direct memory access controller is configured by a first base address register (Base) disposed on the test circuit board. Address Register (BAR) transmits an address data of a second base register of the test circuit board to a central processing unit (CPU) of the circuit board to be tested, and a central processing unit The fast peripheral interconnect standard controller parses the address data, and directs the data to an address of the second base register to which the address data is mapped, thereby the NGFF slot Test the standard data stream of the fast peripheral interconnect. The test circuit board for the NGFF slot, as described in claim 2, wherein the NGFF slot is directly electrically connected to a central processing unit (CPU) of the circuit board to be tested. A test circuit board for an NGFF slot, comprising: a plurality of NGFF (Next Generation Form Factor) connection interfaces, using a Peripheral Component Interconnect Express (PCI-E) connection interface for each NGF The connection interface is respectively inserted into an NGFF slot of a circuit board to be tested; at least one shortcut peripheral interconnects a standard switching (Switch) module, and the fast peripheral interconnection standard switching module is divided into two logic units, each logic The unit includes a virtual shortcut peripheral interconnect standard switching module and a non-transparent bridge (NT Bridge) module, and the non-transparent bridge module includes a non-transparent link (NT Link) module and a non-transparent link a virtual virtual (NT Virtual) module, the virtual shortcut peripheral interconnect standard switching module is electrically connected to one of the NGFF connection interfaces and the non-transparent virtual module, and the non-transparent connection module and the other The NGFF connection interface is electrically connected; and a test module, the test module is respectively connected to the NGFF connection interface and the virtual shortcut peripheral The standard switching module and the non-transparent virtual electrical connection are used to test the fast peripheral interconnection standard signal of the NGFF slot through the NGFF connection interface and the shortcut peripheral interconnection standard switching module. Power supply test, Auxiliary input (AUX) test, and System Management Bus (SMBus) test. The test circuit board applicable to the NGFF slot according to claim 5, wherein the test circuit board further comprises two direct memory access (DMA) controllers, and the direct memory is stored. The controller is electrically connected to the virtual shortcut peripheral interconnect standard switching module and the non-transparent virtual module, respectively, for testing the standard peripheral data of the fast peripheral interconnection of the NGFF slot. The test circuit board applicable to the NGFF slot according to claim 5, wherein the direct memory access controller is configured by a first base address register (Base) disposed on the test circuit board. Address Register (BAR) sends address data of a second base address register disposed on the test circuit board to the circuit board to be tested, and the circuit board to be tested is connected to the standard controller by the shortcut peripheral interconnect The address data is parsed, and the data is directed to an address of the second base register to which the address data is mapped, thereby performing a fast peripheral interconnection standard data flow to the NGFF slot. Test. The test circuit board for the NGFF slot, as described in claim 5, wherein the central processing unit (CPU) of the circuit board to be tested reads a data from the memory and sends it to the server. a base address register address space corresponding to the non-transparent virtual module, the data being directed to the non-transparent virtual module through the virtual shortcut peripheral interconnect standard switching module, the non-transparent virtual module And translating the address between the non-transparent link modules to direct the data to a base address register address space corresponding to the non-transparent link module, thereby performing fast peripheral interconnection on the NGFF slot. Testing of standard data streams. The test circuit board applicable to the NGFF slot according to claim 5, wherein the central processor of the circuit board to be tested regards the virtual fast peripheral interconnection standard switching module as a fast peripheral interconnection Upstream of the standard switch module (PCIe Switch Upstream); and the central processor of the circuit board to be tested treats the opaque link module as a PCIe Device.