CN102043643B - Method for installing interrupt event processing program - Google Patents
Method for installing interrupt event processing program Download PDFInfo
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- CN102043643B CN102043643B CN 200910204136 CN200910204136A CN102043643B CN 102043643 B CN102043643 B CN 102043643B CN 200910204136 CN200910204136 CN 200910204136 CN 200910204136 A CN200910204136 A CN 200910204136A CN 102043643 B CN102043643 B CN 102043643B
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Abstract
The invention relates to a method for installing an interrupt event processing program, and the method is suitable for installing the interrupt event processing program to serve an interruption event by a computer system at an operating system. The method provided by the invention comprises the following steps: establishing a virtual function of a multifunctional peripheral component interconnection device through a basic input-output system, and selecting an unused or a virtual interruption pin to simulate a virtual interface device through the interruption pin and the virtual function; then, recording the interruption related data of the virtual interface device to an interruption routing table through the basic input-output system; and finally, setting and acquiring an interruption number of the virtual interface device according to the interruption routing table through the processing system so as to install the interruption event processing program according to the interruption number. The method for installing the interruption event processing program provided by the invention is used for installing the interruption event processing program on account of the interruption event without the corresponding peripheral component interconnection device.
Description
Technical field
The present invention relates to a kind of interrupt service mechanism, relate in particular to that a kind of (Peripheral Component Interconnect is not referred to as the PCI) method of the installation interrupt event processing program of the interrupt event of device for there being corresponding periphery component interconnection.
Background technology
Interrupt request (Interrupt Request, referred to as: be when certain device will specifically move IRQ), in order to notify and to require the CPU (central processing unit) break-off, so that CPU (central processing unit) is carried out corresponding calculating action.Traditional computer adopts programmable interruptable controller (Programmable InterruptController, referred to as: PIC) or advanced programmable interruptable controller (Advanced ProgrammableInterrupt Controller, referred to as: APIC) come the receive interruption request, and send corresponding look-at-me to CPU (central processing unit).
Generally speaking, under operating system, for example, when the application of hot plug and so on occured, peripheral unit can send interrupt event (event) and remove to trigger the interrupt event processing program (interrupt event handler) that interrupts starting correspondence.Yet, this interruption does not have corresponding periphery component interconnection (PeripheralComponent Interconnect, referred to as: PCI) device is present in the computer system, also just can't share interrupt request with other PCI device, therefore operating system can not find this handling procedure that interrupts correspondence, therefore, operating system just can't be served this interrupt event.
Summary of the invention
The purpose of this invention is to provide a kind of method that interrupt event processing program is installed, with for do not have corresponding periphery component interconnection (Peripheral Component Interconnect, referred to as: PCI) interrupt event of device is installed interrupt event processing program.
The embodiment of the invention provides a kind of method that interrupt event processing program is installed, and is applicable to a computer system and utilizes interrupt event processing program to serve an interrupt event under operating system.At this, computer system comprises Basic Input or Output System (BIOS) (Basic Input Output System, referred to as: BIOS) and multifunction peripheral assembly interconnect (Peripheral Component Interconnect, referred to as: PCI) device, wherein multifunction peripheral assembly interconnect device has and does not have use or virtual interrupt pin.The method comprises: set up a virtual functions by Basic Input or Output System (BIOS) in the multifunction peripheral assembly interconnect, and select not use or virtual interrupt pin one of them, to simulate a virtual interface device by selected interrupt pin and virtual functions; By Basic Input or Output System (BIOS) the interruption related data of virtual interface device is recorded to Interrupt Routing Table; Set and obtain the interruption numbering of virtual interface device according to Interrupt Routing Table by operating system; And by operating system according to interrupting numbering, interrupt event processing program is installed.
In one embodiment of this invention, the above-mentioned step of setting and obtain the interruption numbering of virtual interface device according to Interrupt Routing Table by operating system comprises: bus-bar number, device number and the interrupt pin number of the virtual interface device that records according to Interrupt Routing Table, set and obtain the interruption numbering of virtual interface device.
In one embodiment of this invention, above-mentioned by operating system according to interrupting numbering, the step that interrupt event processing program is installed comprises: according to interrupting numbering, by operating system interrupt event processing program is mounted in the corresponding interruption numbering field of interrupt vector table.
In one embodiment of this invention, but above-mentioned Interrupt Routing Table comprises program interrupt controller (Programmable Interrupt Controller, referred to as: interrupt request route (IRQRouting) form PIC), MultiProcessor Specification (Multi-Processor Specification, referred to as: MPS) (Advanced Configuration and PowerInterface is referred to as ACPI) form for configuration form and advanced configuration and power interface.
In one embodiment of this invention, the method for above-mentioned installation interrupt event processing program also comprises: keep an interrupt request to the virtual interface device by Basic Input or Output System (BIOS), and interrupt request is set as accurate trigger (the level trigger) in position.
In one embodiment of this invention, above-mentioned multifunction peripheral assembly interconnect device can not be disabled.
Based on above-mentioned, the embodiment of the invention is simulated a virtual interface device by existing PCI device, so that the interrupt event that hardware unit was sent is connected to arbitrarily interrupt pin, so that can installing corresponding interrupt event processing program, operating system serves this interrupt event.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and be described in detail below by reference to the accompanying drawings.
Description of drawings
Fig. 1 is the method flow diagram of the installation interrupt event processing program of one embodiment of the invention.
Fig. 2 is the synoptic diagram of the simulation one virtual interface device of one embodiment of the invention.
The main element symbol description:
200: computer system; 210: CPU (central processing unit);
220: the north bridge wafer; 230: the south bridge wafer;
The 240:PIC controller; 250: the wiring working storage;
260:IO APIC controller; The 270:PCI device;
280: the virtual interface device;
S105～S120: each step of method of the installation interrupt event processing program of one embodiment of the invention.
Embodiment
In order to make content of the present invention more clear, below the example that really can implement according to this as the present invention especially exemplified by embodiment.
Fig. 1 is the method flow diagram of the installation interrupt event processing program of one embodiment of the invention.Please refer to Fig. 1, in step S105, by Basic Input or Output System (BIOS) (Basic Input Output System, referred to as: BIOS) simulation one virtual interface device.Particularly, BIOS sets up a virtual functions in multifunction peripheral assembly interconnect (multi-function PCI device) device, and this multi-functional PCI device do not use or virtual interrupt pin in select one of them, to simulate a virtual interface device by this interrupt pin and virtual functions.
For instance, Fig. 2 is the synoptic diagram of the simulation one virtual interface device of one embodiment of the invention.Please refer to Fig. 2, in the present embodiment, computer system 200 comprises CPU (central processing unit) 210, north bridge wafer 220 and south bridge wafer 230.But south bridge wafer 230 comprises program interrupt controller (ProgrammableInterrupt Controller, referred to as: the PIC controller) 240, wiring (routing) but working storage 250, the advanced program interrupt controller of input and output (IO Advanced Programmable InterruptController, referred to as: IO APIC controller) 260 and PCI device 270.
The interrupt request that PIC controller 240 and IO APIC controller 260 send in order to receive the peripheral unit (not shown), to produce corresponding PCI look-at-me and to be sent to CPU (central processing unit) 210, can make CPU (central processing unit) 210 respond these PCI look-at-mes and start and carries out the interrupt event processing program of correspondence.
In the present embodiment, the BIOS (not shown) is sought a multi-functional PCI device that can not be disabled in computer system 200, and for example the PCI device 270 in the south bridge wafer 230 is simulated a virtual interface device to utilize PCI device 270.At this, PCI device 270 has a plurality of functions (function 0～6), and interrupt pin INT A, B.Because PCI device 270 only has and uses INT A, B, so INT C, D are non-existent interrupt pin (namely virtual interrupt pin).Therefore BIOS (for example just selects a non-existent interrupt pin, INT C), and (for example from PCI device 270, set up a non-existent function, function 7), use non-existent virtual interface device 280 of simulation, namely have the Virtual PC I device bus0/device31/function 7 of interrupt pin INT C.
At this, the interrupt event of present embodiment for example is hot plug (hot plug) interrupt event of hardware unit.Because the hot plug interrupt event does not have corresponding PCI device, therefore the virtual interface device 280 of simulating of interrupt pin INT C and the function 7 by PCI device 270 is so that CPU (central processing unit) 210 thinks that the hot plug interrupt event is to be sent by virtual interface device 280.
After the above-mentioned virtual interface device 280 of simulation, then return Fig. 1, in step S110, by BIOS the interruption related data of virtual interface device 280 is recorded to Interrupt Routing Table.Generally speaking, the Interrupt Routing Table that BIOS provides comprises: but program interrupt controller (Programmable InterruptController, referred to as: interrupt request route PIC) (IRQ Routing) form, MultiProcessor Specification (Multi-Processor Specification, referred to as: MPS) configuration form and advanced configuration and power interface (Advanced Configuration and Power Interface, referred to as ACPI) form, for operating system at mode standard (PIC), MPS pattern (APIC) or ACPI pattern (PIC or APIC) are lower to be used.
Say that further when operating system was the PIC pattern, BIOS can keep an interrupt request to virtual interface device 280, and interrupt request is set as accurate trigger (the level trigger) in position.And BIOS can set up a project (entry) with the interruption related data of record virtual interface device 280 in PIR (PCI Interrupt Request) form.
For instance, with Fig. 2, the project of PIR form for example is:＜00h, 0F8h, 0062h, 0DC58h, 0061h, 0DC58h, 006Ah, 00020h, 0000,00000,00,0 〉.Wherein, to represent the bus-bar number be 0 to 00h; It is 31 that 0F8h represents device number; " 0062h, 0DC58h ", " 0061h, 0DC58h ", " 006Ah, 00020h ", " 0000,00000 " represent respectively the working storage address of INT A, B, C, D and the bit reflection (bitmap) of available interrupt request numbering.That is to say, the interrupt pin INT C of the PCI device of bus-bar number 0/ device number 31 (virtual interface device 280 employed interrupt pin) is connected to the interruption router that the working storage address is 6Ah (interrupt router), and available interrupt request number is 5.
Moreover when the PIC pattern, BIOS also can set up the project of this virtual interface device in the program (method) of the AML of ACPI form (ACPI MachineLanguage) program _ PRT.With Fig. 2, this project for example is: Package () 0x001FFFFF, and 2, LNKG, 0}, wherein, it is 31,2 to represent INT C that 001F represents device number, program (method) LNKG then is the number of repaying IRQ.
In addition, when the MPS pattern, BIOS sets up a project equally in the MPS form.With Fig. 2, this project can be divided into source (resource) and purpose (destination).Come source record bus-bar number, interrupt pin number and device number, for example, " 0:PCI, 7eh:INT_C#1fh ", 0 represents the bus-bar number, and 1fh represents device number.And goal record the identification code of IO APIC controller 260, interrupt pin numbering, polarity (polarity), trigger condition etc., for example, " 2,22, Low; Level; INT ", 2 represent the identification code of IO APIC controller 260, and 22 represent the interrupt pin numbering, Low represents low level polarity, and Level representative level triggers; That is to say be numbered IO APIC controller 260 its interrupt pin 22 of 2 will be in the low level water interruption that is triggered at ordinary times.
In addition, when ACPI APIC pattern, the program (method) of the AML program in the ACPI form _ PRT sets up the project of virtual interface device.For example be: { wherein, 001F represents device number to Package () for 0x001FFFFF, 2,0,22}, and 2 represent INT C, and 22 represent the universe interrupt pin number of IO APIC controller; It is 22 interrupt pin that the interrupt pin INTC (virtual interface device 280 employed interrupt pin) that is to say the PCI device of bus-bar number 0/ device number 31 will be connected to universe interrupt pin number.
Afterwards, in step S115, the interruption numbering of virtual interface device be set and be obtained to operating system just can according to Interrupt Routing Table.Say further, can be reached by the initialize routine call operation system of interrupt event processing program to such an extent that interrupt numbering.Operating system then is that bus-bar number, device number and the interrupt pin number of the virtual interface device that records according to Interrupt Routing Table set south bridge wafer 230, north bridge wafer 220, to obtain the interruption numbering of virtual interface device 280.
At last, in step S120, operating system is installed interrupt event processing program according to interrupting numbering.That is to say, in the storer the inside interrupt vector table is arranged, operating system can write the inlet point of interrupt event processing program in the field of the corresponding interruption numbering in the interrupt vector table, so when CPU (central processing unit) 210 is received interruption, it can go to read in the interrupt vector table and interrupt numbering corresponding value, to obtain the inlet point of interrupt event processing program, and with CPU (central processing unit) (Central Processing Unit, referred to as: CPU) 210 control meets at this inlet point.
Interrupt event processing program with the hardware unit hot plug, when hardware unit during by hot removal, interrupt event processing program can go to check which hardware unit is removed, and notifies other application program or this hardware unit of service routine to be removed, and makes it make suitable response.For example, the diagram (icon) of hardware unit is set as the state of removing, and notice operating system is removed the driver of unloading (uninstall) hardware unit controller.On the other hand, when hardware dress dress was inserted by heat, interrupt event processing program can go just to check which hardware unit is inserted into, and notifies other application program or this hardware unit of service routine to be inserted into, and makes it make suitable response.For example, the diagram (icon) of hardware unit is set as the insertion state, and notice operating system removes to install the driver of hardware unit controller.
In sum, above-described embodiment is based on and simulates a virtual functions on the PCI device, and based on the virtual functions of this PCI device so that operating system can correctly interrupt event processing program be mounted in the interruption numbering field of correct interrupt vector table.That is to say, because therefore the not corresponding PCI device of this interrupt event simulates a virtual interface device so that CPU (central processing unit) thinks that above-mentioned interrupt event is that the PCI device sends thus.Accordingly, by above-described embodiment method, the interrupt event that hardware can be sent is connected to arbitrarily interrupt pin, serves this interrupt event so that operating system can be installed corresponding interrupt event processing program.
It should be noted that at last: above embodiment is only in order to technical scheme of the present invention to be described but not limit it, although with reference to preferred embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment or be equal to replacement technical scheme of the present invention, and these modifications or be equal to replacement and also can not make amended technical scheme break away from the spirit and scope of technical solution of the present invention.
Claims (6)
1. method that interrupt event processing program is installed, be applicable to computer system and under operating system, utilize described interrupt event processing program service disruption event, described computer system comprises Basic Input or Output System (BIOS) and multifunction peripheral assembly interconnect device, wherein said multifunction peripheral assembly interconnect device comprises not use or virtual a plurality of interrupt pin, and described method comprises:
In described multifunction peripheral assembly interconnect device, set up virtual functions by described Basic Input or Output System (BIOS), and select not use or virtual described a plurality of interrupt pin one of them, to simulate the virtual interface device by described interrupt pin and described virtual functions;
By described Basic Input or Output System (BIOS) the interruption related data of described virtual interface device is recorded to Interrupt Routing Table;
Set and obtain the interruption numbering of described virtual interface device according to described Interrupt Routing Table by described operating system; And
According to described interruption numbering, described interrupt event processing program is installed by described operating system.
2. the method for installation interrupt event processing program according to claim 1 wherein obtains the step of the described interruption numbering of described virtual interface device by described operating system according to described Interrupt Routing Table, comprising:
Bus-bar number, device number and the interrupt pin number of the described virtual interface device that records according to described Interrupt Routing Table are obtained the described interruption numbering of described virtual interface device.
3. the method for installation interrupt event processing program according to claim 1 is wherein numbered according to described interruption by described operating system, and the step that described interrupt event processing program is installed comprises:
According to described interruption numbering, by described operating system described interrupt event processing program is mounted in the corresponding interruption numbering field of interrupt vector table.
4. the method for installation interrupt event processing program according to claim 1, but wherein said Interrupt Routing Table comprises interrupt request route form, MultiProcessor Specification configuration form and advanced configuration and the power interface form of program interrupt controller.
5. the method for installation interrupt event processing program according to claim 1 also comprises:
Described Basic Input or Output System (BIOS) keeps interrupt request to described virtual interface device, and described interrupt request is set as the accurate triggering in position.
6. the method for installation interrupt event processing program according to claim 1, wherein said multifunction peripheral assembly interconnect device can not be disabled.
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| CN 200910204136 CN102043643B (en) | 2009-10-15 | 2009-10-15 | Method for installing interrupt event processing program |
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| CN 200910204136 CN102043643B (en) | 2009-10-15 | 2009-10-15 | Method for installing interrupt event processing program |
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| TWI479419B (en) * | 2012-02-08 | 2015-04-01 | Wistron Corp | Computer system and computer system processing method thereof |
| WO2017107120A1 (en) * | 2015-12-24 | 2017-06-29 | Intel Corporation | Modifying operating system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1152965A (en) * | 1994-06-08 | 1997-06-25 | 英特尔公司 | Disk drive connector interface for use PCI bus |
| CN1845086A (en) * | 2005-04-08 | 2006-10-11 | 英业达股份有限公司 | User-defined interrupt signal response processing method and system under interrupt share mechanism |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1152965A (en) * | 1994-06-08 | 1997-06-25 | 英特尔公司 | Disk drive connector interface for use PCI bus |
| CN1845086A (en) * | 2005-04-08 | 2006-10-11 | 英业达股份有限公司 | User-defined interrupt signal response processing method and system under interrupt share mechanism |
Non-Patent Citations (1)
| Title |
|---|
| 吕振洪，贾泂.《配置和获取PCI设备资源》.《计算机与现代化》.2001,(第3期),第128-134页. * |
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Effective date of registration: 20191209 Address after: Jin Xi Zhen Guan Yin Cun Fang Wu Zu, Taihu County, Anqing City, Anhui Province Patentee after: Anqing Haicheng Electronic Technology Co., Ltd Address before: Taipei City, Taiwan Chinese Shilin District Hougang Street No. 66 Patentee before: Yingda Co., Ltd. |
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Granted publication date: 20131016 Termination date: 20191015 |