TW201820572A - Chip packaging structure and manufacturing method thereof by exposing heat dissipating substrate out of the upper surface of packaging structure to effectively dissipate waste heat generated by chip - Google Patents

Abstract

The present invention discloses a chip packaging structure suitable for mounting on a circuit board. The chip packaging structure comprises a heat dissipating substrate, a chip disposed on the heat dissipating substrate, a lead frame disposed between the heat dissipating substrate and the circuit board, and an insulation packaging layer. The heat dissipating substrate comprises a first surface facing the circuit board and a second surface opposite to the first surface. The chip is disposed on the first surface of the heat dissipating substrate. The lead frame is disposed between the heat dissipating substrate and the circuit board, and comprises multiple leads electrically connected with the chip. These leads are electrically connected with the circuit board, so the chip is electrically connected with the circuit board. The insulation packaging layer encapsulates the chip and a portion of the heat dissipating substrate and the lead frame, so a portion of the second surface of the heat dissipating substrate and a portion of the leads are exposed from the insulation packaging layer.

Description

Chip package structure and manufacturing method thereof

The present invention relates to a chip packaging structure, and particularly to a chip packaging structure with good heat dissipation function and a manufacturing method thereof.

A semiconductor package is a structure for accommodating or covering one or more semiconductor wafers. Its role is to prevent the wafers from being damaged by external forces or moisture, and it can also be used as a medium for heat dissipation of the wafers.

At present, there is a Quad Flat NO-Lead package (QFN package). Because the package structure is not provided with external leads, there will be no packaging, transportation and production. The problem of lead damage greatly improves the stability of the package structure. Due to the high heat dissipation efficiency, electrical functions, and quality stability of the package structure, coupled with the characteristics of lightness, thinness, shortness, and smallness, it has now become the mainstream of the Lead Frame Base Package.

The heat dissipation substrate used for mounting a semiconductor wafer in a generally square flat leadless package structure is exposed on the lower surface of the package structure, and can be directly soldered to a printed circuit board (PCB) in use, and the wafer is radiated by the heat dissipation substrate The heat generated during operation is conducted to the printed circuit board and dissipated. However, the thermal conductivity of the printed circuit board is limited and it is difficult to use it as a good heat dissipation medium for the package structure.

Therefore, one object of the present invention is to provide a chip package structure in which a heat dissipation substrate is exposed on the upper surface of the package structure.

Therefore, another object of the present invention is to provide a method for manufacturing a chip package structure in which a heat dissipation substrate is exposed on the upper surface of the package structure.

Therefore, in some embodiments, the chip package structure of the present invention is suitable for being mounted on a circuit board. The chip package structure includes a heat dissipation substrate, a wafer disposed on the heat dissipation substrate, a chip disposed on the heat dissipation substrate, and the heat dissipation substrate. A lead frame between the circuit boards, and an insulating packaging layer covering the chip. The heat dissipation substrate includes a first surface facing the circuit board and a second surface opposite to the first surface. The wafer is disposed on the first surface of the heat dissipation substrate. The lead frame is disposed between the heat dissipation substrate and the circuit board. The lead frame includes a plurality of pins electrically connected to the chip, and the pins are electrically connected to the circuit board so that the chip is electrically connected through the pins. The circuit board. The insulating packaging layer covers the chip, and a portion of the heat dissipation substrate and the lead frame such that a portion of the second surface of the heat dissipation substrate and portions of the pins of the lead frame are exposed to the insulating packaging layer.

In some embodiments, the material of the heat dissipation substrate is metal.

In some embodiments, the heat-dissipating substrate includes a ceramic plate body and a first metal layer combined with the ceramic plate body. The ceramic plate body has a first surface connected to the chip and an opposite surface to the first surface. The second surface of the first metal layer is combined with the second surface of the ceramic plate body to form a second surface of the heat dissipation substrate together with the second surface.

In some embodiments, the ceramic plate body of the heat dissipation substrate further has a plurality of conductive structures formed on the first surface and electrically connected to the chip, and the pins of the lead frame are electrically connected to the conductive structures, respectively. So that the chip is electrically connected to the pins through the conductive structures.

In some embodiments, the heat dissipation substrate further includes a plurality of second metal layers coupled to the second surface of the ceramic plate body, and a plurality of first metal layers embedded in the ceramic plate body and having two ends penetrating the ceramic plate body. A conductive line on one surface and a second surface, one end of the conductive lines is connected to the second metal layer and the other end is connected to a part of the conductive structures.

In some embodiments, the material of the first metal layer of the heat dissipation substrate is copper, and the first metal layer is combined with the first plate of the ceramic plate by eutectic bonding, electroplating, or thick film printing technology. Two surfaces.

In some embodiments, the material of the ceramic plate of the heat dissipation substrate is aluminum nitride or aluminum oxide.

In some embodiments, the heat dissipation substrate further includes a thermally conductive metal layer disposed on the first metal layer for attaching a heat sink.

Therefore, in some embodiments, the manufacturing method of the chip packaging structure of the present invention is suitable for manufacturing a chip packaging structure mounted on a circuit board. The manufacturing method includes the following steps: (A) providing a heat dissipation substrate and a wire Frame, the heat dissipation substrate includes an opposite first surface and a second surface, and a chip is disposed on the first surface of the heat dissipation substrate; the lead frame includes a plurality of pins; (B) the first One side faces down and faces the connection surface of each pin of the lead frames, and electrically connects the chip and the pins of the lead frame; and (C) forms a covering the chip, and the heat dissipation The substrate and a portion of the lead frame are insulated with an insulating encapsulation layer such that a portion of the second surface of the heat dissipating substrate and portions of the pins of the lead frame are exposed from the upper surface of the insulating encapsulation layer.

In some embodiments, the heat dissipation substrate of step (A) includes a ceramic plate body and a first metal layer coupled to the ceramic plate body. The ceramic plate body has a first surface connected to the wafer and an opposite surface. On the second surface of the first surface, the first metal layer is bonded to the second surface of the ceramic plate body to form a second surface of the heat dissipation substrate together with the second surface.

In some embodiments, the method for manufacturing a chip package structure further includes a step (D) after the step (C), plating a first metal layer of the heat sink substrate for a heat sink to be attached. Thermally conductive metal layer.

The invention has at least the following effects: the heat dissipation substrate for mounting the chip is exposed on the upper surface of the packaging structure, and the heat generated during the operation of the chip will be conducted to the upper surface and dissipated. Compared with the conventional package structure, the heat generated during the operation of the wafer is conducted to the printed circuit board more effectively to dissipate the waste heat generated by the wafer.

Referring to FIG. 1, an embodiment of a method for manufacturing a chip packaging structure according to the present invention is suitable for manufacturing a chip packaging structure mounted on a circuit board 7 (see FIG. 7). The following describes the implementation steps of this embodiment in detail with reference to FIGS. 2 to 8.

Referring to FIGS. 2 and 3, steps S1 and S2: before performing assembly of step S3, steps S1 and S2 are performed to prepare and provide a heat dissipation substrate 1 and a lead frame 3, and a chip 2 is disposed on the heat dissipation For the substrate 1, the step S1 and the step S2 have no specific execution sequence relationship. The heat dissipation substrate 1 includes a first surface 11 and a second surface 12 opposite to each other, a ceramic plate body 13 and a first metal layer 14 coupled to the ceramic plate body 13. The material of the ceramic plate body 13 of the heat dissipation substrate 1 may be aluminum nitride or alumina, and the heat dissipation substrate 1 has a first surface 131 connected to the wafer 2 and a second surface opposite to the first surface 131. 132. The chip 2 is adhered to the first surface 131 of the ceramic plate body 13 by silver glue. The first metal layer 14 combines a metal foil with the second surface 132 of the ceramic plate body 13 by eutectic bonding, or is formed on the second surface 132 of the ceramic plate body 13 by electroplating. Together with the second surface 132 of the ceramic plate body 13, the second surface 12 of the heat dissipation substrate 1 is formed. The ceramic plate body 13 further includes a plurality of conductive structures 133 formed on the first surface 131 and electrically connected to the chip 2 by wire bonding.

In this embodiment, the heat-dissipating substrate 1 further includes a plurality of second metal layers 15 bonded to the second surface 132 of the ceramic plate body 13, and a plurality of embedded in the ceramic plate body 13, and the two ends thereof pass through respectively. The conductive line 16 between the first surface 131 and the second surface 132 of the ceramic plate body 13. One end of the conductive lines 16 is connected to the second metal layer 15 and the other end is connected to a part of the conductive structures 133, so that the chip 2 is connected to the conductive structure 133 of the conductive lines 16 and the conductive structure 133. The second metal layer 15 is electrically connected. The lead frame 3 includes a plurality of pins 31 and is temporarily fixed on an adhesive tape 8. Each of the pins 31 includes an adhesive surface 311 to which the adhesive tape 8 is adhered and a connecting surface 312 opposite to the adhesive surface 311.

Referring to FIG. 4, step S3: in this step, the assembling of the heat dissipation substrate 1 and the lead frame 3 is performed. Specifically, the first surface 11 of the heat dissipation substrate 1 faces downward, and the lead frame 3 is placed on the assembly before assembly. Below the heat-dissipating substrate 1, the chip 2 and the pins 31 of the lead frame 3 are connected to form an electrical connection. In this embodiment, the connection method between the heat dissipation substrate 1 and the lead frame 3 is to place silver glue on the conductive structure 133 of the ceramic plate body 13 and mark metal wires on the connection surfaces 312 of the pins 31, and then The silver glue on the conductive structure 133 is bonded with the metal wire, so that the heat dissipation substrate 1 is connected to the lead frame 3 and the pins 31 are electrically connected to the chip 2. After the assembly is completed, the first surface 11 of the heat dissipation substrate 1 is a connection surface 312 facing downward and facing each pin 31 of the lead frames 3.

Referring to FIG. 5, step S4: after the assembling of the heat dissipation substrate 1 and the lead frame 3 is completed, an insulating encapsulation layer 4 covering the wafer 2, the heat dissipation substrate 1 and the lead frame 3 is formed in this step. After the silver glue applied in steps S1 and S3 is cured and dried, the wafer 2, the heat dissipation substrate 1 and the lead frame 3 are covered with a fluid or powdery insulating material, and are formed after the insulating material is consolidated. The insulating encapsulation layer 4 of the wafer 2 is covered and sealed. The insulating packaging layer 4 is used to protect the chip 2 from radiation, moisture, oxygen, and external forces. Suitable insulating materials such as epoxy resin, polyimide, etc., or some silicides, oxides, etc., which do not affect the properties of the chip 2 when consolidated into an insulating encapsulation layer 4.

Referring to FIGS. 6 and 8, step S5: this step is a step of removing glue and grinding. Specifically, it is necessary to remove the adhesive tape 8 adhered to the adhesive surface 311 of each pin 31 and polish the upper surface 41 of the insulating packaging layer 4. So that the bonding surface 311 of each pin 31 exposes the lower surface 42 of the insulating encapsulation layer 4 and a part of the second surface 12 of the heat dissipation substrate 1 (the first metal layer 14 and the second metal layers). 15) The upper surface 41 of the insulating packaging layer 4 is exposed (see FIG. 8). Since the heat dissipation substrate 1 exposes the upper surface 41 of the insulating encapsulation layer 4, the waste heat generated during the operation of the wafer 2 can be led out of the insulation encapsulation layer 4 through the heat dissipation substrate 1. Compared with the conventional chip packaging structure, The way in which the waste heat is conducted to the circuit board is more effective in dissipating the waste heat generated by the wafer 2.

Referring to FIG. 7, step S6: in this step, a heat conductive metal layer 17 is plated on the heat dissipation substrate 1. The thermally conductive metal layer 17 is plated on the first metal layer 14 and the second metal layer 15 of the heat dissipation substrate 1. In this embodiment, a heat sink 9 can also be installed on the upper surface 41 of the insulating packaging layer 4 to improve the heat dissipation capability of the chip packaging structure. The thermally conductive metal layer 17 may be tin, tin-silver alloy, or Electroless Nickel Immersion Gold (ENIG). Its function is to increase the mechanical strength, thermal conductivity, and resistance of the first metal layer 14. Corrosive ability. In addition, if the chip package structure is to be mounted on the circuit board 7, the bonding surfaces 311 of the pins 31 of the lead frame 3 must also be tin-plated, tin-silver alloy, or nickel-impregnated gold to protect the Wait for pin 31. The surface of the first metal layer and the bonding surfaces 311 of the pins are plated with metal to complete the fabrication of the chip package structure.

In this embodiment, both the upper surface 41 and the lower surface 42 of the insulating encapsulation layer 4 have electrical input / output (I / O) electrical contacts, which are more flexible in use. However, in other implementations, it is also possible to set the input / output only on the lower surface 42 of the insulating encapsulation layer 4. In this case, it is not necessary to provide the second metal layers on the second surface 132 of the ceramic board 13 15 also does not need to provide such conductive lines 16 penetrating the ceramic plate body 13. In addition, the heat-dissipating substrate 1 may also be a single metal plate. Since the thermal expansion coefficient of the metal material is larger than that of the ceramic material, it is easier to expand and deform when it encounters heat, resulting in structural collapse. Since the thermal expansion coefficient of the ceramic material is close to that of the semiconductor wafer, it is less likely to be separated by stress under frequent cold and heat cycles. Therefore, the heat dissipation substrate 1 is preferably a ceramic material.

In summary, the chip packaging structure obtained by the method for manufacturing the chip packaging structure of the present invention, the heat dissipation substrate 1 for mounting the chip 2 is exposed on the upper surface 41 of the insulating packaging layer 4, and is generated when the chip 2 is in operation. The heat is conducted to the upper surface 41 to be radiated. Compared with the conventional method of chip packaging structure, the heat generated during the operation of the chip is conducted to the printed circuit board more effectively to dissipate the waste heat generated by the chip. In addition, the manufacturing method proposed in this case can realize the fabrication of the chip package structure in a simple and efficient manner, which helps to improve the yield and reduce the cost. Therefore, the chip packaging structure and manufacturing method of the present invention can indeed achieve the purpose of the present invention.

However, the above are only examples of the present invention. When the scope of implementation of the present invention cannot be limited in this way, any simple equivalent changes and modifications made in accordance with the scope of the patent application and the content of the patent specification of the present invention are still Within the scope of the invention patent.

1‧‧‧ heat dissipation substrate

11‧‧‧ the first side

12‧‧‧ second side

13‧‧‧Ceramic plate

131‧‧‧ the first surface

132‧‧‧Second surface

133‧‧‧ conductive structure

14‧‧‧ first metal layer

15‧‧‧Second metal layer

16‧‧‧Leading line

17‧‧‧ Thermally conductive metal layer

2‧‧‧Chip

3‧‧‧ lead frame

31‧‧‧pin

311‧‧‧ Adhesive surface

312‧‧‧Connecting surface

4‧‧‧ insulation package

41‧‧‧upper surface

42‧‧‧ lower surface

7‧‧‧Circuit Board

8‧‧‧Tape

9‧‧‧ heat sink

S1‧‧‧step

S2‧‧‧step

S3‧‧‧step

S4‧‧‧step

S5‧‧‧step

S6‧‧‧step

Other features and effects of the present invention will be clearly presented in the embodiment with reference to the drawings, in which: FIG. 1 is a block diagram showing a step flow of an embodiment of a manufacturing method of a chip packaging structure of the present invention; FIGS. 2 to 7 FIG. 8 is a schematic flowchart of the embodiment; and FIG. 8 is a schematic diagram illustrating a state when step S5 of one of the embodiments is completed.

Claims (11)

A chip packaging structure suitable for being mounted on a circuit board. The chip packaging structure includes: a heat dissipation substrate including a first surface facing the circuit board and a second surface opposite to the first surface; a chip Is disposed on the first side of the heat dissipation substrate; a lead frame is disposed between the heat dissipation substrate and the circuit board, the lead frame includes a plurality of pins electrically connected to the chip, and the pins are electrically connected to the circuit board So that the chip is electrically connected to the circuit board through the pins; and an insulating encapsulation layer covering the chip, and a portion of the heat dissipation substrate and the lead frame, so that a portion of the second surface of the heat dissipation substrate and a lead Parts of the pins of the rack are exposed to the insulating packaging layer. The chip package structure according to claim 1, wherein a material of the heat dissipation substrate is metal. The chip package structure according to claim 1, wherein the heat dissipation substrate includes a ceramic plate body and a first metal layer coupled to the ceramic plate body, the ceramic plate body has a first surface connected to the chip and a In contrast to the second surface of the first surface, the first metal layer is bonded to the second surface of the ceramic plate body to form a second surface of the heat dissipation substrate together with the second surface. The chip package structure according to claim 3, wherein the ceramic plate body of the heat dissipation substrate further has a plurality of conductive structures formed on the first surface and electrically connected to the chip, and the pins of the lead frame are respectively The conductive structures are electrically connected such that the chip is electrically connected to the pins through the conductive structures. The chip package structure according to claim 4, wherein the heat dissipation substrate further comprises a plurality of second metal layers bonded to the second surface of the ceramic plate body, and a plurality of embedded in the ceramic plate body with two ends penetrating therethrough. The conductive lines of the first surface and the second surface of the ceramic plate body have one end connected to the second metal layer and the other end connected to a part of the conductive structures. The chip packaging structure according to claim 5, wherein the material of the first metal layer of the heat dissipation substrate is copper, and the first metal layer is combined with the eutectic bonding, electroplating method, or thick film printing technology. The second surface of the ceramic plate body. The chip packaging structure according to claim 6, wherein the material of the ceramic plate body of the heat dissipation substrate is aluminum nitride or aluminum oxide. The chip package structure according to claim 7, wherein the heat dissipation substrate further comprises a thermally conductive metal layer disposed on the first metal layer for attaching a heat sink. A manufacturing method of a chip packaging structure is suitable for manufacturing a chip packaging structure mounted on a circuit board. The manufacturing method includes the following steps: (A) providing a heat dissipation substrate and a lead frame, the heat dissipation substrate includes an opposite one A first surface and a second surface, and a chip is disposed on the first surface of the heat dissipation substrate; the lead frame includes a plurality of pins; (B) the first surface of the heat dissipation substrate faces downward and faces the A connection surface of each pin of the lead frame, and electrically connecting the chip and the pins of the lead frame; and (C) forming a covering the chip, and insulation of the heat dissipation substrate and a portion of the lead frame The encapsulation layer exposes a portion of the second surface of the heat dissipation substrate and portions of the pins of the lead frame to the upper surface of the insulating encapsulation layer. The method for manufacturing a chip package structure according to claim 9, wherein the heat dissipation substrate of step (A) includes a ceramic plate body and a first metal layer combined with the ceramic plate body, and the ceramic plate body has a connection The first surface of the wafer and a second surface opposite to the first surface. The first metal layer is combined with the second surface of the ceramic plate body to form a second surface of the heat dissipation substrate together with the second surface. The method for manufacturing a chip package structure according to claim 10, further comprising a step (E) after the step (C), plating a first metal layer of the heat sink substrate for a heat sink to be attached. Thermally conductive metal layer.