TW201819283A - Graphene nanoribbon interconnects and interconnect liners - Google Patents

Abstract

Graphitic nanoribbon interconnects are described. The graphitic nanoribbon interconnects are fabricated by forming a graphitic layer (such as graphene) on a metal feature growth catalyst. The metal feature growth catalyst is selectively removed, leaving a graphitic nanoribbon remaining as the interconnect. Graphitic nanoribbon interconnects have a thickness of from 0.3 nanometers (nm) to 2 nm and a height of at least 40 nm. The conductive graphitic nanoribbon interconnect overcomes the need to include conventionally composed interconnect liners. Furthermore, the reduced feature size of the graphitic nanoribbon interconnect compared to conventional liners enables greater interconnect density and semiconductor device density.

Description

Graphene nanoribbon interconnects and interconnect spacers

The present invention relates to graphene nanoribbon interconnects and interconnect spacers.

In manufacturing integrated circuits, interconnects can be formed on the semiconductor substrate using a copper damascene process. Such a process typically begins with trenches and/or vias being etched into the insulator layer, barrier material deposited in the trenches, and then copper metal deposited on the barrier material to form interconnects. As device sizes continue to decrease, various interconnect components become narrower and tighter, resulting in many problems.

100‧‧‧Integrated circuit

102‧‧‧device layer

104‧‧‧Interlayer dielectric (ILD) layer

106‧‧‧Interconnect structure

112‧‧‧Metal parts

116‧‧‧Graphite barrier layer

120‧‧‧First ILD layer

X ₁ ‧‧‧Interconnect thickness

Y ₁ ‧‧‧ Thickness of tantalum-based barrier layer

Y ₂ ‧‧‧Graphene barrier layer thickness

200‧‧‧Method

204‧‧‧Step

208‧‧‧Step

212‧‧‧Step

216‧‧‧Step

220‧‧‧Step

224‧‧‧Step

304‧‧‧Base ILD layer

308‧‧‧ blanket metal layer

312‧‧‧Metal parts

316‧‧‧Graphite layer

320‧‧‧First ILD material layer

324‧‧‧Etching stop barrier

328‧‧‧The first interconnect structure

α‧‧‧Thickness

β‧‧‧Part width dimension

χ‧‧‧Part height dimension

ε‧‧‧Thickness

Φ‧‧‧Height

400‧‧‧Method

402‧‧‧Step

404‧‧‧Step

408‧‧‧Step

412‧‧‧Step

416‧‧‧Step

504‧‧‧Second ILD layer

508‧‧‧ Barrier layer

512‧‧‧Second metal parts

516‧‧‧Second interconnect structure

600‧‧‧Method

602‧‧‧Step

604‧‧‧Step

608‧‧‧Step

612‧‧‧Step

616‧‧‧Step

620‧‧‧Step

624‧‧‧Step

628‧‧‧Step

704‧‧‧Second ILD layer

706‧‧‧Second etching stop barrier

708‧‧‧ Barrier layer

712‧‧‧ blanket metal layer

714‧‧‧Second metal parts

720‧‧‧Graphite barrier layer

722‧‧‧Second interconnection structure

724‧‧‧third layer ILD

800‧‧‧Method

804‧‧‧Step

808‧‧‧Step

812‧‧‧Step

816‧‧‧Step

822‧‧‧Step

820‧‧‧Step

824‧‧‧Step

828‧‧‧Step

904‧‧‧Second blanket metal layer

912‧‧‧Second metal parts

916‧‧‧Graphite layer

918‧‧‧Stacked through holes

920‧‧‧Second ILD layer

924‧‧‧Second etching stop barrier

1000‧‧‧Method

1002‧‧‧Step

1004‧‧‧Step

1008‧‧‧Step

1012‧‧‧Step

1016‧‧‧Step

1020‧‧‧Step

1024‧‧‧Step

1028‧‧‧Step

1104‧‧‧ Cavity

1108‧‧‧ Dielectric material

1112‧‧‧Etching stop barrier

1116‧‧‧ILD layer

1118‧‧‧ barrier layer

1120‧‧‧Metal layer

1124‧‧‧Graphene Nanobelt Interconnect

1200‧‧‧Method

1204‧‧‧Step

1208‧‧‧Step

1212‧‧‧Step

1213‧‧‧Step

1216‧‧‧Step

1217‧‧‧Step

1220‧‧‧Step

1222‧‧‧Step

1224‧‧‧Step

1228‧‧‧Step

1232‧‧‧Step

1300‧‧‧Base ILD layer

1304‧‧‧Temporary ILD layer

1308‧‧‧Temporary pad

1312‧‧‧First metal parts

1314‧‧‧First metal parts

1316‧‧‧The first interconnect structure

1318‧‧‧Graphite barrier

1320‧‧‧Second ILD layer

1322‧‧‧Air gap

1404‧‧‧ blanket metal layer

1412‧‧‧The first metal part

1416‧‧‧Graphite layer

1420‧‧‧Second ILD layer

1500‧‧‧computing system

1502‧‧‧Motherboard

1504‧‧‧ processor

1506‧‧‧Communication chip

FIG. 1A shows an example integrated circuit structure including a graphite barrier layer according to an embodiment of the present disclosure.

FIG. 1B schematically shows the lateral cross-section of the interconnect body of the embodiment, and the thickness of the tantalum-based barrier layer relative to the total width of the interconnect body.

FIG. 1C schematically illustrates the lateral cross-section of the interconnect body of the example and the thickness of the graphite barrier layer relative to the total thickness of the interconnect body according to the embodiment of the present disclosure.

FIG. 2 is a flowchart of an example method of manufacturing an integrated circuit using an interconnect having a graphite barrier layer according to an embodiment of the present disclosure.

3A-3E are a series of cross-sectional side views showing a schematic integrated circuit structure of a graphite barrier layer manufactured according to the method shown in FIG. 2 according to a series of embodiments of the present disclosure.

FIG. 4 is a method flow diagram illustrating an example method for manufacturing additional interconnects and metal levels for electrical communication with graphite liner interconnects according to an embodiment of the present disclosure.

5A-5C are a series of schematic integrated circuit structures illustrating the formation of an additional interconnect layer electrically communicating with a graphite pad interconnect manufactured according to the method shown in FIG. 4 according to one embodiment of the present disclosure Cross-sectional side view.

FIG. 6 is a method flow diagram illustrating an example method for manufacturing an additional interconnector that is used to fabricate a portion of the graphite pad and electrically communicate with the graphite pad interconnect at a low level according to an embodiment of the present disclosure.

7A-7D are a series of additional interconnects according to one embodiment of the present disclosure showing a portion of the graphite liner manufactured according to the method shown in FIG. 6 and electrically communicating with the graphite liner interconnect at the lower level A cross-sectional side view of the formed rough integrated circuit structure.

FIG. 8 is a method flow diagram illustrating an example method for manufacturing an interconnection that is part of a graphite liner and that electrically communicates with the graphite liner interconnection at a low level in accordance with an embodiment of the present disclosure.

9A-9C are a series of additional interconnects according to one embodiment of the present disclosure showing a portion of the graphite liner manufactured according to the method shown in FIG. 8 and electrically communicating with the graphite liner interconnect at the lower level A cross-sectional side view of the formed rough integrated circuit structure.

10 is a method flow diagram illustrating an example method for manufacturing a graphite nanoribbon interconnect according to an embodiment of the present disclosure.

11A-11D are a series of cross-sectional side views showing a schematic integrated circuit structure of a graphite nanobelt manufactured according to a method shown in FIG. 10 according to one embodiment of the present disclosure.

FIG. 12 is a method flowchart illustrating an example method for manufacturing a graphite liner interconnect that includes an air gap as an element of an interlayer dielectric structure according to an embodiment of the present disclosure.

13A-13E are a series of schematic integrated circuit structures showing the formation of a graphite barrier layer including an air gap as an element of an interlayer dielectric structure manufactured according to the method shown in FIG. 12 according to one embodiment of the present disclosure Cross-sectional side view.

14A-14D are a series of schematic integrated circuit structures showing the formation of a graphite barrier layer including an air gap as an element of an interlayer dielectric structure manufactured according to the alternative method shown in FIG. 12 according to an embodiment of the present disclosure Cross-sectional side view.

FIG. 15 shows a mobile computing system configured according to an embodiment of the present disclosure.

It is understood that the drawings are not necessarily drawn to scale or are intended to limit the disclosure to the specific configuration shown. For example, although some drawings generally indicate straight lines, right angles, and smooth surfaces, actual implementations of the structure may have imperfect straight lines and right angles, and some components may have surface topography or otherwise be non-smooth, given the real world Processing equipment and technology limitations. In short, the drawings are provided only to show the structure of the embodiment.

[Summary of the Invention] and [Implementation Mode]

A technique for forming an integrated circuit structure including a graphite barrier layer is disclosed. Examples of the graphite barrier layer include but are not limited to graphene monolayers and groups of 1 to 5 graphene monolayers. In some embodiments herein, the terms "graphene" and "graphitic" and "graphite" are used interchangeably for convenience and without loss of breadth. Instead, all these terms refer to allotropes of carbon organized in crystalline monolayers.

These graphite barrier layers help reduce or eliminate the diffusion of metal from the metal features of one interconnect to adjacent metal features in the integrated circuit. In some embodiments, the graphite barrier layer may synthesize a crystal carrier at a position between the dielectric and the metal interconnect, for example, by using a previously deposited metal interconnect structure as a growth substrate for graphite materials ( For example, graphene, graphite, or other carbon allotropes, or carbon-containing compounds composed as one or more crystalline monolayers). In this way, according to certain embodiments, a uniform and extremely thin graphite barrier layer can be fabricated in situ on the metal portion of the interconnect. A dielectric material is then deposited around the graphene-coated metal interconnect. In some embodiments, the metal portion of the graphite liner interconnect is removed, leaving the graphite nanoribbon as the interconnect. As used herein, a graphite nanoribbon is any nano-grade graphite structure or component used as a conductive interconnect component, with virtually no other conductive bulk interconnect material. It should be noted that there may be a small amount of residual residues or traces of the previously removed conductive material bulk interconnect material, but the main conductive interconnect component material is graphite.

The disclosed technique may provide various advantages over conventional deposition techniques used to form barrier layers (also referred to as "pads") associated with interconnects. For example, the disclosed methods and materials may allow the creation of a single layer of graphite (or other suitable thickness) so that it surrounds the metal of the interconnect structure and is substantially conformal with the metal portion of the interconnect. In some embodiments, the graphite barrier layer has a thickness ranging from 0.3 nanometer (nm) to 2 nanometers. This thickness is much smaller than the thickness of a typical diffusion barrier (eg, tantalum nitride) (which ranges from 5 nm to 10 nm thick). A thinner graphite barrier layer effectively improves the electrical conductivity of metal interconnects, because a larger proportion of conductive metal can be deposited as a typical interconnect with thicker liners (eg, tantalum-based liners) The metal part of the interconnect, and therefore the area of the metal part is smaller. Furthermore, the conventional barrier layer is generally a relatively poor electrical conductor compared to the graphite layer (especially graphene). The conductivity of this improved barrier also improves the conductivity of the interconnect as a whole. Ultimately, the interface between the graphite barrier layer and the metal of the interconnect produces less surface scattering than the interface between the metal and the conventional barrier layer. Compared to conventional pad interconnects, this lower surface scattering component also tends to increase the electrical conductivity of the disclosed interconnects. According to the present invention, many configurations and changes will be apparent.

General overview

The barrier material is deposited in a layer between the non-conductive (eg, dielectric) and conductive (eg, copper metal) components of the integrated circuit. The barrier material can prevent the metal parts of the interconnect from diffusing or otherwise migrating into the dielectric material. In some cases, by making the dielectric material between these interconnects more conductive, especially when the distance between these interconnects is small, the metal diffusion from the interconnects may even be placed adjacent to each other Caused a short circuit between the interconnections. However, it is difficult to reduce the size of conventional barrier materials deposited using conventional deposition techniques. As a result, as the size of semiconductor devices and their interconnect structures gradually decreases with successive generations of technology, conventional (and poorly conductive) barrier materials occupy an increasing portion of the cross-sectional area of the interconnect. Because a smaller proportion of metal can be deposited inside the barrier layer portion of the interconnect, this increases the resistance of the interconnect. In addition, as the size shrinks, the metal deposited within the interconnect is more likely to contain voids or other defects, especially for high aspect ratio vias and interconnect components. As the size of the metal part shrinks, these defects may have a greater negative impact on the conductivity of the interconnect.

It will be understood from the present disclosure that replacing conventional barrier materials with graphite barrier layers, and particularly graphene (atomically thin and conductive carbon allotropes) barrier layers, can increase the effective conductivity of the interconnect. This advantage is achieved by reducing the proportion of interconnects occupied by less conductive pads, while increasing the proportion of cross-sectional area of interconnects occupied by more conductive metal cores. The graphite barrier layer also provides an effective diffusion barrier between the dielectric and the metal of the interconnect structure, thus reducing the possibility of short circuits between adjacent conductive structures. However, there are several challenges related to the formation of nano- or sub-nanometer graphite barriers. For example, transferring graphene or graphite material grown on a separate substrate to an integrated circuit wafer having a morphology (eg, trench) is not trivial or otherwise difficult to achieve. Furthermore, graphite materials are not easily formed on interlayer dielectric materials. This makes graphene deposition using conventional liner deposition techniques challenging in damascene or dual damascene processes.

Therefore, according to the embodiments of the present disclosure, a technique for forming a graphite barrier layer (or “graphite liner”) for an interconnect structure is provided. In a specific embodiment, the metal portion of the interconnect (referred to herein as a "metal component") is formed using a subtractive etching process. This metal part is then used as a catalyst for growing a graphite barrier layer thereon. In another embodiment, a damascene process is used to form the metal component. Then the metal parts are exposed by removing the interlayer dielectric in which the metal is deposited. Therefore, the exposed metal part can then be used as a catalyst for growing a graphite barrier layer thereon. In some embodiments, the subsequently deposited interlayer dielectric is used to form an air gap around the interconnect portion, thus improving the insulation of the dielectric layer (and reducing the capacitive effects associated with it). In another embodiment, after the graphite barrier layer is grown on the metal component, the metal component is removed. The remaining conductive graphite structure (generally referred to herein as a nanoribbon, due to its nanoscale size) is then used as an interconnect. Note that the reference to the nanobelt does not imply a specific shape. In contrast, a nanoribbon can effectively be of any shape, and generally conforms to the shape of the interconnection area it is lined with or a portion of that shape. For example, the nanobelt can be ring-shaped or box-shaped, or a single wall or part of such a shape.

The disclosed technique of forming a graphite barrier layer can provide various advantages. For example, the disclosed technology may be able to produce a graphite barrier layer having a thickness of less than 5 nanometers or less than 2 nanometers, or in the range of sub-nanometer thickness (eg, less than 1, less than 0.75, less than 0.5 nanometer thickness) , Or single layer). In a specific embodiment, the graphite barrier layer is a single layer of graphene. In other embodiments, the graphite barrier layer is a group of two to five graphene monolayers. Additionally, the graphite barrier layer may be substantially consistent with the metal components of the interconnect, and in several embodiments provide an interface that produces less surface scattering at the metal-graphene interface. Other advantages include higher interconnect conductivity than interconnects with conventional barrier layers, increased (lower) capacitance between interconnects, smaller minimum size, which can be matched with smaller Continuous technology generation of component sizes and higher device density within integrated circuits. According to the present invention, many variations and configurations will be apparent.

Graphite barrier layer

FIG. 1A shows an example of an integrated circuit 100 having an interconnection of a graphite barrier layer (such as graphene) according to an embodiment of the present disclosure. It should be noted that FIG. 1A (and FIGS. 1B and 1C) are simplified for illustrative purposes, and the actual interconnect structure generally includes structures corresponding to both conductive lines and vias.

As can be seen, the integrated circuit 100 includes a semiconductor device layer 102 (omitted from the figure below for clarity), a selective interlayer dielectric (ILD) layer 104 and an interconnect structure 106, an interconnect The structure 106 includes a first ILD layer 120 having a plurality of metal parts 112 therein, each metal part 112 having a graphite barrier layer 116. Although only one interconnect structure 106 is shown in this embodiment, other embodiments may include any number of such structures in a stacked configuration (eg, metal layers M0-M9). In addition, other embodiments may not include the selective base ILD layer 104, such as in the case where the graphene-containing interconnect structure 106 is directly disposed on the device layer 102, and functional integrated circuits are provided in this manner.

Examples of semiconductor devices that can be formed in the device layer 102 include, but are not limited to, planar field effect transistors (FETs) and non-planar FETs (eg, finned FETs or nanowire FETs), capacitors (eg, Embedded DRAM (eDRAM) capacitor), DRAM cell and SRAM cell, etc. As will be understood, the actual device implemented in the device layer 102 will depend on the target application and function of the integrated circuit 100, and the present disclosure is not intended to be limited to any particular application or functional circuit. Conversely, the technology provided herein can be used with any number of device layer 102 configurations. These devices, which are usually fabricated on a semiconductor substrate (eg, a single crystal silicon wafer) and/or within the semiconductor substrate, are in electrical communication with at least one interconnect 106. The interconnect structure 106 connects the semiconductor device of the device layer 102 to other semiconductor devices elsewhere in the integrated circuit or to the upper layer of the integrated circuit 100 through a network of selectively connected vias and conductive lines Lower level contact. For each successive layer of interconnect structure 106, generally a greater number of semiconductor devices 102 can be connected together. Finally, the semiconductor device is placed in electrical communication with the input and/or output through a series of interconnect structures 106, so that commands and/or data can be received at and/or sent from the integrated circuit 100. In other figures herein, the semiconductor device layer 102 is not shown.

The selective base ILD layer 104 (in the illustrated embodiment) is conformally disposed above the semiconductor device layer 102, thereby protecting the semiconductor device layer 102 from accidental electrical contact with other conductive components within the integrated circuit 100 And the subsequent processing for manufacturing the integrated circuit 100. In addition, the base ILD layer 104 can also be used as a surface in which the interconnect structure 106 is formed and one or more interconnect structures 106 are selectively connected to the semiconductor device layer 102. When included, the ILD 104 may be, for example, silicon dioxide or silicon nitride or some other suitable insulator material or passivation material. The thickness of the layer can be set as needed to provide the required insulation and/or protection to the underlying device layer 102.

In the illustrated embodiment implementation, the side surface of each metal component 112 included in the interconnect structure 106 is in contact with the graphite barrier layer 116. Together, the metal component 112 and the graphite barrier layer 116 form a conductive interconnect component. As described above, the barrier layer is generally used to prevent the diffusion of metal from the metal component 112 into the adjacent insulator material, thereby preventing short circuits in the integrated circuit 100 and/or otherwise preventing the interconnection and/or integrated body as a whole The electrical performance of the circuit 100 is reduced. Although traditional barrier layers are generally tantalum-based, the barriers described herein contain graphene materials, such as graphene, which can be thinner and/or more conductive.

FIGS. 1B and 1C schematically show the transverse cross-section of the interconnection member, and in the embodiment show the relative thickness of the conventional and graphite barrier layer with respect to the total width of the interconnection member. FIG. 1B schematically shows the relative thickness of the tantalum-based barrier layer relative to the thickness of the overall interconnect component. Figure 1C schematically shows the thickness of the graphite barrier layer relative to the thickness of the overall interconnect component. Upon reviewing these figures (and as described herein), it is apparent that the tantalum-based barrier layer is thicker than the graphite barrier layer, and occupies a larger cross-sectional area of the interconnect component. For example, some interconnect components may have a total width X _{1 of} 25 nm to 30 nm (and in some specific examples, the target total width X ₁ is 27 nm). As shown in FIG. 1B, a conventional (eg, tantalum-based) barrier layer may have a liner thickness Y ₁ of 5 nanometers to 10 nanometers, thus occupying an overall interconnect component width of 10 nanometers to 20 nanometers. This is compared to a graphite barrier layer having a pad thickness Y _{2 of,} for example, 0.3 nm to 1.5 nm (as shown in FIG. 1C), and therefore only occupies the overall interconnect thickness of 0.6 nm to 3 nm. Such a relatively large amount of metal in the graphene liner interconnection can partially improve the conductivity of the graphene liner interconnection and improve the efficiency of the integrated circuit device.

Method and architecture

FIG. 2 shows a method 200 for manufacturing an integrated circuit interconnect including a graphite barrier layer according to an embodiment of the present disclosure. The description of the method 200 is accompanied by a parallel description corresponding to the rough cross section of the interconnect structure of the embodiment. These cross-sections are depicted in Figures 3A to 3E.

As can be seen in this embodiment, the method 200 includes forming 204 a base ILD layer 304 on, for example, a semiconductor substrate or device layer or other ILD layer. The embodiments described in the context of FIGS. 2 and 3A-3E assume the formation of the base ILD layer 304 204, although other embodiments described below do not require the base ILD layer to be formed first (or exactly as previously explained with respect to FIG. 1A ). Furthermore, it will be understood that the embodiments of the interconnect described herein are directly or indirectly connected to the semiconductor device and contacts, regardless of whether the connection is shown in the figure. Devices that can be connected can be passive (eg, capacitors, inductors, resistors) or active (eg, transistors, diodes, amplifiers, memory cells).

In an example embodiment, the base ILD layer 304 insulates the underlying device layer, and may further include one or more interconnect components through the insulator material to electrically couple the device of the device layer to the above mutual Siamese structure and/or contacts. Examples of insulator materials that can be used for the base ILD layer 304 include, for example, nitride (eg, Si ₃ N ₄ ), oxide (eg, SiO ₂ , Al ₂ O ₃ ), oxynitride (eg, SiO _x N _y ), carbides (eg, SiC), carbon oxides, polymers, silanes, siloxanes, or other suitable insulator materials. In some embodiments, depending on the application, the base ILD layer 304 is implemented as an ultra-low-k insulator material, a low-k dielectric material, or a high-k dielectric material. Examples Low-k and ultra-low-k dielectric materials include: porous silicon dioxide, carbon-doped oxide (CDO), organic polymers such as perfluorinated cyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG) and organosilicates such as hemisiloxane, siloxane or organosilicate glass. Examples of high-k dielectric materials include, for example, hafnium oxide, silicon hafnium oxide, lanthanum oxide, aluminum lanthanum oxide, zirconia, zirconia silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium oxide Titanium, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

The technique used to form 204 the base ILD layer 304 can be any wide range of suitable deposition techniques, including but not necessarily limited to: physical vapor deposition (PVD); chemical vapor deposition (CVD); spin coating/spin coating Deposition (SOD); and/or any combination mentioned above. Other suitable configurations, materials, deposition techniques, and/or thicknesses for the base ILD layer 304 will depend on the given application and will be apparent with reference to the present disclosure.

Although some of the embodiments described herein may use damascene processes (this usually refers to both "single damascene" and "dual damascene" technologies) to etch trenches in the ILD layer, which are then filled with metal, but Method 200 uses a subtractive metal etching process instead. Therefore, as further shown in FIG. 2 and with further reference to FIG. 3A, the method 200 continues by forming 208 a blanket metal layer 308 on the base ILD layer 304. This blanket metal layer 308 will then be subtractively etched to form a metal part. These metal parts can be used as catalysts for growing graphene layers thereon, as described in more detail below.

Example deposition techniques for forming 208 the blanket metal layer 308 include, but are not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). The thickness (α) of the blanket metal layer may be, for example, greater than the final size of the metal part on which the graphene barrier layer will be deposited, because the blanket metal layer 308 can withstand various etchings that can reduce the thickness. In an embodiment, the size α may be from 10 nm to 500 nm, from 10 nm to 100 nm, from 10 nm to 50 nm, from 40 nm to 60 nm. As will be understood, the scope of these embodiments is merely illustrative, as α can be based on the type of interconnect being fabricated (eg, vias or conductive lines) and other factors, such as the metal within the fabricated integrated circuit Factors such as level and size constraints of the technology are quite different.

Example metals used to form 208 the blanket metal layer 308 and which can be subtractively etched and used as a graphene growth catalyst in subsequent stages of the method 200 include, for example, copper, aluminum, tungsten, and tantalum. Practical considerations can often require the least expensive metal acceptable for use.

After forming 208, blanket metal layer 308 is etched 212 to form metal feature 312 from blanket metal layer 308, as shown in FIG. 3B. That is, the material is selectively removed from the blanket metal layer 308. The portion of the blanket metal layer 308 remaining after etching is generally referred to herein as a metal component. In the context of FIGS. 2 and 3A-3E, the metal feature deposited on top of the base ILD layer 304 and within the first ILD layer is described as the first metal feature 312. The first metal part 312 is separated by a trench formed by the removal of other parts of the blanket metal layer 308. In some embodiments, these first metal features 312 will form part of the interconnect between the device and another metal layer or metal contact, or between metal layers, or metal contacts.

When formed, each first metal component 312 includes an exposed top surface and one or more exposed side surfaces, as shown in FIG. 3B. As will be understood, the bottom surface (relative to the top surface) of each first metal feature 312 remains in contact with the ILD layer 304 and/or the conductive interconnect features formed within the layer 304, where the conductive interconnect features are effective Ground allows proper electrical connection to the underlying device layer. In the embodiment shown in FIGS. 3B-3E, the bottom surface of the first metal member 312 is not manufactured with a gasket, graphene, or other means.

In some embodiments, subtracting the etch 212 includes selectively applying a mask to the blanket metal layer 308, thus protecting portions of the blanket metal layer 308 corresponding to the first metal component 312 from being etched. Once the mask is applied, a directional (anisotropic) etch 212 can be used to remove portions of the blanket metal layer 308 that are not protected by the mask. Anisotropic etching is used to keep the part width dimension β (represented in FIG. 3B) of the first metal part 312 from the bottom surface to the top surface approximately uniform (for example, 5 nm or less, or 2 nm or less, Or 1 nanometer or less). Anisotropic etching includes, for example, dry etching, such as reactive ion etching (RIE) using ozone, ionized argon, and the like. Other etching processes (eg, wet or isotropic) can also be used, which can result in more tapered sidewalls if a given circuit is acceptable. In a more general sense, the sidewalls and top of the interconnect member with graphite pads thereon can have any shape or profile (eg, s-shaped or other wavy, to make the cone wider at the lower part and narrower at the top Shape, orthogonal on one side and tapered, convex top, concave top, concave side wall on the other side, to name a few examples). The shape of the component can vary widely, and any such shape can be conformally coated or otherwise have a graphite liner disposed thereon.

The size β of the first metal component 312 may include, for example but not limited to, from 10 nm to 50 nm, from 5 nm to 100 nm, from 20 nm to 30 nm, and from 50 nm to 100 nm Scope. The component height dimension χ of the first metal component 312 may include but is not limited to the range indicated above as the dimension α or slightly smaller. Example values of the size χ include but are not limited to the range from 10 nm to 100 nm, from 10 nm to 50 nm, from 40 nm to 60 nm, and from 50 nm to 100 nm. Similar to the size α, the sizes β and χ are one or more types of interconnect types being manufactured, metal levels are manufactured within the integrated circuit, design rules of the technology, used to form the first metal component 312 Of etching etc.

As mentioned above, the metal used for interconnects (eg, Cu, W, Ta, etc.) can diffuse through the ILD material, thereby potentially shorting the circuits together and impairing the overall function of the integrated circuit. To prevent this diffusion, the barrier layer is typically used to encapsulate (in whole or in part) the metal parts of the interconnect. In the damascene process, where trenches are etched into the ILD layer and then filled with metal, pads are usually deposited before depositing metal features. As shown diagrammatically in FIG. 1B and the above description, the conventional liner (usually tantalum or tantalum nitride) occupies one third or more of the cross-sectional area of the trench, leaving it deposited for a given interconnect Narrow channel for body parts. This narrow channel may be difficult to fill uniformly with metal, thus further reducing the electrical performance of the interconnect.

To overcome this and other challenges, a graphite layer 316 (such as graphene) is conformally formed 216 on the exposed top or side surface of the first metal component 312, as shown in FIG. 3C. In this context, conformal means that the graphene layer is arranged on the surface of the underlying component in a relatively uniform manner (negligible changes within +/- 0.2 nm to 1 nm for the desired performance level) Above, contains the appearance of any below parts. As shown, graphene is not deposited on the bottom surface of the first metal component 312 in this embodiment because the bottom surface is in contact with the substrate ILD 304 (or more likely some underlying conductive components of the circuit). The first metal member 312 serves as a catalyst that promotes the deposition of graphene. This is beneficial because graphene and other graphite materials may be difficult to deposit on surfaces composed of materials commonly used in ILD.

In some embodiments, the thickness dimension ε of the graphite layer 316 may range from about 0.3 nm to about 1.5 nm (within normal measurement accuracy and precision limits), which corresponds to 1 graphene monolayer Up to about 5 graphene monolayers. The overall height dimension Φ shown in FIG. 3C is approximately the sum of χ and ε. The benefits of the graphene barrier layer include reduced resistance of the interconnect (the conductive path through the interconnect) and increased short circuit tolerance (between conductive features) and other benefits shown herein. In an embodiment, the aspect ratio of the height Φ and the thickness ε of the graphite layer may be from 26:1 to 133:1, from 40:1 to 200:1, or even higher than 200:1.

An example method of forming 216 a graphene layer 316 on a first metal component 312 (and any other similar metal components as will be understood) involves the use of hydrocarbon precursors (such as hexane, methane, ethylene, acetylene, etc.) Decomposition during slurry or heat enhanced chemical vapor deposition process. In one embodiment, a gas source of carbon (eg, methane) is mixed with hydrogen, and then thermally decomposed by heating the mixed gas between 800°C and 950°C. Pressure enhanced chemical vapor deposition can also be used, which reduces the deposition temperature of the carbon decomposition gas source to between 700°C and 850°C compared to the above method. The copper metal part is then exposed to the heated gas mixture at a pressure between 0.5 Torr and 50 Torr (for low pressure CVD deposition) or up to atmospheric pressure and at a flow rate of 0.5 standard cubic centimeters per minute (sccm) to 10 sccm. For the case where metal parts may be oxidized before graphene deposition, the substrate may be reduced by heating (for example, up to 1000°C for copper) and exposing the metal to hydrogen for 30 to 60 minutes. This is an example of a set of conditions for depositing graphene on copper metal parts. It should be understood that other combinations of gas, thermal profile, pressure, flow rate, and other parameters can be used to deposit graphene on a given metal part. Additional examples can be found in "A Review of Chemical Vapor Deposition of Graphene on Copper" by Mattevi, which is published in Journal of Materials Chemistry, Volume 21, pages 3324-3334 (2011).

As shown in FIG. 3D, a first ILD material layer 320 is deposited 220 between its first metal features 312 within its corresponding graphene layer 316, and then planarized. The method used to deposit 220 the first ILD layer 320 may be, for example, any method that has been described in the context of FIG. 3A. The method for depositing 220 the first ILD layer 320 also includes techniques for filling high-aspect-ratio trenches (eg, having a height-to-width aspect ratio of 2:1 or higher), like those shown in FIG. 3C It is shown between the graphene 316 coating the first metal part 312. These subsequent techniques include spin coating/spin coating deposition (SOD) of applying a reaction (optionally at the time when heat is applied) to form one or more chemical precursors of the ILD. Once the first ILD layer 320 has been deposited 220, it is planarized and/or polished 220 to form a uniform flat surface suitable for subsequent manufacturing and processing. The planarization and/or polishing techniques include a chemical mechanical planarization (CMP) process or other suitable polishing/planarization processes as needed so that another layer can be formed on top of the layer already shown in FIG. 3D. This forms a first interconnect structure 328 that contains several conductive interconnect components. The conductive interconnect components as used herein are collectively referred to as the first metal component 312 and its corresponding graphene barrier layer 316.

As shown in the example embodiment of FIG. 3D, a portion of the graphene layer 316 corresponding to the top surface of the first metal part 312 is removed. Although not wishing to be bound by theory, it has been observed that the electrical sheet resistance of graphene is extremely low in a direction parallel to the plane of the monolayer carbon atom structure (ie, parallel to the main surface of the graphene sheet). The sheet resistance of graphene sheets is higher in the direction perpendicular to the plane of the organized single-layer carbon atoms. During the deposition of the graphite layer 316, the monolayer is organized parallel to the surface of the metal member 312 on which the monolayer is formed. Therefore, a single layer of carbon atoms on the measurement surface of the first metal part 312 is parallel to those side surfaces. This provides low sheet resistance in a direction parallel to the side surface of the first metal member 312. For similar reasons, the single layer of graphene on the top surface of the first metal part 312 is parallel to the top surface of the first metal part 312. The graphene monolayer on top of the first metal part 312 provides a higher sheet resistance than the graphene monolayer on the side surface of the first metal part 312 because the monolayer on the top surface is perpendicular to the possible pass The electron flow orientation of the first metal part. For this reason, in some embodiments, one or more graphene layers on the top surface of the first metal component 312 are removed, thereby exposing the low sheet resistance graphene layer on the side of the first metal component 312 to The second interconnect formed later.

In some embodiments, an etch stop barrier 324 is deposited 224 on top of the planarization 220 top surface of the first ILD layer 320, the graphene barrier layer 316, and the first metal feature 312. An example implementation of this configuration is shown in Figure 3E. The etch stop barrier 324 is generally a material that is not affected by the etch used to etch the continuous ILD layer or has a very slow etch rate compared to the ILD. Therefore, the etch stop barrier protects the underlying components from the processing performed on the components above the etch stop barrier. Examples of the etch stop barrier 324 include aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), silicon nitride, and the like. The etch stop barrier 324 is deposited and planarized using any deposition and planarization techniques previously described in the context of the base ILD layer 304 and ILD 320.

In another embodiment, an interconnect structure fabricated according to a damascene process and having a conventional pad is placed as a first interconnect with a graphene liner interconnect component configured according to method 200 Body structure 328 electrical communication. According to one such example embodiment, FIG. 4 shows an example method 400 for manufacturing such a structure, and FIGS. 5A-5C schematically show cross-sections of example structures at various stages of manufacturing according to the method 400. It may be suitable to mix graphene-based interconnect structures (such as 328) and conventional interconnect structures on the same die or integrated circuit. For example, relatively crowded or dense interconnect structures or layers in In the case where the graphene-based interconnect component provided in is implemented, and the next interconnect structure or layer stacked thereon is implemented at a relatively low density with the conventional interconnect component. In other embodiments, all interconnect structures in a given circuit or die can be implemented with graphene-based interconnect components. Many such other embodiments and variations will be apparent from this disclosure.

It should be understood that in some embodiments, a liner (whether a tantalum-based liner or a graphite liner) may be disposed between the blanket metal layer 308 and the base ILD layer 304. Although the selective liner is omitted in the embodiment shown in FIGS. 3A-3E, when the method 200 is performed, an embodiment including such an optional liner will be included in the base ILD layer 304 and the first interconnect A portion of the pad between structures 328.

As shown in FIG. 4, and referring to FIGS. 5A-5C at the same time, the method 400 begins by performing 402 the method 200. Therefore, the previous discussion and various permutations and implementations provided with reference to Figures 2 and 3 apply here as well. The method 400 continues to deposit 404 a second ILD layer 504 on the etch stop barrier 324 of the structure shown in FIG. 3E. Next, according to the damascene manufacturing method, the trench (shown in FIG. 5B) is etched 408 into the second ILD layer 504 and passes through the etch stop barrier 324. The etch 404 through the etch stop barrier 324 exposes the top surface of the interconnect component of the first interconnect structure 328. Techniques for etching 404 the second ILD layer 504 and the etch stop barrier 324 include dry and/or wet etching (such as RIE, potassium hydroxide (KOH), and/or hydrofluoric acid (HF)) formulated to remove the ILD The insulator material of layer 504 and the material used to form etch stop barrier 324 are removed. As will be understood, several suitable etching schemes are feasible. At 412 and 416, a barrier layer 508 (such as the conventional tantalum-based barrier layer described above) and a second metal component 512 (shown in FIG. 5C) are then formed in the trench. As can be seen in the case of this embodiment, the second metal part 512 shown includes a through hole portion and a line portion. The barrier layer 508 and the second metal part 512 collectively form the conductive interconnect part of the second interconnect structure 516 directly in contact with the conductive interconnect part of the first interconnect structure 328.

According to an embodiment, another example method 600 for manufacturing an interconnect structure appears in FIG. 6. This method combines the use of both tantalum-based liners and graphite liners, each for a different part of the second interconnect structure. 7A-7D show schematic cross-sections of structures in various stages of manufacturing according to embodiments. As can be seen, an embodiment of the device manufactured by the embodiment method 600 includes a first portion with a conventional barrier layer (corresponding to the through-hole portion) and a second portion with a graphite liner (corresponding to the connection to the through-hole The second interconnect structure configured by the conductive interconnect component of the metal wire).

The embodiment method 600 includes first performing 602 method 200 (or an equivalent method) to produce the structure shown schematically in FIG. 3E. Therefore, the previous discussion and various permutations and implementations provided with reference to FIGS. 2 and 3 apply here as well. A second ILD layer 704 (shown in FIG. 7A) is formed 604 on top of the etch stop barrier 324. The second etch stop barrier 706 may be formed on the second ILD layer 704. The second ILD layer 704 and the second etch stop barrier 706 are etched 608 to form an interconnect trench. This interconnect trench is scaled and configured to form vias in a single damascene process (relative to the vias and metal lines typically formed in dual damascene process trenches as shown in FIG. 5B). This etch 608 also exposes the top surface of the underlying conductive interconnect component under the first interconnect structure 328 by etching through the etch stop barrier 324. A barrier layer 708 (eg, a tantalum-based barrier layer) is conformally deposited 612 into the trench. The blanket metal layer 712 is then deposited 616 in the via trench and above the second ILD layer 704 using any of the techniques described above in the context of FIGS. 2 and 3A.

As described above in the context of Figures 2 and 3B, the blanket metal layer is etched 620. The etching 620 is performed to form the wire part of the interconnect body part from the blanket metal layer 712 integrated with the through hole part of the interconnect body part. The metal surface exposed by etching 620 also serves as a catalyst for forming 624 the graphite barrier layer 720 thereon. The through hole portion and the pad portion form the second metal part 714. The second metal component 714 and the graphite barrier layer 720 and the barrier layer 708 collectively form the conductive interconnect component of the second interconnect structure 722 directly in contact with the conductive interconnect component of the first interconnect structure 328. A third layer of ILD 724 is deposited 628 to fill the trench between the etched metal features. An illustration of the final structure of the embodiment is presented in FIG. 7D.

Similar to method 600, some or all of the elements of method 200 can be repeated to create an interconnect stack. An embodiment method 800 for repeating some elements to produce a stacked via configuration including via interconnects through two or more ILD layers is shown in FIG. 8, while referring to the corresponding Figures 9A-9C of schematic cross-sections. Method 800 includes performing 804 method 200. Therefore, the previous discussion and various permutations and implementations provided with reference to FIGS. 2 and 3 apply here as well. The method 800 continues to expose 808 the top of the conductive interconnect features included in the first interconnect structure 328 by removing a portion of the etch stop barrier 324. A second blanket metal layer 904 is formed 812 such that the metal contacts and integrates with the top surface of the exposed conductive interconnect component of the first interconnect structure 328. The second blanket metal layer 904 is then etched 816 to produce a second metal feature 912, in this case a via integrated with the underlying first metal feature 312. Any suitable metal etching scheme can be used. Next, using a process as described above, a graphite layer 916 is formed 820 on the top surface and side surfaces of the second metal component 912. As will be understood, the second metal part 912 and its corresponding graphite layer 916 together with the underlying first metal part 312 and its corresponding graphite layer 316 collectively form a stacked through hole 918. Note that in this example implementation, the graphite layer 916 is shown fully aligned with the graphite layer 316. In other embodiments, note that the two graphite layers 916 and 316 may be at least somewhat offset from each other to provide a step or cone when transitioning from one layer to another. A second ILD layer 920 is formed at 822 around the second interconnect 918, which can then be planarized. A second etch stop barrier 924 is deposited 824 on the planarized surface of the second ILD layer 920. This process can then be selectively repeated 828 to create additional interconnects in subsequent levels of the integrated device. These interconnections may be another through hole portion or a wiring portion.

Graphite Nanobelt Interconnect Architecture

Another embodiment method 1000 (shown in FIG. 10) describes the manufacture of graphite nanoribbons (nano-grade graphite interconnection parts) that can be used as interconnections without corresponding metal parts. In contrast, the method 1000 uses only the first metal part 312 as a catalyst for forming the graphite layer. After forming the graphite layer, the metal is removed and replaced with a dielectric material (whole or part). A structural diagram of an embodiment corresponding to some stages of method 1000 is shown in FIGS. 11A-11D. The benefits of these embodiments include those indicated above, and also include reducing the size of interconnects and correspondingly increasing the density of interconnects per unit area. For example, according to some embodiments, graphene nanoribbon interconnects have a cross-sectional width from 0.3 nanometers to 2 nanometers thick, while the cross-sectional widths of conventional interconnectors far exceed 5 nanometers, such as greater than 10 nanometers Rice, or from 20 nanometers to 30 nanometers. Therefore, a smaller interconnect size can be used to support a greater number of circuits and more closely spaced circuits than can be achieved using conventional interconnects.

The embodiment method 1000 includes performing 1002 the embodiment method 200 (or equivalent method) to produce the structure shown diagrammatically in FIG. 3D. Therefore, the previous discussion and various permutations and implementations provided with reference to FIGS. 2 and 3 apply here as well. As shown in FIG. 11A (and equivalent to FIG. 3D), the top surface of the conductive interconnect component of the first interconnect structure 328 is exposed. As shown in FIG. 11B, the first metal component 312 is then removed 1004 to form a cavity 1104 defined by the graphite barrier layer 316 and the underlying substrate ILD layer 304. The first metal component 312 can be removed, for example, using directional etching, such as those above to selectively remove the metal component without removing one or more of the ILD 320 materials in the context of FIGS. 2 and 3B. Alternatively, or in addition, a mask may be used to protect portions of the ILD 320 and the graphene barrier layer 316 from metal etching.

As shown in FIG. 11C, a dielectric material 1108 such as an ILD (which may be the same as or different from one or both of those used for the base ILD 304, the first ILD layer 320) is then selectively formed 1008 in the air Cavity 1104. The techniques used to form the dielectric material 1108 in the cavity 1104 include any of the ILD deposition techniques presented above. These techniques include, but are not limited to, those used for deposition to higher aspect ratio cavities, such as spin coating/spin coating deposition (SOD). In some embodiments, other deposition techniques that are not suitable for deposition into higher aspect ratio cavities may be used. This is because the dielectric material 1108 does not necessarily need to be free of defects, and may contain voids or other defects that do not impair the function of the graphite nanoribbons as interconnects. In yet other embodiments, the cavity 1104 may remain free of ILD, thereby creating an air gap between the graphite layers (the advantages are described below).

When the graphene barrier layer 316 is placed in electrical communication with a semiconductor device or contact (not shown) and/or another electrically conductive interconnect (for example, another metal level within an integrated circuit), Each graphene barrier layer 316 may serve as a graphite nanoribbon interconnect. The following describes the manufacture and connection to another electrical interconnect, as shown in FIG. 11D.

The exposed top surfaces of the dielectric material 1108 and the graphene barrier layer 316 are planarized 1012. An etch stop barrier 1112 is deposited 1016 on this planarized surface. An ILD layer 1116 is deposited 1020 on the etch stop barrier 1112. Both the etch stop barrier 1112 and the ILD layer 1116 can be deposited according to any suitable deposition technique, such as those described above.

According to the damascene processing technique, 1024 trenches are etched in the ILD layer 1116, so that the etch stop barrier 1112 is also partially removed to expose the top surface of the underlying graphene nanoribbon interconnect component (others provided herein) Used as an interconnect pad in the embodiment). A barrier layer 1118 (eg, alumina, zirconia, or silicon nitride) and a metal layer 1120 are deposited 1028 in the trench and above the ILD layer 1116. A portion of the metal layer 1120 in the trench directly contacts the graphene nanoribbons, thus forming graphene (or more general graphite) nanoribbon interconnects 1124. This structure is shown in FIG. 11D.

As shown in FIG. 11D, it is a graphite layer previously provided on the side surface of the first metal member 312 instead of the top surface, which is used as a graphene nanoribbon interconnector. That is, as explained above in the context of FIG. 3D, the graphene layer (eg, one or more monolayers) shown in FIG. 11D is oriented parallel to the side surface. This uses a single layer of graphene with a lower sheet resistance parallel to the direction of current flow as the interconnect. However, in another embodiment not shown, some or all of the graphene layer 316 corresponding to the top surface of the first metal component may be maintained to increase the area for making contact with another interconnect. This can be achieved by, for example, adjusting the size of the protective mask or otherwise using selectively applied etching to avoid removing the top surface graphene layer when removing (eg, etching or polishing) other parts of the structure shown a part of.

In other embodiments, it should be understood that the dielectric material 1108 and/or the first ILD layer 320 may be configured to include an "air gap." The manufacture and benefits of air gaps are described in the context of Figures 12 and 13A-13E below. The application of the technology described below to the embodiments shown and described in the context of FIGS. 8 and 9A-9C will be apparent.

Although the damascene process for connecting the metal layer 1120 to the graphene nanoribbon interconnect 1124 is described in the description of FIG. 11D above, the metal layer 1120 can also be manufactured through an etching process, as described in the context of FIG. 2 above. That is, the top surface of the graphene nanoribbon interconnect 1123 is exposed, and the blanket metal layer is deposited on the exposed top surface of the barrier etch stop 1112 and the graphene nanoribbon interconnect. The metal parts are then etched from the blanket metal layer, which can then be lined with tantalum or graphite liners (as described herein). In any case, the resulting structure can be encapsulated in ILD material.

It should be understood that although the aforementioned methods are described independently, they can be combined to produce a combined integrated circuit device having one or more of the structures shown in FIGS. 3E, 5C, 7D, 9C, 11D, 13E, and 14D. For example, the graphite nanoribbon interconnect 1124 may be combined with other embodiments described above, such that the tantalum-based barrier layer is disposed between the graphite nanoribbon 1124 and the second interconnect, and the graphite barrier layer is disposed on the graphite nanoribbon Between 1124 and the second interconnector, or the metal part of the second interconnector is in direct contact with the graphite nanoribbon interconnection 1124. Each of these can in turn be fabricated to contain air gaps within one or more insulator layers (described in more detail below). Furthermore, the foregoing various embodiments may be manufactured to include a graphite barrier layer on the side surface of the metal part of the second interconnector. Various other combinations of the embodiments described herein are also possible.

Graphite barrier with air gap dielectric

Yet another embodiment of the present disclosure can be manufactured to include air gaps. The air gap is the volume within the dielectric layer, and is defined by the dielectric layer that contains no dielectric material. In addition to the improved conductivity and capacitance of the graphite barriers already discussed above, the benefits of including air gaps in the dielectric layer include lowering the capacitance of the integrated circuit.

An example method 1200 for manufacturing an embodiment including an air gap is shown in FIG. 12. 13A-13E and 14A-14D are also indicated in the description of FIG. 12 below.

As described above in the context of FIGS. 2 and 3A, method 1200 includes forming 1204 a base ILD layer 1300. Recall that the base ILD layer 1300 is selective, and if included, may further include conductive features to facilitate the desired electrical connection to any given interconnect layer or structure. Then one of two techniques is used to form 1208 a first metal feature on the base ILD layer. One technique is the damascene process, and the other technique is the etching process described in the context of FIG. 2.

As shown in FIG. 13A, the formation 1208 of the first metal component using the damascene process begins by forming 1212 the temporary ILD layer 1304 on the base ILD layer 1300. Next, a 1216 trench is etched in the temporary ILD layer 1304. As shown in FIG. 13B, a temporary barrier layer 1308 is formed 1220 within a trench such as a tantalum-based barrier. This is followed by the formation 1222 of the metal 1312 within the portion of the trench that is not occupied by the temporary liner 1308. As shown in FIG. 13C, a selective etch (eg, an etch consisting of removing the temporary ILD 1304 at a significantly faster rate than other exposed materials) is then used to remove 1224 the temporary ILD layer 1304, such as Ozone or ionized argon RIE. An embodiment of the temporary ILD layer 1304 includes the composition described above for other ILDs. Although FIGS. 13B to 13E show the complete removal of the temporary ILD layer 1304, this is not necessarily the case. In some embodiments, for example, a portion of the temporary ILD layer 1304 may remain on the substrate ILD 1300 until approximately 1/3 of the height of the metal 1312. However, for ease of explanation, the drawings and narrative assume a temporary removal of the ILD layer 1304.

Regardless, the removal of some or all of the temporary ILD layer 1304 exposes some or all of the first metal component 1312. As a result of the damascene process previously described, which deposits a temporary liner on the exposed surface of the trench before metal deposition, the first metal part 1312 includes the liner 1308 disposed between the metal 1312 and the substrate ILD 1300 Part, as shown in Figure 13C. It should be understood that processes similar to this can be applied to any of the embodiments described herein so that the first or second interconnect structure (eg, 328, 512, 722) can be included between the interconnect structure and the underlying layer The liner includes a tantalum-based liner manufactured as part of the dual damascene process.

As shown in FIG. 13D, a graphite barrier (eg, graphene) 1318 is conformally formed 1228 over the exposed first metal component 1312 and the remaining temporary liner 1308, which together form the first interconnect structure 1316. Techniques for forming 1228 graphene on a metal catalyst (such as the first metal component 1312) have been described above.

As shown in FIG. 13E, a second ILD layer 1320 is formed over the first interconnect 1316 using any suitable deposition process (such as, for example, CVD, PCVD, or PECVD). The formation of the second ILD layer 1320 using vapor deposition technology (as opposed to the technology of SOD containing flowable liquid precursors) facilitates formation within the second ILD layer 1320 between the first interconnect structures 1316 Air gap 1322. The air gap 1322 is established because the gas-phase precursor molecules nucleate on the surface of the first interconnect 1316 closest to the source of the precursor (ie, the top surface of the first interconnect 1316) and the side surface near the top surface. Once nucleated, the second ILD layer 1320 grows faster than those surfaces of the second ILD material crystallites that have not yet nucleated. Therefore, the second ILD layer 1320 eventually forms a continuous barrier near the top surface of the one or more first interconnects 1316, thereby preventing further deposition between the first interconnects. This results in the gap or air gap 1322 shown in FIG. 13E. The size of the air gap can vary, but in some cases the widest part is in the range of about 1 nanometer to 5 nanometers, although larger air gaps can also be implemented. In a more general sense, air gaps can often be discerned from unintentional gaps that are relatively small (eg, less than 1 nanometer). One benefit of including an air gap 1322 in the second ILD layer 1320 includes reduced capacitance between adjacent first interconnects.

FIG. 12 also shows an alternative technique for forming the first metal component using an etching process (also described in the context of FIG. 2). Cross-sectional views illustrating some stages of this alternative technique appear in Figures 14A-14D. As described above in the context of FIG. 2, a blanket metal layer 1404 is formed 1213 on the base ILD layer 1300. The first metal part 1412 is etched 1217 from the blanket metal layer 1404. The formation 1213 and the subsequent etching 1217 are collectively referred to as an etching process.

As also described above in the context of FIG. 2, a graphite layer 1416 is formed 1228 on the top and side surfaces of the first metal component. Unlike the technique using the damascene procedure, no barrier or intermediate layer is provided between the first metal component 1412 and the base ILD layer 1300. In contrast, the first metal part formed in the etching process is similar to the structure shown in FIG. 3D. Method 1200 continues by manufacturing a second ILD layer 1420 that defines an air gap, as described above with respect to element 1232, and as shown in FIG. 14D.

As described above, the method 1200 can be combined with any of the above-described embodiments to produce a device having one or more of the above-described structures.

When analyzing (for example, using scanning/transmission electron microscopy (SEM/TEM), composition mapping, secondary ion mass spectrometry (SIMS), atomic probe tomography, Raman spectroscopy, crystallography, and combinations thereof), according to The structure or device configured in one or more embodiments will display a carbon-rich layer having an atomic percentage greater than 75 atomic% (ie, graphene) at a position within the integrated circuit and the integrated circuit in the drawings ).

Example system

FIG. 15 shows a computing system 1500 implemented with one or more integrated circuit structures configured and/or manufactured in other ways according to the embodiment of the present disclosure. As can be seen, the computing system 1500 houses a motherboard 1502. The motherboard 1502 includes multiple components. The multiple components include but are not limited to the processor 1504 and at least one communication chip 1506, each of which may be physically and electrically coupled to the motherboard 1502, or otherwise integrated therein. It should be appreciated that the motherboard 1502 may be, for example, any printed circuit board, whether it is a motherboard, a daughter board mounted on the motherboard, or the only board of the computing system 1500, or the like. Depending on its application, the computing system 1500 includes one or more other components that may or may not be physically and electrically coupled to the motherboard 1502. These other components may include, but are not limited to, volatile memory (eg, DRAM), non-volatile memory (eg, ROM), graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display , Touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage Devices (such as hard drives, compact discs (CD), digital multi-functional audio-visual discs (DVD), etc.). Any component included in the computing system 1500 may include one or more integrated circuit structures configured with one or more conductive interconnect components having graphite barrier layers or nano-scale conductive interconnect components, as described herein Narrated. These integrated circuit structures can be used, for example, to implement on-board processor caches or memory arrays or other circuit components that include interconnects. In some embodiments, multiple functions may be integrated into one or more chips (for example, such as noting that the communication chip 1506 may be part of the processor 1504 or integrated into the processor 1504).

The communication chip 1506 causes the transfer of data to and from the wireless communication of the computing system 1500. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., which can communicate data through the use of modulated electromagnetic radiation through non-solid media. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 1506 can implement any of many wireless standards or protocols, including (but not limited to) Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO , HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols named 3G, 4G, 5G, and beyond. The computing system 1500 may include multiple communication chips 1506. For example, the first communication chip 1506 is dedicated to shorter-range wireless communication such as Wi-Fi and Bluetooth, while the second communication chip 1506 is dedicated to GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc. Long-range wireless communication.

The processor 1504 of the computing system 1500 includes an integrated circuit die packaged in the processor 1504. In some embodiments of the present disclosure, the integrated circuit die of the processor includes an on-board memory circuit, which is composed of one or more components equipped with a graphite barrier layer or a nano-level conductive interconnect The implementation of the multi-integrated circuit structure is as described in this article. The term "processor" may refer to any device or part of a device that processes electronic data from a scratchpad and/or memory and converts the electronic data into other data that can be stored in the scratchpad and/or memory Electronic information.

The communication chip 1506 may also include an integrated circuit die packaged in the communication chip 1506. According to some such embodiment implementations, the integrated circuit die of the communication chip includes one or more integrated circuit structures formed as described in each article (eg, conductive at a given interconnect layer or nanoscale One or more devices implemented by metal damascene and bimetal damascene graphite barrier layers within interconnect semiconductor components or other semiconductor structures that may benefit from thin graphite barrier layers. According to the present disclosure, it should be noted that multi-standard wireless capabilities can be directly integrated into the processor 1504 (eg, where the functions of any communication chip 1506 are integrated into the processor 1504 instead of having a separate communication chip). In addition, it is noted that the processor 1504 may be a chipset with such wireless capabilities. In short, any number of processors 1504 and/or communication chips 1506 can be used. Likewise, any one wafer or wafer set may have multiple functions integrated therein.

In various embodiments, the computing system 1500 may be a laptop, light laptop, laptop, smart phone, tablet, personal digital assistant (PDA), ultra-thin mobile PC, mobile phone, desktop Computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further embodiments, the computing system 1500 may be any other electronic device that processes data as described herein or employs integrated circuit components configured with one or more conductive interconnect components having graphite barrier layers.

Further examples

The following examples relate to further implementations, from which many permutations and configurations can be seen.

Embodiment 1 is a semiconductor device, including: a graphite nanoribbon interconnector, disposed within the first insulator layer; a second insulator layer; and a second interconnector, including a metal component and disposed on the second insulator Within the layer, the second interconnect is in contact with the graphite nanoribbon interconnect.

Embodiment 2 includes the subject matter of embodiment 1, wherein the graphite nanoribbon interconnect has two opposite lateral sides, and each of the sides does not have liner material or barrier material or metal thereon.

Embodiment 3 includes the subject matter of embodiment 1 or 2, wherein the first insulator layer includes an interlayer dielectric material having an air gap formed therein.

Embodiment 4 includes the subject matter of any preceding embodiment, wherein the first insulator layer includes at least two different types of insulator materials.

Embodiment 5 includes the subject matter of any previous embodiment, and further includes an etch stop barrier provided at least between the portion of the first insulator layer and the portion of the second insulator layer.

Embodiment 6 includes the subject matter of any of the previous embodiments, and further includes a barrier layer disposed between the metal part of the second interconnect and the graphite nanoribbon interconnect.

Embodiment 7 includes the subject matter of embodiment 6, wherein the barrier layer is a tantalum-based barrier layer.

Embodiment 8 includes the subject matter of embodiment 6, wherein the barrier layer is a graphite barrier layer.

Embodiment 9 includes the subject matter of any preceding embodiment, wherein the metal component of the second interconnect is in contact with the graphite nanoribbon interconnect to provide a continuous conductive path.

Embodiment 10 includes the subject matter of any preceding embodiment, wherein the graphite nanoribbon interconnect has a height of at least 40 nm.

Embodiment 11 includes the subject matter of any preceding embodiment, wherein the graphite nanoribbon interconnect has an aspect ratio of height to thickness of at least 26 to 1.

Embodiment 12 includes the subject matter of any preceding embodiment, wherein the graphite nanoribbon interconnect has an aspect ratio of height to thickness of at least 133 to 1.

Embodiment 13 includes the subject matter of any preceding embodiment, wherein the graphite nanoribbon interconnect has a height of at least 60 nm.

Embodiment 14 includes the subject matter of any preceding embodiment, wherein the graphite nanoribbon interconnect has an aspect ratio of height to thickness of at least 40 to 1.

Embodiment 15 includes the subject matter of any preceding embodiment, wherein the graphite nanoribbon interconnect has an aspect ratio of at least 200 to 1 in height to thickness.

Embodiment 16 includes the subject matter of any preceding embodiment, wherein the graphite nanoribbon interconnect has a thickness of less than 5 nm.

Embodiment 17 includes the subject matter of any preceding embodiment, wherein the graphite nanoribbon interconnect has a thickness of less than 2 nm.

Embodiment 18 includes the subject matter of any preceding embodiment, wherein the graphite nanoribbon interconnect has a thickness of less than 1 nm.

Embodiment 19 includes the subject matter of any of the previous embodiments, wherein the graphite nanoribbon interconnect has at least one single layer oriented in the direction of the height of the graphite nanoribbon interconnect, which also flows through the current Graphite nanoribbons in the direction of the interconnect.

Embodiment 20 includes the subject matter of any preceding embodiment, wherein the graphite nanoribbon interconnect has a top surface and a side surface, and wherein the side surface is in direct contact with the first insulator layer.

Embodiment 21 is a computing system that includes the subject matter of any preceding embodiment.

Embodiment 22 is a method of manufacturing a semiconductor device, including: forming a first metal member on a substrate, the first metal member including a top surface and a side surface; forming a graphite layer on the side surface of the first metal member; Forming a first dielectric layer in contact with the graphite layer on the side surface of the first metal component; removing the first metal component thereby forming a graphite nanobelt interconnect and cavity; and interconnecting the second The body contacts the graphite nanoribbon interconnect to provide a conductive path.

Embodiment 23 includes the subject matter of embodiment 22, wherein forming the first dielectric layer includes defining at least one air gap within the first dielectric layer during formation.

Embodiment 24 includes the subject matter of embodiment 22 or 23, wherein the graphite layer formed on the side surface of the first metal member is in the direction of the height of the graphite layer, which also flows current through the graphite nanometer In the direction with the interconnect, at least one monolayer of the graphite layer is oriented.

Embodiment 25 includes the objects of embodiments 22 to 24, and further includes disposing a dielectric material in the cavity.

Embodiment 26 includes the subject matter of any of embodiments 22 to 25, wherein the dielectric material within the cavity is a first material and the first dielectric layer is different from the first material Second material.

Embodiment 27 includes the subject matter of any of embodiments 22 to 26, further including depositing an etch stop barrier on at least a portion of the top surface of the first dielectric layer.

Embodiment 28 includes the subject matter of any of embodiments 22 to 27, wherein contacting the second interconnector to the graphite nanoribbon interconnect includes contacting the barrier layer to the graphite nanoribbon interconnect.

Embodiment 29 includes the subject matter of embodiment 28, wherein the barrier layer is formed of a tantalum-based barrier material.

Embodiment 30 includes the subject matter of embodiment 28, wherein the barrier layer is formed of graphite barrier material.

Embodiment 31 includes the subject matter of embodiment 28, wherein the metal part of the second interconnect is disposed on the first surface of the barrier layer, the first surface being opposite to the contact with the graphite nanoribbon interconnect The second surface of the barrier layer.

Embodiment 32 includes the subject matter of any of embodiments 22 to 31, wherein contacting the second interconnect to the graphite nanobelt interconnect includes directly contacting a metal component to the graphite nanobelt interconnect.

Embodiment 33 includes any of the targets of embodiments 22 to 32, wherein the second interconnection system is formed by an etching process.

Embodiment 34 includes the subject matter of any of embodiments 22 to 33, and further includes forming a graphite liner on at least a side surface of the metal part of the second interconnect.

Embodiment 35 includes the targets of any of embodiments 22 to 34, wherein the second interconnection system is formed by a damascene process.

Embodiment 36 is a semiconductor device including: a device layer including one or more metal oxide semiconductor (MOS) transistors; and a first interconnect structure above the device layer and including graphite naphthalene disposed within an insulator material A meter ribbon interconnector, wherein the graphite nanoribbon interconnector electrically connects at least one of the transistors to another interconnector component.

Embodiment 37 includes the subject matter of embodiment 36, wherein another interconnect component is included in the first interconnect structure.

Embodiment 38 includes the subject matter of any of Embodiments 36 to 37, wherein the other interconnect component is contained in a second interconnect structure disposed above the first interconnect structure.

Embodiment 39 includes the subject matter of any of embodiments 36 to 38, and the first interconnect structure includes one or more air gaps.

Embodiment 40 includes the subject matter of any of embodiments 36 to 39, wherein the first interconnect structure includes a plurality of graphite nanoribbon interconnects, and the plurality of at least two adjacent graphite nanoribbon interconnects are composed of The air gap is separated.

The foregoing description of the embodiments of the examples has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit this disclosure to the precise form disclosed. According to the present invention, many modifications and changes are possible. The intention is that the scope of this disclosure is not limited by the detailed description, but by the scope of the attached patent application. Applications filed in the future that claim the priority of this application may request the disclosed subject matter in different ways, and may generally contain any set of one or more restrictions as various disclosures or otherwise indicated herein.

Claims (25)

A semiconductor device includes: a first insulator layer; a graphite nanobelt interconnector, disposed within the first insulator layer; a second insulator layer; and a second interconnector, including a metal component and disposed on the second Within the insulator layer, the second interconnect is in contact with the graphite nanoribbon interconnect. The semiconductor device of claim 1, wherein the graphite nanoribbon interconnect has two opposite lateral sides, and each of the sides does not have a liner material or barrier material or metal thereon. The semiconductor device according to claim 1, further comprising a barrier layer provided between the metal part of the second interconnect and the graphite nanoribbon interconnect. The semiconductor device of claim 1, wherein the metal part of the second interconnect is in contact with the graphite nanoribbon interconnect to provide a continuous conductive path. The semiconductor device of claim 1, wherein the graphite nanoribbon interconnect has a height of at least 40 nm. The semiconductor device of claim 5, wherein the graphite nanoribbon interconnect has an aspect ratio of height to thickness of at least 26 to 1. The semiconductor device of claim 1, wherein the graphite nanoribbon interconnect has a thickness of less than 5 nm. The semiconductor device according to claim 1, wherein the graphite nanobelt interconnect has at least one single layer oriented in the direction of the height of the graphite nanobelt interconnect, which also flows in the graphite nanocurrent In the direction of the interconnection. The semiconductor device of claim 1, wherein the graphite nanoribbon interconnect has a top surface and a side surface, and wherein the side surface is in direct contact with the first insulator layer. A computing system includes the semiconductor device according to any one of claims 1 to 9. A semiconductor device includes: a device layer including one or more metal oxide semiconductor (MOS) transistors; and a first interconnect structure above the device layer and including a graphite nano-band interconnection disposed within an insulator material Wherein the graphite nanoribbon interconnect electrically connects at least one of the transistors to another interconnect component. The semiconductor device of claim 11, wherein the other interconnect body component is included in the first interconnect body structure. The semiconductor device of claim 11, wherein the first interconnect structure includes one or more air gaps. A method of manufacturing a semiconductor device, comprising: forming a first metal part on a substrate, the first metal part including a top surface and a side surface; forming a graphite layer on the side surface of the first metal part; and forming the first metal Forming a first dielectric layer in contact with the graphite layer on the side surface of the component; removing the first metal component thereby forming a graphite nanoribbon interconnect and cavity; and contacting the second interconnect to the Graphite nanoribbon interconnects to provide conductive paths. The method of claim 14, wherein the graphite layer is formed on the side surface of the first metal member in the direction of the height of the graphite layer, which also flows in the current flowing through the graphite nanobelt interconnector In the direction, at least a single layer of the graphite layer is oriented. The method of claim 14, further comprising depositing a dielectric material within the cavity. The method of claim 16, wherein the dielectric material within the cavity is a first material and the first dielectric layer is a second material different from the first material. The method of claim 14, wherein contacting the second interconnector with the graphite nanoribbon interconnect includes contacting the barrier layer to the graphite nanoribbon interconnect. The method of claim 18, wherein the barrier layer is formed of a tantalum-based barrier material. The method of claim 18, wherein the barrier layer is formed of a graphite barrier material. The method of claim 18, wherein the metal part of the second interconnector is provided on the first surface of the barrier layer, the first surface being opposite to the barrier layer in contact with the graphite nanoribbon interconnector Second surface. The method of claim 14, wherein contacting the second interconnector with the graphite nanoribbon interconnect includes directly contacting a metal component to the graphite nanoribbon interconnect. The method of claim 14, wherein the second interconnection system is formed by an etching process. The method of claim 23, further comprising forming a graphite liner on at least a side surface of the metal part of the second interconnect. The method of claim 14, wherein the second interconnection system is formed by a damascene process.