WO2018063289A1

WO2018063289A1 - Graphene nanoribbon interconnects and interconnect liners

Info

Publication number: WO2018063289A1
Application number: PCT/US2016/054675
Authority: WO
Inventors: Kevin Lin; Roman CAUDILLO; Jasmeet S. Chawla; Jessica M. TORRES; Aranzazu MAESTRE CARO
Original assignee: Intel Corporation
Priority date: 2016-09-30
Filing date: 2016-09-30
Publication date: 2018-04-05
Also published as: TWI751187B; TW201819283A

Abstract

Graphitic nanoribbon interconnects are described. The graphitic nanoribbon interconnects are fabricated by forming a graphitic layer (such as graphene) on a metal feature growth catalyst. The metal feature growth catalyst is selectively removed, leaving a graphitic nanoribbon remaining as the interconnect. Graphitic nanoribbon interconnects have a thickness of from 0.3 nanometers (nm) to 2 nm and a height of at least 40 nm. The conductive graphitic nanoribbon interconnect overcomes the need to include conventionally composed interconnect liners. Furthermore, the reduced feature size of the graphitic nanoribbon interconnect compared to conventional liners enables greater interconnect density and semiconductor device density.

Description

GRAPHENE NANORIBBON INTERCONNECTS AND INTERCONNECT LINERS

BACKGROUND

In the manufacture of integrated circuits, interconnects may be formed on a semiconductor substrate using a copper damascene process. Such a process typically begins with a trench and/or via being etched into an insulator layer, a barrier material being deposited into the trench and then copper metal being deposited on the barrier material to form the interconnect. As device dimensions continue to decrease, the various interconnect features become narrower and closer together giving rise to a number of non-trivial problems.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 A illustrates an example integrated circuit structure that includes a graphitic barrier layer, in accordance with an embodiment of the present disclosure.

FIG. IB schematically illustrates a transverse cross-section of an example interconnect, and a thickness of a tantalum-based barrier layer relative to a total width of the interconnect.

FIG. 1C schematically illustrates a transverse cross-section of an example interconnect, and a thickness of a graphitic barrier layer relative to a total thickness of the interconnect, in accordance with an embodiment of the present disclosure.

FIG. 2 is a flow diagram of an example method for fabricating integrated circuits using interconnects with a graphitic barrier layer, in accordance with an embodiment of the present disclosure.

FIGS. 3A-3E are cross-section side views of a series of schematic integrated circuit structures illustrating formation of a graphitic barrier layer fabricated according to the method shown in FIG. 2, in accordance with an embodiment of the present disclosure.

FIG. 4 is a method flow diagram illustrating an example method for fabricating an additional interconnect and metal level that is in electrical communication with a graphiticly lined interconnect, in accordance with an embodiment of the present disclosure.

FIGS. 5A-5C are cross-section side views of a series of schematic integrated circuit structures illustrating formation of an additional interconnect layer in electrical communication with a graphitically lined interconnect fabricated according to the method shown in FIG. 4, in accordance with an embodiment of the present disclosure.

FIG. 6 is a method flow diagram illustrating an example method for fabricating an additional interconnect that is partially graphitically lined and in electrical communication with a graphitically lined interconnect at a lower level, in accordance with an embodiment of the present disclosure.

FIG. 7A-7D are cross-section side views of a series of schematic integrated circuit structures showing formation of an additional interconnect that is partially graphitically lined and in electrical communication with a graphitically lined interconnect at a lower level fabricated according to the method shown in FIG. 6, in accordance with an embodiment of the present disclosure.

FIG. 8 is a method flow diagram illustrating an example method for fabricating an additional interconnect that is partially graphitically lined and in electrical communication with a graphitically lined interconnect at a lower level, in accordance with an embodiment of the present disclosure.

FIGS. 9A-9C are cross-section side views of a series of schematic integrated circuit structures showing formation of an additional interconnect that is partially graphitically lined and in electrical communication with a graphitically lined interconnect at a lower level fabricated according to the method shown in FIG. 8, in accordance with an embodiment of the present disclosure.

FIG. 10 is a method flow diagram illustrating an example method for fabricating a graphitic nanoribbon interconnect, in accordance with an embodiment of the present disclosure.

FIGS. 11A-11D are cross-section side views of a series of schematic integrated circuit structures showing formation of a graphitic nanoribbon fabricated according to the method shown in FIG. 10, in accordance with an embodiment of the present disclosure.

FIG. 12 is a method flow diagram illustrating an example method for fabricating a graphitically lined interconnect that includes an air gap as an element of an interlayer dielectric structure, in accordance with an embodiment of the present disclosure.

FIGS. 13A-13E are cross-section side views of a series of schematic integrated circuit structures showing formation of a graphitic barrier layer that includes an air gap as an element of an interlayer dielectric structure fabricated according to a method shown in FIG. 12, in accordance with an embodiment of the present disclosure.

FIGS. 14A-14D are cross-section side views of a series of schematic integrated circuit structures showing formation of a graphitic barrier layer that includes an air gap as an element of an interlayer dielectric structure fabricated according to an alternative method shown in FIG. 12, in accordance with an embodiment of the present disclosure. FIG. 15 illustrates a mobile computing system configured in accordance with an embodiment of the present disclosure.

As will be appreciated, the figures are not necessarily drawn to scale or intended to limit the disclosure to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of a structure may have less than perfect straight lines, right angles, and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

Techniques are disclosed for forming integrated circuit structures that include graphitic barrier layers. Examples of graphitic barrier layers include, but are not limited to, graphene monolayers and groups of 1 to 5 graphene monolayers. In some examples herein, the terms "graphene" and "graphitic" and "graphite" are used interchangeably for convenience and without loss of breadth. Rather, all these terms refer to allotropes of carbon organized in crystalline monolayer sheets.

These graphitic barrier layers help reduce or eliminate diffusion of metal from a metal feature of one interconnect to neighboring metal features in an integrated circuit. In some embodiments, graphitic barrier layers may be synthesized on-chip, in position between the dielectric and the metal interconnect, for example, by using a previously deposited metal interconnect structure as a growth substrate for the graphitic material (e.g., graphene, graphite, or other carbon allotrope, or carbon-containing compound organized as one or more crystalline monolayers). In this way, uniform and extremely thin graphitic barrier layers can be fabricated in situ over a metal portion of an interconnect, according to some embodiments. A dielectric material is then deposited about the graphene-coated metal interconnect. In some examples, the metal portion of a graphitic-lined interconnect is removed, leaving a graphitic nanoribbon as the interconnect. As used herein, a graphitic nanoribbon is any nano-scale graphitic structure or feature used as a conductive interconnect feature, substantially without other conductive bulk interconnect materials. Note that there may be a minor residue or trace of previously removed conductive bulk interconnect materials, but the dominant conductive interconnect feature material is graphitic.

The disclosed techniques may provide various advantages over traditional deposition techniques for forming a barrier layer (also referred to as a "liner") associated with an interconnect. For example, the disclosed methods and materials may allow a graphitic monolayer (or other suitable thickness) to be produced so that it surrounds the metal of the interconnect structure and is substantially conformal with the metal portion of the interconnect. In some examples, the graphitic barrier layer has a thickness in a range from 0.3 nanometers (nm) to 2 nm. This thickness is much less than the thickness of typical diffusion barriers (e.g., tantalum nitride) which are in a range of from 5 nm to 10 nm thick. The thinner graphitic barrier layer effectively improves the conductivity of the metal interconnect because proportionately more conductive metal can be deposited as the metal portion of the interconnect compared to typical interconnects having a thicker liner (e.g., tantalum-based liners) and thus less area for the metal portion. Furthermore, conventional barriers layers are relatively poor electrical conductors, compared to graphitic layers generally, and graphene particularly. This improved barrier conductivity also improves the electrical conductivity of the interconnect as a whole. Finally, the interface between a graphitic barrier layer and the metal of the interconnect produces less surface scattering than an interface between a metal and a conventional barrier layer. This lower surface scattering feature also tends to increase the conductivity of interconnects of the present disclosure compared to conventionally-lined interconnects. Numerous configurations and variations will be apparent in light of this disclosure.

General Overview

Barrier materials are deposited in a layer between the nonconductive (e.g., the dielectric) and conductive (e.g., the copper metal) features of an integrated circuit. Barrier materials can prevent the metal feature portion of an interconnect from diffusing or otherwise migrating into the dielectric material. In some cases, the diffusion of metal from an interconnect can even cause a short circuit between proximately disposed interconnects, by making the dielectric material between those interconnects more conductive, particular when the distance between those interconnects is small. However, it has been challenging to shrink the dimensions of conventional barrier materials deposited using conventional deposition techniques. As a result, as semiconductor devices and their interconnect structures are reduced in size with successive technology generations, conventional (and poorly conductive) barrier materials take up a progressively greater portion of the cross-sectional area of an interconnect. This increases the resistance of the interconnect as proportionately less metal can be deposited inside the barrier layer portion of the interconnect. Also, as dimensions shrink, the metal deposited within the interconnect is more likely to include voids or other defects, especially for high aspect ratio vias an interconnect features. These defects can have a greater negative effect on conductivity of the interconnect as the dimensions of the metal portion shrink. As will be appreciated in light of this disclosure, replacing conventional barrier materials with a graphitic barrier layer, and in particular a graphene (an atomically-thin and conductive allotrope of carbon) barrier layer can increase the effective conductance of an interconnect. This benefit is accomplished by reducing the proportion of the interconnect occupied by the less 5 conductive liner while increasing the proportion of the cross-sectional area of the interconnect that is occupied by the more conductive metal core. A graphitic barrier layer also provides an effective diffusion barrier between the dielectric and metal of an interconnect structure, thus reducing the likelihood of shorting between adjacent conductive structures. However, there are a number of challenges associated with forming graphitic barriers of nanometer or sublet nanometer thickness. For instance, transferring graphene or a graphitic material grown on a separate substrate to an integrated circuit chip having a topography (e.g., trenches) is not trivial or otherwise not readily accomplished. Furthermore, graphitic materials do not readily form on interlayer dielectric materials. This makes the deposition of graphene in a damascene or dual damascene process using conventional liner deposition techniques challenging.

15 Thus, and in accordance with an embodiment of the present disclosure, techniques are provided for forming graphitic barrier layers (alternatively referred to as a "graphitic liner") for interconnect structures. In one specific embodiment, a metal portion (referred to herein as a "metal feature") of an interconnect is formed using a subtractive etch process. This metal feature is then used as a catalyst on which a graphitic barrier layer is grown. In another specific

20 embodiment, a metal feature is formed using a damascene process. The metal feature is then exposed by removing an interlayer dielectric in which the metal was deposited. Thus exposed, the metal feature can then be used as a catalyst on which a graphitic barrier layer is grown. In some embodiments, a subsequently deposited interlayer dielectric is used to form an air gap around a portion of the interconnects, thus improving the isolation of the dielectric layer (and

25 reducing the capacitive effect associated therewith). In another embodiment, after growing a graphitic barrier layer on a metal feature, the metal feature is removed. The remaining conductive graphitic structure (generally referred to herein as a nanoribbon, due to its nano-scale size) then functions as the interconnect. Note the reference to nanoribbon is not intended to implicate a specific shape. Rather, the nanoribbon can effectively be any shape, and generally

30 conforms to the shape of the interconnect area it is lining or a portion of that shape. For instance, the nanoribbon may be ring-shaped or box-shaped, or a single wall or portion of such shapes.

The disclosed techniques of forming graphitic barrier layers may provide various advantages. For example, the disclosed techniques may be capable of producing a graphitic barrier layer having a thickness of less than 5 nm or less than 2 nm, or a thickness in the sub- nanometer range (e.g., a thickness of less than 1, less than 0.75, less than 0.5 nanometers, or a monolayer). In one specific example, the graphitic barrier layer is a graphene monolayer. In other examples, the graphitic barrier layer is a group of from two to five graphene monolayers. Additionally, the graphitic barrier layer may be substantially conformal to the metal feature of the interconnect, providing an interface that generates less surface scattering at the metal- graphene interface, in some embodiments. Other advantages include higher interconnect conductivity compared to interconnects with conventional barrier layers, improved (lower) capacitance between interconnects, smaller minimum dimensions that can match successive technology generations with smaller feature sizes, and higher device densities within an integrated circuit. Numerous variations and configurations will be apparent in light of this disclosure.

Graphitic Barrier Layer(s)

FIG. 1A illustrates one example of an integrated circuit 100 having an interconnect with a graphitic barrier layer (e.g., graphene), in accordance with an embodiment of the present disclosure. It will be appreciated that FIG. 1A (and FIGS. IB and 1C) are simplified for the purposes of illustration and that actual interconnect structures often include structures corresponding to both conductive lines and vias.

As can be can be seen, the integrated circuit 100 includes a semiconductor device layer 102 (omitted from subsequent figures for clarity of depiction), an optional base interlayer dielectric (ILD) layer 104, and an interconnect structure 106 that includes a first ILD layer 120 having a plurality of metal features 112 therein, each metal feature 112 having a graphitic barrier layer 116. While only one interconnect structure 106 is shown in this example, other embodiments may include any number of such structures in a stacked configuration (e.g., metal layers M0-M9). In addition, other embodiments may not include the optional base ILD layer 104, such as cases where a graphene-containing interconnect structure 106 is disposed directly on the device layer 102, and in such a way so as to provide a functional integrated circuit.

Examples of semiconductor devices that can be formed in device layer 102 include, but are not limited to, planar field effect transistors (FETs), and non-planar FETS (e.g., finFETs or nanowire FETs), capacitors (e.g., embedded DRAM (eDRAM) capacitors), DRAM cells, and

SRAM cells, among others. As will be appreciated, the actual devices implemented in the device layer 102 will depend on the target application and function of the integrated circuit 100, and the present disclosure is not intended to be limited to any particular application or functional circuitry. Rather, the techniques provided herein can be used with any number of device layer 102 configurations. These devices, often fabricated on and/or within a semiconducting substrate (e.g., a single crystal silicon wafer) are in electrical communication with at least one interconnect 106. The interconnect structure(s) 106 connect a semiconductor device of device layer 102 to other semiconductor devices elsewhere within an integrated circuit, or to a contact at an upper or lower layer of the integrated circuit 100, through a network of selectively connected vias and conductive lines. With each successive layer of interconnect structures 106, generally greater numbers of semiconductor devices 102 can be connected together. Ultimately, the semiconductor devices, through a series of interconnect structures 106, are placed in electrical communication with an input and/or an output so that instructions and/or data can be received at and/or sent from the integrated circuit 100. In other figures herein, the semiconductor device layer 102 is not shown.

The optional base ILD layer 104 is, in the example shown, conformally disposed over the semiconductor device layer 102, thus protecting the semiconductor device layer 102 from unintentional electrical contact with other conductive features within the integrated circuit 100 and from subsequent processing used to fabricate the integrated circuit 100. Also, the base ILD layer 104 may also function as a surface in which to form interconnect structures 106 and to selectively connect one or more of the interconnect structures 106 with the semiconductor device layer 102. When included, the ILD 104 may be, for example, silicon dioxide or silicon nitride or some other suitable insulator material or passivation material. The thickness of the layer can be set as needed to provide the desired insulation and/or protection to the underlying device layer 102.

In the example embodiment shown, side surfaces of each metal feature 112 included in interconnect structure 106 are in contact with a graphitic barrier layer 116. The metal feature 112 and the graphitic barrier layer 116 together form a conductive interconnect feature. As presented above, barrier layers generally are used to prevent diffusion of metal from a metal feature 112 into an adjacent insulator material, thus preventing a short circuit in the integrated circuit 100 and/or otherwise preventing a decrease in the electrical performance of the interconnect and/or the integrated circuit 100 as a whole. While traditional barrier layers are often tantalum-based, barriers described herein include a graphitic material, such as graphene, which may be thinner and/or more conductive.

FIGS. IB and 1C schematically illustrate transverse cross-sections of interconnect features, illustrating the relative thicknesses of conventional and graphitic barrier layers relative to a total width of an interconnect feature, in examples. FIG. IB schematically illustrates the relative thicknesses of a tantalum-based barrier layer relative to total interconnect feature thickness. FIG. 1C schematically illustrates a thicknesses of a graphitic barrier layer relative to total interconnect feature thickness. As is apparent upon inspection of these figures (and as described herein), tantalum-based barrier layers are thicker, and occupy proportionately more cross-sectional area of an interconnect feature compared to a graphitic barrier layer. For example, some interconnect features may have a total width X₁ of from 25 nm to 30 nm (and in some specific examples a target total width Xi of 27 nm). As in shown in FIG. IB, conventional (e.g., tantalum-based) barrier layers may have a liner thickness Y₁ of from 5 nm to 10 nm, thus occupying from 10 nm to 20 nm of the total interconnect feature width. This is in comparison to a graphitic barrier layer, as shown in FIG. 1C, that may have a liner thickness Y₂ of from, for example, 0.3 nm to 1.5 nm, thus occupying only 0.6 nm to 3 nm of the total interconnect thickness. This proportionately larger amount of metal in a graphene-lined interconnect enables, in part, improved conductivity of graphene-lined interconnects and improved performance of integrated circuit devices.

Methodology and Architecture

FIG. 2 illustrates a methodology 200 for fabricating integrated circuit interconnects that include a graphitic barrier layer, in accordance with an embodiment of the present disclosure. The description of the method 200 is accompanied by concurrent descriptions of schematic cross-sections of corresponding example interconnect structures. These cross-sections are depicted in FIGS. 3A to 3E.

As can be seen in this example case, the method 200 includes forming 204 a base ILD layer 304 on, for example, a semiconductor substrate or a device layer or another ILD layer. The embodiment described in the context of FIGS. 2 and 3A-3E assumes formation 204 of the base ILD layer 304 at first, although other embodiments described below do not necessarily form a base ILD layer at first (or at all, as previously explained with respect to FIG. 1A). Furthermore, it will be appreciated that the examples of interconnects described herein are directly or indirectly connected to semiconductor devices and contacts, whether or not the connections are shown in the figures. The devices to which connections can be made may be passive (e.g., capacitors, inductors, resistors) or active (e.g., transistors, diodes, amplifiers, memory cells).

In one example embodiment, the base ILD layer 304 insulates the underlying device layer, and may further include one or more interconnect features passing through the insulator material so as to electrically couple devices of the device layer to upper interconnect structures and/or contacts. Example insulator materials that can be used for the base ILD layer 304 include, for instance, nitrides (e.g., Si₃N₄), oxides (e.g. Si0₂, A1₂0₃), oxynitrides (e.g., SiO_xN_y), carbides (e.g., SiC), oxycarbides, polymers, silanes, siloxanes, or other suitable insulator materials. In some embodiments, the base ILD layer 304 is implemented with ultra-low-k insulator materials, low-k dielectric materials, or high-k dielectric materials depending on the application. Example low-k and ultra-low-k dielectric materials include porous silicon dioxide, carbon doped oxide (CDO), organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. Examples of high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

Techniques for forming 204 the base ILD layer 304 can be any of a wide range of suitable deposition techniques, including but not necessarily limited to: physical vapor deposition (PVD); chemical vapor deposition (CVD); spin coating/spin-on deposition (SOD); and/or a combination of any of the aforementioned. Other suitable configurations, materials, deposition techniques, and/or thicknesses for base ILD layer 304 will depend on a given application and will be apparent in light of this disclosure.

While some embodiments described herein may use a damascene process (which is used to generally refer to both "single damascene" and "dual damascene" techniques) to etch trenches in an ILD layer, which are then filled with metal, the method 200 instead uses a subtractive metal etch process. Thus, as further shown in in FIG. 2 and with further reference to FIG. 3A, the method 200 continues by forming 208 a blanket metal layer 308 on the base ILD layer 304. This blanket metal layer 308 will then be subtractively etched to form metal features. These metal features can act as catalysts on which to grow a graphene layer, as will be described below in more detail.

Example deposition techniques for forming 208 the blanket metal layer 308 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD). The thickness (a) of the blanket metal layer can be, for example, greater than a final dimension of the metal feature on which the graphene barrier layer will be deposited, because the blanket metal layer 308 may be subjected to various etches that can reduce the thickness. In examples, the dimension a can be from 10 nm to 500 nm, from 10 nm to 100 nm, from 10 nm to 50 nm, from 40 nm to 60 nm. As will be appreciated, these example ranges are merely illustrative because a can vary greatly according to the type of interconnect being fabricated (e.g., a via or a conductive line), as well as other factors such as the level of metal within the integrated circuit being fabricated, the dimensional constraints of the technology, among other factors.

Example metals used to form 208 the blanket metal layer 308, and that can be subtractively etched and used as a graphene growth catalyst in the following stages of the method 200 include, for instance, copper, aluminum, tungsten, and tantalum, among others. Practical considerations may generally call for the least inexpensive metal that can be acceptably used.

After forming 208, the blanket metal layer 308 is etched 212 to form metal features 312 from the blanket metal layer 308, as shown in FIG. 3B. That is, material is selectively removed from the blanket metal layer 308. The portions of the blanket metal layer 308 remaining after the etch are generically referred to herein as metal features. In the context of FIGS. 2 and 3A- 3E, the metal features disposed on top of a base ILD layer 304 and within a first ILD layer are described as first metal features 312. The first metal features 312 are separated by trenches formed by the removal of other portions of the blanket metal layer 308. In some examples, these first metal features 312 will form a portion of an interconnect between a device and another metal layer or metal contact, or between metal layers, or between metal contacts.

Upon formation, each first metal feature 312 includes an exposed top surface and one or more exposed side surfaces, as shown in FIG. 3B. The bottom surface, opposite the top surface, of each first metal feature 312 remains in contact with the ILD layer 304 and/or a conductive interconnect feature formed within layer 304 that effectively allows for proper electrical connection to the underlying device layer, as will be appreciated. In the embodiment shown in FIGS. 3B-3E, the bottom surface of the first metal feature 312 is not fabricated with a liner, graphene or otherwise.

In some embodiments, the subtractive etching 212 includes selectively applying a mask to the blanket metal layer 308, thus protecting the portions of the blanket metal layer 308 that correspond to the first metal features 312 from an etch. Once the mask is applied, a directional

(anisotropic) etch 212 can be used to remove the portions of the blanket metal layer 308 that are not protected by the mask. Anisotropic etches are used to keep the feature width dimension β

(indicated in FIG. 3B) of the first metal features 312 approximately uniform (e.g., variation of 5 nm or less, or 2 nm or less, or 1 nm or less) from the bottom surface to the top surface.

Anisotropic etches include, for example, dry etches such as reactive ion etches (RTE) using ozone, ionized argon, among others. Other etch processes can be used as well (e.g., wet or isotropic), which may lead to more tapered sidewalls, if acceptable for a given circuit. In a more general sense, the sidewalls and tops of the interconnect features having a graphitic liner thereon can have any shape or profile (e.g., s-shaped or otherwise wavy-shaped, tapered so as to be wider at lower portion and narrower at top portion, orthogonal on one side and tapered on the other side, convex top portion, concave top portion, concave sidewalls, to name a few examples). The shape of the feature can vary greatly, and any such shapes can be conformally coated with or otherwise have a graphitic liner disposed thereon.

The dimension β of the first metal feature 312 may include, for example, but is not limited to, ranges from 10 nm to 50 nm, from 5 nm to 100 nm, from 20 nm to 30 nm, and from 50 nm to 100 nm. The feature height dimension χ of the first metal feature 312 can include, but is not limited to, ranges indicated above as the dimension a or slightly smaller. Example values of the dimension χ include, but are not limited to, from 10 nm to 100 nm, from 10 nm to 50 nm, from 40 nm to 60 nm, and from 50 nm to 100 nm. Analogous to the dimension a, the dimensions β and χ are a function of one or more of the type of interconnect being fabricated, the level of metal within the integrated circuit that is being fabricated, the design rules of the technology, the etch used for form the first metal feature 312, among other factors.

As mentioned above, metals used for interconnects (e.g., Cu, W, Ta, etc.) can diffuse through ILD material, thus potentially shorting circuits together and impairing the function of the integrated circuit as a whole. To prevent this diffusion, a barrier layer is typically used to encapsulate (in whole or in part) the metal feature of the interconnect. In a damascene process, in which a trench is etched into an ILD layer and then filled with metal, the liner is generally deposited before the metal feature is deposited. As schematically shown in FIG. IB and described above, conventional liners, often tantalum or tantalum nitride, occupy a third or more of the cross-sectional area of the trench leaving a narrow channel in which to deposit metal for the given interconnect feature. This narrow channel can be difficult to fill uniformly with the metal, thus further degrading the electrical performance of the interconnect.

To overcome this challenge, among others, a graphitic layer 316, such as graphene, is conformally formed 216 on the exposed top and side surfaces of the first metal features 312, as shown in FIG. 3C. Conformal in this context implies that the graphene layer is disposed in a relatively uniform fashion (within +/- 0.2 nm to 1 nm, or otherwise negligible variation for a desired performance level) over the surface of an underlying feature, including any topography of the underlying feature. As shown, graphene is not deposited on the bottom surface of the first metal feature 312 in this embodiment because the bottom surface is in contact with the base ILD 304 (or more likely, some underlying conductive feature of the circuit). The first metal feature 312 acts as a catalyst that facilitates graphene deposition. This is beneficial because graphene and other graphitic materials can be difficult to deposit on surfaces composed of materials often used for ILD.

The thickness dimension ε of the graphitic layer 316 can range, in some embodiments, from approximately 0.3 nm to approximately 1.5 nm (within normal measurement accuracy and precision limits), which corresponds to a range of from 1 graphene monolayer to about 5 graphene monolayers. The overall height dimension φ shown in FIG. 3C is approximately the sum of the dimensions χ and ε. The benefits of a graphene barrier layer include reduced resistance (through the conductive pathway of the interconnect) and increased shorting margin (between conductive features) of the interconnect, among other benefits indicated herein. In embodiments, the height φ to thickness ε aspect ratio of the graphitic layer can be from 26: 1 to 133 : 1, from 40: 1 to 200: 1, or even higher than 200: 1.

An example method of forming 216 the graphene layer 316 on the first metal feature 312 (as well as any other analogous metal feature, as will be appreciated) includes using a hydrocarbon precursor (such as hexane, methane, ethylene, acetylene, among others) that is decomposed in a plasma or thermal enhanced chemical vapor deposition process. In one example, a gaseous source of carbon (e.g., methane) is mixed with hydrogen, and then thermally decomposed by heating the mixture of gases to between 800°C and 950°C. Pressure enhanced chemical vapor deposition may also be used, which lowers the deposition temperature used to decompose the gaseous source of carbon compared to the methods described above to between 700°C and 850°C. A copper metal feature is then exposed to the heated gas mixture at a pressure of between 0.5 Torr and 50 Torr (for low pressure CVD deposition) or as high as atmospheric pressure and at a flow rate from 0.5 standard cubic centimeters per minute (seem) to 10 seem. For cases in which the metal feature may have been oxidized prior to deposition of the graphene, the substrate may be reduced by heating (e.g., for copper up to 1000°C) and exposing the metal to hydrogen gas for between 30 minutes and 60 minutes. This is one example of a set of conditions by which graphene is deposited on a copper metal feature. It will be appreciated that other combinations of gases, thermal profiles, pressures, flow rates, and other parameters can be used to deposit graphene on a given metal feature. Additional examples may be found in "A Review of Chemical Vapor Deposition of Graphene on Copper" by Mattevi, published in the Journal of Materials Chemistry, in volume 21, pages 3324-3334 (2011).

As shown in FIG. 3D, a first ILD layer material 320 is deposited 220 between the first metal features 312 within their corresponding graphene layers 316 and then planarized. The methods used to deposit 220 the first ILD layer 320 can be, for example, any of the methods already described in the context of the FIG. 3A. Methods for depositing 220 the first ILD layer 320 can also include techniques for filling high aspect ratio trenches (e.g., having a height to width aspect ratio of 2: 1 or higher), like those between the graphene 316 coated first metal features 312 shown in FIG. 3C. These latter techniques include spin coating/spin-on deposition (SOD) that apply one or more chemical precursors that react (optionally upon application of heat) to form the ILD. Once the first ILD layer 320 has been deposited 220, it is planarized and/or polished 220 to form a uniformly flat surface suitable for subsequent fabrication and processing. Planarization and/or polishing techniques include chemical-mechanical planarization (CMP) process or other appropriate polishing/planarization process as desired, so that another layer can be formed on top of the layers already shown in FIG. 3D. This forms a first interconnect structure 328 that includes a number of conductive interconnect features. A conductive interconnect feature as used herein collectively refers to the first metal feature 312 and its corresponding graphene barrier layer 316.

As is also shown in example embodiment of FIG. 3D, the portion of the graphene layer 316 corresponding to the top surface of the first metal feature 312 is removed. While not wishing to be bound by theory, it has been observed that the electrical sheet resistance of graphene is extremely low in directions parallel to a plane in which a monolayer carbon atoms are organized (i.e., parallel to a major surface of a graphene sheet). The sheet resistance of a graphene sheet is higher in a direction perpendicular to the plane in which the monolayer of carbon atoms is organized. During deposition of the graphitic layer 316, the monolayers are organized parallel to the surfaces of the metal feature 312 on which the monolayers form. Thus, the atoms of carbon of the monolayers on the side surfaces of the first metal feature 312 are parallel to those side surfaces. This provides a low sheet resistance in a direction parallel to the side surfaces of the first metal feature 312. For a similar reason, the monolayers of graphene on a top surface of the first metal feature 312 are parallel to the top surface of the first metal feature 312. The monolayers of graphene on the top of the first metal feature 312 provides a higher sheet resistance than the monolayers of graphene on the side surfaces of the first metal feature 312 because the monolayers on the top surface are oriented perpendicular to a flow of electrons that may pass through the first metal feature. For this reason, in some embodiments, the graphene layer(s) on the top surface of the first metal feature 312 is (are) removed, thus exposing the low sheet resistance graphene layers on the sides of the first metal feature 312 to a subsequently formed second interconnect.

In some examples, an etch stop barrier 324 is deposited 224 on top of the planarized 220 top surface of the first ILD layer 320, graphene barrier layer 316 and first metal feature 312. An example embodiment of this configuration is shown in FIG. 3E. The etch stop barrier 324 is typically a material that is either unaffected by etches used to etch successive ILD layers or has a much slower etch rate compared to the ILD. Thus an etch stop barrier protects underlying features from processing performed on features above the etch stop barrier. Examples of the etch stop barrier 324 include alumina (A1₂0₃), zirconia (Zr0₂), silicon nitride, among others. The etch stop barrier 324 is deposited and planarized using any of the deposition and planarization techniques previously described in the context of base ILD layer 304 and ILD 320.

In another example embodiment, an interconnect structure fabricated according to a damascene process and having a conventional liner is placed in electrical communication with a first interconnect structure 328 configured with graphene lined interconnect features fabricated according to the method 200. FIG. 4 illustrates an example method 400 for fabricating such as structure, and FIGS. 5A-5C schematically illustrate cross-sections of example structures in various stages of fabrication according to the method 400, according to one such example embodiment. Mixing graphene-based interconnect structures (such as 328) with conventional interconnect structures on the same die or integrated circuit might be appropriate, for example, in the case where a relatively crowded or dense interconnect structure or layer is implemented with graphene-based interconnect features as provided herein, and a next interconnect structure or layer stacked thereon that is relatively less dense is implemented with conventional interconnect features. In other embodiments, all interconnect structures in a given circuit or die can be implemented with graphene-based interconnect features. Numerous such other embodiments and variations will be appreciated in light of this disclosure.

It will be appreciated that in some examples a liner (whether a tantalum -based liner or a graphitic liner) can be disposed between the blanket metal layer 308 and the base ILD layer 304. While this optional liner has been omitted in the examples shown in FIGS. 3 A-3E, embodiments that do include such an optional liner would, upon performance of the method 200, include a portion of the liner between the base ILD layer 304 and the first interconnect structure 328.

As shown in FIG. 4, and with concurrent reference to FIGS. 5A-5C, the method 400 begins by performing 402 the method 200. Thus, the previous discussion and various permutations and embodiments provided with reference to Figures 2 and 3 are equally applicable here. The method 400 continues with depositing 404 a second ILD layer 504 on the etch stop barrier 324 of the structure shown in FIG. 3E. Then, in accordance with damascene fabrication methods, a trench (shown in FIG. 5B) is etched 408 into the second ILD layer 504 and through the etch stop barrier 324. The etching 404 through the etch stop barrier 324 exposes a top surface of an interconnect feature of the first interconnect structure 328. Techniques for etching 404 the second ILD layer 504 and the etch stop barrier 324 include dry and/or wet etches, such as RIE, potassium hydroxide (KOH), and/or hydrofluoric acid (HF), formulated to remove the insulator material of the ILD layer 504 as well as the material used to form the etch stop barrier 324. Numerous suitable etch schemes are available, as will be appreciated. In the trench are then formed, at 412 and 416 respectively, a barrier layer 508 (such as a conventional tantalum- based barrier layer described above) and a second metal feature 512 (shown in FIG. 5C). As can be seen in this example case, the second metal feature 512 shown includes a via portion and a line portion. The barrier layer 508 and second metal feature 512 collectively form a conductive interconnect feature of a second interconnect structure 516 that is in direct contact with a conductive interconnect feature of the first interconnect structure 328.

Another example method 600 for fabricating an interconnect structure appears in FIG. 6, according to an embodiment. This method combines the use of both a tantalum -based liner and a graphitic liner for different portions of a second interconnect structure. FIGS. 7A-7D display schematic cross-sections of the structures at various stages of fabrication, according to an embodiment. As can be seen, an example of the device fabricated by the example method 600 includes a second interconnect structure configured with a conductive interconnect feature having a first portion (corresponding to a via portion) having a traditional barrier layer and a second portion (corresponding to a metal line connected to the via) having a graphitic liner.

The example method 600 includes first performing 602 the method 200 (or an equivalent method) to produce the structure schematically illustrated in FIG. 3E. Thus, the previous discussion and various permutations and embodiments provided with reference to Figures 2 and 3 are equally applicable here. A second ILD layer 704 (as shown in FIG. 7A) is formed 604 on top of the etch stop barrier 324. A second etch stop barrier 706 may be formed on the second ILD layer 704. The second ILD layer 704 and the second etch stop barrier 706 are etched 608 to form an interconnect trench. This interconnect trench is dimensioned and configured to form a via in a single damascene process (as opposed to a via and metal line formed in a dual damascene process like the trench illustrated in FIG. 5B). This etching 608 also exposes the top surface of the underlying conductive interconnect feature of the first interconnect structure 328 by etching through the etch stop barrier 324. A barrier layer 708 (e.g., a tantalum-based barrier layer) is conformally deposited 612 into the trench. A blanket metal layer 712 is then deposited 616 into the via trench and over the second ILD layer 704, using any of the techniques described above in the context of FIG. 2 and FIG. 3 A.

The blanket metal layer is etched 620, as described above in the context of FIG. 2 and

FIG. 3B. The etch 620 is performed to form a line portion of an interconnect feature from the blanket metal layer 712 that is integral with the via portion of the interconnect feature. The metal surfaces exposed by the etch 620 also act as a catalyst on which a graphitic barrier layer 720 is formed 624. The via portion and the line portion form a second metal feature 714. The second metal feature 714 and the graphitic barrier layer 720 and the barrier layer 708 collectively form a conductive interconnect feature of a second interconnect structure 722 that is in direct contact with a conductive interconnect feature of the first interconnect structure 328. A third layer ILD 724 is deposited 628 to fill trenches between the etched metal features. An illustration of an example final structure is presented in FIG. 7D.

Analogous to the method 600, some or all of the elements of the method 200 can be repeated to produce a stack of interconnects. One example method 800 for repeating some of the elements to produce a stacked via configuration which includes a via interconnect passing through two or more ILD layers is shown in FIG. 8, with concurrent reference to FIGS. 9A-9C that show corresponding cross-sectional schematics. The method 800 includes performing 804 the method 200. Thus, the previous discussion and various permutations and embodiments provided with reference to FIGS. 2 and 3 are equally applicable here. The method 800 continues with exposing 808 a top of a conductive interconnect feature included in the first interconnect structure 328 by removing a portion of the etch stop barrier 324. A second blanket metal layer 904 is formed 812 so that the metal is in contact with, and integral with, the top surface of the exposed conductive interconnect feature of the first interconnect structure 328. The second blanket metal layer 904 is then etched 816 to produce a second metal feature 912, in this case a via that is integral with the underlying first metal feature 312. Any suitable metal etch scheme can be used. A graphitic layer 916 is then formed 820 on a top surface and on side surfaces of the second metal feature 912, using processes as previously described. The second metal feature 912 and its corresponding graphitic layer 916 along with the underlying first metal feature 312 and its corresponding graphitic layer 316 collectively form a stacked via 918, as will be appreciated. Note that the graphitic layer 916 is shown as perfectly aligned with graphitic layer 316 in this example embodiment. In other embodiments, note that the two graphitic layers 916 and 316 may be at least somewhat offset from one another, so as to provide a step or taper when transitioning from one layer to the other. A second ILD layer 920 is formed at 820 around the second interconnect 918, which can then be planarized. A second etch stop barrier 924 is deposited on the planarized surface of the second ILD layer 920. The process may then be optionally repeated to produce additional interconnects in subsequent levels of the integrated device. These interconnects can either be another via portion or a line portion.

Graphitic Nanoribbon Interconnect Architecture Another example method 1000, shown in FIG. 10, describes the fabrication of graphitic nanoribbons (nano-scale graphitic interconnect features) that are used as interconnects without a corresponding metal feature. Instead, the method 1000 uses a first metal feature 312 merely as a catalyst for forming a graphitic layer. After the graphitic layer is formed, the metal is removed and replaced (in whole or in part) with a dielectric material. Example illustrations of structures corresponding to some stages of the method 1000 are shown in FIGS. 11A-11D. Benefits of these embodiments include those indicated above, and also include a decrease in the size of interconnects and correspondingly an increase in a density of interconnects per unit area. For example, graphene nanoribbon interconnects have a cross-sectional width of from 0.3 nm to 2 nm thick according to some embodiments, whereas conventional interconnects have a cross- sectional width well in excess of 5 nm, such as greater than 10 nm, or from 20 nm to 30 nm. The smaller interconnect size can thus be used to support a larger number of circuits and more closely spaced circuits than is achievable with conventional interconnects.

The example method 1000 includes performing 1002 the example method 200 (or an equivalent method) to produce the structure schematically illustrated in FIG. 3D. Thus, the previous discussion and various permutations and embodiments provided with reference to Figures 2 and 3 are equally applicable here. As shown in FIG. 11 A (and equivalently FIG. 3D), a top surface of a conductive interconnect feature of the first interconnect structure 328 is exposed. The first metal feature 312 is then removed 1004 to form a cavity 1104 defined by the graphitic barrier layer 316 and the underlying base ILD layer 304, as shown in FIG. 11B. The first metal feature 312 can be removed, for example, using a directional etch, such as one or more of those described above in the context of FIGS. 2 and 3B, that selectively removes the metal features without removing the ILD 320 material. Alternatively, or in addition, a mask may be used to protect the portions of the ILD 320 and the graphene barrier layer 316 from a metal etch.

As shown in FIG. 11C, a dielectric material 1108, such as an ILD (which can be the same material used for the base ILD 304, first ILD layer 320, or different from one or both of those materials), is then optionally formed 1008 into the cavity 1104. Techniques for forming the dielectric material 1108 in the cavity 1104 include any of the ILD deposition techniques presented above. These techniques include, but are not limited to, those for deposition into high aspect ratio cavities such as spin coating/spin-on deposition (SOD). In some embodiments, other deposition techniques may be used that are not adapted for deposition into high aspect ratio cavities. This is because the dielectric material 1 108 need not necessarily be free of defects and may include voids or other defects without impairing the function of the graphitic nanoribbon as an interconnect. In still other embodiments, the cavity 1104 may remain free of ILD, thus creating an air gap (the benefits of which are described below) between graphitic layers.

Each of the graphene barrier layers 316 can function as a graphitic nanoribbon interconnect when placed into electrical communication with a semiconductor device or contact (not shown) and/or another electrically conductive interconnection (e.g., another level of metal within an integrated circuit). Fabrication of, and connection, to another electrically interconnection is described below and shown in FIG. 1 ID.

The exposed top surfaces of the dielectric material 1108 and the graphene barrier layer 316 are planarized 1012. On this planarized surface is deposited 1016 an etch stop barrier 1112. On the etch stop barrier 1112 is deposited 1020 an ILD layer 1116. Both of etch stop barrier 1112 and the ILD layer 1116 can be deposited according to any suitable deposition techniques, such as those described above.

In accordance with damascene processing techniques, a trench is etched 1024 in the ILD layer 1116 so that the etch stop barrier 1112 is also partially removed to expose a top surface of the underlying graphene nanoribbon interconnect feature (used as an interconnect liner in other embodiments provided herein). A barrier layer 1 118 (e.g., alumina, zirconia, or silicon nitride) and metal layer 1120 layer are deposited 1028 in the trench and over the ILD layer 1116. The portion of the metal layer 1120 in the trench is in direct contact with the graphene nanoribbon, thus forming a graphene (or more generally graphitic) nanoribbon interconnect 1124. This structure is illustrated in FIG. 1 ID.

As shown in FIG. 1 ID, it is the graphitic layer formerly disposed on the side surface of the first metal feature 312, and not the top surface, that is used as the graphene nanoribbon interconnect. That is, as explained above in the context of FIG. 3D, the graphene layer (e.g., one or more monolayers) illustrated in FIG. 1 ID are oriented parallel to the side surface. This uses the graphene monolayers having a lower sheet resistance parallel to the direction of current flow as the interconnect. However, in another embodiment not shown, some or all of a graphene layer 316 corresponding to a top surface of the first metal feature may be retained so as to increase an area for contact to be made with another interconnect. This can be accomplished, for example, by adjusting a size of a protective mask or otherwise using a selectively applied etch to prevent removal of a portion of the top surface graphene layer when removing (e.g., etching or polishing) other portions of the structures shown.

In other embodiments, it will be appreciated that the dielectric material 1108 and/or the first ILD layer 320 can be configured to include "air gaps." The fabrication and benefits of air gaps are described below in the context of FIGS. 12 and 13A-13E. The application of the techniques described below to the embodiments shown and described above in the context of FIGS. 8, and 9A-9C will be apparent.

While the above description of FIG. 11D describes a damascene process for connection of a metal layer 1120 to the graphene nanoribbon interconnect 1124, the metal layer 1120 could also be fabricated through an etch process, as described above in the context of FIG. 2. That is, a top surface of the graphene nanoribbon interconnect 1123 is exposed, a blanket metal layer is deposited on the barrier etch stop 1112 and the exposed top surface of the graphene nanoribbon interconnect. Metal features are then etched from the blanket metal layer, which can then be lined with a tantalum liner or a graphitic liner (as variously described herein). Regardless, the resulting structure can then be encapsulated in ILD material.

It will be appreciated that the preceding methods, while each described independently, can be combined to produce an integrated circuit device having a combination of one or more of the structures shown in FIGS. 3E, 5C, 7D, 9C, 11D, 13E, and 14D. For example, a graphitic nanoribbon interconnect 1124 can be combined with other embodiments described above so that a tantalum-based barrier layer is disposed between the graphitic nanoribbon 1124 and a second interconnect, a graphitic barrier layer is disposed between the graphitic nanoribbon 1124 and a second interconnect, or a metal feature of a second interconnect is in direct contact with the graphitic nanoribbon interconnect 1124. Each of these can, in turn, be fabricated to include air gaps (described below in more detail) within one or more of the insulator layers. Furthermore, each of the preceding examples can be fabricated to include graphitic barrier layers on the side surfaces of the metal features of a second interconnect. Various other combinations of the embodiments described herein are also possible.

Graphitic Barrier with Air Gap Dielectric

Yet other embodiments of the present disclosure can be fabricated to include an air gap. An air gap is a volume within and defined by a dielectric layer that is free of dielectric material. Benefits from including an air gap in a dielectric layer include decreasing the capacitance of the integrated circuit, in addition to the conductance and capacitance improvements of a graphitic barrier, already discussed above.

An example method 1200 for fabricating embodiments that include an air gap is shown in FIG. 12. Concurrent reference to FIGS. 13A-13E and 14A-14D is also indicated below in the following description of FIG. 12. The method 1200 includes forming 1204 a base ILD layer 1300, as described above in the context of FIGS. 2 and 3A. Recall that this base ILD layer 1300 is optional, and if included, may further include conductive features to facilitate desired electrical connections as with any given interconnect layer or structure. A first metal feature is then formed 1208 on the base ILD layer, using either of two techniques. One technique is a damascene process and another technique is an etch process described above in the context of FIG. 2.

The formation 1208 of the first metal feature using a damascene process begins by forming 1212 a temporary ILD layer 1304 on the base ILD layer 1300, as shown in FIG. 13A. Trenches are then etched 1216 in the temporary ILD layer 1304. As shown in FIG. 13B, a temporary barrier layer 1308 is formed 1220 within the trench, such as a tantalum-based barrier. This is followed by formation 1222 of metal 1312 within the portion of the trench not occupied by the temporary liner 1308. As shown in FIG. 13C, the temporary ILD layer 1304 is then removed 1224 using a selective etch (e.g., an etch composed to remove the temporary ILD 1304 at a significantly faster rate than other exposed materials), such as an ozone or ionized argon RIE. Examples of the temporary ILD layer 1304 include compositions described above for other ILDs. While FIGS. 13B to 13E show a complete removal of the temporary ILD layer 1304, this need not be the case. In some examples, for instance, a portion of the temporary ILD layer 1304 may remain on the base ILD 1300 up to about 1/3 of the height of the metal 1312. However, for convenience of explanation, the figures and description assume removal of the temporary ILD layer 1304.

Regardless, removal of some or all of the temporary layer ILD 1304 exposes some or all of a first metal feature 1312. As a result of the previously described damascene process, which deposits a temporary liner on the exposed surfaces of the trenches prior to metal deposition, the first metal feature 1312 includes a portion of the liner 1308 disposed between the metal 1312 and the base ILD 1300, as shown in FIG. 13C. It will be appreciated that a similar process to this one can be applied to any of the embodiments described herein so that a first or second interconnect structure (e.g., 328, 512, 722) can include a liner between the interconnect structure and an underlying layer, including a tantalum-based liner, fabricated as part of a dual damascene process.

As shown in FIG. 13D, a graphitic barrier (e.g., graphene) 1318 is conformally formed

1228 over the exposed first metal feature 1312 as well as the remaining temporary liner 1308, which together form a first interconnect structure 1316. Techniques for forming 1228 graphene on a metal catalyst, such as the first metal feature 1312, are described above. As shown in FIG. 13E, a second ILD layer 1320 is formed over the first interconnect 1316 using any suitable deposition process such as, for example, CVD, PCVD, or PECVD. Using a vapor phase deposition technique (as opposed to a technique like SOD that includes flowable, liquid phase precursors) to form the second ILD layer 1320 has the benefit of creating air gaps 1322 within the second ILD layer 1320 between the first interconnect structures 1316. The air gaps 1322 are created as vapor phase precursor molecules nucleate on the surfaces of the first interconnect 1316 that are closest to the source of the precursor, namely the top surface of the first interconnects 1316 and the side surfaces proximate to the top surface. Once nucleated, the second ILD layer 1320 grows faster than those surfaces that have yet to nucleate a crystallite of the second ILD material. Thus, the second ILD layer 1320 eventually forms a continuous barrier near the top surfaces of one or more first interconnects 1316, thus preventing further deposition between the first interconnects. This results in the voids, or air gaps 1322 shown in FIG. 13E. The size of the air gaps can vary, but in some cases are in the range of about 1 nm to 5 nm across at their widest part, although bigger air gaps can be implemented as well. In a more general sense, an air gap is generally discernible from relatively small (e.g., less than 1 nm) non- intentional voids. One benefit of including air gaps 1322 in the second ILD layer 1320 include decreased capacitance between adjacent first interconnects.

FIG. 12 also illustrates an alternative technique for forming the first metal features using an etch process (also described in the context of FIG. 2). Cross-sectional views illustrating some of the stages of this alternative technique appear in FIGS. 14A-14D. As described above in the context of FIG. 2, a blanket metal layer 1404 is formed 1213 on the base ILD layer 1300. First metal features 1412 are etched 1217 from the blanket metal layer 1404. The forming 1213 and subsequent etching 1217 are collectively referred to as the etch process.

As also described above in the context of FIG. 2, a graphitic layer 1416 is formed 1228 on the top surface and the side surface of the first metal features. Unlike the technique using the damascene process, there is no barrier or intervening layer disposed between the first metal feature 1412 and the base ILD layer 1300. Rather, the first metal feature formed in the etch process is analogous to the structure shown in FIG. 3D. The method 1200 continues by fabricating a second ILD layer 1420 that defines air gaps as described above with regard to element 1232, and as shown in FIG. 14D.

As mentioned above, the method 1200 can be combined with any of the foregoing examples to produce devices having one or more of the structures described above.

Upon analysis (e.g., using scanning/transmission electron microscopy (SEM/TEM), composition mapping, secondary ion mass spectrometry (SEVIS), atom probe tomography, Raman spectroscopy, crystallography, and combinations thereof), a structure or device configured in accordance with one or more embodiments will show carbon rich layers (i.e., graphene) having atomic percentages of greater than 75 atomic % at locations within integrated circuits indicated above and in the accompanying figures.

Example System

FIG. 15 illustrates a computing system 1500 implemented with one or more integrated circuit structures configured and/or otherwise fabricated in accordance with an example embodiment of the present disclosure. As can be seen, the computing system 1500 houses a motherboard 1502. The motherboard 1502 may include a number of components, including but not limited to a processor 1504 and at least one communication chip 1506, each of which can be physically and electrically coupled to the motherboard 1502, or otherwise integrated therein. As will be appreciated, the motherboard 1502 may be, for example, any printed circuit board, whether a main board or a daughterboard mounted on a main board or the only board of computing system 1500, etc. Depending on its applications, computing system 1500 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1502. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1500 may include one or more integrated circuit structures configured with one or more conductive interconnect features having graphitic barrier layers or nano-scale conductive interconnect features, as variously described herein. These integrated circuit structures can be used, for instance, to implement an on-board processor cache or memory array or other circuit feature that includes interconnects. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1506 can be part of or otherwise integrated into the processor 1504).

The communication chip 1506 enables wireless communications for the transfer of data to and from the computing system 1500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1506 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1500 may include a plurality of communication chips 1506. For instance, a first communication chip 1506 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1504 of the computing system 1500 includes an integrated circuit die packaged within the processor 1504. In some embodiments of the present disclosure, the integrated circuit die of the processor includes onboard memory circuitry that is implemented with one or more integrated circuit structures configured with graphitic barrier layers or nano- scale conductive interconnect features, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1506 may also include an integrated circuit die packaged within the communication chip 1506. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more devices implemented with one or more integrated circuit structures formed as variously described herein (e.g., damascene and dual damascene graphitic barrier layers within a given interconnect layer or nano-scale conductive interconnect features, or other semiconductor structures that may benefit from thin graphitic barrier layers). As will be appreciated in light of this disclosure, note that multi- standard wireless capability may be integrated directly into the processor 1504 (e.g., where functionality of any communication chips 1506 is integrated into processor 1504, rather than having separate communication chips). Further note that processor 1504 may be a chip set having such wireless capability. In short, any number of processors 1504 and/or communication chips 1506 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing system 1500 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing system 1500 may be any other electronic device that processes data or employs integrated circuit features configured with one or more conductive interconnect features having graphitic barrier layers, as variously described herein.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is a semiconductor device, comprising: a graphitic nanoribbon interconnect disposed within the first insulator layer; a second insulator layer; and a second interconnect comprising a metal feature and disposed within the second insulator layer, the second interconnect in contact with the graphitic nanoribbon interconnect.

Example 2 includes the subject matter of Example 1, wherein the graphitic nanoribbon interconnect has two opposing lateral sides, and each of the sides has no liner material or barrier material or metal thereon.

Example 3 includes the subject matter of Example 1 or 2, wherein the first insulator layer comprises interlayer dielectric material having air gaps formed therein.

Example 4 includes the subject matter of any of the preceding Examples, wherein the first insulator layer comprises at least two different types of insulator materials.

Example 5 includes the subject matter of any of the preceding Examples, further comprising an etch stop barrier disposed between at least portions of the first insulator layer and portions of the second insulator layer.

Example 6 includes the subject matter of any of the preceding Examples, further comprising a barrier layer disposed between the metal feature of the second interconnect and the graphitic nanoribbon interconnect.

Example 7 includes the subject matter of Example 6, wherein the barrier layer is a tantalum-based barrier layer.

Example 8 includes the subject matter of Example 6, wherein the barrier layer is a graphitic barrier layer.

Example 9 includes the subject matter of any of the preceding Examples, wherein the metal feature of the second interconnect is in contact with the graphitic nanoribbon interconnect to provide a continuous conductive pathway. Example 10 includes the subject matter of any of the preceding Examples, wherein the graphitic nanoribbon interconnect has a height of at least 40 nm.

Example 11 includes the subject matter of any of the preceding Examples, wherein the graphitic nanoribbon interconnect has a height to thickness aspect ratio of at least 26 to 1.

Example 12 includes the subject matter of any of the preceding Examples, wherein the graphitic nanoribbon interconnect has a height to thickness aspect ratio of at least 133 to 1.

Example 13 includes the subject matter of any of the preceding Examples, wherein the graphitic nanoribbon interconnect has a height of at least 60 nm.

Example 14 includes the subject matter of any of the preceding Examples, wherein the graphitic nanoribbon interconnect has a height to thickness aspect ratio of at least 40 to 1.

Example 15 includes the subject matter of any of the preceding Examples, wherein the graphitic nanoribbon interconnect has a height to thickness aspect ratio of at least 200 to 1.

Example 16 includes the subject matter of any of the preceding Examples, wherein the graphitic nanoribbon interconnect has a thickness of less than 5 nm.

Example 17 includes the subject matter of any of the preceding Examples, wherein the graphitic nanoribbon interconnect has a thickness of less than 2 nm.

Example 18 includes the subject matter of any of the preceding Examples, wherein graphitic nanoribbon interconnect has a thickness of less than 1 nm.

Example 19 includes the subject matter of any of the preceding Examples, wherein the graphitic nanoribbon interconnect has at least one monolayer oriented in a direction of a height of the graphitic nanoribbon interconnect that is also in a direction of current flow through the graphitic nanoribbon interconnect.

Example 20 includes the subject matter of any of the preceding Examples, wherein the graphitic nanoribbon interconnect has a top surface and side surfaces, and wherein the side surfaces are in direct contact with the first insulator layer.

Example 21 is a computing system comprising the subject matter of any of the preceding Examples.

Example 22 is a method for fabricating a semiconductor device comprising: forming a first metal feature on a substrate, the first metal feature including a top surface and side surfaces; forming a graphitic layer on the side surfaces of the first metal feature; forming a first dielectric layer in contact with the graphitic layer on the side surfaces of the first metal feature; removing the first metal feature thus forming a graphitic nanoribbon interconnect and a cavity; and contacting a second interconnect to the graphitic nanoribbon interconnect to provide a conductive pathway.

Example 23 includes the subject matter of Example 22, wherein forming the first dielectric layer includes defining at least one air gap within the first dielectric layer during formation.

Example 24 includes the subject matter of Example 22 or 23 , wherein forming the graphitic layer on the side surfaces of the first metal feature orients at least one monolayer of the graphitic layer in a direction of a height of the graphitic layer that is also in a direction of current flow through the graphitic nanoribbon interconnect.

Example 25 includes the subject matter of any of Examples 22 through 24, further comprising depositing a dielectric material within the cavity.

Example 26 includes the subject matter of any of Examples 22 through 25, wherein the dielectric material within the cavity is a first material and the first dielectric layer is a second material different from the first material.

Example 27 includes the subject matter of any of Examples 22 through 26, further comprising depositing an etch stop barrier on at least a portion of a top surface of the first dielectric layer.

Example 28 includes the subject matter of any of Examples 22 through 27, wherein contacting the second interconnect to the graphitic nanoribbon interconnect comprises contacting a barrier layer to the graphitic nanoribbon interconnect.

Example 29 includes the subject matter of Example 28, wherein the barrier layer is formed from a tantalum-based barrier material.

Example 30 includes the subject matter of Example 28, wherein the barrier layer is formed from a graphitic barrier material.

Example 31 includes the subject matter of Example 28, wherein a metal feature of the second interconnect is disposed on a first surface of the barrier layer opposite to a second surface of the barrier layer that is in contact with the graphitic nanoribbon interconnect.

Example 32 includes the subject matter of any of Examples 22 through 31, wherein contacting the second interconnect to the graphitic nanoribbon interconnect comprises contacting a metal feature directly to the graphitic nanoribbon interconnect.

Example 33 includes the subject matter of any of Examples 22 through 32, wherein the second interconnect is formed by an etch process. Example 34 includes the subject matter of any of Examples 22 through 33, further comprising forming a graphitic liner on at least side surfaces of a metal feature of the second interconnect.

Example 35 includes the subject matter of any of Examples 22 through 34, wherein the second interconnect is formed by a damascene process.

Example 36 is a semiconductor device, comprising: a device layer including one or more metal oxide semiconductor (MOS) transistors; and a first interconnect structure over the device layer and including a graphitic nanoribbon interconnect disposed within an insulator material, wherein the graphitic nanoribbon interconnect electrically connects at least one of the transistors to another interconnect feature.

Example 37 includes the subject matter of Example 36, wherein the another interconnect feature is included in the first interconnect structure.

Example 38 includes the subject matter of any of Examples 36 through 37, wherein the another interconnect feature is included in a second interconnect structure disposed over the first interconnect structure.

Example 39 includes the subject matter of any of Examples 36 through 38, wherein the first interconnect structure includes one or more air gaps.

Example 40 includes the subject matter of any of Examples 36 through 39, wherein the first interconnect structure includes a plurality of graphitic nanoribbon interconnects, and at least two adjacent graphitic nanoribbon interconnects of the plurality are separated by an air gap.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

1. A semiconductor device, comprising:

a first insulator layer;

a graphitic nanoribbon interconnect disposed within the first insulator layer;

a second insulator layer; and

a second interconnect comprising a metal feature and disposed within the second insulator layer, the second interconnect in contact with the graphitic nanoribbon interconnect.

2. The semiconductor device of claim 1, wherein the graphitic nanoribbon interconnect has two opposing lateral sides, and each of the sides has no liner material or barrier material or metal thereon.

3. The semiconductor device of claim 1, further comprising a barrier layer disposed between the metal feature of the second interconnect and the graphitic nanoribbon interconnect.

4. The semiconductor device of claim 1, wherein the metal feature of the second interconnect is in contact with the graphitic nanoribbon interconnect to provide a continuous conductive pathway.

5. The semiconductor device of claim 1, wherein the graphitic nanoribbon interconnect has a height of at least 40 nm.

6. The semiconductor device of claim 5, wherein the graphitic nanoribbon interconnect has a height to thickness aspect ratio of at least 26 to 1.

7. The semiconductor device of claim 1, wherein the graphitic nanoribbon interconnect has a thickness of less than 5 nm.

8. The semiconductor device of claim 1, wherein the graphitic nanoribbon interconnect has at least one monolayer oriented in a direction of a height of the graphitic nanoribbon interconnect that is also in a direction of current flow through the graphitic nanoribbon interconnect.

9. The semiconductor device of claim 1, wherein the graphitic nanoribbon interconnect has a top surface and side surfaces, and wherein the side surfaces are in direct contact with the first insulator layer.

10. A computing system comprising the semiconductor device of any of claims 1 -9.

11. A semiconductor device, comprising: a device layer including one or more metal oxide semiconductor (MOS) transistors; and

a first interconnect structure over the device layer and including a graphitic nanoribbon interconnect disposed within an insulator material, wherein the graphitic nanoribbon interconnect electrically connects at least one of the transistors to another interconnect feature.

12. The semiconductor device of claim 11, wherein the another interconnect feature is included in the first interconnect structure.

13. The semiconductor device of claim 11, wherein the first interconnect structure includes one or more air gaps.

14. A method for fabricating a semiconductor device comprising:

forming a first metal feature on a substrate, the first metal feature including a top surface and side surfaces;

forming a graphitic layer on the side surfaces of the first metal feature;

forming a first dielectric layer in contact with the graphitic layer on the side surfaces of the first metal feature;

removing the first metal feature thus forming a graphitic nanoribbon interconnect and a cavity; and

contacting a second interconnect to the graphitic nanoribbon interconnect to provide a conductive pathway.

15. The method of claim 14, wherein forming the graphitic layer on the side surfaces of the first metal feature orients at least one monolayer of the graphitic layer in a direction of a height of the graphitic layer that is also in a direction of current flow through the graphitic nanoribbon interconnect.

16. The method of claim 14, further comprising depositing a dielectric material within the cavity.

17. The method of claim 16, wherein the dielectric material within the cavity is a first material and the first dielectric layer is a second material different from the first material.

18. The method of claim 14, wherein contacting the second interconnect to the graphitic nanoribbon interconnect comprises contacting a barrier layer to the graphitic nanoribbon interconnect.

19. The method of claim 18, wherein the barrier layer is formed from a tantalum- based barrier material.

20. The method of claim 18, wherein the barrier layer is formed from a graphitic barrier material.

21. The method of claim 18, wherein a metal feature of the second interconnect is disposed on a first surface of the barrier layer opposite to a second surface of the barrier layer that is in contact with the graphitic nanoribbon interconnect.

22. The method of claim 14, wherein contacting the second interconnect to the graphitic nanoribbon interconnect comprises contacting a metal feature directly to the graphitic nanoribbon interconnect.

23. The method of claim 14, wherein the second interconnect is formed by an etch process.

24. The method of claim 23, further comprising forming a graphitic liner on at least side surfaces of a metal feature of the second interconnect.

25. The method of claim 14, wherein the second interconnect is formed by a damascene process.