TW201818665A - Transition enforcing coding receiver ahd a receiving method used by the transition enforcing coding receiver - Google Patents

Abstract

The invention provides a transition enforcing coding (TEC) receiver comprising: a delay line circuit, configured to employ a calibrated delay setting to delay a plurality of vector signals to generate a plurality of delayed vector signals under a normal mode, respectively; a transition detection circuit, configured to detect a transition of at least one specific delayed vector signal among the delayed vector signals; a data sampling circuit, configured to sample the vector signals according to a sampling timing, wherein the sampling timing is determined based on an output of the transition detection circuit; and a skew calibration circuit, configured to set the calibrated delay setting under a calibration mode, wherein transition skew between different delayed vector signals is reduced by the calibrated delay setting under the normal mode.

Description

Transition state forced code receiver and receiving method for transition state forced code receiver

The present invention relates to the field of data recovery technologies at the receiver end, and more particularly to a Transition Enforcing Coding (TEC) receiver that does not use Clock and Data Recovery (CDR) to sample vector signals.

The transition forced coding is a technique for converting a bit sequence into a plurality of vector signals transmitted and received between different wafers, and the transitional forced encoding causes the transition to always be in the vector signal. Appearing between adjacent states, for example, the vector signal records a data bit representing the current state in the current transfer clock cycle, and records the data bit representing the next state of the next transfer clock cycle, which represents the current The data bit of the state and the data bit of the next state have a transposition of at least one bit (eg, 1→0 or 0→1). The conventional transition state forced code receiver has a Clock and Data Recovery (CDR) circuit, which is used to adjust the sampling time so that the data sampler can obtain the optimal set/hold time margin. The received vector signal is correctly sampled, however, the clock data recovery circuit will result in a larger die area and higher power consumption, and will require additional lock-in time to ensure correct data sampling, In addition, if the transition state forced code transmitter requires a wide range of data rates, the clock data recovery circuit in the transition state forced code receiver needs to be implemented using a wide range of clock data recovery circuits, which will result in a higher manufacturing cost.

Therefore, there is a need for a transitional forced code receiver design that can correctly sample the received vector signal without using any clock data recovery circuitry.

In accordance with an embodiment of the present invention, a transition state forced code receiver is disclosed that can correctly sample a received vector signal without the need for clock data recovery.

According to a first embodiment of the present invention, a transition state forced code receiver is disclosed, which may include: a delay line circuit for delaying a plurality of vector signals to generate a plurality of respectively using a calibrated delay setting in a normal mode a delayed vector signal; a transition detection circuit configured to detect a transition of a vector signal after the specific delay of the plurality of delayed vector signals; and a data sampling circuit configured to: Sampling a plurality of vector signals, wherein the sampling time is determined according to an output of the transition detecting circuit; and a deviation calibration circuit configured to set the adjusted delay setting in the calibration mode; In the normal mode, the transition deviation of the vector signal after different delays is reduced by the calibrated delay setting.

According to a second embodiment of the present invention, a receiving method for a transition state forced code receiver is disclosed, which may include: performing a offset calibration to set a calibrated delay setting in a calibration mode; and using a calibration in a normal mode The subsequent delay setting delays the plurality of vector signals to respectively generate a plurality of delayed vector signals, wherein, in the normal mode, the transition state deviation of the vector signals after the different delays is reduced by the calibrated delay setting Detecting a transition state of a vector signal after the specific delay in the plurality of delayed vector signals; sampling the plurality of vector signals according to a sampling time, wherein the sampling time is according to the transition state The measured output is determined.

With the above described embodiments, the present invention can correctly sample the received vector signal without the need for clock data recovery.

Certain terms are used throughout the description and claims to refer to particular elements. Those skilled in the art will appreciate that a hardware manufacturer may refer to the same component by a different noun. The scope of the present specification and the patent application do not use the difference in the name as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The words "including" and "including" as used throughout the specification and claims are intended to be interpreted as "including but not limited to". "Substantially" means that within the acceptable tolerances, those skilled in the art will be able to solve the technical problem within a certain error range, substantially achieving the technical effect. In addition, the term "coupled" is used herein to include any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, the first device can be directly electrically connected to the second device, or can be electrically connected to the second device through other devices or connection means. Device. The following is a preferred embodiment of the present invention, and is intended to be illustrative of the scope of the invention, and the scope of the invention is defined by the scope of the appended claims.

1 is a schematic diagram of a communication system including an encoder 112 and a transmitter 114 located in a first wafer 102 and a receiver 122 located in a second wafer 104, and in accordance with an embodiment of the present invention. The decoder 124, the encoder 112 may encode the n-bit binary data b[n-1, 0] into k vector signals v[k-1, 0] according to the used forced coding algorithm. The transmitter 114 has a serializer (not shown) to convert k vector signals v[k-1, 0] into m vector signals s[m-1, 0 for high speed data transfer. The m vector signals s[m-1, 0] are then transferred from the first wafer 102 to the second wafer 104 through m parallel channels. The receiver 122 receives the m vector signals s[m-1, 0] from the m parallel channels and has a deserializer (not shown) to receive the received m vector signals s[m The sample data of -1, 0] is converted into sample data of k vector signals v[k-1, 0]; the decoder 124 can convert k vector signals v[k-1 according to the transition state forced coding algorithm used. , 0] is restored to the n-bit binary data b[n-1, 0]. In this embodiment, the receiver 122 utilizes the proposed transition state forced encoding receiver architecture without using the conventional clock data recovery circuit. The sampling data of the m vector signals s[m-1, 0] are generated, and the details of the structure of the transitional forced coding receiver will be described in the following paragraphs.

2 is a first conceptual diagram of sampling a vector signal without using a conventional clock data recovery circuit, assuming m=3, three vector signals s[2], s[1], s[0, in accordance with an embodiment of the present invention. ] The transmissive forced code receiver is received separately from the parallel channel. As described above, the transition state forcing the code receiver causes at least one transition to occur between adjacent states of the vector signal, in the end between the neighboring states (eg, near the edge of the transmit clock cycle) The last transition can be detected. If only one transition occurs between adjacent states of the vector signal, the detected transition will be regarded as the final transition; if the vector signal is in the adjacent state When there are multiple transitions, the transition with the last occurrence of the detected transitions is considered the last transition. The time of the last transition detected is delayed by a preset delay time D to satisfy one sampling time of the vector signals s[2], s[1], s[0]. Observable from the eye diagram of the vector signals s[2], s[1], s[0], from the last transition between the current state to the first transition between the next state transitions The signal level is stable and clean. By setting the preset delay time D appropriately, the preset delay time D will be sufficient to satisfy the data sampling operation setting/holding time. Therefore, the representative vector signal s[2], s[1], s can be correctly restored by the sampling time. A data bit of the state of [0], wherein the sampling time is determined based on a delayed version of the last transition detected between adjacent states.

3 is a second conceptual diagram of sampling a vector signal without using a conventional clock data recovery circuit, assuming m=3, three vector signals s[2], s[1], s[0, in accordance with an embodiment of the present invention. Obtained by the transition state forced code receiver from the parallel channels, as described above, the transition state forcing the code receiver to cause at least one transition state to occur between adjacent states of the vector signal in the proximity state (eg, in transmission) The first transition between the edges of the clock cycle can be detected. If only one transition occurs between adjacent states of the vector signal, the detected transition state is regarded as the first transition state; if multiple transition states occur between adjacent states of the vector signal, the detected The transition state with the first occurrence time in the transition state is regarded as the first transition state, and the first transition state detected by advance by a preset advance time D' The time is such that it satisfies a sampling time of the vector signals s[2], s[1], s[0]. Observed from the eye diagrams of the vector signals s[2], s[1], s[0], the signal level from the first transition state between the current state to the last transition state between the previous states is stable and clean. . Appropriately setting the preset advance time D', the preset advance time D' will be sufficient to satisfy the setting/holding time of the data sampling operation, and therefore, the representative vector signal s[2], s[1] can be correctly restored by the sampling time. ], the data bit of the state of s[0], wherein the sampling time is determined based on an early version of the first transition detected between adjacent states.

The proposed transition state forced code receiver can be configured according to the concepts described in FIG. 2 and FIG. 3 to recover/sampling the correct data without using the conventional data clock recovery circuit. Multiple examples of encoding receivers.

Figure 4 is a schematic diagram of a transition state forced code receiver in accordance with a first embodiment of the present invention. The receiver 122 shown in FIG. 1 can be implemented by using the transition state forced code receiver shown in FIG. 4. The transition state forced code receiver 400 includes a delay line circuit 402, a transition state detection circuit 404, and a data sampling circuit 406. It should be noted that FIG. 4 only shows some of the components related to the present invention. In fact, the transitional forced code receiver 400 may include additional circuit components. For example, the transitional forced code receiver 400 may have At least one deserializer that processes the output of the data sampling circuit 406.

The delay line circuit 402 is configured to delay a plurality of vector signals (such as m vector signals s[m-1] - s[0]) to respectively generate a plurality of delayed vector signals (eg, m delayed vector signals m) Vector signal s[m-1]_D- s[0]_D), it should be noted that the delay time D applied to each of the vector signals s[m-1]-s[0] is sufficient for the data sampling circuit The set/hold time margin of 406, in one embodiment, the same set delay time D can be applied to all vector signals, and in another embodiment, different delay times D can be applied to different vectors. The signal is used to ensure that there is sufficient set/hold time margin to sample different vector signals and to reduce the transitional deviation between different vector signals (ie, the calibration transition between adjacent states of different vector signals).

The transition detection circuit 404 is configured to detect a transition state of the vector signal after the at least one specific delay in the delayed vector signal s[m-1]_D−s[0]_D, in this embodiment, the at least The transition of the vector signal after a particular delay is the last transition detected between adjacent states of the delayed vector signal s[m-1]_D−s[0]_D. It should be noted that the delayed vector signal s[m-1]_D–s[0]_D and the vector signal s[m-1]–s[0] convey the same data bit but the time interval delay time D. The data sampling circuit 406 is configured to sample the vector signal s[m-1]−s[0] according to the sampling time TS, wherein the sampling time TS is determined according to the output of the transition detecting circuit 404. In this embodiment, the transition state forced code receiver 400 determines the sampling time TS without using the clock data recovery circuit, for example, directly setting the sampling time TS to the transition state of the vector signal after the at least one specific delay. Time (ie, the time of the last transition detected between adjacent states).

As described above, the delay line circuit 402 is used to delay the vector signal s[m-1]–s[0] to generate the delayed vector signal s[m-1]_D–s[0]_D, where the transition detection Circuit 404 uses the delayed vector signal s[m-1]_D−s[0]_D to detect the transition of the vector signal after at least one particular delay. Since the delay line circuit 402 is located before the transition detection circuit 404, the deviation problem between the vector signals s[m-1]–s[0] may be overcome by some calibration methods, and therefore, in addition to being generated as a delayed vector signal The delay line circuit 402 can additionally serve as a cancellation offset circuit for the calibration transition between adjacent states of the vector signal s[m-1] - s[0], such that the delay line circuit 402 can eliminate the vector signal s[m -1] - s[0] deviation and delay vector signal s[m-1]–s[0].

Fig. 5 is a diagram showing an example of a data sampling operation performed by the transition state forced code receiver shown in Fig. 4, wherein the transition state forced code receiver 400 can be designed according to the concept shown in Fig. 2. The transition detection circuit 404 checks the delayed vector signal s[m-1]_D−s[0]_D to find the last transition state between adjacent states, the delayed vector signal s[m-1] The time of the last transition state possessed by at least one of the signals _D - s[0]_D is equal to the time of the last transition state possessed by at least one of the vector signals s[m-1] - s[0] The delay, therefore, the time of the last transition state possessed by at least one of the delayed vector signals s[m-1]_D−s[0]_D can be used as the sampling time TS of the data sampling circuit 406. The sampled data is obtained from the vector signal s[m-1]–s[0].

Figure 6 is a schematic diagram of the circuit implementation of the transition state forced code receiver according to Fig. 4. As shown in Fig. 6, the delay line circuit 402 includes a vector signal s[m-1]_D for generating the delay, respectively. Multiple delay lines of –s[0]_D (labeled "D") 6020-602m-1, delay time settings used by delay lines 6020-602m-1 may be the same or different, depending on design considerations Decide. In this circuit design, the vector signal s[m-1]-s[0] is supplied to the data sampling circuit 406 and the transition detection circuit 404. Therefore, in addition to including the delayed vector signal s[m-1]_D- s[0]_D, the final transition detection also includes the vector signal s[m-1]-s[0].

The transition detection circuit 404 includes a plurality of logic gates 6040-604m-1 (such as an exclusive NOR (XNOR)) and a logic gate 606 (such as an AND gate) according to logic gates 6040-604m. -1 and 606 logic operations, the output of the transition detection circuit 404 (especially the output of the logic gate 606) is detected between adjacent states of the delay vector signal s[m-1]_D-s[0]_D This last transition has a rising edge. The data sampling circuit 406 includes a plurality of data samplers 6080-608m-1 implemented by D-type flip flips (DFFs), and the data samplers 6080-608m-1 are controlled by the transition detection circuit 404. The same rising edge of the output is clocked to sample the vector signal s[m-1]-s[0] at the same time, thereby obtaining the sampled data bit s[0]_receive-s[m-1], respectively. _receive.

7 is a schematic diagram of a transition state forced code receiver according to a second embodiment of the present invention, and the receiver 122 shown in FIG. 1 can be implemented by using the transition state forced code receiver 700 shown in FIG. The forced code receiver 700 includes a delay line circuit 702, a transition state detection circuit 704, and a data sampling circuit 706. It should be noted that FIG. 7 only shows the circuit elements related to the present invention. In fact, the transition state forced code receiver 700 Additional circuit components may be included, for example, the transitional forced code receiver 700 may have at least one deserializer to process the output of the data sampling circuit 706.

The delay line circuit 702 is configured to delay a plurality of vector signals (such as m vector signals s[m-1] - s[0]) to respectively generate a plurality of delayed vector signals (eg, m delayed vector signals m) The vector signal s[m-1]_D - s[0]_D), it should be noted that the delay time D' is sufficient to satisfy the set/hold time margin of the data sampling circuit 406, in an embodiment, with appropriate settings The same delay time D' can be applied to all vector signals, in another embodiment, different delay times D' can be applied to different vector signals to ensure that there is sufficient set/hold time margin to sample different Vector signals and reduce the deviation of the transition between different vector signals.

The transition detection circuit 704 is configured to detect a transition state of at least one specific vector signal in the vector signal s[m-1]-s[0], in this embodiment, the transition state of the at least one specific vector signal For the first transition detected between the adjacent states of the vector signal s[m-1]-s[0], the data sampling circuit 706 is configured to sample the delayed vector signal s[m- according to the sampling time TS. 1]_D-s[0]_D, wherein the sampling time TS is determined according to the output of the transition detecting circuit 704. In this embodiment, the transition state forced encoding receiver 700 determines sampling without using clock data recovery. The time TS, for example, directly sets the sampling time TS to the time of the transition of the at least one particular vector signal (ie, the time of the first transition detected between adjacent states).

Fig. 8 is a diagram showing an example of a data sampling operation performed by the transition state forced code receiver 700 shown in Fig. 7, wherein the transition state forced code receiver 700 can be set according to the concept shown in Fig. 3. The transition detection circuit 704 acknowledges the vector signal s[m-1]-s[0] to find the first transition between adjacent states, since the vector signal s[m-1 is delayed in order for the data sampling circuit 706 to sample the data. ]-s[0], the time of the first transition state possessed by one of the reference vector signals s[m-1]-s[0] is the sample vector signal s[m-1]-s[0] Therefore, the time of the first transition state possessed by at least one signal of the vector signal s[m-1]-s[0] can be used as the sampling time TS of the data sampling circuit 406 to the self-delayed vector signal s [m-1]_D-s[0]_D obtains sampling data, wherein the delayed vector signal s[m-1]_D-s[0]_D is a vector signal s[m-1]-s[0] The delay, and therefore the same data bits transmitted by the vector signal s[m-1]-s[0].

Figure 9 is a circuit diagram showing the implementation of the transition state forced code receiver shown in Fig. 7 of the present invention. As shown in Fig. 9, the delay line circuit 702 includes the vector signal s[m-1]-s[0]. To generate a plurality of delay lines 7030-703m-1 (labeled as "D'") of the delayed vector signal s[m-1]_D−s[0]_D, it should be noted that the delay line 7030-703m- The delay times used may be the same or different and are determined by design considerations. The delayed vector signal s[m-1]_D−s[0]_D is supplied to the data sampling circuit 706 and the transition detection circuit 704, thus, in addition to including the vector signal s[m-1]-s[0] In addition, the detection of the first transition also includes the delayed vector signal s[m-1]_D-s[0]_D.

The transition detection circuit 704 includes a plurality of logic gates 6040-604m-1 (such as a negation or gate (XNOR)) and a logic gate 906 (such as a NAND gate) according to logic gates 6040-604m-1. And the logic operation of 906, the output of the transition detection circuit 704 (especially the output of the logic gate 906) is detected between the adjacent states of the vector signal s[m-1]-s[0] The transition has a rising edge. The data sampling circuit 706 includes a plurality of samplers 6080-608m-1 implemented using D-type flip-flops, and the samplers 6080-608m-1 are controlled by the same rising edge clock of the output of the transition detection circuit 704 at the same time. The sample vector signal s[m-1]-s[0] is sampled, thereby obtaining the sampled data bit s[0]_received-s[m-1]_ received, respectively.

As shown in Figures 6 and 9, logic gates 606/906 are used to drive the clock input nodes of all data samplers 6080-608m-1. When the data rate is high, the pulse width is shorter, when the sampler 6080-608m -1 operation in the full rate clock domain, it may be difficult for logic gates 606/906 to drive the clock input nodes of all data samplers 6080-608m-1 in a short time, and/or may consume more power for a short time In order to drive the clock input nodes of all data samplers 6080-608m-1, in order to ease the driving requirements of the logic gates 606/906, the present invention proposes to have clock generation and related reduction serialization (for example, 1 to 2 reduction serialization (1) -to-2 deserialization)) and a more power-saving transition state forced code receiver design.

10 is a schematic diagram of a transition state forced code receiver according to a third embodiment of the present invention. The main difference between the transition state forced code receivers 400 and 1000 is that the transition state forced code receiver 1000 further includes a frequency divider 1002. The data sampling circuit 1006 is configured to drive a plurality of data sampler groups (such as the first data sampler group 1003 and the second data sampler group 1004). In this embodiment, the first data sampling group 1003 is composed of multiple data. The sampler 10080-1008m-1 is composed of a plurality of data samplers 10090-1009m-1, and the frequency divider 1002 is used to perform frequency division on the output of the rotation detecting circuit 404 to generate a clock. Signal CK is applied to data sampling circuit 1006. For example, the frequency divider 1002 can be implemented by a divide-by-2 counter, such that the input of the frequency divider 1002 can operate in the full rate clock domain, while the output of the frequency divider 1002 can operate in the half rate clock domain, although The pulse width of the output of the state detecting circuit 404 is short, but due to the inherent characteristics of the 2 counter, the duty cycle of the clock signal CK may be equal to or close to 50%. In this embodiment, the first data sampler group 1003 can be designed to be clocked by the rising edge of the clock signal CK, and the second data sampler group 1004 can be designed to be clocked by the falling edge of the clock signal CK, thus The data sampler 10080-1008m-1 is configured to sample the vector signal s[0]-s[m-1] according to the rising edge of the clock signal CK, and the data sampler 10090-1009m-1 is used according to the clock signal CK. The falling edge is used to sample the vector signal s[0]-s[m-1].

Compared with the output of the transition detection circuit 404, the clock signal CK has a lower clock rate and a longer logic high value/logic low value width, and the frequency divider 1002 represents the transition detection circuit 404 to drive the data sampling circuit 1006. . Compared with the transition detection circuit 404, when all the data samplers 10080-1008m-1 (or 10090-1009m-1) are driven at the same time, the frequency divider 1002 has a relatively slow driving demand, and the transition detection circuit The output of the 404 only needs to drive the frequency divider 1002, and the driving demand of the transition detection circuit 404 can be relieved. In addition, since the first data sampler group 1003 and the second data sampler group 1004 are clocked by the rising edge and the falling edge of the clock signal CK, the retransition serialization of 1 to 2 can also be completed by the data sampling circuit 1006.

11 is a schematic diagram of a transition state forced code receiver according to a fourth embodiment of the present invention. The main difference between the transition state forced code receivers 700 and 1100 is that the transition state forced code receiver 1100 further includes a plurality of data for driving. a frequency divider 1102 of the data sampling circuit 1106 of the sampler group (such as the first data sampler group 1103 and the second data sampler group 1104). In this embodiment, the first data sampling group 1103 is composed of a plurality of data samplers. 11080-1108m-1, the second data sampler group 1104 is composed of a plurality of data samplers 11900-1109m-1, and the frequency divider 1102 is used to perform frequency division on the output of the transition detection circuit 704 to generate a clock signal CK. To the data sampling circuit 1106. For example, the frequency divider 1102 can be implemented by a divide-by-2 counter, such that the input of the frequency divider 1102 can operate in the full rate clock domain, while the output of the frequency divider 1102 can operate in the half rate clock domain, although The pulse width of the output of the state detecting circuit 704 is short, but due to the inherent characteristics of the two counters, the duty cycle of the clock signal CK may be equal to or close to 50%. In this embodiment, the first data sampler group 1103 can be designed to be clocked by the rising edge of the clock signal CK, and the second data sampler group 1104 can be designed to be clocked by the falling edge of the clock signal CK, thus The data sampler 11080-1108m-1 is configured to sample the vector signal s[0]-s[m-1] according to the rising edge of the clock signal CK, and the data sampler 11090-1109m-1 is used according to the clock signal CK. The falling edge is used to sample the vector signal s[0]-s[m-1].

Compared with the output of the transition detection circuit 704, the clock signal CK has a lower clock rate and a longer logic high value/logic low value width, and the frequency divider 1102 represents the transition detection circuit 704 to drive the data sampling circuit 1106. . Compared with the transition detection circuit 704, when all the data samplers 11080-1108m-1 (or 11900-1109m-1) are driven at the same time, the frequency divider 1102 has a relatively slow driving demand, and the transition detection circuit The output of 704 only needs to drive the frequency divider 1402, and the driving demand of the transition detection circuit 704 can be relieved. In addition, since the first data sampler group 1103 and the second data sampler group 1104 are clocked by the rising edge and the falling edge of the clock signal CK, respectively, the retransition serialization of 1 to 2 can also be completed by the data sampling circuit 1106.

12 is a circuit implementation diagram of the frequency divider 1002 and the data sampling circuit 1006 shown in FIG. 10. In this embodiment, the frequency divider 1002 is implemented by setting a D-type flip-flop as a divide-by-2 counter, data sampling. The 10080-1008m-1 is implemented by using a D-type flip-flop controlled by the rising edge clock of the clock signal CK to sample the vector signal s[0]-s[m-1] to respectively generate the sample data bit s[0] _ODD-s[m-1]_ODD, and the data sampler 10090-1009m-1 is implemented by using a D-type flip-flop controlled by the falling edge clock of the clock signal CK to sample the vector signal s[0]-s[m -1] to generate the sample data bit s[0]_EVEN-s[m-1]_EVEN, respectively.

FIG. 13 is a schematic diagram of the circuit implementation of the frequency divider 1102 and the data sampling circuit 1106 shown in FIG. 11. In this embodiment, the frequency divider 1102 is implemented by setting a D-type flip-flop as a divide-by-2 counter, data sampling. The 11080-1108m-1 is implemented by using a D-type flip-flop controlled by the rising edge clock of the clock signal CK to sample the vector signal s[0]-s[m-1] to respectively generate the sample data bit s[0] _ODD-s[m-1]_ODD, and the data sampler 11090-1109m-1 samples the vector signal s[0]-s[m-1 by using a D-type flip-flop controlled by the falling edge clock of the clock signal CK. ] to generate the sample data bit s[0]_EVEN-s[m-1]_EVEN, respectively.

For the transition state forced code receiver 400 shown in FIG. 4, the vector signal is first delayed by the delay line circuit 402, and then processed by the transition detection circuit 404 to detect the final transition state, in addition to the same delay line. The circuit is used to delay the data and the transition state. However, this is merely an example and is not a limitation of the present invention. The same concept shown in FIG. 2 can be applied to the transition state forced code receiver shown in FIG. 4 by appropriate modification. 400 to complete, the details will be described in the following paragraphs.

Figure 14 is a schematic diagram of a transition state forced code receiver according to a fifth embodiment of the present invention, and the receiver 122 shown in Fig. 1 can be implemented by using the transition state forced code receiver 1400 shown in Fig. 14, wherein The state-enforced code receiver 1400 includes a transition state detection circuit 1402, a delay line circuit 1404, and a data sampling circuit 1406. It should be noted that FIG. 14 only shows some components related to the present invention, and actually the state-locked coded receiver The 1400 can include additional circuit components. For example, the transition state forced code receiver 1400 can have at least one deserializer to process the output of the data sampling circuit 1406.

The transition state forced code receiver 1400 can be implemented by exchanging the transition state detecting circuit 404 and the delay line circuit 402 shown in FIG. 4, and therefore, for the transition state forced code receiver 1400 shown in FIG. The detecting circuit 1402 is configured to detect a transition state of at least one specific vector signal in the vector signal s[m-1]-s[0]. In this embodiment, the transition state of the at least one specific vector signal is a vector. a final transition detected between adjacent states of the signal s[m-1]-s[0]; the delay line circuit 1404 is configured to generate a delayed signal according to the output of the transition detection circuit, wherein the delay time D Sufficient to meet the set/hold time margin of the data sampling circuit 1406; the data sampling circuit 1406 is configured to sample the vector signal s[m-1]-s[0] according to the sampling time TS, wherein the sampling time TS is according to the delay line circuit 1404. The resulting delayed signal is determined. In this embodiment, the transition state forced code receiver 1400 determines the sampling time TS without using clock data recovery, for example, directly setting the sampling time TS to the intentional delay transition time of the at least one particular vector signal. (ie the time of the last transition of the intentional delay).

15 is a schematic diagram of a transition state forced code receiver according to a sixth embodiment of the present invention, and the receiver 122 shown in FIG. 1 can be implemented by using the transition state forced code receiver 1500 shown in FIG. The state-enforced code receiver 1500 includes a plurality of delay circuits 1502 and 1506. One of the delay circuits is located before the transition detection circuit 1504 and the other delay circuit is located between the transition detection circuit 1504 and the data sampling circuit 1508. Figure 15 shows only some of the components associated with the present invention. In effect, the transitional forced code receiver 1500 can include additional circuit components. For example, the transitional forced code receiver 1500 can have processing data samples. At least one deserializer of the output of circuit 1508.

In this embodiment, the delay line circuit 1502 is configured to delay the vector signal s[m-1]-s[0] to generate the delayed vector signal s[m-1]_D-s[0]_D, where the transition state The detecting circuit 1504 uses the delayed vector signal s[m-1]_D-s[0]_D to detect the transition state of the vector signal after at least one specific delay. Since the delay line circuit 1502 is located before the transition detection circuit 1504, it is possible to overcome the deviation problem between the vector signals s[m-1] - s[0] by some calibration methods. In other words, the delay line circuit 1502 can be used as Vector signal s[m-1] – s[0] The deviation of the calibration transition between adjacent states.

In this embodiment, the transition state of the at least one specific delayed post vector signal is the last transition detected between the adjacent states of the delayed vector signal s[m-1]_D-s[0]_D, The other delay line circuit 1506 is configured to generate a delayed signal according to the output of the transition detection circuit 1504, wherein the sampling time TS is determined according to the delayed signal. In this embodiment, the transition state forced code receiver 1400 determines the sampling time TS without using clock data recovery. For example, the delay line circuit 1506 is configured to delay the detected last transition time to set the data. The sampling time TS used by the sampling circuit 1508 samples the vector signal s[m-1]-s[0].

The technical content of using a frequency divider to generate a clock signal having a lower clock rate and a longer period to slow down the driving demand can be integrated into the transition state forced code receiver 1500 shown in FIG.

Figure 16 is a diagram showing a transition state forced code receiver 1600 according to a seventh embodiment of the present invention. In this embodiment, the data sampling function can be implemented using the data sampling circuit 1006 shown in Fig. 10, and the frequency divider 1002 (such as the divide-by-2 counter) may be located between the transition detection circuit 1504 and the delay line circuit 1506. Therefore, after the frequency divider 1002 generates a clock signal according to the output of the transition detection circuit 1504, the delay line circuit 1506 delays the clock. Signal CK is generated to generate delayed post clock signal CK_D to data sampling circuit 1006. Since the delay line circuit 1506 delays the clock signal CK to generate the delayed clock signal CK_D to set the sampling time of the data sampling circuit 1006 as the delayed signal, the data sampler 10080-1008m-1 in the data sampling circuit 1006 is used to delay. The rising edge of the rear clock signal CK_D samples the vector signal s[0]-s[m-1], respectively, and the data sampler 10090-1009m-1 in the data sampling circuit 1006 is used to follow the falling edge of the delayed clock signal CK_D. To sample the vector signal s[0]-s[m-1] separately.

Figure 17 is a diagram showing a transition state forced code receiver 1700 according to an eighth embodiment of the present invention. In this embodiment, the data sampling function can be implemented using the data sampling circuit 1006 shown in Fig. 10, and the frequency divider 1002 (such as a divide-by-2 counter) may be located between the delay line circuit 1506 and the data sampling circuit 1006. Therefore, after the delay line circuit 1506 generates the delayed signal according to the output of the transition detecting circuit 1504, the frequency divider 1002 according to the delay The post signal generates a clock signal CK. Therefore, the data sampler 10080-1008m-1 in the data sampling circuit 1006 is configured to separately sample the vector signal s[0]-s[m-1] according to the rising edge of the clock signal CK. The data sampler 10090-1009m-1 in the data sampling circuit 1006 is configured to separately sample the vector signal s[0]-s[m-1] according to the falling edge of the clock signal CK.

As shown in Fig. 2, the data bits transmitted by the vector signals s[2], s[1], s[0] can be recovered correctly by the sampling time, wherein the sampling time is based on the vector signal s[2], The delay of the last transition detected by the neighboring states of s[1] and s[0] is determined, however, the final transition state after the delay cannot obtain the vector signals s[2], s[1], and s[ The sampling result of the initial state of 0]. Regarding the transition state forced code receiver using the concept shown in FIG. 2, the data sampling circuit can be used to output a preset bit form as a sampling result of the initial state of the vector signal, that is, the turn used by the transmitter end. The state forcing coding algorithm can force the initial state of the vector signal to have the preset bit form, such that the initial state of the vector signal can be correctly recreated at the receiver end using the same transitional forced coding algorithm.

As shown in Fig. 3, the data bits transmitted by the vector signals s[2], s[1], s[0] can be recovered correctly by the sampling time, wherein the sampling time is based on the vector signal s[2], The advance of the first transition state detected by the proximity state of s[1], s[0], however, the first transition state of the advance cannot obtain the vector signal s[2], s[1] And the sampling result of the end state of s[0]. Regarding the transition state forced code receiver using the concept shown in FIG. 3, the data sampling circuit can be used to output the preset bit form as the sampling result of the end state of the vector signal, that is, the turn used by the transmitter end. The state-enforced coding algorithm can force the end state of the vector signal to have the preset bit form, such that the end state of the vector signal can be correctly recreated at the receiver end using the same transitional forced coding algorithm.

In the above embodiment, each of the vector signals s[m-1]-s[0] may have a binary voltage level signal to represent a logical value of 0 or a logical value of 1, or a vector signal s Each of [m-1]-s[0] may be a multi-level signal, such as a voltage signal having more than two voltage levels. Figure 18 is a schematic diagram of a multilevel vector signal according to an embodiment of the present invention. A vector signal implemented using a multilevel signal can perform a forced encoding in an analog domain (e.g., a voltage domain), for example, The encoder 112 and the decoder 124 are omitted, and each bit in the binary data b[n-1:0] can be forced/decoded by using a particular combination of voltage levels possessed by the multilevel signal.

Moreover, the multilevel vector signal can be used to reduce the number of pins of the transfer interface and/or carry more data. For example, the multilevel can be used in different pins DP and DN to define the level transition. As shown in Figure 19.

As shown in Fig. 2, the vector signals s[2], s[1] and s[0] are respectively obtained from the parallel channels by the transition state forced code receiver. However, when a plurality of transitions occur between the current state in which the current transfer clock cycle is in memory and the next state in which the next transfer clock cycle memory is present, a specific factor may cause the plurality of transition states to time each other. not aligned. The time difference between the plurality of transition states is referred to as a deviation between different vector signals or a coding jitter caused by a multi-level transition. When the delay time D used by the delay linear circuit 402 is insufficient to hide the code jitter, the sampling time TS defined by the trigger clock generated by the transition detection circuit 404 to the data sampling circuit 406 will encounter undesired short-term pulse interference. Figure 20 shows a situation in which the trigger clock encounters short-term pulse wave interference due to the short delay time D. Suppose there are three vector signals AB, BC, and CA. Therefore, according to the embodiment of the transition detection circuit shown in FIG. 6, the vector signals AB, BC and CA and the corresponding delay vector signals AB_D, BC_D and CA_D are used to generate a trigger clock defining the sampling time TS. However, in this case, the delay time D length supplied to the vector signals AB, BC, and CA is insufficient. Therefore, the trigger clock encounters glitches and provides an incorrect sampling time TS.

Conversely, if the delay time D used by the delay line circuit 402 is reasonably set, the sampling time TS defined by the trigger clock generated by the transition detecting circuit 404 to the data sampling circuit 406 will not suffer from glitch. Figure 21 shows a situation in which the trigger clock does not encounter short-term pulse wave interference due to a reasonably configured delay time D. Since the delay time D length supplied to the vector signals AB, BC, and CA is sufficiently long, the combinational logic of the transition detection circuit 404 will not generate glitches.

To prevent the trigger clock from encountering glitches, the present invention uses a phase or time offset de-skew mechanism to minimize or eliminate the time difference (i.e., code jitter) between multiple transitions of different vector signals. Figure 22 illustrates a sample vector signal using a sample time determined from a phase or time offset compensated vector signal, in accordance with one embodiment of the present invention. Assuming that m=3, the vector signals s[2], s[1], and s[0] are respectively obtained from the parallel channels by the transition state forced code receiver. Regarding the generation of the sampling time, the vector signals s[2], s[1] and s[0] are respectively compensated by the phase or time offset to generate the vector signal s[2:0]' compensated by the phase or time offset. As shown in FIG. 22, when a plurality of transition states occur between the current state of the memory in the current transfer clock cycle and the next state of the memory in the next transfer clock cycle, the phase or time offset compensation mechanism is used. The plurality of transition states are aligned with each other. As previously mentioned, the transition state forced code receiver causes at least one transition to always occur between adjacent states of the vector signal. The last transition between adjacent states can be detected (eg, around the edge of a transmission clock cycle). If only one transition occurs between adjacent states of the vector signal, the detected transition is considered to be the last transition. If a plurality of transition states occur between adjacent states of the vector signal, any one of the plurality of transition states that are detected to be aligned with each other is regarded as the last transition state. The time of the detected last transition state may be extended from the preset delay time D to the received vector signal s[2], s[1] and one sampling time of s[0]. As shown by the eye diagram of the phase or time offset compensated vector signal s[2:0]', the signal level from the last transition state of the current state to the first transition state of the next state is stable and clean. In addition, since the sampling time is taken from the vector signal s[2:0]' after phase or time offset compensation, the sampling time of the received vector signals s[2], s[1] and s[0] is not short. Pulse wave interference. Therefore, a plurality of data bits representing a state of the vector signals s[2], s[1], and s[0] can be recovered by a sampling time determined directly by a delay of the detected last transition state. The final transition is detected between adjacent states of the vector signal s[2:0] ' after phase or time offset compensation.

In some embodiments, the delay line circuit in the transition state forced code receiver can also function as a phase or time offset compensation circuit. That is, the phase or time offset compensation function can be obtained by controlling the delay time of different test vector signals received by the transition state forced code receiver. More detailed details of the phase or time offset compensation design will be presented later.

Figure 23 shows a transitional forced code receiver including offset calibration in accordance with a ninth embodiment of the present invention. The receiver 122 shown in Fig. 1 can be replaced with the transition state forced code receiver 2300 shown in Fig. 23. The transition state forced code receiver 2300 includes a deviation calibration circuit 2302, a delay line circuit 2304, a transition state detection circuit 404, and a data sampling circuit 406. It is to be noted that Fig. 23 only shows circuit elements related to the present invention. In a practical application, the transition state forced code receiver 2300 can include other additional circuit elements. For example, the transition state forced code receiver 2300 can include at least one deserializer for processing the output of the data sampling circuit 406.

In the present embodiment, the offset calibration circuit 2302 is configured to set the calibrated delay setting DS in the calibration mode. The delay line circuit 2304 delays the plurality of vector signals s[m-1], s[m-2] ... s[0], respectively, in the normal mode using the calibration delay settings (which may include a plurality of different delay times) A plurality of delayed vector signals s[m-1]_D, s[m-2]_D ... s[0]_D are generated. Wherein, in the normal mode, the delay of the transition state of the different delay vector signals is reduced by the post-calibration delay setting. Unlike the aforementioned delay line circuit 402, which uses the same delay time D for all vector signals, the delay line circuit 2304 uses different delay times for different vector signals, whereby the deviation of different vector signals is minimized or eliminated. . Further, the delay time D required to set the sampling time TS without using clock and data recovery can also be used to set the calibrated delay setting DS. That is, the calibrated delay setting DS used by the delay line circuit 2304 can have both a clockless and data recovery sampling time setting function and a phase or time offset compensation function.

Fig. 24 shows an embodiment of the data sampling operation performed by the transition state forced code receiver 2300 of Fig. 23. The transition state forced code receiver 2300 can be configured in accordance with the concept shown in FIG. The vector signal s[m-1]_D, s[m-2]_D ... s[0]_D is a phase or time offset compensation and a delayed vector signal. The transition detection circuit 404 detects the vector signal s[m-1]_D, s[m-2]_D ... s[0]_D to find the last transition between adjacent states. Due to the delayed vector s[m-1]_D, s[m-2]_D ... s[0]_D is compensated by the phase or time offset, which may be a transition state or a plurality of aligned transition states. Any of them depends on the number of transitions that occur between adjacent states. Furthermore, at least one of the delayed vector signals s[m-1]_D, s[m-2]_D ... s[0]_D occupies the last transition state equal to at least one of the phase or time offset compensated vector signals The delay in the time of the last transition. Therefore, the time of the last transition state occupied by at least one of the delayed vector signals s[m-1]_D, s[m-2]_D ... s[0]_D can be directly used as the sampling time TS of the data sampling circuit 406. The data sampling circuit 406 is configured to acquire sampling data from the vector signal s[m-1]-s[0].

In a first exemplary design, the delay line circuit 2304 shown in FIG. 23 can be reused in the calibration mode to provide a signal that needs to be subjected to the offset calibration by the offset calibration circuit 2302. Please also refer to Figure 25 and Figure 26. Fig. 25 shows a circuit which can simultaneously realize the delay line circuit 2304, the state transition detecting circuit 404, and the data sampling circuit 406 of Fig. 23. Fig. 26 shows a circuit which can realize the deviation calibration circuit of Fig. 23. When the transition state forced code receiver 2300 operates in the normal mode, the delay line circuit 2304, the transition state detection circuit 404, and the data sampling circuit 406 are enabled, and the offset calibration circuit 2302 is disabled. When the transition state forced code receiver 2300 is operating in the calibration mode, the transition detection circuit 404 and the data sampling circuit 406 are disabled, and the offset calibration circuit 2302 and the delay line circuit 2304 are enabled. Therefore, delay line circuit 2304 is used in both normal and calibration modes. Delay line circuit 2304 includes a plurality of delay lines 25020-2502m-1. The delay line 25020-2502m-1 is used in the normal mode according to the vector signal s[0]-s[m-1] (normal vector transmitted from the corresponding transition state forced encoding transmitter in the normal mode) Signal) and calibration setting DS (including multiple delay times Dm-1-D0 set in the calibration mode, Dm-1-D0 may be different from each other) to generate the delayed vector signal s[0]_D-s[m- 1]_D is given to the subsequent transition detection circuit 404. The delay line 25020-2502m-1 is also used in the calibration mode for the vector signal s[m-1]-s[0] (the test vector signal transmitted from the corresponding transition state forced code transmitter in calibration mode) Each of them provides a plurality of delayed vector signals s[m-1]_D[n:0], s[m-2]_D[n:0] ...s[0]_D[n:0]. For example, when operating in a calibration mode, each delay line (eg, 2502m-1) uses a different amount of unit delay for the input test signal (eg, s[m-1]) to generate a delayed test vector signal (eg, , s[m-1]_D[n]... s[m-1]_D[0]), each unit delay is provided by a delay unit in the delay line, and the series delay unit is passed according to each test vector signal The number of units determines the number of unit delays applied to the test vector signal. Thus, for the same test vector signal (eg, s[m-1]), the delayed multiple test vector signals (eg, s[m-1]_D[n]... s[m-1]_D[0 ]) has different delay times. The delayed plurality of test vector signals s[m-1]_D[n]...s[m-1]_D[0] are supplied to the deviation calibration circuit 2302 for subsequent processing.

As shown in FIG. 26, the offset calibration circuit 2302 includes a Time-to-Digital Converter (TDC) 2602 and a calibration state machine 2604. The time-to-digital converter is a processing circuit for testing a plurality of time differences in a calibration mode, each time difference being a time difference between any two of the received plurality of test signals s[0]-s[m-1]. The time difference obtained for each measurement is indicated by a time-to-digital converter code consisting of sample bits [n:0]. The calibration state machine 2604 is a processing circuit for determining a calibrated delay setting DS based on the time difference (indicated by the time-to-digital converter code measured by the time-to-digital converter 2602) (including being applied to receive in normal mode) The multiple delay times of the normal vector s[0]-s[m-1] are Dm-1-D0). For example, assume that the test vector signal s[0]-s[m-1] includes s[0], s[1] and s[2] (m=3), and the time-to-bit converter 2602 is used to measure s[0 The time difference TD0-2 between s[2], the time difference TD0-1 between s[0] and s[1], and the time difference TD1-2 between s[1] and s[2]. The calibration state machine 2604 determines the calibrated delay setting DS based at least on the time differences TD0-2, TD0-1, and TD1-2.

Furthermore, the test vector s[0]-s[m-1] received in the calibration mode should be suitably set so that only two occurrences between adjacent states of the test vector signal s[0]-s[m-1] A change of state. In one embodiment, the transition state forced code receiver 2300 receives the test vector signal s generated by the transition state forced code transmitter (eg, the transmitter 114 shown in FIG. 1) according to a preset calibration pattern. 0]-s[m-1]. It is assumed that the transitional forced code receiver 2300 is used in an interface that follows the Mobile Industry Processor Interface (MIPI) C-PHY specification. The predetermined calibration mode can be the worst skew pattern used to induce the maximum switching jitter. For example, as shown in FIG. 27, the predetermined calibration mode can be set by a string of "2" symbols (which are double-transitions) in accordance with the MIPI C-PHY specification. As another example, as shown in FIG. 28, the predetermined calibration mode can be set by a string of "4" symbols (which are double transition symbols) in accordance with the MIPI C-PHY specification.

Assume that the test vector signal s[0]-s[m-1] includes s[0], s[1] and s[2] (m=3). In the first calibration phase, the test vector signal s[0]-s[2] is reasonably set so that only two transition states occur between every two adjacent states of the test vector signals s[0] and s[1], and There is no transition in the test vector s[2]. Furthermore, the time-to-digital converter 2602 is controlled to obtain the measurement time difference between s[0] and s[1] using a single measurement result or an average of multiple measurement results. TD0-1 (ie, code jitter). In the second calibration phase, the test vector signal s[0]-s[2] is reasonably set so that only two transition states occur between every two adjacent states of the test vector signals s[0] and s[2], and There is no transition in the test vector s[1], and in addition, the time-to-digital converter 2602 is controlled to obtain a measurement time difference between s[0] and s[2] using a single measurement result or an average of a plurality of measurement results. TD0-2 (ie, code jitter). In the third calibration phase, the test vector signal s[0]-s[2] is reasonably set so that only two transition states occur between every two adjacent states of the test vector signals s[1] and s[2], and There is no transition in the test vector s[0]. Furthermore, the time-to-digital converter 2602 is controlled to obtain the measurement time difference between s[1] and s[2] using a single measurement result or an average of multiple measurement results. TD1-2 (ie, code jitter). It should be noted that the measurement order of the time differences TD0-1, TD0-2, and TD1-2 can be adjusted according to actual design considerations.

As shown in FIG. 26, the time-to-digital converter 2602 includes a plurality of multiplexers (MUXes) 2612, 2614 and sampling circuits (e.g., D-type flip-flops) 2616. The multiplexer 2612 selects the delayed test vector signal of the first test vector signal (ie, one of s[m-1], s[m-2]...s[0]) (ie, s[m- 1] _D[n:0], s[m-2]_D[n:0]... s[0]_D[n:0]), and output the selected delayed test vector signal to the sampling circuit 2616 (in particular, the data registration node output to the sampling circuit 2616). The multiplexer 2614 selects the second test vector signal (ie, s[m-1], the other of s[m-2]...s[0]), and outputs the selected second test vector signal to Sampling circuit 2616 (in particular, a clock input node that is output to sampling circuit 2616). When triggered by the second test vector signal, the sampling circuit 2616 measures the first test vector signal and the second test by sampling the delayed test vector signal of the first test vector signal The time difference of the vector signal to produce a time-to-digital converter code consisting of sample bits D[n:0]. Figure 29 illustrates an embodiment of a time-to-digital converter and delay line cooperative operation to obtain time-to-digital conversion, in accordance with one embodiment of the present invention. Assume that the time-to-digital converter 2602 is required to measure the time difference between the first test vector signal (eg, s[0]) and the second test vector signal (eg, s[1]) during a calibration phase, wherein During the calibration phase, the first test vector signal s[0] and the second test vector signal s[1] have transitions between every two states. A delay line can include a plurality of delay cells connected in series, wherein each delay cell can provide a unit delay to the first test vector signal s[0]. Therefore, the delayed test vector signals s[0]_D[0], s[0]_D[1]...s[0]_D[n] are respectively generated by the output nodes of the series delay units. The sampling circuit of the time-digital converter may include a plurality of D-type flip-flops, and each D-type flip-flop has multiple input nodes (for example, data login node D, clock input node C, and re-determined input node) And multiple output nodes (eg, data output node Q and inverted data output node) ). The delayed test vector signal s[0]_D[0], s[0]_D[1]...s[0]_D[n] is sent to the data entry node of the D-type trigger. Furthermore, the second test vector signal s[1] is fed to the clock input node of the D-type flip-flop, and the sample bit D[0]_D[n] is generated by the data output node of the D-type flip-flop.

Figure 30 illustrates an embodiment of performing a time-to-digital conversion to measure the time difference of two test vector signals, in accordance with one embodiment of the present invention. When the transition state of the second test vector signal s[1] occurs, the delayed test vector signal s[0]_D[0], s[0]_D[1]...s[0]_D [n] performs sampling to generate a time-to-digital converter code composed of sampling bits D[0], D[1]... D[n], wherein the digit 1's included in the time-to-digital converter code indicates the said The time difference between a test vector signal s[0] and a second test vector signal s[1]. With appropriate selection of multiplexers 2612 and 2614, time-to-digital converter 2602 can obtain the time difference of any two of the test vector signals s[0]-s[m-1].

When the calibration state machine 2604 knows the time difference of the test vector signal s[0]-s[m-1], the actual deviation condition of the test vector signal s[0]-s[m-1] can be easily known. In the normal mode, the calibration state machine 2604 determines the calibration that the delay line circuit 2304 can use based on the actual deviation condition of the test vector signal s[0]-s[m-1] and the delay time D for setting the sampling time TS. The DS is delayed, thereby obtaining a sampling time setting without clock data recovery and a vector signal for eliminating the deviation.

In a second exemplary design, delay line circuit 2304 in FIG. 23 may be reused in calibration mode to provide the signals required by deviation calibration circuit 2302 to perform offset calibration. When the transition state forced code receiver 2300 operates in the normal mode, the delay line circuit 2304, the transition state detection circuit 404, and the data sampling circuit 406 are enabled, and the offset calibration circuit 2302 is disabled. When the transition state forced code receiver 2300 operates in the calibration mode, the delay line circuit 2304, the transition state detection circuit 404, and the data sampling circuit 406 are disabled, and the offset calibration circuit 2302 is enabled. Therefore, the delay line circuit 2304 is only used in the normal mode. To obtain the delayed signal required for the offset calibration, the offset calibration circuit 2302 can be configured to include a replica delay line therein.

Fig. 31 shows an embodiment of an alternative circuit of the offset calibration circuit 2302 shown in Fig. 23. The main difference between the circuit design shown in FIG. 26 and FIG. 31 is that the circuit design of FIG. 31 includes a replica delay line 3114 coupled between the multiplexer 3112 of the time-to-digital converter 3102 and the sampling circuit 2616. When the offset calibration circuit 2302 is replaced by the replacement circuit shown in FIG. 31, the delay line circuit 2304 can be replaced with a delay line 25020-2502m-1 that operates only in the normal mode. Therefore, the delay line 25020-2502m-1 of the delay line circuit 2304 is not used in the calibration mode to provide the delayed test signal s[0]_D[n:0]-s[m-1]_D[n :0]. For example, when one of the test vector signals s[0]-s[m-1] is selected by the multiplexer 3112, the replica delay line 3114 delays the selected test vector signal to produce a test that is compared to the selection. The vector signal has a plurality of delayed test vector signals c[n:0] having different delay times. For example, when the selected test vector signal is s[0], the delayed test vector signal c[n:0] is s[0]_D[n:0]; when the selected test vector signal is s[m-1 ], the delayed test vector signal c[n:0] is s[m-1]_D[n:0]; when the selected test vector signal is s[m-2], the delayed test vector signal c[ n:0] is s[m-2]_D[n:0]. After reasonable selection by the multiplexers 3112 and 2614, the time difference of any two test vector signals in the test vector signal s[0]-s[m-1] can be obtained using the time-to-digital converter 3102 shown in FIG. .

Similarly, when the calibration state machine 2604 knows the time difference of the test vector signal s[0]-s[m-1], the actual deviation of the test vector signal s[0]-s[m-1] can be Easy to know. In the normal mode, the calibration state machine 2604 determines the calibration that the delay line circuit 2304 can use based on the actual deviation condition of the test vector signal s[0]-s[m-1] and the delay time D for setting the sampling time TS. The DS is delayed, thereby obtaining a sampling time setting without clock data recovery and a vector signal for eliminating the deviation.

The offset calibration circuit 2302 is used to appropriately set the calibrated delay setting DS in the calibration mode, and the delay line circuit using the calibrated delay setting DS in the normal mode can function as a cancellation bias circuit to minimize or eliminate the normal mode. The deviation of the received vector signal. The same inventive concept can also be applied to other transitional forced code receivers.

Figure 32 shows a transition state forced code receiver including a deviation calibration function in accordance with a tenth embodiment of the present invention. The transition state forced code receiver 3200 can be formed by adding a deviation calibration circuit 2302 to the transition state forced code receiver architecture shown in FIG. 10, wherein in the normal mode, the delay line circuit 3202 uses the calibrated delay setting DS. To obtain the sampling time setting without clock data recovery and the vector signal for eliminating the deviation.

In the foregoing embodiment, in the normal mode, the calibration state machine 2604 determines that it can be determined based on the actual deviation condition of the test vector signal s[0]-s[m-1] and the delay time D for setting the sampling time TS. The calibrated delay setting DS used by the delay line circuit 2304/3202, thereby obtaining a sampling time setting without clock data recovery and a vector signal for eliminating the deviation. However, this is merely an exemplification and is not intended to limit the invention. Alternatively, in the normal mode, the calibration state machine 2604 can determine the calibrated delay setting DS that can be used by the delay line circuit based only on the actual deviation condition of the test vector signal s[0]-s[m-1]. This alternative design is still within the scope of the invention.

Figure 33 shows an escrow forced code receiver including a deviation calibration function in accordance with an eleventh embodiment of the present invention. The transition forced code receiver 3300 can be formed by adding a deviation calibration circuit 2302 to the transition state forced code receiver architecture shown in FIG. 15, wherein in the normal mode, the delay line circuit 3302 uses the calibrated delay setting DS. To obtain the sampling time setting without clock data recovery and the vector signal for eliminating the deviation.

Figure 34 shows a transition state forced code receiver including a deviation calibration function in accordance with a twelfth embodiment of the present invention. The transition state forced code receiver 3400 can be formed by adding a deviation calibration circuit 2302 to the transition state forced code receiver architecture shown in FIG. 16, wherein in the normal mode, the delay line circuit 3402 uses the calibrated delay setting DS. To obtain the sampling time setting without clock data recovery and the vector signal for eliminating the deviation.

Figure 35 shows a transition state forced code receiver including a deviation calibration function in accordance with a thirteenth embodiment of the present invention. The transition forced code receiver 3500 can be formed by adding a deviation calibration circuit 2302 to the transition state forced code receiver architecture shown in FIG. 17, wherein in the normal mode, the delay line circuit 3502 uses the calibrated delay setting DS. To obtain the sampling time setting without clock data recovery and the vector signal for eliminating the deviation.

Portions of the described apparatus and techniques of the present invention may be used independently, or in combination, or in other ways not previously described herein, and thus, the invention is not limited to the components described above or illustrated in the drawings. Application or arrangement. For example, the components described in one embodiment can also be combined in any manner with the components described in the other embodiments.

The use of ordinal numbers such as "first," "second," etc., used to modify elements in the scope of the claims is not intended to suggest any priority, prioritization, or It is only used as an identifier to distinguish different components with the same name (with different ordinal numbers).

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of protection of the invention is subject to the definition of the scope of the patent application. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Communication system
10‧‧‧First chip
104‧‧‧second chip
112‧‧‧Encoder
114‧‧‧transmitter
122‧‧‧ Receiver
124‧‧‧Decoder
400,700,1000,1100,1400,1500,1600,1700,2300,3200,3300,3400,3500‧‧‧Transitive forced code receiver
402,702,1404,1502,1506,2304,3202,3302,3402,3502‧‧‧ delay line circuit
404, 704, 1402, 1504‧‧‧Transient detection circuit
406,706,1006,1106,1406,1508‧‧‧ data sampling circuit
604 ₀ -604 _m-1 ‧‧‧ logic gate
_{608 0 -608 m-1, 1008} 0 -1008 m-1, 1009 0 -1009 m-1 ‧‧‧ data sampler
1002, 1102‧‧ ‧ crossover
1003, 1103‧‧‧First data sampling group
1004, 1104‧‧‧Second data sampling group
2302‧‧‧ Deviation calibration circuit
2602, 3102‧‧‧Time-Digital Converter
2612, 2614, 3112‧‧‧ multiplexers
2616‧‧‧D type trigger
2604‧‧‧calibration state machine
3114‧‧‧Copy delay line

Figure 1 is a schematic illustration of a communication system in accordance with one embodiment of the present invention. 2 is a first conceptual diagram of a sample vector signal recovered without using conventional clock data, in accordance with one embodiment of the present invention. Figure 3 is a second conceptual diagram of a sample vector signal recovered without the use of conventional clock data, in accordance with one embodiment of the present invention. Figure 4 is a schematic diagram of a transition state forced code receiver in accordance with a first embodiment of the present invention. Fig. 5 is a diagram showing an example of a data sampling operation performed by the transition state forced code receiver shown in Fig. 4. Fig. 6 is a schematic diagram showing the circuit implementation of the transition state forced code receiver shown in Fig. 4. Figure 7 is a schematic diagram of a transition state forced code receiver in accordance with a second embodiment of the present invention. Fig. 8 is a diagram showing an example of a data sampling operation performed by the transition state forced code receiver shown in Fig. 7. Figure 9 is a schematic diagram showing the circuit implementation of the transition state forced code receiver shown in Figure 7. Figure 10 is a schematic diagram of a transition state forced code receiver in accordance with a third embodiment of the present invention. Figure 11 is a diagram showing a transition state forced code receiver according to a fourth embodiment of the present invention. Fig. 12 is a schematic diagram showing the circuit implementation of the frequency divider and the data sampling circuit shown in Fig. 10. Figure 13 is a schematic diagram showing the circuit implementation of the frequency divider and data sampling circuit shown in Figure 11. Figure 14 is a diagram showing a transition state forced code receiver according to a fifth embodiment of the present invention. Figure 15 is a diagram showing a transition state forced code receiver according to a sixth embodiment of the present invention. Figure 16 is a diagram showing a transition state forced code receiver according to a seventh embodiment of the present invention. Figure 17 is a diagram showing a transition state forced code receiver according to an eighth embodiment of the present invention. Figure 18 is a schematic diagram of a multilevel vector signal in accordance with an embodiment of the present invention. Figure 19 is a schematic illustration of level transitions defined by multilevel signals transmitted through different pins, in accordance with an embodiment of the present invention. Figure 20 shows a situation in which the trigger clock encounters short-term pulse wave interference due to the short delay time D. Figure 21 shows a situation in which the trigger clock does not encounter short-term pulse wave interference due to a reasonably configured delay time D. Figure 22 illustrates a sample vector signal using a sample time determined from a phase or time offset compensated vector signal, in accordance with one embodiment of the present invention. Figure 23 shows a transitional forced code receiver including offset calibration in accordance with a ninth embodiment of the present invention. Fig. 24 shows an embodiment of the data sampling operation performed by the transition state forced code receiver 2300 of Fig. 23. Fig. 25 shows a circuit which can simultaneously realize the delay line circuit 2304, the state transition detecting circuit 404, and the data sampling circuit 406 of Fig. 23. Fig. 26 shows a circuit which can realize the deviation calibration circuit of Fig. 23. Figure 27 shows a string of "2" symbols (which are double-transition symbols) in accordance with the MIPI C-PHY specification. Figure 28 shows a string of "4" symbols (which are double-transition symbols) in accordance with the MIPI C-PHY specification. Figure 29 illustrates an embodiment of a time-to-digital converter and delay line cooperative operation to obtain time-to-digital conversion, in accordance with one embodiment of the present invention. Figure 30 illustrates an embodiment of performing a time-to-digital conversion to measure the time difference of two test vector signals, in accordance with one embodiment of the present invention. Fig. 31 shows an embodiment of an alternative circuit of the offset calibration circuit 2302 shown in Fig. 23. Figure 32 shows a transition state forced code receiver including a deviation calibration function in accordance with a tenth embodiment of the present invention. Figure 33 shows an escrow forced code receiver including a deviation calibration function in accordance with an eleventh embodiment of the present invention. Figure 34 shows a transition state forced code receiver including a deviation calibration function in accordance with a twelfth embodiment of the present invention. Figure 35 shows a transition state forced code receiver including a deviation calibration function in accordance with a thirteenth embodiment of the present invention.

Claims (20)

A transition state forced code receiver comprising: a delay line circuit for delaying a plurality of vector signals using a calibrated delay setting to generate a plurality of delayed vector signals in a normal mode; a transition detection circuit, And a data sampling circuit, configured to sample the plurality of vector signals according to a sampling time, wherein the sampling The time is determined according to the output of the transition detection circuit; and the offset calibration circuit is configured to set the adjusted delay setting in the calibration mode; wherein, in the normal mode, the vector signals after different delays The transition deviation is reduced by the calibrated delay setting. The transition state forced code receiver as described in claim 1 of the patent application determines the sampling time without using clock data recovery. The transition state forced code receiver as described in claim 1, wherein the calibrated delay setting includes different delay times, the delay line circuits respectively using different delay times for different vector signals. The transition state mandatory code receiver according to claim 1, wherein the deviation calibration circuit comprises: a time-digital converter for measuring a plurality of time differences in the calibration mode, wherein each time difference is every two a time difference between the test vector signals; and a calibration state machine for determining the calibrated delay setting based on the time difference measured by the time-to-digital converter. The transition state forced code receiver of claim 4, wherein the delay line circuit is reused in the calibration mode to delay each of the test vector signals to generate a plurality of delayed test vector signals. The plurality of delayed test vector signals have different delay times than the test vector signals; after the time-digital converter is triggered by the second test signal, the first test vector signal is passed The delayed test vector signal is sampled to measure the time difference between the first test vector signal and the second test vector signal. The transition state mandatory code receiver according to claim 4, wherein the deviation calibration circuit further comprises: a delay line for delaying each test vector signal to generate a plurality of delayed test vector signals, The delayed test vector signal has a different delay time than the test vector signal; after the time-digital converter is triggered by the second test signal, by delaying the first test vector signal The test vector signal is sampled to measure a time difference between the first test vector signal and the second test vector signal. The transition state forced code receiver as described in claim 4, wherein only two transition states occur between every two adjacent states of the test vector signal. The transition state forced code receiver according to claim 4, wherein the test vector signal generated by the transition state forced code transmitter is received according to a predetermined calibration mode. The transition state mandatory code receiver of claim 8, wherein the predetermined calibration mode is set by a set of "2" symbols in accordance with the mobile industry processor interface C-PHY specification. The transition state mandatory code receiver of claim 8, wherein the predetermined calibration mode is set by a set of "4" symbols in accordance with the mobile industry processor interface C-PHY specification. A receiving method for a transition state forced code receiver, comprising: performing a offset calibration in a calibration mode to set a calibrated delay setting; and in a normal mode, using a calibrated delay setting to delay a plurality of vector signals to respectively Generating a plurality of delayed vector signals, wherein, in the normal mode, a transition state deviation of the vector signals after different delays is reduced by the calibrated delay setting; detecting the plurality of delayed vector signals a transition state of the vector signal after a particular delay; sampling the plurality of vector signals according to a sampling time, wherein the sampling time is determined according to the transition detection output. As in the receiving method described in claim 11, the sampling time is determined without using clock data recovery. In the receiving method according to claim 11, the calibrated delay setting includes different delay times, and different delay times are respectively used for different vector signals. The receiving method according to claim 11, wherein the offset calibration comprises: performing a time-digital conversion to measure a plurality of time differences in the calibration mode, wherein each time difference is between every two test vector signals a time difference; and determining the adjusted delay setting based on the time difference obtained by the time-to-digital conversion measurement. The receiving method according to claim 14, wherein the delayed vector signal is generated by the delay line circuit delaying the vector signal according to the calibrated delay setting in the normal mode; the receiving method The method further includes: reusing the delay line circuit to delay each of the test vector signals to generate a plurality of delayed test vector signals in the calibration mode, the plurality of delayed test vector signals being compared to The test vector signal has a different delay time; the performing the time-digital conversion to measure the time difference comprises: after being triggered by the second test signal, performing the delayed test vector signal of the first test vector signal Sampling to measure a time difference between the first test vector signal and the second test vector signal. The receiving method of claim 14, wherein the offset calibration further comprises: delaying each test vector signal to generate a plurality of delayed test vector signals, wherein the plurality of delayed test vector signals are compared to The test vector signal has a different delay time; the performing the time-digital conversion to measure the time difference comprises: after being triggered by the second test signal, passing the delayed test vector signal of the first test vector signal Sampling is performed to measure a time difference between the first test vector signal and the second test vector signal. In the receiving method of claim 14, the two transition states occur between every two adjacent states of the test vector signal. The receiving method according to claim 14, wherein the test vector signal generated by the transition state forced code transmitter is received according to a predetermined calibration mode. The receiving method of claim 18, wherein the predetermined calibration mode is set by a set of "2" symbols in accordance with a mobile industry processor interface C-PHY specification. The receiving method of claim 18, wherein the predetermined calibration mode is set by a set of "4" symbols in accordance with a mobile industry processor interface C-PHY specification.