TW201818381A - Driving circuit for panel - Google Patents
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- TW201818381A TW201818381A TW105136959A TW105136959A TW201818381A TW 201818381 A TW201818381 A TW 201818381A TW 105136959 A TW105136959 A TW 105136959A TW 105136959 A TW105136959 A TW 105136959A TW 201818381 A TW201818381 A TW 201818381A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
Description
本發明係關於一種面板驅動電路，特別是一種針對阻抗調節的面板驅動電路。The invention relates to a panel driving circuit, in particular to a panel driving circuit for impedance adjustment.
隨著顯示面板的使用越來越普及，面板產業的技術也趨於成熟。然而顯示面板的內部運作仍存在一些缺陷。一般來說，顯示面板內部設置有時序控制器，通過差動信號線對，提供必要的信號至多個源極驅動晶片，用以顯示畫面。然而，由於位於時序控制器一端的阻抗與源極驅動晶片一端的阻抗不一致，導致時序控制器所提供的信號無法有效地傳遞至源極驅動晶片，且使時序控制器消耗過多的電能。因此，如何解決所述的差動信號線對之阻抗匹配的問題係一個重要的課題。As the use of display panels becomes more and more popular, the technology of the panel industry is also becoming mature. However, there are still some defects in the internal operation of the display panel. Generally, a timing controller is provided inside the display panel, and through a differential signal line pair, necessary signals are provided to a plurality of source driving chips for displaying a picture. However, because the impedance at one end of the timing controller is inconsistent with the impedance at one end of the source driver chip, the signals provided by the timing controller cannot be effectively transmitted to the source driver chip, and the timing controller consumes too much power. Therefore, how to solve the problem of impedance matching of the differential signal line pair is an important issue.
本發明提供一種面板驅動電路，可以自動地調節差動信號線對的終端阻抗，進而達到最佳化的阻抗匹配。The invention provides a panel driving circuit, which can automatically adjust the terminal impedance of a differential signal line pair, thereby achieving an optimal impedance matching.
依據本發明之一實施例揭露一種面板驅動電路，包含差動信號線對與阻抗調節電路。差動信號線對，包含第一信號傳輸線與第二信號傳輸線。第一信號傳輸線具有第一端、第二端與第一節點。第一信號傳輸線的第一端接收第一信號。第二信號傳輸線具有第一端、第二端與第二節點。第二信號傳輸線鄰近於第一信號傳輸線。第二信號傳輸線的第一端接收第二信號。其中第二節點係第二信號傳輸線上與第一節點距離最近的節點。阻抗調節電路分別電性連接第一節點與第二節點。阻抗調節電路依據第一信號與第二信號，調整第一節點與第二節點之間的阻抗值。According to an embodiment of the present invention, a panel driving circuit is disclosed, including a differential signal line pair and an impedance adjusting circuit. The differential signal line pair includes a first signal transmission line and a second signal transmission line. The first signal transmission line has a first end, a second end, and a first node. The first end of the first signal transmission line receives the first signal. The second signal transmission line has a first end, a second end, and a second node. The second signal transmission line is adjacent to the first signal transmission line. The first end of the second signal transmission line receives the second signal. The second node is the node closest to the first node on the second signal transmission line. The impedance adjustment circuit is electrically connected to the first node and the second node, respectively. The impedance adjustment circuit adjusts the impedance value between the first node and the second node according to the first signal and the second signal.
綜上所述，本發明的面板驅動電路，係藉由阻抗調節電路耦接於第一信號傳輸線的第一節點與第二信號傳輸線的第二節點，使得第一節點與第二節點之間的阻抗可以自動受到調節，從而達到最佳化的阻抗匹配。In summary, the panel driving circuit of the present invention is coupled to the first node of the first signal transmission line and the second node of the second signal transmission line through the impedance adjusting circuit, so that the The impedance can be adjusted automatically to achieve an optimal impedance match.
以上之關於本揭露內容之說明及以下之實施方式之說明係用以示範與解釋本發明之精神與原理，並且提供本發明之專利申請範圍更進一步之解釋。The above description of the contents of this disclosure and the description of the following embodiments are used to demonstrate and explain the spirit and principle of the present invention, and provide a further explanation of the scope of the patent application of the present invention.
以下在實施方式中詳細敘述本發明之詳細特徵以及優點，其內容足以使任何熟習相關技藝者了解本發明之技術內容並據以實施，且根據本說明書所揭露之內容、申請專利範圍及圖式，任何熟習相關技藝者可輕易地理解本發明相關之目的及優點。以下之實施例係進一步詳細說明本發明之觀點，但非以任何觀點限制本發明之範疇。The detailed features and advantages of the present invention are described in detail in the following embodiments. The content is sufficient for any person skilled in the art to understand and implement the technical content of the present invention, and according to the content disclosed in this specification, the scope of patent applications and the drawings. Anyone skilled in the relevant art can easily understand the related objects and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way.
請參照圖1，圖1係依據本發明之一實施例所繪示的顯示裝置的結構示意圖。如圖1所示，顯示裝置包含時序控制器1與面板2。面板2上設置有多個源極驅動電路S3~S6。根據一實施例，所述的時序控制器1係用以提供數位資料(例如 顯示色彩的資料)至源極驅動電路S3~S6，使得源極驅動電路S3~S6可以將所述的數位資料轉換成類比電壓，從而提供給面板2中的畫素單元，以進行畫面的顯示。如圖1的實施例所示，時序控制器1係過傳輸信號線對30~60，將數位資料分別地傳送至源極驅動電路S3~S6。本發明雖僅以源極驅動電路S3~S6作為舉例說明，然而，本發明不以上述源極驅動電路的數量為限。於此實施例中，傳輸信號線對30~60係為差動信號傳輸線對，其具有差動阻抗。每個源極驅動電路S3~S6中均具有面板驅動電路，可以用以調整差動信號線對的終端阻抗。Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in FIG. 1, the display device includes a timing controller 1 and a panel 2. The panel 2 is provided with a plurality of source driving circuits S3 to S6. According to an embodiment, the timing controller 1 is configured to provide digital data (such as data for displaying colors) to the source driving circuits S3 to S6, so that the source driving circuits S3 to S6 can convert the digital data. The analog voltage is provided to the pixel unit in the panel 2 for displaying the picture. As shown in the embodiment of FIG. 1, the timing controller 1 transmits the digital data to the source driving circuits S3 to S6 through the transmission signal line pairs 30 to 60, respectively. Although the present invention only uses source driving circuits S3 to S6 as examples, the present invention is not limited to the number of the above source driving circuits. In this embodiment, the transmission signal line pairs 30 to 60 are differential signal transmission line pairs, which have differential impedances. Each source driving circuit S3 ~ S6 has a panel driving circuit, which can be used to adjust the terminal impedance of the differential signal line pair.
請一併參照圖1與圖2，圖2係依據本發明之一實施例所繪示的面板偵測電路的電路架構圖。為了方便說明，圖2係以源極驅動電路S3中的面板偵測電路3的電路架構來舉例說明。如圖2所示，面板偵測電路3包含差動信號線對30與阻抗調節電路32。差動信號線對30包含第一信號傳輸線301與第二信號傳輸線302。第一信號傳輸線301具有第一端T1與第二端T2以及第一節點N1。第二信號傳輸線302具有第一端T3與第二端T4以及第二節點N2。第一信號傳輸線301的第一端T1接收第一信號SIG1。第二信號傳輸線302的第一端T3接收第二信號SIG2。第二信號傳輸線302鄰近於第一信號傳輸線301。於一實施例中，相互平行的第一信號傳輸線301與第二信號傳輸線302之間的線距大於等於2密耳(mil)。於一實施例中，如圖2所示，所述的第一信號SIG1與第二信號SIG2係來自於時序控制器1。時序控制器1具有第一端C1與第二端C2。時序控制器1的第一端C1電性連接第一信號傳輸線301的第一端T1，且通過第一信號傳輸線301提供第一信號SIG1。時序控制器1的第二端C2電性連接第二信號傳輸線302的第一端T3，且通過第二信號傳輸線302提供第二信號SIG1。於圖2的例子中，面板偵測電路3並未包含時序控制器1。於另一個例子中， 面板偵測電路3係包含了時序控制器1。Please refer to FIG. 1 and FIG. 2 together. FIG. 2 is a circuit architecture diagram of a panel detection circuit according to an embodiment of the present invention. For convenience of explanation, FIG. 2 illustrates the circuit structure of the panel detection circuit 3 in the source driving circuit S3 as an example. As shown in FIG. 2, the panel detection circuit 3 includes a differential signal line pair 30 and an impedance adjustment circuit 32. The differential signal line pair 30 includes a first signal transmission line 301 and a second signal transmission line 302. The first signal transmission line 301 has a first end T1 and a second end T2 and a first node N1. The second signal transmission line 302 has a first terminal T3 and a second terminal T4 and a second node N2. The first end T1 of the first signal transmission line 301 receives the first signal SIG1. A first end T3 of the second signal transmission line 302 receives a second signal SIG2. The second signal transmission line 302 is adjacent to the first signal transmission line 301. In one embodiment, a line distance between the first signal transmission line 301 and the second signal transmission line 302 that are parallel to each other is greater than or equal to 2 mils. In an embodiment, as shown in FIG. 2, the first signal SIG1 and the second signal SIG2 are from the timing controller 1. The timing controller 1 has a first terminal C1 and a second terminal C2. A first terminal C1 of the timing controller 1 is electrically connected to a first terminal T1 of the first signal transmission line 301, and a first signal SIG1 is provided through the first signal transmission line 301. The second terminal C2 of the timing controller 1 is electrically connected to the first terminal T3 of the second signal transmission line 302, and the second signal SIG1 is provided through the second signal transmission line 302. In the example in FIG. 2, the panel detection circuit 3 does not include the timing controller 1. In another example, the panel detection circuit 3 includes a timing controller 1.
阻抗調節電路32分別電性連接第一節點N1與第二節點N2。第二節點N2係為第二信號傳輸線302上與第一節點N1距離最近的節點。阻抗調節電路32依據第一信號SIG1與第二信號SIG2，調節第一節點N1與第二節點N2之間的阻抗值。具體來說，時序控制器1係為信號發送端，用以通過第一傳輸線301與第二傳輸線302發送出第一信號SIG1與第二信號SIG2至信號接收端的源極驅動電路S3，由於第一信號SIG1與第二信號SIG2係為差動信號，阻抗調節電路32可以根據該差動信號，自動地調整第一節點N1與第二節點N2之間的阻抗值，進而達到最佳化的阻抗匹配。The impedance adjustment circuit 32 is electrically connected to the first node N1 and the second node N2, respectively. The second node N2 is a node closest to the first node N1 on the second signal transmission line 302. The impedance adjustment circuit 32 adjusts the impedance value between the first node N1 and the second node N2 according to the first signal SIG1 and the second signal SIG2. Specifically, the timing controller 1 is a signal transmitting end, and is used to send the first signal SIG1 and the second signal SIG2 through the first transmission line 301 and the second transmission line 302 to the source driving circuit S3 of the signal receiving end. The signal SIG1 and the second signal SIG2 are differential signals, and the impedance adjustment circuit 32 can automatically adjust the impedance value between the first node N1 and the second node N2 according to the differential signal, thereby achieving an optimal impedance matching. .
請一併參照圖2與圖3，圖3係依據本發明 之一實施例所繪示的阻抗調節電路的電路架構圖。如圖3所示，阻抗調節電路32包含電阻3200、多個調變電阻3201~3204與切換電路320。電阻3200具有第一端與第二端，其第一端電性連接第一節點N1。每個調變電阻3201~3204具有第一端與第二端，其第二端電性連接第二節點N2。切換電路320電性連接電阻3200的第二端與每個調變電阻3201~3204的第一端以及第二節點N2。切換電路320依據第一信號SIG1與第二信號SIG2，選擇性地導通電阻3200的第二端至調變電阻3201~3204其中之一的第一端或第二節點N2的電流路徑。其中，調變電阻3201~3204均具有不同的阻抗值。Please refer to FIG. 2 and FIG. 3 together. FIG. 3 is a circuit architecture diagram of an impedance adjustment circuit according to an embodiment of the present invention. As shown in FIG. 3, the impedance adjustment circuit 32 includes a resistor 3200, a plurality of modulation resistors 3201 to 3204, and a switching circuit 320. The resistor 3200 has a first terminal and a second terminal, and the first terminal is electrically connected to the first node N1. Each of the modulation resistors 3201 to 3204 has a first terminal and a second terminal, and the second terminal is electrically connected to the second node N2. The switching circuit 320 is electrically connected to the second terminal of the resistor 3200 and the first terminal of each of the modulation resistors 3201 to 3204 and the second node N2. The switching circuit 320 selectively conducts the current path from the second terminal of the resistor 3200 to the first terminal of one of the modulation resistors 3201 to 3204 or the second node N2 according to the first signal SIG1 and the second signal SIG2. Among them, the modulation resistors 3201 to 3204 all have different impedance values.
具體來說，阻抗調節電路32可以通過切換電路320的切換，來導通其中一個的電流路徑，以達到所需的阻抗值來達到阻抗的匹配。於此實施例中，電阻3200的阻抗值為80歐姆，而調變電阻3201~3204的阻抗值分別為5歐姆、10歐姆、15歐姆與20歐姆。若以一個實際的例子來說，假設要達到阻抗匹配的的阻抗值為80歐姆，阻抗調節電路32中的切換電路320可以依據第一信號SIG1與第二信號SIG2，導通電阻3200的第二端至第二節點N2的電流路徑，如此一來，第一節點N1與第二節點N2之間的阻抗值被調節為80歐姆。又於另一個例子中，假設要達到阻抗匹配的阻抗值為85歐姆，阻抗調節電路32中的切換電路320可以依據第一信號SIG1與第二信號SIG2，導通電阻3200的第二端至調變電阻3201的第一端的電流路徑，進而使得第一節點N1與第二節點N2之間的阻抗值被調節為85歐姆，而達到阻抗的匹配。Specifically, the impedance adjustment circuit 32 can conduct the current path of one of them through the switching of the switching circuit 320 to achieve the required impedance value to achieve impedance matching. In this embodiment, the impedance value of the resistor 3200 is 80 ohms, and the impedance values of the modulation resistors 3201 to 3204 are 5 ohms, 10 ohms, 15 ohms, and 20 ohms, respectively. Taking a practical example, assuming that the impedance value to achieve impedance matching is 80 ohms, the switching circuit 320 in the impedance adjustment circuit 32 can turn on the second terminal of the resistance 3200 according to the first signal SIG1 and the second signal SIG2 The current path to the second node N2, so that the impedance value between the first node N1 and the second node N2 is adjusted to 80 ohms. In yet another example, assuming that the impedance value of the impedance matching is 85 ohms, the switching circuit 320 in the impedance adjustment circuit 32 can turn on the second end of the resistance 3200 to the modulation according to the first signal SIG1 and the second signal SIG2. The current path at the first end of the resistor 3201 further adjusts the impedance value between the first node N1 and the second node N2 to 85 ohms to achieve impedance matching.
請一併參照圖2與圖4，圖4係依據本發明 之另一實施例所繪示的阻抗調節電路的電路架構圖。如圖4所示，阻抗調節電路32包含電阻3220、多個調變電阻3221~3225與切換電路322。電阻3220具有第一端與第二端，其第一端電性連接第一節點N1。每個調變電阻3221~3225具有第一端與第二端，其第二端電性連接第二節點N2。切換電路322電性連接電阻3220的第二端與調變電阻3221~3225的第一端。切換電路322依據第一信號SIG1與第二信號SIG2，選擇性地導通電阻3220的第二端至調變電阻3221~3225至少其中之一的第一端的電流路徑。其中，部分的調變電阻3221~3225具有相同的阻抗值。Please refer to FIG. 2 and FIG. 4 together. FIG. 4 is a circuit architecture diagram of an impedance adjustment circuit according to another embodiment of the present invention. As shown in FIG. 4, the impedance adjustment circuit 32 includes a resistor 3220, a plurality of modulation resistors 3221 to 3225, and a switching circuit 322. The resistor 3220 has a first terminal and a second terminal, and the first terminal is electrically connected to the first node N1. Each modulation resistor 3221 ~ 3225 has a first terminal and a second terminal, and the second terminal is electrically connected to the second node N2. The switching circuit 322 is electrically connected to the second terminal of the resistor 3220 and the first terminals of the modulation resistors 3221 to 3225. The switching circuit 322 selectively turns on the current path from the second terminal of the resistor 3220 to the first terminal of at least one of the modulation resistors 3221 to 3225 according to the first signal SIG1 and the second signal SIG2. Among them, some of the modulation resistors 3221 ~ 3225 have the same impedance value.
於此實施例中，電阻3220與調變電阻3221的阻抗值分別為80歐姆與60歐姆，而調變電阻3222~3225均為20歐姆。相較於前述的圖3的實施例僅係導通單一電流路徑，於圖4的實施例中，切換電路322可以選擇導通一個或多個電流路徑，以達到阻抗的匹配。舉例來說，若假設要達到阻抗匹配所需要的阻抗值為100歐姆，切換電路322可以導通電阻3220至調變電阻3222~3225其中一個的電流路徑，便可以使得第一節點N1與第二節點N2之間的阻抗值被調節為100歐姆而達到阻抗匹配。於另一個例子中，假設要達到阻抗匹配所需要的阻抗值為95歐姆，切換電路322可以導通電阻3220至調變電阻3221的電流路徑，並且導通電阻3220至調變電阻3222~3225其中一個的電流路徑，進而使的第一節點N1與第二節點N2之間的阻抗值被調節為95歐姆而達到阻抗匹配。In this embodiment, the resistance values of the resistor 3220 and the modulation resistor 3221 are 80 ohms and 60 ohms, respectively, and the modulation resistors 3222 to 3225 are 20 ohms. Compared to the foregoing embodiment of FIG. 3, which only conducts a single current path, in the embodiment of FIG. 4, the switching circuit 322 may selectively conduct one or more current paths to achieve impedance matching. For example, if it is assumed that the impedance value required to achieve impedance matching is 100 ohms, the switching circuit 322 can turn on the current path of one of the resistors 3220 to 3222 ~ 3225, so that the first node N1 and the second node can be made. The impedance between N2 is adjusted to 100 ohms to achieve impedance matching. In another example, assuming that the impedance value required to achieve impedance matching is 95 ohms, the switching circuit 322 can turn on the current path from the resistor 3220 to the modulation resistor 3221, and the on-resistance of one of the resistors 3220 to 3222 ~ 3225 The current path further adjusts the impedance value between the first node N1 and the second node N2 to 95 ohms to achieve impedance matching.
請一併參照圖2與圖5，圖5係依據本發明之另一實施例所繪示的阻抗調節電路的電路架構圖。如圖5所示，阻抗調節電路32包含電阻3240、調變電阻3241~3244與切換電路324。電阻3240具有第一端與第二端，其第一端與第二端分別電性連接第一節點N1與第二節點N2。每個調變電阻3241~3244具有第一端與第二端，其第二端電性連接第二節點N2。切換電路324具有第一端與第二端，其第一端電性連接第一節點N1，其第二端電性連接調變電阻3241~3244的第一端。切換電路324依據第一信號SIG1與第二信號SIG2，選擇性地導通第一節點N1至該些第二調變電阻至少其中之一的第一端的電流路徑。其中，部分的調變電阻3241~3244具有相同的阻抗值。Please refer to FIG. 2 and FIG. 5 together. FIG. 5 is a circuit architecture diagram of an impedance adjustment circuit according to another embodiment of the present invention. As shown in FIG. 5, the impedance adjustment circuit 32 includes a resistor 3240, modulation resistors 3241 to 3244, and a switching circuit 324. The resistor 3240 has a first end and a second end, and the first end and the second end are electrically connected to the first node N1 and the second node N2, respectively. Each of the modulation resistors 3241 to 3244 has a first terminal and a second terminal, and the second terminal is electrically connected to the second node N2. The switching circuit 324 has a first terminal and a second terminal. The first terminal is electrically connected to the first node N1, and the second terminal is electrically connected to the first terminals of the modulation resistors 3241 to 3244. The switching circuit 324 selectively conducts the current path from the first node N1 to the first end of at least one of the second modulation resistors according to the first signal SIG1 and the second signal SIG2. Among them, some of the modulation resistors 3241 to 3244 have the same impedance value.
與前述實施例不同的是，於圖5的實施例的電路架構中，阻抗調節電路32具有電阻3240，電性連接於第一節點N1與第二節點N2。於一個例子中，電阻3240的阻抗值係為100歐姆，而調變電阻3241~3244的電阻值係為2千歐姆。於此實施例中，切換電路324可以依據第一信號SIG1與第二信號SIG2，隨機地導通第一節點N1與調變電阻3241~3244之間的電流路徑，以達成阻抗匹配。以一個實際例子來說，若要達到阻抗匹配所需要的阻抗值為95歐姆，切換電路324可以導通第一節點N1至調變電阻3241的第一端的電流路徑，藉此可以使得第一節點N1與第二節點N2的阻抗值被調節至大約95歐姆，進而達到阻抗的匹配。於另一個例子中，假設達到阻抗匹配所需要的阻抗值為90歐姆，切換電路324可以導通第一節點N1至調變電阻3241以及調變電阻3242的第一端的電流路徑，藉此第一節點N1與第二節點N2的阻抗值便可以調節成大約90歐姆。Different from the foregoing embodiment, in the circuit architecture of the embodiment of FIG. 5, the impedance adjusting circuit 32 has a resistance 3240 and is electrically connected to the first node N1 and the second node N2. In one example, the resistance value of the resistor 3240 is 100 ohms, and the resistance value of the modulation resistors 3241 to 3244 is 2 kiloohms. In this embodiment, the switching circuit 324 can randomly conduct the current path between the first node N1 and the modulation resistors 3241 to 3244 according to the first signal SIG1 and the second signal SIG2 to achieve impedance matching. For a practical example, if the impedance value required for impedance matching is 95 ohms, the switching circuit 324 can conduct a current path from the first node N1 to the first end of the modulation resistor 3241, thereby making the first node The impedance value of N1 and the second node N2 is adjusted to about 95 ohms, thereby achieving impedance matching. In another example, assuming that the impedance value required to achieve impedance matching is 90 ohms, the switching circuit 324 can conduct the current path from the first node N1 to the modulation resistor 3241 and the first end of the modulation resistor 3242, so that the first The impedance values of the node N1 and the second node N2 can be adjusted to about 90 ohms.
於前述圖5的實施例中，部分的調變電阻3241~3244具有相同的阻抗值。而於另一實施例中，在相同圖5的實施例的電路架構中，調變電阻3241~3244均具有不同的阻抗值。舉例來說，調變電阻3241~3244的電阻值分別為2千歐姆、1千歐姆、600歐姆與400歐姆，而電阻3240的阻抗值為100歐姆。在這個實施例中，切換電路324可以選擇性地導通第一節點N1至調變電阻3241~3244其中之一的第一端的電流路徑。以實際的例子來說，假設若要達到阻抗匹配的阻抗值為90歐姆，此時，切換電路324導通第一節點N1至調變電阻3242的電流路徑，便可以使得第一節點N1與第二節點N2之間的阻抗值被調節大約為90歐姆。若是要達到阻抗匹配的阻抗值為80歐姆，切換電路324導通第一節點N1至調變電阻3244的電流路徑，便可以使得第一節點N1與第二節點N2之間的阻抗值被調節為80歐姆。In the foregoing embodiment of FIG. 5, some of the modulation resistors 3241 to 3244 have the same impedance value. In another embodiment, in the same circuit structure as the embodiment in FIG. 5, the modulation resistors 3241 to 3244 have different impedance values. For example, the resistance values of the modulation resistors 3241 to 3244 are 2 kohm, 1 kohm, 600 ohm, and 400 ohm, respectively, and the resistance value of the resistor 3240 is 100 ohm. In this embodiment, the switching circuit 324 can selectively conduct a current path from the first node N1 to the first end of one of the modulation resistors 3241 to 3244. Taking a practical example, assuming that the impedance value of the impedance matching is 90 ohms, at this time, the switching circuit 324 conducts the current path from the first node N1 to the modulation resistor 3242, so that the first node N1 and the second node The impedance value between the nodes N2 is adjusted to about 90 ohms. If the impedance value of the impedance matching is 80 ohms, the switching circuit 324 conducts the current path from the first node N1 to the modulation resistor 3244, so that the impedance value between the first node N1 and the second node N2 can be adjusted to 80 ohm.
前述圖3至圖5的實施例係為阻抗調節電路32所具有之不同實施態樣。該些實施例皆可以通過切換電路的自動切換，使得第一節點N1與第二節點N2之間的阻抗可以在五段不同的阻抗值(也就是80歐姆、85歐姆、90歐姆、95歐姆、100歐姆)之間被調整。然而，前述實施例的阻抗值的調整僅係作為舉例說明，於其他實施例中，第一節點N1與第二節點之間阻抗可以調整為其他的阻抗值，本發明不以上述的實施例為限。由於顯示面板內部通常設置有多個源級驅動器，實際的線路佈局可能會有差異，而導致所需要的匹配阻抗值也不同。因此，通過本發明的面板驅動電路，可以依據線路佈局的不同，而個別調整阻抗值，使得整體的顯示裝置的阻抗可以達到最佳化，且降低時序控制器的驅動力而減少電能消耗。The foregoing embodiments of FIGS. 3 to 5 are different implementations of the impedance adjustment circuit 32. In these embodiments, the automatic switching of the switching circuit can make the impedance between the first node N1 and the second node N2 in five different impedance values (that is, 80 ohm, 85 ohm, 90 ohm, 95 ohm, 100 ohms). However, the adjustment of the impedance value in the foregoing embodiment is merely an example. In other embodiments, the impedance between the first node N1 and the second node may be adjusted to other impedance values. limit. Because multiple source drivers are usually set inside the display panel, the actual circuit layout may be different, which results in different matching impedance values. Therefore, through the panel driving circuit of the present invention, the impedance value can be adjusted individually according to different circuit layouts, so that the impedance of the overall display device can be optimized, and the driving force of the timing controller is reduced to reduce power consumption.
於一實施例中，如圖2所示，偵測電路34電性連接第一信號傳輸線301的第二端T2與第二信號傳輸線302的第二端T4。偵測電路34依據第一信號SIG1與第二信號SIG2，使阻抗調節電路32調整第一節點N1與第二節點N2之間的阻抗值。具體來說，偵測電路34係用以根據第一信號SIG1與第二信號SIG2，進而選擇性地通知阻抗調節電路32進行第一節點N1與第二節點N2之間的阻抗值調節。於一實施例中，如圖2所示，偵測電路34包含運算電路342、第一比較器344與第二比較器346。運算電路342包含電阻R1~R4。電阻R1與電阻R2的一端分別耦接運算放大器3420的輸入端，電阻R1與電阻R2的另一端分別接收第一信號SIG1與第二信號SIG2。運算電路342依據第一信號SIG1與第二信號SIG2，輸出第三信號SIG3。In an embodiment, as shown in FIG. 2, the detection circuit 34 is electrically connected to the second end T2 of the first signal transmission line 301 and the second end T4 of the second signal transmission line 302. The detection circuit 34 causes the impedance adjustment circuit 32 to adjust the impedance value between the first node N1 and the second node N2 according to the first signal SIG1 and the second signal SIG2. Specifically, the detection circuit 34 is configured to selectively notify the impedance adjustment circuit 32 to adjust the impedance value between the first node N1 and the second node N2 according to the first signal SIG1 and the second signal SIG2. In an embodiment, as shown in FIG. 2, the detection circuit 34 includes an operation circuit 342, a first comparator 344, and a second comparator 346. The arithmetic circuit 342 includes resistors R1 to R4. One ends of the resistors R1 and R2 are respectively coupled to the input ends of the operational amplifier 3420, and the other ends of the resistors R1 and R2 receive the first signal SIG1 and the second signal SIG2, respectively. The arithmetic circuit 342 outputs a third signal SIG3 according to the first signal SIG1 and the second signal SIG2.
於此實施例中，運算電路342係為一個減法器，其所輸出的第三信號SIG3的電位係等於第二信號SIG2與第一信號SIG1的電位差值。第一比較器344電性連接運算電路342。第一比較器344用以依據第三信號SIG3與參考電壓Vcm，選擇性產生高電位信號或低電位信號的比較結果。也就是說，當第三信號SIG3的電位大於參考電壓Vcm時，輸出一個高電位信號。反之，當第三信號SIG3的電位小於參考電壓Vcm時，輸出一個低電位信號。通過第一比較器344輸出的結果，阻抗調節電路32會自動地調整第一節點N1與第二節點N2之間的阻抗值，以達到最佳化的阻抗匹配。根據一實施例，阻抗調節電路32會循序地切換其阻抗值，並使第一比較器344循序比較第三信號SIG3與參考電壓Vcm之間的大小關係，讓阻抗調節電路32調整第一節點N1與第二節點N2之間的阻抗值，以達到最佳化的阻抗匹配。根據一實施例，通過循續性地切換阻抗調節電路32會自動地調整第一節點N1與第二節點N2之間的阻抗值，以達到最佳化的阻抗匹配。而此外，第二比較器346電性連接運算電路342。第二比較器346用以依據第三信號SIG3與一預設電壓比較，該預設電壓例如為接地電壓GND，當第三信號SIG3的電位等於接地電壓GND時，代表傳輸不正常，不進行阻抗的調整，而產生一錯誤訊息。In this embodiment, the operation circuit 342 is a subtractor, and the potential of the third signal SIG3 is equal to the potential difference between the second signal SIG2 and the first signal SIG1. The first comparator 344 is electrically connected to the operation circuit 342. The first comparator 344 is configured to selectively generate a comparison result of a high-potential signal or a low-potential signal according to the third signal SIG3 and the reference voltage Vcm. That is, when the potential of the third signal SIG3 is greater than the reference voltage Vcm, a high-potential signal is output. Conversely, when the potential of the third signal SIG3 is less than the reference voltage Vcm, a low-potential signal is output. Through the output from the first comparator 344, the impedance adjustment circuit 32 automatically adjusts the impedance value between the first node N1 and the second node N2 to achieve an optimal impedance matching. According to an embodiment, the impedance adjustment circuit 32 sequentially switches its impedance value, and causes the first comparator 344 to sequentially compare the magnitude relationship between the third signal SIG3 and the reference voltage Vcm, so that the impedance adjustment circuit 32 adjusts the first node N1. And the second node N2 to achieve an optimized impedance matching. According to an embodiment, by continuously switching the impedance adjustment circuit 32, the impedance value between the first node N1 and the second node N2 is automatically adjusted to achieve an optimal impedance matching. In addition, the second comparator 346 is electrically connected to the operation circuit 342. The second comparator 346 is used to compare with a preset voltage according to the third signal SIG3. The preset voltage is, for example, the ground voltage GND. When the potential of the third signal SIG3 is equal to the ground voltage GND, it means that the transmission is abnormal and no impedance is performed. Adjustment, and an error message is generated.
綜合以上所述，本發明所提供的面板驅動電路，係通過阻抗調節電路所具有的多段不同阻抗值的切換，依據第一信號與第二信號，自動地調節兩個信號傳輸線之間的阻抗值，而達到最佳化的阻抗匹配，進而使得信號可以自時序控制器被完整且有效率地傳送至面板。To sum up, the panel driving circuit provided by the present invention automatically adjusts the impedance value between two signal transmission lines according to the first signal and the second signal through the switching of multiple different impedance values of the impedance adjustment circuit To achieve the optimal impedance matching, so that the signal can be completely and efficiently transmitted from the timing controller to the panel.
雖然本發明以前述之實施例揭露如上，然其並非用以限定本發明。在不脫離本發明之精神和範圍內，所為之更動與潤飾，均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。Although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. Changes and modifications made without departing from the spirit and scope of the present invention belong to the patent protection scope of the present invention. For the protection scope defined by the present invention, please refer to the attached patent application scope.
1‧‧‧時序控制器1‧‧‧ timing controller
2‧‧‧面板2‧‧‧ Panel
3‧‧‧面板偵測電路3‧‧‧ panel detection circuit
30~60‧‧‧傳輸信號線對30 ~ 60‧‧‧Transmission signal wire pair
301‧‧‧第一信號傳輸線301‧‧‧first signal transmission line
302‧‧‧第二信號傳輸線302‧‧‧Second signal transmission line
32‧‧‧阻抗調節電路32‧‧‧Impedance adjustment circuit
320~324‧‧‧切換電路320 ~ 324‧‧‧switching circuit
3201~3204、3221~3225、3241~3244‧‧‧調變電阻3201 ~ 3204, 3221 ~ 3225, 3241 ~ 3244‧‧‧ Modulation resistor
34‧‧‧偵測電路34‧‧‧detection circuit
342‧‧‧運算電路342‧‧‧ Operation Circuit
344‧‧‧第一比較器344‧‧‧first comparator
346‧‧‧第二比較器346‧‧‧Second Comparator
3420‧‧‧運算放大器3420‧‧‧ Operational Amplifier
S3~S6‧‧‧源極驅動電路S3 ~ S6‧‧‧ source drive circuit
T1‧‧‧第一信號傳輸線的第一端T1‧‧‧ the first end of the first signal transmission line
T2‧‧‧第一信號傳輸線的第二端T2‧‧‧ the second end of the first signal transmission line
T3‧‧‧第二信號傳輸線的第一端T3‧‧‧ the first end of the second signal transmission line
T4‧‧‧第二信號傳輸線的第二端T4‧‧‧ the second end of the second signal transmission line
C1‧‧‧時序控制器的第一端The first end of C1‧‧‧ timing controller
C2‧‧‧時序控制器的第二端C2‧‧‧Second end of timing controller
N1‧‧‧第一節點N1‧‧‧First Node
N2‧‧‧第二節點N2‧‧‧Second Node
R1~R4、3200、3220、3240‧‧‧電阻R1 ~ R4, 3200, 3220, 3240‧‧‧ resistance
SIG1‧‧‧第一信號SIG1‧‧‧First Signal
SIG2‧‧‧第二信號SIG2‧‧‧Second Signal
SIG3‧‧‧第三信號SIG3‧‧‧ Third Signal
Vcm‧‧‧參考電壓Vcm‧‧‧Reference voltage
GND‧‧‧接地電壓GND‧‧‧ ground voltage
圖1係依據本發明之一實施例所繪示的顯示裝置的結構示意圖。 圖2係依據本發明之一實施例所繪示的面板偵測電路的電路架構圖。 圖3係依據本發明之一實施例所繪示的阻抗調節電路的電路架構圖。 圖4係依據本發明之另一實施例所繪示的阻抗調節電路的電路架構圖。 圖5係依據本發明之另一實施例所繪示的阻抗調節電路的電路架構圖。FIG. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention. FIG. 2 is a circuit architecture diagram of a panel detection circuit according to an embodiment of the present invention. FIG. 3 is a circuit architecture diagram of an impedance adjustment circuit according to an embodiment of the present invention. FIG. 4 is a circuit architecture diagram of an impedance adjustment circuit according to another embodiment of the present invention. FIG. 5 is a circuit architecture diagram of an impedance adjustment circuit according to another embodiment of the present invention.
Claims (9)
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| TW105136959A TWI603306B (en) | 2016-11-11 | 2016-11-11 | Driving circuit for panel |
| CN201710036035.4A CN106548742B (en) | 2016-11-11 | 2017-01-17 | Panel driving circuit |
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| TWI603306B TWI603306B (en) | 2017-10-21 |
| TW201818381A true TW201818381A (en) | 2018-05-16 |
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| CN (1) | CN106548742B (en) |
| TW (1) | TWI603306B (en) |
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| CN112017581B (en) * | 2020-09-03 | 2022-02-22 | Tcl华星光电技术有限公司 | Differential signal interface and display device using same |
| CN115035833B (en) * | 2022-05-12 | 2023-06-16 | 重庆惠科金渝光电科技有限公司 | Control circuit, signal control circuit and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100825096B1 (en) * | 2001-12-08 | 2008-04-25 | 삼성전자주식회사 | A Liquid Crystal Display for removing ripple noise |
| TWI253612B (en) * | 2004-02-03 | 2006-04-21 | Novatek Microelectronics Corp | Flat panel display and source driver thereof |
| CN100403096C (en) * | 2004-03-10 | 2008-07-16 | 友达光电股份有限公司 | Terminal circuit of liquid crystal display and its manufacturing method |
| KR20080066107A (en) * | 2007-01-11 | 2008-07-16 | 삼성전자주식회사 | Display apparatus |
| CN101540146B (en) * | 2008-03-20 | 2011-04-06 | 奇信电子股份有限公司 | Liquid crystal display driving device with interface conversion function |
| TWI407421B (en) * | 2009-02-17 | 2013-09-01 | Au Optronics Corp | Driving apparatus for driving a liquid crystal display panel |
| KR101129242B1 (en) * | 2010-05-18 | 2012-03-26 | 주식회사 실리콘웍스 | Liquid crystal display device using chip on glass method |
| CN103810983A (en) * | 2012-11-14 | 2014-05-21 | 联咏科技股份有限公司 | Driving integrated circuit |
| CN103886844A (en) * | 2013-12-31 | 2014-06-25 | 深圳市华星光电技术有限公司 | Display panel assembly and adjusting method thereof, and display device |
| CN105096906B (en) * | 2014-05-20 | 2018-06-08 | 联咏科技股份有限公司 | Optical signal Transmission system |
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2016
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Also Published As
| Publication number | Publication date |
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| CN106548742A (en) | 2017-03-29 |
| CN106548742B (en) | 2019-05-21 |
| TWI603306B (en) | 2017-10-21 |
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