TW201813103A - High voltage semiconductor device - Google Patents

Abstract

High voltage semiconductor devices are provided. The high voltage semiconductor device includes a substrate. A source region and a drain region are disposed in the substrate and separated by an isolation structure. A first metal layer is disposed on the substrate, including a first metal body portion electrically connected to the source region and the drain region respectively, and a plurality of first metal blocks disposed directly above the isolation structure. A second metal layer disposed on the first metal layer includes a second metal body region electrically connected to the source region and the drain region respectively, and a plurality of second metal blocks disposed directly above the isolation structure, wherein an overlap portion is between each of the first metal blocks and the second metal blocks corresponding to the first metal block. A via is disposed between the first metal layer and the second layer, wherein the via is disposed in the overlap portion between the first metal block and the second metal block.

Description

   High-voltage semiconductor device   

The present invention relates to a semiconductor device, and more particularly, to a high-voltage semiconductor device.

High-voltage semiconductor device technology is applicable to the field of integrated circuits with high voltage and high power. Traditional high-voltage semiconductor devices, such as vertically diffused metal oxide semiconductor (VDMOS) transistors and horizontally diffused metal oxide semiconductor (LDMOS) transistors, are mainly used in the field of device applications above 18V. The advantage of high-voltage semiconductor device technology is that it is cost-effective and easily compatible with other processes. It has been widely used in display drive IC components, power supplies, power management, communications, automotive electronics or industrial control.

In traditional high-voltage semiconductor devices, the isolation structure (such as a field oxide layer) is directly exposed to the protective layer or molding compound. During the process of forming the above materials, cracks may occur, so that the mobile charge will penetrate into the field. On the oxide layer, the breakdown voltage decreases and the probability of leakage increases.

Therefore, it is necessary to find a new high-voltage semiconductor device structure to solve the above problems.

Some embodiments of the present disclosure relate to a high-voltage semiconductor device, which includes a substrate, and a source region and a drain region are respectively disposed in the substrate and separated by an isolation structure. A first metal layer is disposed on the substrate and includes: a first The body portion of the metal layer is electrically connected to the source region and the drain region, respectively, and a plurality of first metal blocking blocks are disposed directly above the isolation structure. The second metal layer is disposed on the first metal layer and includes: a second The main body portion of the metal layer is electrically connected to the source region and the drain region, respectively, and a plurality of second metal barrier blocks are disposed directly above the isolation structure, wherein each of the first metal barrier blocks and the corresponding second metal barrier block There is an overlapping portion therebetween, and a via hole is disposed between the first metal layer and the second metal layer, wherein the via hole is disposed at the overlapping portion between the first metal barrier block and the second metal barrier block.

100‧‧‧ substrate

102‧‧‧The first well area

104‧‧‧Second Well District

106‧‧‧ first doped region

108‧‧‧ second doped region

110‧‧‧ third doped region

112‧‧‧ Fourth doped region

114, 116, 118‧‧‧ isolated structures

120‧‧‧Gate structure

120a‧‧‧Gate dielectric layer

120b‧‧‧Gate electrode

122‧‧‧ Insulated sidewall layer

124‧‧‧contact window

126‧‧‧Dielectric layer

130‧‧‧first metal layer

132‧‧‧First metal body

134‧‧‧The first metal block

140‧‧‧Second metal layer

142‧‧‧Second metal body

144‧‧‧Second Metal Block

150, 152, 154‧‧‧vias

160‧‧‧Metal interlayer dielectric layer

170‧‧‧The first high-pressure well area

180‧‧‧Second high pressure well area

190‧‧‧polycrystalline silicon layer

200, 300, 400‧‧‧‧high voltage semiconductor devices

A, B‧‧‧ Overlap

D, D1, D2, D3, D4‧‧‧ length

In order to make the features and advantages of the present invention more comprehensible, preferred embodiments are exemplified below and described in detail with the accompanying drawings.

FIG. 1 is a cross-sectional view of a high-voltage semiconductor device.

FIG. 2 is a cross-sectional view of a high-voltage semiconductor device according to some embodiments of the present invention.

FIG. 3 is a cross-sectional view of a high-voltage semiconductor device according to some embodiments of the present invention.

4A-4D are cross-sectional views of the layout of the first metal blocking block, the second metal blocking block, and the via hole according to some embodiments of the present invention.

The high-voltage semiconductor device and the manufacturing method thereof disclosed in this disclosure are described in detail below. It should be understood that the following description provides many different embodiments or examples for implementing different aspects of the present disclosure. The specific components and arrangements described below are simply a description of this disclosure. Of course, these are only examples and are not intended to limit the scope of the disclosure. In addition, repeated reference numerals or designations may be used in different embodiments. These repetitions are merely for the purpose of simply and clearly describing this disclosure, and do not imply any relevance between the different embodiments and / or structures discussed. Furthermore, for example, when referring to a first material layer on or above a second material layer, it includes the case where the first material layer is in direct contact with the second material layer. Alternatively, it is also possible to have one or more other material layers spaced apart, in which case the first material layer and the second material layer may not be in direct contact.

It must be understood that the specifically described illustrated elements may exist in various forms well known to those skilled in the art. In addition, when a layer is "on" another layer or substrate, it may mean "directly" on the other layer or substrate, or it may mean that another layer is sandwiched between other layers or substrates.

In addition, embodiments may use relative terms, such as "lower", "below" or "bottom" and "higher", "above" or "top" to describe one element shown in the figure to another element Relative relationship. It can be understood that if the illustrated device is turned upside down and turned upside down, the component described on the "lower" side will become the component on the "higher" side.

Here, the terms "about" and "approximately" usually indicate within 20% of a given value or range, preferably within 10%, and more preferably within 5%. The quantity given here is an approximate quantity, which means that the meanings of "about" and "approximately" can still be implied without specific instructions.

The present invention discloses an embodiment of a high-voltage semiconductor device, and the above-mentioned embodiments may be included in, for example, a integrated circuit (IC) of a microprocessor, a memory element, and / or other elements. The integrated circuit (IC) described above may also include different passive and active microelectronic components, such as thin-film resistors, other types of capacitors (such as metal-insulator-metal capacitors, MIMCAP) )), Inductors, Diodes, Metal-Oxide-Semiconductor field-effect transistors (MOSFETs), Complementary MOS Transistors, BJTs, Lateral Diffusion Type MOS transistor (LDMOS), high power MOS transistor or other type of transistor. Those having ordinary knowledge in the technical field to which the present invention pertains can understand that the high-voltage semiconductor device can also be used for other types of semiconductor elements.

Referring to FIG. 1, FIG. 1 is a cross-sectional view of a high-voltage semiconductor device 200. First, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, the above semiconductor substrate may also be an element semiconductor, including germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, and indium phosphide ), Indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium alloy (SiGe), gallium phosphorus arsenide alloy (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide Alloy (AlGaAs), indium gallium alloy (GaInAs), indium gallium phosphorus (GaInP) and / or indium gallium phosphorus arsenide (GaInAsP) or a combination of the above materials. In addition, the substrate 100 may be a semiconductor on insulator. In addition, the substrate 100 may also include an epitaxial layer (not shown). The epitaxial layer may include silicon, germanium, silicon and germanium, a III-V compound, or a combination thereof. The epitaxial layer can be formed by an epitaxial growth process, such as metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), plasma-enhanced chemical vapor deposition (PECVD), remote plasma chemical vapor deposition (RP-CVD), molecular beam epitaxy (molecular beam epitaxy (MBE)), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy, Cl-VPE) or similar methods.

In addition, as shown in FIG. 1, the substrate 100 also includes isolation structures 114, 116, and 118 formed therein. The isolation structures 114, 116, and 118 can be formed by a local oxidation method (LOCOS).

As shown in FIG. 1, the high-voltage semiconductor device 200 includes a gate structure 120. The gate structure 120 is disposed on the substrate 100, and a part of the gate structure 120 extends above the isolation structure 116.

The gate structure 120 includes a gate dielectric layer 120a and a gate electrode 120b disposed thereon. A dielectric material layer (for forming the gate dielectric layer 120a) and a conductive material layer (for forming the gate electrode 120b) thereon may be blanket-deposited sequentially on the substrate 100. The photolithography process and the etching process pattern the dielectric material layer and the conductive material layer to form a gate dielectric layer 120a and a gate electrode 120b, respectively.

The material of the above-mentioned dielectric material layer (that is, the material of the gate dielectric layer 120a) may be silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, or any other suitable material. A dielectric material, or a combination thereof. The material of the high-k dielectric material may be metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, Metal aluminate, zirconium silicate, zirconium aluminate. For example, the high-k dielectric material can be LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO ₂ , HfO ₃ , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr) TiO ₃ (BST), Al ₂ O ₃ , other high dielectric constants of other suitable materials A dielectric material, or a combination thereof. This dielectric material layer can be formed by the aforementioned chemical vapor deposition (CVD) method or spin coating method.

The material of the aforementioned conductive material layer (that is, the material of the gate electrode 120b) may be amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, conductive metal oxides, or a combination thereof. The above metal may include, but is not limited to, molybdenum, tungsten, titanium, titanium, tantalum, platinum, or hafnium. The metal nitride may include, but is not limited to, molybdenum nitride, tungsten nitride, titanium nitride, and titanium nitride. The conductive metal oxide may include, but is not limited to, ruthenium oxide and indium tin oxide. The material of the conductive material layer can be formed by the aforementioned chemical vapor deposition (CVD) method, sputtering method, resistance heating evaporation method, electron beam evaporation method, or any other suitable deposition method. A low pressure chemical vapor deposition (LPCVD) method is used to deposit an amorphous silicon conductive material layer or a polycrystalline silicon conductive material layer at a temperature between 525 and 650 ° C, and the thickness can range from about 1000 Å to about 10,000 Å. The gate electrode 120b may be a polycrystalline silicon layer.

In addition, the high-voltage semiconductor device 200 also includes insulating sidewall layers 122 disposed on both sidewalls of the gate structure 120. Low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition can be used to deposit an insulating layer with a thickness of about 200 to 2000 Å at 350 to 850 ° C, such as silicon oxide or silicon nitride; composite) sidewall layer, more than one insulating layer can be deposited. After deposition, using SF ₆ , CF ₄ , CHF ₃ , or C ₂ F ₆ as an etching source and performing anisotropic etching using a reactive ion etching process, an insulating sidewall can be formed on the sidewall of the gate structure 120. Layer 122.

As shown in FIG. 1, the high-voltage semiconductor device 200 also includes a first well region 102 and a second well region 104. The first well region 102 and the second well region 104 are disposed on both sides of the isolation structure 116. The first well region 102 has a first conductivity type, and the second well region 104 has a second conductivity type different from the first conductivity type. The first conductivity type may be a P type, the second conductivity type may be an N type, and the first well region 102 may be doped with, for example, boron (B), aluminum (Al), gallium (Ga), indium (In), or the above. composition, doping concentration may be, for example, ^{10 15 cm 3 -10 17 cm 3} , the second well region 104 may be doped with phosphorus, for example, the doping concentration may be, for example, ^{10 15 cm 3 -10 17 cm 3} . The high-voltage semiconductor device 200 includes a first high-pressure well region 170 and a second high-pressure well region 180. The first high-pressure well region 170 has a second conductivity type, and the second high-pressure well region 180 has a first conductivity type. The doping concentration of the region 170 may be, for example, 10 ¹⁴ cm ³ -10 ¹⁷ cm ³ , and the doping concentration of the second high-pressure well region 180 may be, for example, 10 ¹⁴ cm ³ -10 ¹⁷ cm ³ .

As shown in FIG. 1, the high-voltage semiconductor device 200 includes a first doped region 106, a second doped region 108, a third doped region 110, and a fourth doped region 112 and is disposed in the substrate 100. The first doped region 106 and the second doped region 108 are located between the isolation structure 114 and the isolation structure 116, and also between the isolation structure 114 and the gate structure 120. It is located in the first well area 102. The first doped region 106 has a first conductivity type, and the second doped region 108 has a second conductivity type. The doping concentration of the first doped region 106 and the second doped region 108 may be, for example, 10 ¹⁸ / cm ³ -10 ²⁰ / cm ³ , the first doped region 106 and the second doped region 108 may serve as a source region of the high-voltage semiconductor device 200. The third doped region 110 is disposed between the isolation structure 116 and the isolation structure 118 and is located in the second well region 104. The third doped region 110 has a second conductivity type and the doping concentration of the third doped region 110. It may be, for example, 10 ¹⁸ / cm ³ -10 ²⁰ / cm ³ , and the third doped region 110 may serve as a drain region of the high-voltage semiconductor device 200. The fourth doped region 112 is disposed on the other side of the isolation structure 114 opposite to the first doped region 106. The fourth doped region 112 has a first conductivity type. The doping concentration of the fourth doped region 112 may be, for example, of ^{10 18 / cm 3 -10 20 /} cm 3.

As shown in FIG. 1, the high-voltage semiconductor device 200 includes a dielectric layer 126 provided on a substrate 100. The dielectric layer 126 may include a multilayer structure formed of a plurality of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) ), Low-k dielectric materials or other suitable dielectric materials. Low dielectric constant dielectric materials include fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, and parylene , Bis-benzocyclobutenes (BCB), polyimide, but it is not limited to this.

As shown in FIG. 1, the high-voltage semiconductor device 200 includes a contact window 124 disposed on the substrate 100, which is disposed in the dielectric layer 126, and the contact window 124 is electrically connected to the first doped region 106 and the second dopant. The region 108, the third doped region 110, and the fourth doped region 112. The material of the contact window 124 includes a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), silicidation Nickel (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other suitable Conductive material or a combination of the foregoing.

In addition, as shown in FIG. 1, the high-voltage semiconductor device 200 includes a first metal layer 130, a second metal layer 140, and a via 150 disposed on an inter-metal dielectric (IMD) layer located on the dielectric layer 126. ) Within 160.

As shown in FIG. 1, the first metal layer 130 includes a first metal layer main body portion 132 and a plurality of first metal blocking blocks 134. The first metal layer main body portion 132 and the first doped region 106 are each connected through a contact window 124. The second doped region 108, the third doped region 110, and the fourth doped region 112 are electrically connected, that is, the first metal layer body portion 132 is electrically connected to the source region and the drain region, respectively. These first metal blocking blocks 134 are disposed directly above the isolation structure 116. The second metal layer 140 is disposed on the first metal layer and includes a second metal layer body portion 142 and a plurality of second metal blocking blocks 144. The second metal layer body portion 142 passes through the via 150 and the first metal layer body. The portion 132 and the contact window 124 are electrically connected to the first doped region 106, the second doped region 108, the third doped region 110, and the fourth doped region 112, that is, the second metal layer body portion 142 and The source region and the drain region are each electrically connected. These second metal blocking blocks 144 are disposed directly above the isolation structure 116 and the first metal blocking block 134.

The material of the first metal layer 130, the second metal layer 140, and the via 150 may be the same as that of the contact window 124, and the material of the metal interlayer dielectric layer 160 may be the same as that of the dielectric layer 126.

As shown in FIG. 1, each first metal blocking block 134 and a corresponding second metal blocking block 144 have an overlapping portion A, and the width of the overlapping portion A is not particularly limited.

The arrangement of the first metal blocking block 134 and the second metal blocking block 144 can reduce the probability of free electrons penetrating into the isolation structure 116, thereby preventing the breakdown voltage of the high-voltage semiconductor device 200 from falling.

Referring to FIG. 2, FIG. 2 is a cross-sectional view of a high-voltage semiconductor device 300 according to some embodiments of the present invention. The high-voltage semiconductor device 300 shown in FIG. 2 is different from the high-voltage semiconductor device 200 shown in FIG. 1 in that the high-voltage semiconductor device 300 further includes a via 152. In some embodiments, the via hole 152 is disposed in the overlapping portion A between the first metal blocking block 134 and the second metal blocking block 144. As shown in FIG. 2, the via hole 152 is disposed directly above the isolation structure 116, and the first metal blocking block 134 is connected to the second metal blocking block 144 through the via hole 152. The material of the via hole 152 may be the same as that of the via hole 150, and the via hole 152 and the via hole 150 may be formed in the same step. The first metal blocking block 134 and the second metal blocking block 144 are not electrically connected to the first doped region 106, the second doped region 108, the third doped region 110, and the fourth doped region 112.

The via 152 disposed directly above the isolation structure 116 and located between the first metal blocking block 134 and the second metal blocking block 144 can further limit the path of the free electron migration, thereby reducing the probability of the free electrons penetrating into the isolation structure 116. When the first metal blocking block 134, the second metal blocking block 144, and the via 152 are not provided, especially in a high-temperature environment (for example, a temperature greater than 150 ° C), the electrons have a larger kinetic energy and are easier to penetrate into The isolation structure 116 reduces the breakdown voltage of the high-voltage semiconductor device and causes leakage. The high-voltage semiconductor device 300 shown in FIG. 2 has more through-holes 152 than the high-voltage semiconductor device 200 shown in FIG. 1. The through-holes 152 are disposed between the first metal blocking block 134 and the second metal blocking block 144. The function of 152 is the same as that of the first metal blocking block 134 and the second metal blocking block 144, and it is used as a means for blocking the migration of free electrons. In the high-voltage semiconductor device 200 shown in FIG. 1, free electrons can migrate in a region between the first metal blocking block 134 and the second metal blocking block 144. For example, the free electrons can move from the leftmost second metal blocking block 144. To the rightmost first metal blocking block 134. The via hole 152 provided in the high-voltage semiconductor device 300 shown in FIG. 2 cuts off the possibility of the migration path, that is, the free electron migration can only migrate from between the two adjacent second metal barriers 144 to the corresponding ones. Between two adjacent first metal blocking blocks 134. With the arrangement of the vias 152, the migration path of the free electrons is more restricted.

In some embodiments, the breakdown voltage of the high-voltage semiconductor device 200 as shown in FIG. 1 is about 789V, and the breakdown voltage of the high-voltage semiconductor device 300 as shown in FIG. 2 is about 745V. Although the breakdown voltage of the high-voltage semiconductor device 300 shown in FIG. 2 is slightly lower than that of the high-voltage semiconductor device 200 shown in FIG. 1, the high-voltage semiconductor device 300 shown in FIG. 2 is more capable of preventing free electrons from penetrating into the isolation structure. 116, while reducing the probability of crash voltage drop and leakage. In a high-temperature environment (eg, a temperature greater than 150 ° C), the kinetic energy of the free electrons is high. In this case, the probability of the free electrons of the high-voltage semiconductor device 300 shown in FIG. 2 penetrating into the isolation structure 116 will be significantly lower. In the high-voltage semiconductor device 200 shown in FIG. 1, leakage current can be more prevented.

Referring to FIG. 3, FIG. 3 is a cross-sectional view of a high-voltage semiconductor device 400 according to some embodiments of the present invention. In some embodiments, the high-voltage semiconductor device 400 further includes a polycrystalline silicon layer 190 and a via 154. The polycrystalline silicon layer 190 functions similarly to the first metal blocking block 134 and the second metal blocking block 144 to generate more stacks to limit the release. Electron migration path. The polycrystalline silicon layer 190 is located between the first metal blocking block 134 and the isolation structure 116, and is directly above the isolation structure 116. In addition, the via hole 154 is provided in the overlapping portion B between the polycrystalline silicon layer 190 and the first metal blocking block 134. In some embodiments, the overlapping portion A and the overlapping portion B may overlap. In some embodiments, the overlapping portion A and the overlapping portion B do not overlap. As shown in FIG. 3, the via hole 154 has the same function as the via hole 152, and is used as a means to block the migration of free electrons. The material of the via hole 154 can be the same as that of the contact window 124, and the conduction can be formed in the same step Hole 154 and contact window 124. Compared with the high-voltage semiconductor device 300 shown in FIG. 2, the migration path of free electrons can be further restricted, and therefore, leakage current can be more prevented in a high-temperature environment.

Referring to FIGS. 4A-4D, FIGS. 4A-4D are cross-sectional views of the layout of the first metal blocking block 134, the second metal blocking block 144, and the via 152 according to some embodiments of the present invention. In some embodiments, as shown in FIG. 4A, the length D of each first metal blocking block 134 is the same as the length D of each second metal blocking block 144, and each first metal blocking block 134 is corresponding to a corresponding first The projections of the two metal blocking blocks 144 on the substrate 100 completely overlap. In some embodiments, as shown in FIG. 4B, the length D of each first metal blocking block 134 is the same as the length D of each second metal blocking block 144, and each first metal blocking block 134 is corresponding to a corresponding first The projections of the two metal barriers 144 on the substrate 100 do not completely overlap, that is, the projections of a portion of the first metal barriers 134 and a portion of the second metal barriers 144 on the substrate 100 overlap, and the vias 152 are provided there. In the overlap. In some embodiments, as shown in FIG. 4C, the first metal blocking blocks 134 have a first length D1 and a second length D2 different from the first length D1. The second metal blocking blocks 144 have a first length D1 and The second length D2, and the length of the first metal blocking block 134 and the corresponding second metal blocking block 144 are the same. For example, the corresponding first metal blocking block 134 and the second metal blocking block 144 are both the first length D1 or both. Is the second length D2. In some embodiments, as shown in FIG. 4D, the first metal blocking blocks 134 have a first length D1, a second length D2, a third length D3, and a fourth length D4, and the second metal blocking blocks 144 have a first length The length D1, the second length D2, the third length D3, and the fourth length D4, and the lengths of the first metal blocking block 134 and the corresponding second metal blocking block 144 are the same. In this embodiment, the relationship between the first length D1, the second length D2, the third length D3, and the fourth length D4 may be linearly decreasing, for example, the first length D1> the second length D2> the third length D3> the first Four lengths D4. In some embodiments, the relationship between the first length D1, the second length D2, the third length D3, and the fourth length D4 may be linearly increasing, for example, the first length D1 <the second length D2 <the third length D3 <the Four lengths D4.

Although it is disclosed in the embodiments of the present invention that the high-voltage semiconductor device includes a first metal layer and a second metal layer, in other embodiments, the high-voltage semiconductor device further includes a third metal layer, a fourth metal layer, or more metal layers. The invention is not limited to this. In addition, the length of the first metal blocking block and the corresponding second metal blocking block may be the same or different, and the present invention is not limited thereto.

Although the embodiments and advantages of this disclosure have been disclosed as above, it should be understood that anyone with ordinary knowledge in the technical field can make changes, substitutions, and decorations without departing from the spirit and scope of this disclosure. In addition, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, devices, methods and steps in the specific embodiments described in the description. Any person with ordinary knowledge in the technical field to which this disclosure pertains may disclose content from this disclosure To understand the current or future development of processes, machines, manufacturing, material composition, devices, methods and steps, as long as they can implement substantially the same functions or achieve approximately the same results in the embodiments described herein, they can be used according to this disclosure. Therefore, the protection scope of this disclosure includes the above-mentioned processes, machines, manufacturing, material composition, devices, methods and steps. In addition, each patent application scope constitutes a separate embodiment, and the protection scope of this disclosure also includes a combination of each patent application scope and embodiment.

Claims (10)

    A high-voltage semiconductor device includes: a substrate; a source region and a drain region disposed in the substrate and separated by an isolation structure; a first metal layer disposed on the substrate including: a first The main body of the metal layer is electrically connected to each of the source region and the drain region; and a plurality of first metal blocking blocks are disposed directly above the isolation structure; a second metal layer is disposed on the first metal The layer includes: a second metal layer main body electrically connected to the source region and the drain region respectively; and a plurality of second metal barrier blocks disposed directly above the isolation structure, each of which There is a first overlapping portion between a metal blocking block and the corresponding second metal blocking block; and a first via hole is provided between the first metal layers and the second metal layers, wherein the first conduction A hole is provided in the first overlapping portion between the first metal blocking block and the second metal blocking block.         The high-voltage semiconductor device according to item 1 of the scope of patent application, wherein the first via hole is disposed directly above the isolation structure.         The high-voltage semiconductor device according to item 1 of the scope of the patent application, wherein each of the first metal barrier blocks has the same length, and each of the second metal barrier blocks has the same length.         The high-voltage semiconductor device according to item 1 of the scope of patent application, wherein the first metal blocking blocks have a first length and a second length different from the first length.         The high-voltage semiconductor device according to item 4 of the scope of patent application, wherein the second metal barrier blocks have the first length and the second length, and each of the first metal barrier blocks and the corresponding second metal barrier block The blocks are the same length.         The high-voltage semiconductor device according to item 1 of the scope of patent application, wherein each of the first metal barrier blocks completely overlaps the corresponding second metal barrier block.         The high-voltage semiconductor device according to item 1 of the scope of patent application, wherein each of the first metal barrier blocks does not completely overlap with the corresponding second metal barrier block.         The high-voltage semiconductor device according to item 1 of the patent application scope further includes: a gate structure disposed on the substrate, wherein the gate structure extends to the isolation structure.         The high-voltage semiconductor device according to item 1 of the scope of patent application, wherein the length of each of the first metal blocking blocks is different, and the lengths of the first metal blocking blocks decrease or increase linearly.         The high-voltage semiconductor device described in item 1 of the patent application scope further includes: a polycrystalline silicon layer disposed between the first metal barriers and the isolation structure, the polycrystalline silicon layer having a plurality of sections, each of the polycrystalline silicon layer There is a second overlapping portion between the portion and the corresponding first metal blocking block; and a second via hole is disposed between the first metal layers and the polycrystalline silicon layer, wherein the second via hole is disposed on the The second overlapping portion between the first metal blocking block and the polycrystalline silicon layer.