TW201803053A - Fan-out muti-chip stacking assembly structure and manufacturing method - Google Patents

Abstract

This investigation is providing a manufacturing method of Fan-out muti-chip stacking assembly structure, to set stacking chips on substrate and bottom chip is connected with substrate by metal bumping and top chip is connected by wire process on substrate, and then using epoxy compound to cover it and protect chips/devices and wires. Proceeding through mold via and filling contactor material in the via, we could transfer connecting function from substrate surface to epoxy compound surface and through I/O process, it could complete fan-out muti-chips stacking assembly structure.

Description

Fan-out type multi-chip stacked package electronic device and method for forming the same

The invention relates to a stackable packaging structure and a method for forming the same, and more particularly to an electronic device with a ball grid array (BGA) package and a method for forming the same.

As consumer electronics products become more and more diversified in their multi-functional and portable needs, it is necessary to change the electronic packaging structure toward small size and multi-performance. However, as the overall package structure becomes smaller and smaller, factors such as component size, chip size, number of I / O contacts, size, and pitch must be considered to determine whether its space is sufficient to accommodate all circuit endpoints. A single integrated circuit chip cannot easily increase the number of circuit terminals due to the area limitation. However, due to the current advances in semiconductor technology, the size of the chip has become smaller, the chip has powerful functions, the number of I / O contacts has increased, and the corresponding packaging substrate has also The problem of corresponding circuit layout must be considered. Multilayer printed circuit board substrates are used to overcome the problems of multiple circuit output terminals. But when space is limited, you must think about how to increase the circuit output structure design.

In order to solve the above-mentioned problems, the present invention provides a three-dimensionally stackable, double-sided Fan-out multi-chip packaging structure and a method for forming the same under a limited increase in substrate area, so as to increase the circuit of an integrated circuit package The number of output terminals has more than doubled the number of output terminals of traditional packages. In detail, the present invention uses a chip top and bottom stacked package, and then adds a layer of perforated metal plating or a filled conductor to form a loop, and adds double-sided circuit endpoints. To meet the needs of multiple I / O packages, without affecting the original package size and area.

The Republic of China Patent No. 407446 discloses a multi-chip stacked package electronic device and a method for forming the same. As shown in FIG. 1, the structure includes a circuit board 10; the lower-layer chip 21 is connected to the substrate 10 through an I / O contact 23. The upper-layer chip 22 is connected to the substrate 10 through a lead 50, and the chip and the lead are covered with a packaging layer 40. The stacked wafers 24 may include a non-conductive material, which has a bonding effect. This patent can use different types of chips for signal connection and stacking to increase its component application functions.

The Republic of China Patent No. I441312 proposes a three-dimensional three-dimensional structure 300. The bottom wafer 301 is fixed to the substrate 350 by a connection layer 310, and then the stacked wafer 302 is stacked on the bottom wafer 301. The stacked wafer 302 has a through-hole design 303. Vias for telecommunication connections. The via is covered with an insulating layer 311, and the insulating layer 311 partially or completely covers the stacked chip 302 at the same time, thereby achieving the effect of protecting the chip and the insulated telecommunications. A single or a plurality of first telecommunication contacts 321 are made on the surface of the insulating layer, and the first telecommunication contacts 321 are completely, partially or uncovered on the surface of the insulating layer 310, and are completely or partially covered with the hole-filling conductive material. 320; this first telecommunication contact 321 can be directly fabricated on the hole-filling conductive material 320, Or made on the surface of the insulating layer 310 after wiring treatment; a single or plural second telecommunication contacts 322 are made on the other surface, and the second telecommunication contacts 322 are completely, partially or uncovered on the insulating layer 310 The surface is completely or partially covered with the hole-filling conductive material 320. A single or multiple third telecommunication contacts 323 are made on the bottom board, and the third telecommunication contacts 323 are partially or completely covered on the upper surface of the bottom chip 301. The stacked chip 302 having an insulating layer 311, through holes 303 and 312, a hole-filling conductive material 320, a first telecommunication contact 321, and a second telecommunication contact 322 is structured with a telecommunication contact layer 325 and a second telecommunication contact 322 performs a telecommunications connection with a third telecommunication contact 323 fabricated on the underlying wafer 301, and this telecommunication contact adjoining layer 325 may be any conductive material. The first telecommunication contact 321 of the stacked chip 302 is connected to the fourth telecommunication contact 324 by using a single or plural wire bonding wires 330 and wire bonding technology to achieve a telecommunication connection with the substrate 350.

The main object of the present invention is to propose a fan-out type single or multi-chip stacked package device and a method for forming the same. Use stacked wafers to mount on the substrate. The lower wafers are connected to the substrate through I / O contacts. The upper or lower wafers are connected to the substrate through wire bonds. After the resin is sealed, the holes are filled with conductors. The electronic connection signal is transmitted upward to the surface of the component, so that it forms a double-sided package component capable of outputting the electronic signal, so as to solve the multi-layer I / O packaging demand device. And by extending a variety of structures, a fan-shaped multi-chip stacking structure for different applications can be explored to meet the multifunctional and large-capacity requirements required by current mobile devices.

In order to further understand the purpose, technical content, characteristics of the present invention and the effects achieved by it, Acknowledgement, I would like to accompany the description of the preferred embodiment with a detailed description, as follows:

The invention discloses an electronic packaging structure, which is a fan-shaped stacked wafer structure. The first chip is connected by metal I / O contacts, the second chip is connected by wire bonding, and then the resin vias are matched to the resin surface, and then the signal conduction is performed by a metal planting ball.

FIG. 3 is a cross-sectional view of the fan-out stacked chip 120 package structure of the first case of the present invention. This package structure first uses the substrate 110 as a carrier, and the first chip 121 is connected to the substrate I / O by the I / O contact 123. The terminal 111 and the second chip 122 use a wire 150 to connect signals. However, the first wafer 121 and the second wafer 122 may be bonded using a wafer connection layer 124 made of a conductive or non-conductive material, and then covered by a cover layer 140. Then, the electronic signal of the substrate 110 is transmitted to the resin surface electronic terminal 113 through the conductor-filled through-hole 112, and then the I / O contact 130 is manufactured to complete the package structure.

The first wafer 121 and the second wafer 122 may be active or passive electronic components, sensing components, test components, micro-electro-mechanical wafers or a combination of electronic components thereon. The conductive material filled in the through-hole 112 can be a conductive metal, such as tin, aluminum, copper, silver, tungsten, lead or the above metal material alloy or other conductive material, and can also be applied to the substrate circuit end 111 and the resin surface. Electronic terminal 113.

Figure 4 shows the design of the extended structure of the present invention. The fan-out chip stacking package structure 200 uses the substrate 210 as a carrier. The first wafer 221 is connected and fixed on the substrate by the connection layer 223, and then connected to the substrate by the 250 wire method. The electronic terminal 211, and the first chip circuit pad 214 generates the circuit terminal 213 through the wiring design circuit 215 so as to be connected to the second chip I / O terminal 216. The signal can be processed by solder ball reflow or bump 224 process. connection. Covering is then completed by the cover layer 240, and then by the conductive vias 212 The electronic signal of the substrate 210 is transmitted to the resin surface electronic terminal 217 on the network, and then the I / O contact 260 is performed to complete the package structure.

Figure 5 shows the design of the extended structure of the present invention. The multi-chip sector structure 400 uses the substrate 410 as a carrier. The first chip 421 is connected to the circuit end 412 of the substrate by an I / O contact 423, and the second chip 422 is connected using a wire 450. Signal. However, the first wafer 421 and the second wafer 422 can be bonded by using a wafer connection layer 425 of conductive or non-conductive adhesive, and then covered by a cover layer 440. Then via the via 413, the electronic terminal 411 signal of the substrate is transmitted upward to the resin surface electronic terminal 414, and the wiring design 416 can also be formed to form the resin surface electronic terminal 417. The via 413 can be designed on both sides of the structure, and then proceed. After the I / O contacts 429 of the third chip 426 and the fourth chip 427 are connected, the cover layer 428 is protected, and finally the metal ball 460 is used to complete the package structure.

FIG. 6 is an extended structure design of the present invention. The multi-chip fan-shaped package structure 500 uses a substrate 510 as a carrier. The first chip 521 is connected to the substrate metal pad 512 by a metal bump 523 and the second chip 522 is connected to a signal using a wire 550 . However, the first wafer 521 and the second wafer 522 can be joined by using a conductive or non-conductive adhesive wafer connection layer 525, and then covered by a cover layer 540. Then, the signal from the substrate metal pad 511 is transmitted upward to the electronic pad 514 on the resin surface metal via hole 513 through the via 513, and the wiring design 531 on the resin surface can also be used to form the electronic surface of the resin surface. Both sides of the structure can be used for via holes 513 design, and then carry out the third wafer 526 and the fourth wafer 527 using the connection layer 528 to the substrate, and then perform a gold wire 529 wire packaging process, and then protected by the cover layer 540 to perform the first I / O contact 530 production. A second I / O contact 560 is made to complete the package structure.

10‧‧‧ carrier (substrate)

11‧‧‧Circuit side

12‧‧‧ plated through hole

20‧‧‧ stacked chip

21‧‧‧The first chip

22‧‧‧Second Chip

23‧‧‧ metal connection (bump)

24‧‧‧chip connection layer

25‧‧‧ Non-conductive cover

30‧‧‧ solder ball

40‧‧‧ filler

50‧‧‧ Lead

100‧‧‧fan-out structure design

110‧‧‧ carrier (substrate)

111‧‧‧I / O terminal

112‧‧‧via

113‧‧‧Resin surface electronic terminal

120‧‧‧ stacked chip

121‧‧‧The first chip

122‧‧‧Second Chip

123‧‧‧I / O contact

124‧‧‧chip connection layer

125‧‧‧ Overlay

130‧‧‧ solder ball or bump

140‧‧‧ filler

150‧‧‧ Lead

200‧‧‧Fan-out chip stack package structure

210‧‧‧ substrate

211‧‧‧I / O contact

212‧‧‧via

213‧‧‧I / O contact

214‧‧‧First chip circuit pad

215‧‧‧Wiring Design Circuit

216‧‧‧Second chip electronic pad

217‧‧‧Resin surface electronic terminal

221‧‧‧First Chip

222‧‧‧Second Chip

223‧‧‧ conductive or non-conductive connecting layer

224‧‧‧I / O contact

230‧‧‧I / O contact

240‧‧‧ Overlay

250‧‧‧Gold wire lead

260‧‧‧I / O contact

300‧‧‧Three-dimensional three-dimensional chip stack package structure

301‧‧‧ underlying chip

302‧‧‧stacked chip

303‧‧‧through hole

310‧‧‧ Adjacent Layer

311‧‧‧insulation layer

312‧‧‧through hole

320‧‧‧ hole-filling conductive material

321‧‧‧First Telecom Contact

322‧‧‧Second telecommunication contact

323‧‧‧Telecommunications contact

324‧‧‧Fourth telecommunication contact

325‧‧‧Telecom contact layer

330‧‧‧ wire

340‧‧‧sealing resin

350‧‧‧ substrate

400‧‧‧Multi-chip fan-out structure

410‧‧‧Electronic substrate

411‧‧‧Substrate metal pad

412‧‧‧ substrate metal pad

413‧‧‧via

414‧‧‧Electronic pad on via

415‧‧‧ electronic pad on chip

416‧‧‧ wiring design on the surface of the overlay

421‧‧‧First Chip

422‧‧‧Second Chip

423‧‧‧I / O contact

424‧‧‧ Overlay

425‧‧‧chip connection layer

426‧‧‧Third chip

427‧‧‧Fourth chip

428‧‧‧line protection layer

429‧‧‧I / O contact

440‧‧‧ Overlay

450‧‧‧Gold Wire

460‧‧‧I / O contact

500‧‧‧multi-chip fan-out package structure

510‧‧‧ substrate

511‧‧‧ substrate metal pad

512‧‧‧ substrate metal pad

513‧‧‧via

514‧‧‧ electronic pads on vias

521‧‧‧First Chip

522‧‧‧Second Chip

523‧‧‧I / O contact

524‧‧‧Joint protective layer

525‧‧‧chip connection layer

526‧‧‧Third chip

527‧‧‧Fourth chip

528‧‧‧chip connection layer

529‧‧‧Gold Wire

530‧‧‧Substrate electronic pad

531‧‧‧ resin surface wiring design

540‧‧‧ Overlay

550‧‧‧Gold Wire

560‧‧‧I / O contact

FIG. 1 is a schematic diagram of a three-dimensional three-dimensional stacking structure using conventional wire bonding technology.

FIG. 2 is a schematic diagram of a conventional fan-shaped package structure.

FIG. 3 is a cross-sectional view of a fan-shaped stacked wafer structure of the present invention

Figure 4 is a cross-sectional view of the extended design of a fan-shaped stacked wafer structure

Figure 5 is an extended design of the present invention: a cross-sectional view of a multi-wafer fan structure

Figure 6 is an extended design of the present invention: a cross-sectional view of a multi-chip fan-shaped package

100‧‧‧fan-out structure design

110‧‧‧ carrier (substrate)

111‧‧‧Circuit (I / O pad)

112‧‧‧via

120‧‧‧ stacked chip

121‧‧‧The first chip

122‧‧‧Second Chip

123‧‧‧metal connection (bump), I / O contact

124‧‧‧chip connection layer

125‧‧‧ non-conductive cover

130‧‧‧ solder ball or I / O contact

140‧‧‧ filler

150‧‧‧ Lead

Claims (10)

An electronic device with a fan-out multi-chip stacked package includes a substrate, a packaging substrate, and a stacked wafer thereon; a lower wafer of the stacked wafer is connected to the substrate by a conductive bump, and an upper wafer is connected by a lead Connected to the substrate; and an encapsulation layer on the substrate covering the entire stacked chip and the leads. After that, the vias are filled with conductors so that the electronic transmission signals are connected to the surface of the packaging layer, and the wiring process is performed to move the signal connection metal pads to a suitable position to facilitate the next design of components and component stacking. Another extended invention of an electronic device with a fan-out multi-chip stacked package includes a substrate, which is a packaging substrate, on which the stacked wafers are carried; the lower wafers of the stacked wafers are connected to the substrate by conductive or non-conductive glue. The lead is connected to the substrate; the upper-layer wafer I / O pad is used to generate the circuit end by the wiring design circuit so as to connect with the second wafer I / O end. The information can be transmitted by solder ball reflow or bump process. No. connection, the cover layer protects the entire stacked chip and the lead. After that, the vias are filled with conductors so that the electronic transmission signals are connected to the surface of the packaging layer, and the wiring process is performed to move the signal connection metal pads to a suitable position to facilitate the next design of components and component stacking. The electronic device as described in claims 1 and 2, wherein the substrate is a metal substrate, which can be an organic substrate such as FR4, BT, ABF, or silicon, gallium arsenide, or other materials or the above materials. Of combination. According to the electronic device described in claims 1 and 2, the hole-filling conductive material with conductive properties may be copper, tin, silver, lead, tungsten, or an alloy of metal materials or other conductive materials. combination. According to the electronic device described in claims 1 and 2, the stacked chip and the lower layer chip may be active or passive electronic components, sensing components, test components, or a combination of electronic components or more. According to the electronic device described in claims 1 and 2, the through-hole structure can be made by laser drilling, photolithography, mechanical drilling or other methods. According to the electronic device described in claims 1 and 2, the adhesive layer may be BCB, ABF, PI, or other adhesive materials. A multi-chip stacked packaging method includes: A. a substrate; B. directly coupling a circuit end of a first chip to a substrate through a conductive bump; C. bonding and bonding to a first chip with a second chip stack D. At the circuit end of the second chip, the leads are coupled to the substrate by wire bonding; E. Injection molding, so that a packaging layer covers the entire wafer and leads on the substrate; F. Packaging layer Make holes and fill conductors so that The connection signal is transmitted to the surface of the packaging layer; G. The wiring process is performed, and the metal wiring is to a suitable position; H. After the solder ball is re-soldered, the final fan-out multi-chip stacked structure is formed. The electronic device according to item 7 of the scope of the patent application, wherein the stacking or bonding process can be made by, for example, hot pressing, reflow or other methods. The multi-chip stacked packaging method according to item 8 of the scope of the patent application, wherein the telecommunications connection may include connection purposes such as conduction, insulation, and ground and includes any upward conductor fabrication.