TW201802692A - Memory device for performing internal process and operating method thereof - Google Patents

Abstract

A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

Description

Memory device for executing internal program and method of operating the same

RELATED APPLICATIONS This application claims the benefit of the Korean Patent Office No. 10-2016-0071074, filed on Jun. 8, 2016, the entire disclosure of which is incorporated herein by reference. Revealing.

FIELD OF THE INVENTION The present disclosure relates to memory devices and, more particularly, to memory devices for performing internal programs and methods of operating the same.

The capacity and speed of semiconductor memory devices widely used in high-performance electronic systems are increasing. As an example of a semiconductor memory device, a dynamic random access memory (DRAM) is an electrical memory in which data is determined by a change in charge stored in a capacitor.

The semiconductor memory device can exchange data with an external memory controller through one or more channels. For example, according to the type of the instruction provided from the memory controller, the processing operation of the data provided from the memory controller can be performed, or the data stored therein can be read, and the processing operation for reading the data can be performed, and The processed data can then be provided to the memory controller. In this case, since the bandwidth between the semiconductor memory device and the memory controller is occupied, there may be a problem in that the use efficiency of the channel is reduced and the power consumption is increased.

SUMMARY OF THE INVENTION The present invention is directed to a memory device, and a method of operating a memory device, employing an internal processing channel shared between at least two groups of memory cells for at least the memory device The memory cells of the two memory cell groups perform internal processing operations.

In accordance with an aspect of the present invention, a memory device is provided that includes a buffer die having an internal command generator that is assembled to receive from an external memory controller for Performing, by the memory device, a first external command of the at least one internal data processing operation, and in response to the receiving, generating at least two internal instructions for causing the memory device to perform the corresponding The internal memory operates to perform the at least one internal data processing operation; a first core die and a second core die stacked with the buffer die, the first and second core die Each of the plurality of dynamic random access memory (DRAM) cells, the DRAM cells being arranged into at least a first memory cell group of the first core die and the second core crystal a second group of memory cells of the granule; a plurality of through-via vias (TSVs) extending through the first and second core dies and thereby coupled to the buffer dies; each of the first and Second memory At least two independent channels associated with a corresponding one of the cell groups, each of the at least two independent channels including a corresponding set of the TSVs; and the first and second core dies in the first and second core dies A shared internal processing channel shared between the first and second memory cell groups.

According to another aspect of the inventive concept, a memory device is provided, comprising: a buffer die having an internal command generator, configured to be received from an external memory controller for use by the memory The device performs a first external command of the at least one internal data processing operation, and in response thereto, generates at least two internal instructions for causing the memory device to perform a corresponding internal memory operation to perform the at least An internal data processing operation; at least one core die stacked with the buffer die, the at least one core die having a plurality of dynamic random access memory (DRAM) cells arranged in a plurality of memory cell groups; a plurality of through-via vias (TSVs) extending through the at least one core die are coupled to the buffer die; and at least two independent channels each associated with a corresponding one of the groups of memory cells, The at least two independent channels each include a corresponding set of the TSVs, wherein the TSVs when the memory device performs the at least one internal data processing operation Most part of such lines by the memory cells of the group at least at least two-membered share.

According to still another aspect of the present invention, a memory device includes: a plurality of dynamic random access memory (DRAM) cells arranged in a plurality of memory cell groups; and each of the plurality of memory cells a plurality of independent channels associated with one of the meta-groups; an internal command generator configured to receive at least one first external command from an external memory controller for performing at least one internal data by the memory device Processing operations, and in response thereto for generating at least two internal instructions for causing the corresponding memory operations to be performed to perform the at least one internal data processing operation; and sharing between the plurality of memory cell groups Shared internal processing channels.

According to still another aspect of the present invention, a method includes receiving an external command in a memory device, the memory device including a plurality of dynamic random access memories arranged in at least two groups of memory cells (DRAM) cells, at least two independent channels each associated with a corresponding one of the at least two memory cell groups, and one shared between the at least two memory cell groups Sharing an internal processing channel; determining, in response to the external command, whether at least one internal data processing operation is performed by the memory device; and when determining that the at least one internal data processing operation is performed by the memory device: generating at least two internal instructions The at least one internal data processing operation is performed to cause the corresponding memory operation to be performed, and one or more of the plurality of memory cell groups are selected to perform the memory operations.

According to still another aspect of the present invention, a method is provided, comprising: receiving an external command in a memory device, the memory device comprising a plurality of dynamic random accesses arranged in at least two groups of memory cells Memory (DRAM) cells, each of at least two independent channels associated with a corresponding one of the at least two memory cell groups, and shared between the at least two memory cell groups a shared internal processing channel; determining, in response to the external command, whether the external command is a normal command or an instruction for performing at least one internal data processing operation by the memory device; when determining that the memory device performs the During at least one internal data processing operation, the at least one internal data processing operation is performed by a shared internal processing channel shared by at least two memory cell groups; and when determining whether the external command is a normal command, The normal instruction is executed by one of a plurality of independent channels associated with a corresponding one of the at least two memory cell groups.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the inventive concept will be exemplified in detail with reference to the accompanying drawings.

1 is a block diagram illustrating one embodiment of a memory system.

Referring to FIG. 1, the memory system 10A may include a memory controller 100A and a memory device 200A. The memory controller 100A includes a memory interface 110A and controls memory operations such as writing, reading, etc. by providing various types of signals to the memory device 200A through the memory interface 110A. For example, the memory controller 100A accesses the data DATA of the memory cell array 210A by providing the instruction CMD and the address ADD to the memory device 200A. The instruction CMD may include instructions for normal memory operations such as data writing, data reading, and the like. Again, the instruction CMD can include an instruction to request the memory device 200A to perform an internal data processing operation that can include a series of memory operations.

The memory controller 100A can access the memory device 200A in response to a request from the host HOST. The memory controller 100A can communicate with the host using various protocols. For example, the memory controller 100A can communicate with the host using interface protocols such as Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA). Or Small Computer System Interface (SCSI) (SAS). In addition, various other interface protocols, such as Universal Serial Bus (USB), MultiMediaCard (MMC), Enhanced Small Disc Interface (ESDI), Integrated Drive Electronics (IDE), etc., can be applied to the host and memory controllers. Agreement between 100A.

The memory device 200A may include a memory cell array 210A, an internal shared bus 220A, and an internal command generator 230A. Again, the memory device 200A can include n independent channels, and in this case, the memory device 200A can include n independent interfaces corresponding to n independent channels. In other words, the independent channels can include separate interfaces, and thus each of the individual channels can operate in the same manner as individual memory devices.

According to one embodiment, the memory device 200A can include an independent signal transmission path for each of the independent channels, and thus an independent signal transmission path that can implement a delivery instruction/address for each of the independent channels, and An independent signal transmission path for delivering data can also be implemented for each of the independent channels.

The memory cell array 210A can include a majority of memory cell groups corresponding to a plurality of independent channels. For example, when the memory device 200A includes n independent channels, the memory cell array 210A may include n memory cell groups Cell_CH1 to Cell_CHn.

Meanwhile, when the memory device 200A has a structure in which a plurality of layers are stacked, the memory device 200A may include one or more layers each including a memory cell. This layer, including memory cells, may be referred to as core grains, and each core grain may comprise separate independent channels or groups of memory cells. Further, a single core dies may comprise two or more independent channels or groups of memory cells, and in this case, the core dies may comprise a majority of independent independent channels or groups of memory cells. interface.

Meanwhile, the memory device 200A may be a dynamic random access memory (DRAM) such as double data rate synchronous DRAM (DDR SDRAM), low power DDR (LPDDR) SDRAM, graphics DDR (GDDR) SDRAM, and a memory bus ( Rambus) DRAM (RDRAM) and the like. However, the embodiments are not limited thereto, and for example, the memory device 200A may be embodied as a non-electrical memory such as a flash memory, a magnetic RAM (MRAM), a ferroelectric RAM (FeRAM), a phase. Variable RAM (PRAM), resistive RAM (ReRAM), etc.

At the same time, internal shared bus 220A may include a bus shared by a majority of memory cell groups for implementing a shared internal processing channel shared by a majority of memory cell groups. For example, one or more types of signals may be provided to a majority of memory cell groups through a common internal processing channel provided by internal shared bus 220A. The internal shared bus 220A may include a shared data bus that collectively provides information to a majority of memory cell groups. Again, internal shared bus 220A can include a shared instruction bus that collectively provides internal instructions to a majority of memory cell groups. According to one embodiment, data for any one of the memory cell groups may be provided to one or more other memory cell groups via a shared internal processing channel provided by internal shared bus 220A.

According to one embodiment, when the busbars shared by the majority of memory cell groups are not already present in the memory device 200A, the internal shared busbar 220A may be further added for delivery of memory in addition to any existing busbars. Instructions/data in device 200A. On the other hand, since the test block having the direct access (DA) mode can be provided in the memory device 200A, when the bus bar shared by the majority of the memory cell group is already present in the test block, The internal shared bus 220A may correspond to a portion of an existing bus that is shared by a majority of the memory cell groups.

The internal command generator 230A can generate various types of internal instructions related to the operation of the memory, and provide the generated internal instructions to the memory cell group of the memory device 200A through the shared internal processing channel. For example, various types of instructions may be defined between memory controller 100A and memory device 200A, and instructions for performing normal memory operations, such as writing, reading, etc., may be defined. According to one embodiment, in normal memory operations, instructions and addresses can be independently delivered to respective groups of memory cells in memory device 200A through their respective counterparts in separate channels.

Meanwhile, taking the specific command CMD as an example, the memory device 200A can perform an internal data processing operation in which most of the memory operations can be performed in response to a specific command string. The internal command generator 230A can generate a plurality of internal instructions to sequentially perform a majority of memory operations in response to receiving a specific command CMD from the memory controller 100A. Further, when the internal data processing operation is performed, at least one of the instructions and the data can be delivered to the memory cell group through the shared internal processing channel provided by the internal shared bus 220A, and thus the internal data processing operation During the process, the internal shared bus 220A can form a transmission path of internal instructions/data between the majority of the memory cell groups.

In order to improve the performance of the memory device 200A, various types of internal data processing operations can be performed. For example, since a segment occurs in the cell region of the memory device 200A, one portion of the memory cell region becomes smaller than the smallest cell for writing data, and thus the portion of the memory cell region cannot be used. . In this case, since the data copying operation is performed, a continuous free memory space can be obtained in the memory cell region of the memory device 200A, and thus a more efficient use of the memory can be obtained.

In order to perform the aforementioned internal data processing operation, a copy instruction CMD for copying data stored at one location of the memory device 200A to another location may be defined. When the memory device 200A receives the copy command CMD from the memory controller 100A, the internal command generator 230A can generate a series of internal instructions for data copying. When the data of the first memory cell group Cell_CH1 is copied into the second memory cell group Cell_CH2, the memory device 200A may generate internal instructions for reading the data of the first memory cell group Cell_CH1 and An internal command for writing the read data to the second memory cell group Cell_CH2. Further, the data read from the first memory cell group Cell_CH1 can be delivered to the memory cell group Cell_CH2 through the internal shared bus 220A.

In a conventional manner, since the memory device 200A has a general structure in which individual independent channel interfaces for respective memory cell groups are independent, for the data copying operation, reading from the first memory cell group Cell_CH1 The data must be supplied to the memory controller 100A through the communication path of the first channel CH1 corresponding to the memory cell group Cell_CH1, and the memory controller 100A must communicate through the second channel CH2 of the corresponding memory cell group Cell_CH2. The path provides the received data to the memory device 200A. On the other hand, according to an embodiment, the memory operation for one of the data copies can be performed by the internal material processing operation of the memory device 200A without the intervention of the memory controller 100A.

Accordingly, in the memory system 10A, data processing bandwidth and energy efficiency can be improved, and internal power consumption and operating speed and system performance can be improved.

Meanwhile, the data copying operation is exemplified in the foregoing embodiment, but the embodiment is not limited thereto. For example, in various types of memory operations, such as data movement, data exchange, read-correction-write (RMW), mask writing, etc., data can be transmitted and received between groups of memory cells. And the memory operations as described above can be performed by internal data processing operations using internal command generation and shared internal processing channels provided by the internal shared bus 220A of the memory device 200A.

2 is a block diagram illustrating another embodiment of a memory system. In FIG. 2, a data processing system 10B including an application processor 100B and a memory device 200B, and a memory control module 110B included in the application processor 100B and the memory device 200B are constituting a memory system. Further, the memory device 200B may include a memory cell array 210B, an internal shared bus 220B, and an internal command generator 230B.

The application processor 100B can function as a host in FIG. Again, the application processor 100B can be embodied as a single chip system (SoC). The SoC may include a system bus (not illustrated in the figure) to which the agreement with predetermined standard busbar specifications is applied, and may include various types of intellectual property (IP) cores that are linked to the system bus. As for the standard specifications of the system bus, the Advanced Microcontroller Bus Queue (AMBA) agreement of the advanced RISC machine (ARM) holding company can be applied. Advanced High Efficiency Bus (AHB), Advanced Peripheral Bus (APB), Advanced Derivable Interface (AXI), AXI4, AXI Coherent Extension (ACE), etc. can be included as a type A confluence of the AMBA agreement. row. In addition, other types of protocols may be applied, such as uNetwork by Sonics Inc., CoreConnect of IBM, and Open Core Agreement of the Open Core Agreement International Partnership Association (OCP-IP).

The memory control module 110B can perform the functions of the memory controller in the foregoing embodiment. Further, the memory device 200B can perform various types of memory operations through internal processing operations without the intervention of the memory control module 110B. For example, the memory device 200B can perform data reading and writing operations by generating internal instructions, and the data can be shared among the majority of the memory cell groups through the shared internal processing channel provided by the internal shared bus 220B. Transmit and receive.

FIG. 3 is a block diagram illustrating a specific embodiment of the application processor 100B of FIG. 2.

Referring to Figures 2 and 3, the application processor 100B can include a plurality of IP cores coupled by a system bus 150B. The application processor 100B may include, for example, a memory control module 110B, a data processor 120B, a central processing unit (CPU) 130B, and an embedded memory 140B. The CPU 130B can control various types of operations of the IP cores within the application processor 100B, and the data processor 120B is a processor for wireless communication with a base station or other communication device.

At the same time, the memory control module 110B can communicate with the memory device 200B placed outside the application processor 100B through a plurality of independent channels corresponding to the majority of the memory cell groups Cell_CH1 to Cell_CHn of the memory device 200B. Moreover, the memory control module 110B can communicate with the embedded memory 140B through the system bus 150B. The embedded memory 140B may also be implemented in the same or similar manner as the memory device 200B according to the foregoing embodiment, and thus the embedded memory 140B may be generated by an internal shared bus (not illustrated in the figure) and internal instructions. Common internal processing channels provided by the device (not shown in the figure).

4 is a block diagram illustrating another embodiment of a memory system.

Referring to FIG. 4, the memory system 10C can include a memory controller 100C and one or more memory modules 201C. Each of the memory modules 201C includes a module board on which one or more memory devices 200C are mounted. Furthermore, the memory module 201C can be embodied in the form of a single column memory module (SIMM) or a dual column memory module (DIMM).

The aforementioned independent channels can be defined in various ways. According to one embodiment, one or more of the memory modules 201C may include one or more of the aforementioned independent channels. For example, each of the memory modules 201C can include a single one of the independent channels. In addition, a plurality of memory devices 200C can be mounted on each of the memory modules 201C, and each of the memory devices 200C can include a single one of the independent channels. Additionally, each of the memory devices 200C can include a plurality of memory cell groups, and each of the memory devices 200C can include a plurality of independent channels corresponding to the plurality of memory cell groups. .

According to one embodiment, memory system 10C may include an internal shared bus (not illustrated in the figures) for implementing a common internal processing channel. When each of the memory modules 201C includes a single one of the independent channels for a single memory cell group, the bus bars shared by the majority of the memory modules 201C may be embodied. In addition, when each of the memory devices 200C includes a single one of the independent channels for a single memory cell group, the majority memory can be implemented in each of the memory modules 201C. The busbars shared by the body device 200C. Additionally, when each of the memory devices 200C includes a plurality of independent channels for a corresponding majority of memory cell groups, the bus bars shared by the majority of the memory cell groups can be in the memory devices 200C. Each of them is implemented internally.

5 and 6 are block diagrams illustrating the configuration of a specific embodiment of a memory device.

Referring to FIG. 5, the memory device 300A may include a plurality of independent channels for corresponding majority memory cell groups Cell_CH1 311A to Cell_CH4 314A. Each of the memory cell groups Cell_CH1 311A to Cell_CH4 314A can be defined in various ways. For example, each of the memory cell groups Cell_CH1 311A through Cell_CH4 314A can include a cell region and can be defined to further include one or more components associated with memory operations. For example, each of the memory cell groups Cell_CH1 311A to Cell_CH4 314A may include a column of decoders, a row of decoders, a sense amplifier, an instruction decoder, and the like.

Further, the memory device 300A may further include an internal shared bus 320A, an internal command generator 330A, and a data processor 340A for implementing a shared internal processing channel. The internal shared bus 320A may have a signal transmission path shared by the majority of the memory cell groups Cell_CH1 311A to Cell_CH4 314A, and may deliver, for example, data for the majority of the memory cell groups Cell_CH1 311A to Cell_CH4 314A. For example, the first memory cell group Cell_CH1 311A may output the first data Data_1 to the internal shared bus 320A, and the first data Data_1 may be provided through a shared internal processing channel provided by the internal shared bus 320A. Another group of memory cells. Similarly, the fourth memory cell group Cell_CH4 314A can output the fourth data Data_4 to the internal shared bus 320A, and the fourth data Data_4 can be provided to the other through the shared internal processing channel provided by the internal shared bus 320A. A group of memory cells.

The internal command generator 330A can generate a plurality of internal instructions ICMD_1 to ICMD_4 in accordance with an instruction CMD from the memory controller. For example, separate signal transmit paths for internal instructions may be implemented for most memory cell groups Cell_CH1 311A through Cell_CH4 314A, and thus internal command generator 330A may provide internal instructions ICMD_1 through ICMD_4 to memory through independent paths. The cell group is Cell_CH1 311A to Cell_CH4 314A.

At the same time, the data processor 340A can be coupled to the internal shared bus 320A, receive the data delivered through the internal shared bus 320A, and perform internal data processing operations on the received data. For example, the data processor 340A can perform a latch operation, a calculation operation, and the like on the data, and output the processed data to the internal shared bus 320A.

The internal command generator 330A can generate various types of internal instructions ICMD_1 to ICMD_4. For example, the internal command generator 330A may generate internal instructions ICMD_1 to ICMD_4 for performing internal position change, internal position modification, comparison operation, and the like. Further, the internal command generator 330A can generate internal commands ICMD_1 to ICMD_4 for performing RMW, data exchange between memory cell groups, mask writing, and the like.

The data processor 340A can perform various types of functions related to the aforementioned internal material processing operations. For example, when performing a data copy operation or a data exchange operation, a function of temporarily storing data read from any one of the memory cell groups can be performed. In addition, when an RMW operation or a mask write operation is performed, a bit comparison operation of the material can be performed, and the bit comparison operation can be performed in the data processor 340A.

When the memory device 300A has a structure in which a buffer die and a multi-core die are stacked, the internal shared bus 320A can be disposed in the buffer die and can be transmitted and received between the majority of the memory cell groups. data. Additionally, a plurality of through-via vias (TSVs) for electrically connecting the buffer die to the core dies can be placed, and the internal shared busbar 320A can correspond to one or more TSVs that deliver data. In particular, each group of memory cells on the core dies may have separate channels for communicating therewith, and the individual channels may each comprise a corresponding set of TSVs.

Further, the internal command generator 330A and the data processor 340A can be embodied in various ways. For example, internal command generator 330A can be included in the buffer die. Again, data processor 340A can be included in each of the buffer die or core die.

Meanwhile, referring to FIG. 6, the memory device 300B may include a majority of memory cell groups Cell_CH1 311B to Cell_CH4 314B, first and second internal shared bus bars 320B and 350B, an internal command generator 330B, and a data processor 340B. The busbars shared by the majority of the memory cell groups Cell_CH1 311B to Cell_CH4 314B, the first internal shared bus 320B may correspond to a shared data bus, and are also shared by the majority of the memory cell groups Cell_CH1 311B to Cell_CH4 314B. The bus bar, the second internal shared bus bar 350B, can correspond to a shared data bus. The internal instructions ICMD<1:4> for the majority of the memory cell groups Cell_CH1 311B to Cell_CH4 314B generated in the internal command generator 330B can be delivered through the second internal shared bus 350B, and the memory cell group The data Data<1:4> of Cell_CH1 311B to Cell_CH4 314B may be delivered through the first internal shared bus 320B. The first and second internal shared busses 320B and 350B together provide a shared internal processing channel to the memory device 300B.

In the embodiment illustrated in FIG. 6, the second internal shared bus bar 350B can be embodied in various manners. For example, the second internal shared bus 350B can be placed in the buffer die and can transmit and receive internal commands between a plurality of memory cell groups. Additionally, a plurality of TSVs for electrically connecting the buffer die and the core die can be placed, and the second internal shared bus bar 350B can correspond to one or more TSVs of the delivery command.

7, 8A, and 8B are flow diagrams illustrating a specific embodiment of a method of operating a memory device. The memory device can include a plurality of independent channels corresponding to a plurality of memory cell groups, and a shared internal processing channel shared by the plurality of memory cell groups.

Referring to Figure 7, the memory device receives an instruction from an external memory controller (S11). Each type of command can be set between the memory controller and the memory device, and portions of the instructions can correspond to instructions that cause the memory device to perform an internal data processing operation, which can include two or more internal memory operations.

The memory device can determine whether a predetermined internal material processing operation is required by the decoding operation for the received instruction (S12). When it is determined that it is not necessary to perform the internal data processing operation in which most of the memory operations are sequentially performed, the memory device can perform an operation of the instruction for the external memory controller by performing the normal memory operation (S13).

On the other hand, according to a specific instruction received from the memory controller, the memory device can sequentially generate two or more internal instructions (S14). Further, the plurality of memory cell groups can perform mutually different memory operations according to internal instructions, and thus the memory device can generate a memory cell group selection signal corresponding to the individual internal instructions (S15).

Each of the internal instructions and the memory cell group selection signal generated in the memory device can be provided to the corresponding memory cell group. The selected group of memory cells can perform a memory operation according to the received internal command, and output a result according to the memory operation (for example, according to the data of the read operation) (S16). Further, the data processed according to the memory can be transmitted and received between the groups of memory cells by a shared internal processing channel provided by the internal shared bus (S17), and, for example, in any one of the memories The data provided in the cell group can be provided to another memory cell group through a shared internal processing channel provided by the internal shared bus. The group of memory cells receiving the data can perform memory operations using the received data according to internal instructions.

8A and 8B illustrate an example of data delivery when a memory device includes a plurality of layers.

The memory device can include a plurality of layers, and each of the layers can be a die corresponding to a different group of memory cells. For example, a memory device can include a single buffer die and a majority of core die.

A plurality of internal instructions are generated according to an instruction received from the memory controller, and the memory device performs an internal data processing operation according to the internal instructions. The operation in which the data is read from the first core die can be performed according to any of the internal instructions (S21).

In order to perform various types of internal processing programs, such as data copying, data exchange, RMW, mask writing, etc., an internal data processing operation for reading data can be performed (S22). For example, a temporary latching operation for reading data can be performed as the internal data processing operation. In addition, a comparison operation for reading data and various types of data such as writing data, mask data, and the like can be performed as an internal data processing operation. The circuitry for processing the data can be embodied in a variety of ways, and, by way of example, circuitry for processing the data (eg, a data processor) can be implemented separately in the core die or by implementation in the buffer die. Most core dies are shared.

According to one embodiment, the processed data may be delivered through a shared internal processing channel provided by an internal shared bus, and the processed data may be delivered to another core die (eg, a second core die) (S23). In other words, the data can be transmitted and received between different core dies through a shared internal processing channel provided by an internal shared bus.

Meanwhile, referring to FIG. 8B, when the internal material processing operation is performed in accordance with an instruction from the memory controller, an operation in which data is read from the first core die can be performed (S31). Moreover, the write data for the RMW, the mask write, and the like can be received from the memory controller (S32), and the memory device can use the read data from the first core die and the received write data. The calculation processing is performed (S33). Similar to the previous embodiment, the computational processing using the read data and the received write data can be performed in the first core die, in another core die, or in the buffer die.

The calculation result may be provided to the first core die through a shared internal processing channel provided by the internal shared bus bar, or to the second core die having a different memory cell group than the first core die (S34) ). According to the foregoing operation, a series of operations for internal data processing operations can be performed in a plurality of dies, and the result of the calculation process can be shared by the internal shared busbars shared by the groups of memory cells. Processing channel transmission and reception.

Hereinafter, an embodiment in which the memory devices each include a plurality of layers (for example, a plurality of crystal grains) having a stacked structure, and an internal data processing operation of each type in a memory device having a stacked structure will be described later. Detailed.

Figure 9 is a block diagram illustrating one embodiment of a memory device having a stacked structure. In FIG. 9, a memory device in the form of a high frequency wide memory (HBM) is illustrated that has an increased bandwidth by including a plurality of independent channels having independent interfaces for a corresponding majority of memory cell groups.

Referring to Figure 9, memory device 400 can include a plurality of layers. For example, the memory device 400 can include a buffer die 410 and one or more core dies 420 stacked on the buffer die 410. In the example of FIG. 9, although the first to fourth core crystal grains 421 to 424 are illustrated as being provided, the number of core crystal grains may be varied differently.

Also, core dies 420 can each include one or more groups of memory cells. In the example of FIG. 9, single core die 420 includes two groups of memory cells, and thus is illustrated in an example in which memory device 400 has eight memory cell groups Cell_CH1 through Cell_CH8. For example, the first core die 421 may include a first memory cell group Cell_CH1 and a third memory cell group Cell_CH3, and the second core die 422 may include a second memory cell group Cell_CH2 and The fourth memory cell group Cell_CH4, the third core crystal 423 may include a fifth memory cell group Cell_CH5 and a seventh memory cell group Cell_CH7, and the fourth core die 424 may include a sixth memory. The cell group Cell_CH6 and the eighth memory cell group Cell_CH8.

The buffer die 410 is in communication with the memory controller, receives instructions, addresses, and data from the memory controller, and provides received instructions, addresses, and data to the core die 420. The buffer die 410 can communicate with the memory controller through a conductive member (not shown) formed on its outer surface, such as a bump or the like. Buffer die 410 can buffer instructions, addresses, and data, and thus the memory controller can interface with core die 420 by driving only the load of buffer die 410.

Again, memory device 400 can include a plurality of TSVs 430 extending through the layers. The TSV 430 may be placed corresponding to a majority of the memory cell group Cell_CH1 to the memory cell group Cell_CH8, and when the independent channels for the corresponding memory cell group each have a 128-bit bandwidth, the TSV 430 can include components for inputting and outputting 1024-bit data.

According to one embodiment, as described in the previous embodiments, at least a portion of the TSVs 430 can be used as an internal shared bus for sharing internal processing channels. For example, the TSV 430 can be configured to extend through the first through fourth core dies 421 through 424, and the first through fourth core dies 421 through 424 can each include a transmitter/receiver coupled to the TSV 430. In the ordinary operation in which the input and output of data are independently performed for each memory cell group, only the transmitter/receiver of any one of the core dies can be enabled for each of the TSVs 430, and Thus, each of the TSVs 430 can independently deliver data for any one of the core dies, any one of the memory cell groups as an independent channel for the one core dies or group of memory cells.

Meanwhile, according to an embodiment, when the TSV 430 is used as the aforementioned internal shared bus for sharing internal processing channels for internal data processing operations, such as data copying, data exchange, etc., in the case of each of the TSVs 430 The transmitter/receiver of the two or more core dies may be enabled sequentially or simultaneously, and thus the data may be transmitted and received between the at least two groups of memory cells.

Buffer die 410 may include an internal command generator 411, a TSV zone 412, a physical (PHY) zone 413, and a DA zone 414. In accordance with the foregoing embodiments, internal command generator 411 can generate internal instructions and provide the generated internal instructions to core die 420 via TSV 430. The TSV region 412 is a region formed by the TSV 430 used to communicate with the core die 420. Moreover, the physical area 413 is an area including a plurality of input and output (IO) circuits for communicating with the external memory controller, and various types of signals from the memory controller are provided to the TSV area 412 through the physical area 413, and The core die 420 is provided by the TSV 430.

At the same time, the DA zone 414 can communicate directly with the external tester for the test mode of the memory device 400 via conductive members placed on the outer surface of the memory device 400. The various types of signals provided by the tester can be provided to the core die 420 through the DA zone 414 and the TSV zone 412. Additionally, as a modifiable embodiment, various types of signals may be provided from the tester to the core die 420 through the DA zone 414, the physical zone 413, and the TSV zone 412.

Figure 10 is a schematic illustration of an illustration of an internal processing operation illustrated in the memory device of Figure 9.

Referring to Figures 9 and 10, the buffer die 410 includes an internal command generator 411, and internal instructions from the internal command generator 411 are provided to the core die by an instruction TSV TSV_cmd generated independently for each memory cell group. 420. The buffer die 410 can control the memory operation of the core die 420 by outputting internal instructions.

At the same time, the core die 420 can include the instruction decoders 421_1 to 424_1 to output internal control signals by decoding internal instructions, and the data processors 421_2 to 424_2 to perform processing operations of reading data and/or writing data.

Referring to any of the core dies (eg, the first core die 421), the first core die 421 can perform a memory operation according to the decoding result of the instruction decoder 421_1, and, for example, is stored in the first core dies. The data of most of the bits in the internal memory cell area of 421 can be read and provided to the data processor 421_2. The data processor 421_2 can process the data of a plurality of bits in parallel, and output the data processed in parallel to the majority data TSV TSV_data in parallel.

According to the one-type memory operation, the data processor 421_2 can temporarily store the read data and output the stored data to the data TSV TSV_data. Moreover, according to the control of the instruction decoder 421_1, the data from the data processor 421_2 can be provided to at least one of the other core dies via the data TSV TSV_data. When the internal data processing operation is performed, the data of the first core die 421 is copied into the second core die 422, and the data from the data processor 421_2 can be supplied to the second core die 422 through the data TSV TSV_data.

Figure 11 is a block diagram illustrating an embodiment of a data copying operation performed in one embodiment of a memory device. In the following, for the convenience of description, the operation of a single buffer die and two core dies is illustrated. Further, the processor in the memory illustrated in the following embodiments can perform the instruction decoding function in the foregoing embodiment. Moreover, the processor in memory can further provide a function in which a wafer select signal chip_select for selection of a memory cell group or wafer is provided in accordance with an internal data processing operation. According to a modified embodiment, the wafer select signal chip_select exemplified in the following figures can be implemented to be generated by respective instruction decoders of the core dies.

Referring to FIG. 11, the memory device 500 can include a buffer die 510 and first and second core dies 520 and 530. The first core die 520 can include an A-th channel CH A for the A-th memory cell core or group 521, and the second core die 530 can include a B-th memory cell core or group 531. The B channel CH B.

The buffer die 510 can communicate with the memory controller to generate internal instructions for performing a series of internal data processing operations in response to specific instructions from the memory controller, and provide the internal instructions to the first And the second core dies 520 and 530, while changing the wafer selection signal chip_select for selecting the core dies. Moreover, data can be transmitted and received between the buffer die 510 and the first and second core dies 520 and 530, and the TSV for transmitting and receiving data can be commonly placed in the buffer die 510 and One and second core dies 520 and 530.

The buffer die 510 can include a plurality of input/output (I/O) circuitry to independently interface the A and B channels for the first and second core dies 520 and 530. For example, the buffer die 510 may include an I/O circuit that interfaces with the first core die 520 for the A channel CH A for the A memory cell core or group 521, and The I/O circuit of the second core die 530 for the B-th channel CH B for the B-th memory cell core or group 531 is connected. The various components of each of the I/O circuits can be placed in at least one region of the buffer die 510, and, for example, components of each of the I/O circuits can be placed Physical area.

Buffer die 510 can include a memory-in-process processor 511 for generating internal instructions in accordance with the foregoing embodiments. According to one embodiment, the processor 511 in memory can be a component shared by a majority of memory cell groups. Moreover, the I/O circuit corresponding to each channel for each of the memory cell groups may include an interface 512 that interfaces with the memory controller, the path controller 513, the read data path 514, and the write Data path 515, and one or more latches 516.

The processor 511 in the memory can sequentially output a plurality of internal instructions, thereby performing internal data processing operations in accordance with instructions from the memory controller. Moreover, each of the core dies can perform a predetermined function according to an internal command, and the processor 511 in the memory can select the core dies in which the chip select signal chip_select is to be output according to the function of the internal command. The first and second core dies 520 and 530 can include transceivers 525 and 535, respectively, through the data TSV input and output data, and the transceivers of each of the core dies can be controlled to be selected by the wafer. The signal chip_select is enabled.

Meanwhile, the first core die 520 may include an A-th memory cell core or group 521 including a cell region, an instruction decoder 522 that decodes internal instructions, a write data path 523, a read data path 524, And transceiver 525. Also, the first core die 520 can further include a circuit for performing predetermined processing on the written data and/or the read data. For example, one of the data processors 526 that performs the processing of controlling the delivery of data or temporarily storing the data is exemplified in FIG. The data processor 526 can include a latch and a switch for controlling electrical connection to the data TSV.

The second core die 530 can be implemented in the same or similar manner as the first core die 520, and thus the second core die 530 can include a B-th memory cell core or group 531, an instruction decoder 532, The data path 533, the read data path 534, the transceiver 535, and the data processor 536 are written. Data processor 536 can also include latches and switches.

An internal data processing operation for copying data of the second core die 530 into the first core die 520 may be performed according to an instruction from the external memory controller, and the internal processing program may be borrowed from the memory device 500 Internal generation of internal instructions is performed without the intervention of the memory controller. For example, the buffer die 510 can provide internal instructions to the second core die 530, and the second core die 530 can read data in response to received internal instructions and by using data as an internal shared bus. The TSV provides the read data to the first core die 520. Moreover, the buffer die 510 can provide internal instructions to the first core die 520, and the first core die 520 can write the data received through the data TSV in response to an internal command to the A memory cell core or Group 521. As such, the data of the second core die 530 can be copied into the A-th cell core or group 521 of the first core die 520.

According to a modified embodiment, the data read from the second core die 530 can be stored in the latch of the data processor 536, and the data stored in the latch of the data processor 536 can be provided to the first through the data TSV. Core die 520.

According to the foregoing embodiment, even when performing a memory operation in which data is moved between different core dies or groups of memory cells, the copying operation of the data between the groups of memory cells can be performed by the memory. The internal data processing operation of device 500 proceeds without the intervention of a memory controller.

12A and 12B are block diagrams illustrating an embodiment of a data exchange operation in one embodiment of a memory device. Since the components of the memory device 500 illustrated in FIG. 12A are the same as or similar to those of the memory device 500 of the foregoing embodiment of FIG. 11, a repetitive description of the components illustrated in FIG. 12A will be deleted.

Referring to FIGS. 12A and 12B, internal data processing operations for exchanging data of the first core die 520 and data of the second core die 530, and the buffer die 510 may be performed in accordance with an instruction from the external memory controller. A series of internal instructions for data exchange can be generated and the serial internal instructions are provided to the first and second core dies 520 and 530. In addition, the processor 511 in the memory can select a core die, which will perform a function according to internal instructions by using the output chip select signal chip_select.

As an example of an internal data processing operation for exchanging data, referring to FIG. 12B, first, the data corresponding to the first core die 520 of the first channel CH A, that is, the A memory cell core or group 521 The data is read according to an internal command (CH A RD), and the read data is stored in a latch of the data processor 526 of the first core die 520. After the data of the first core die 520 is stored in the latch of the data processor 526, the switch of the data processor 526 can be closed to block the electrical connection (CH A lat_off) of the latch and the data TSV of the delivery material.

Moreover, the data corresponding to the second core die 530 of the second channel CH B, that is, the data of the B memory cell core or the group 531 is read and read according to the internal command (CH B RD). The data from the second core die 530 is supplied to the first core die 520 through the data TSV used as the internal shared bus. Further, the data supplied to the first core die 520 is written to the A-th memory cell core or group 521 of the first core die 520 in accordance with an internal command (CH A WR). Then, when the switch of the data processor 526 of the first core die 520 is turned on (CH A lat on), the data read from the first core die 520 is supplied to the data TSV as the internal shared bus bar. The two core die 530, and the data provided to the second core die 530, are written to the Bth memory cell core or group 531 of the second core die 530 according to an internal command (CHBWR).

As described above, even when data is exchanged between different groups of memory cells, data read from any one of the memory cell groups can be supplied to another memory cell through a shared internal processing channel provided by the internal shared bus. The meta-group without the intervention of the memory controller, and thus the exchange of data between the groups of memory cells, can be performed by internal data processing operations of the memory device without increasing the frequency of access by the system to the memory device.

13A through 13C are block diagrams illustrating an embodiment in which an RMW operation is performed in one embodiment of a memory device. Since the components of the memory device 600 illustrated in FIG. 13A are the same as or similar to those of the memory device 500 of the foregoing embodiments of FIGS. 11, 12A and 12B, the respective repetitive descriptions of the components illustrated in FIG. 13A will be deleted.

Referring to FIGS. 13A through 13C, the memory device 600 can include a buffer die 610 and first and second core dies 620 and 630 as one or more core dies, first and second core dies 620 and 630. Different channels may be included, channel A and channel B, respectively, and corresponding memory cell cores or groups 621 and 631, and buffer die 610 may include I/O circuits corresponding to individual channels. The buffer die 610 can include a processor 611 in memory, and each of the I/O circuits can include an interface 612, a path controller 613, a read data path 614, a write data path 615, and one or more latches. Lock 616. The processor 611 in the memory can perform various control functions related to internal data processing operations, and by way of example, the processor 611 in the memory can perform an operation of generating an internal command. Moreover, the processor 611 in the memory can further generate a chip select signal chip_select for selecting a core die, and the core die will perform a memory operation according to an internal instruction.

Moreover, the first core die 620 can include a memory cell core or group 621 including a cell region, an instruction decoder 622 that decodes internal instructions, a write data path 623, a read data path 624, and a transceiver. 625. Also, the first core die 620 can include a memory in-processor (PIM) functional block 626 that performs computational processing on the data to be written and/or read data. For most of the bits, accesses such as data writes, data reads, etc. to the memory cell core or group 621 can be performed in parallel, and thus most of the transceivers 625 and most of the PIM functional blocks corresponding to most of the transceivers 625 626 can be included in the first core die 620.

In one embodiment, the operation of PIM function block 626 can be controlled in various ways, and, for example, PIM function block 626 can be controlled by PIM control signal PIM_ctrl based on the decoding result of the internal instructions.

Moreover, the second core die 630 can be in the same or similar manner as the first core die 620, and thus the second core die 630 can include a memory cell core or group 631, an instruction decoder 632, write The data path 633, the read data path 634, the transceiver 635, and the PIM function block 636. Depending on the type of internal instructions provided to the core die, the PIM functional block 626 of the first core die 620 and the PIM functional block 636 of the second core die 630 can perform different functions from each other.

PIM functional blocks 626 and 636 can be computationally processed by various implementations. According to one embodiment, each of the PIM functional blocks 626 and 636 can include functional units that perform Boolean functions, and perform, for example, AND, OR, mutual exclusion, or (XOR), Non-(NOT) and other functions. In one embodiment, as illustrated in FIG. 13B, PIM functional blocks 626 and 636 can each include one or more switches A0 and A1, one or more latches Lat 1 and Lat 2, functional units, and buffers. A2. The functional unit can perform the aforementioned Boolean function.

As for the release of the RMW operation, when the data is written into a region of the core of the memory cell, the data stored in the region is read, and then one bit value of the data is read and one of the data to be written is read. The bit values are compared. Then, based on the comparison result, the data in which the bit value of the read data is different from the bit value of the data to be written can be selectively selected into the region of the core of the memory cell.

Referring to FIG. 13C, when the RMW operation is performed on a memory cell core of the second core die 630 or a region of the group 631, the data in the memory cell core or the region of the group 631 is read. (CH B RD), and the read data is stored in the latch Lat 1 by the first switch A0 of the PIM function block 636. After the data is stored in the latch Lat 1, the first switch A0 is turned off (A0 Off) and the second switch A1 is turned on (A1 On).

Further, the write data to be written in the memory cell core or the area of the group 631 is supplied to the second core die 630 (Data_WR) through the material TSV as the internal shared bus. Since the comparison operation for writing data is performed before the write data is written to the cell core 631, the receiver (or write buffer) can be in the off state (WR Buf Off). The write data is provided to the functional unit via the second switch A1 of the PIM function block 636. The functional unit reads the data from the memory cell core or the group 631 and writes the data for comparison. Further, the comparison result is temporarily stored in the latch Lat 2.

Based on the comparison, only a few bits of the written data can be selectively written into the memory cell core or the region of group 631. The second switch A1 can be turned off (A1 Off), the buffer A2 can be enabled (A2 On), and the data in which the bit value of the read data is different from the bit value of the data to be written can be passed. Buffer A2 is provided to the memory cell core or group 631. Accordingly, a write operation for a number of bits of the write data can be selectively performed (CH B WR).

14A and 14B are block diagrams illustrating an embodiment of a RMW operation performed simultaneously on two or more memory core dies in one embodiment of a memory device. Since the components of the memory device 600 illustrated in FIG. 14A are the same as or similar to those of the memory device 600 of the foregoing embodiment of FIG. 13A, the repeated description of each of the components illustrated in FIG. 14A will be deleted.

Referring to FIGS. 14A and 14B, according to the RMW operation, the write data can be simultaneously written into the first and second core dies 620 and 630, and first, can be read from the memory cell core of the second core die 630 or Group 631 data in this area (CH B RD). The data read from the memory cell core or group 631 is stored in the latch Lat 1 by the first switch A0 (refer to FIG. 13B) of the PIM function block 636. After the data is stored in the latch Lat 1, the first switch A0 is turned off (CH B A0 Off). Again, the data in the memory cell core or group 621 of the first core die 620 can be read (CH A RD). The data read from the memory cell core or group 621 is stored in the latch Lat 1 through the first switch A0 of the PIM function block 626, and the data is stored in the latch Lat 1, the first switch A0 is Off (CH A A0 Off).

Then, the second switch A1 of all channels can be turned on (All CH A1 On), and the receiver (or write buffer) of all channels can be turned off (WR Buf Off). Further, the write data is supplied to the first core die 620 and the second core die 630 (Data_WR) through the data TSV used as the internal shared bus. When the write data is supplied to the functional unit, the comparison operation of reading the data and writing the data can be performed similarly to the foregoing embodiment, and the second switch A1 of all the channels can be changed to the OFF state (All CH A1 Off).

Then, based on the comparison, at least a few bits of the write data can be written to each of the first core die 620 and the second core die 630. For example, the buffer A2 of the first core die 620 is enabled (CH A A2 On), and at least a few bits of the write data are written to the memory cell core or group of the first core die 620. 621 (CH A WR). Moreover, the buffer A2 of the second core die 630 is enabled (CH B A2 On), and at least a few bits of the write data are written into the memory cell core or group 631 of the second core die 630. (CH B WR).

According to this embodiment, when the RMW operation is performed on at least two core dies, the write data can be simultaneously supplied to the at least two core dies through the internal shared bus bar without the intervention of the memory controller, so that two The core die is simultaneously subjected to RMW operation.

15A and 15B are block diagrams illustrating an embodiment in which mask writing is performed in one embodiment of a memory device. In Figures 15A and 15B, for ease of description, only the PIM functional blocks included in the core die of the memory device are illustrated.

When mask writing is performed, the memory controller can provide write data and mask data corresponding to the written data. For example, the value of the mask data corresponding to each of the majority of the bits included in the mask data can be set to logic high or logic low, and the write operation can selectively target only the mask data. The value is carried out with a logic low. Further, when mask writing is performed, since some data blocks are maintained in the previously written state according to the mask data value, the internal reading operation can be performed before the writing operation.

Referring to FIGS. 15A and 15B, the memory device 700 can include a buffer die and one or more core dies (not illustrated in the foregoing description), and the first core die can include a first PIM functional block 720. And the second core die can include a second PIM functional block 730. The first PIM functional block 720 can include one or more switches A0 and A1, one or more latches Lat A1 and Lat A2, a buffer A2, and a multiplexer MUX A. Again, the second PIM functional block 730 can include one or more switches B0 and B1, one or more latches Lat B1 and Lat B2, a buffer B2, and a multiplexer MUX B.

A case is illustrated in which mask writing is performed in the second core dies of the corresponding channel B. First, when the mask write command is received from the memory controller, the data can be read from a cell core (CH B RD) of the second core die, and read according to the internal data processing operation of the memory device 700. The retrieved data can be stored in the latch Lat B1 of the second PIM function block 730. After the read data is stored in the latch Lat B1, the first switch B0 can be turned off (CH B B0 Off).

Also, the receiver (or write buffer) of all channels is turned off (WR Buf Off), and the write data is supplied to the memory device (Data_WR). The write data can be provided to the first core die through the data TSV corresponding to the internal shared bus, and can be stored in the latch Lat A1 of the first PIM function block 720. After the read data is stored in the latch Lat A1, the first switch A0 of the first PIM function block 720 can be turned off (CH A A0 Off).

Also, the second switches A1 and B1 of all channels can be turned on (All CH A1, B1 On), and the mask data from the memory controller can be supplied to the memory device (Data_mask). The mask data can be stored in the latch Lat A2 through the multiplexer MUX A of the first PIM function block 720, and can be stored in the latch Lat B2 through the multiplexer MUX B of the second PIM function block 730. According to one embodiment, by reversing the bit value of the mask data in the first PIM function block 720, the individual bits of the mask data can be stored in the latch Lat A2 and not inverted in the second PIM function block. The bit value of the mask data in 730, the bits of the mask data can be stored in the latch Lat B2.

Then, according to the bit value of the mask data, the write data stored in the first PIM function block 720 can be provided to the memory cell core or group of the second core die of the write target, or The read data stored in the second PIM functional block 730 can be provided to the memory cell core or group of the second core die of the write target. For example, the buffer A2 of the first PIM function block 720 can be enabled based on the bit value of the inverted mask data, and the buffer of the second PIM function block 730 according to the bit value of the mask data. B2 can be enabled.

When the bit of the mask data has a logic high and the write data is blocked from being written into the memory cell core or group, the buffer B2 of the second PIM function block 730 is logically high in response to the mask data. The read data that can be enabled, and thus stored in the second PIM functional block 730, is provided to the memory cell core or group of the second core die of the write target. In other words, the write data corresponding to the mask data having the logic height can be blocked from being supplied to the memory cell core or group of the second core die.

On the other hand, when the bit of the mask data has a logic low, the buffer A2 of the first PIM function block 720 is activated, and thus the write data supplied from the memory controller is supplied to the write target. The memory cell core or group of the second core dies. On the other hand, since the buffer B2 of the second PIM function block 730 is deactivated, the read data can be blocked from being supplied to the memory cell core or group of the second core die of the write target. .

In the foregoing embodiment, an embodiment has been described in which the data of the second core die read from the write target is stored in the second PIM function block 730 and the write data is stored in the first PIM function. Block 720, but the embodiments are not limited thereto. For example, after the data read from the second core die is stored in the first PIM functional block 720 and the written data is stored in the second PIM functional block 730, the bit according to the mask data is used. Values, write data, or read data can be selectively written into the memory cell core or group of the second core die.

In accordance with the foregoing embodiments, mask writing can be performed by internal data processing operations in memory device 700 without the intervention of a memory controller. Further, the read data and the write data used in the internal data processing operation of the mask write can be transmitted and received between the core dies through a common internal processing channel provided by the internal shared bus, and thus The data bandwidth efficiency can be improved according to the reduction of the access frequency of the memory device by the system.

Figure 16 is a block diagram illustrating a modified embodiment of one of the memory devices. In FIG. 16, an example of a memory device including a plurality of layers is illustrated, at least one of which constitutes a master die, and at least one of which constitutes a slave die.

For example, the main die and the slave die can be stacked on the substrate, and the stacked main die and the slave die can transmit and receive a signal through the TSV. Moreover, the main crystal grains and the subordinate crystal grains may be specifically implemented by the same memory processing, and each of the main crystal grains and the subordinate crystal grains may include a memory cell core or group in which the data is stored. Also, the main die can include I/O circuitry for communicating with an external memory controller.

In accordance with an embodiment, the master die may include a processor in memory that sequentially generates internal instructions for performing internal processing in accordance with instructions from the memory controller. Moreover, each of the slave dies includes a PIM functional block, and various types of operations of the data can be performed by the PIM functional block internal to the memory device in accordance with the foregoing embodiments. Moreover, at least part of the majority of the TSVs formed in the TSV area can be used as an internal shared bus, providing a common internal processing channel inside the memory device, and using the internal shared bus through the shared internal processing channel, the data can be in the main Grain and subordinate grain transmission and reception.

Hereinafter, a specific embodiment of a memory device in which internal shared busbars are placed in a buffer die (or main die) will be described.

17 and 18 are block diagrams illustrating one embodiment of a buffer die included in one embodiment of a memory device.

Similar to the previous embodiments, the memory device includes a plurality of layers, and any of the plurality of layers can be a buffer die (or main die) that communicates with an external memory controller. For example, the memory device can have the form of HBM, and the one or more core dies stacked on the snubber die can include a plurality of channels that are independent of each other. Also, by way of example, the core grains each may include two or more independent channels for two or more groups of memory cells.

The buffer die can include a physical region that interfaces with the memory controller, and a TSV region forms a plurality of TSBs therein for communicating with one or more core dies. Still further, in accordance with an embodiment, the buffer die may further comprise an internal shared busbar shared by a plurality of memory cell groups included in the core die. Each type of signal can be provided to a majority of the memory cell group through the internal shared bus, supporting a shared internal processing channel, thereby enabling one or more internal data processing operations.

In one embodiment, the buffer die may further include an internal command generator and a data processor. For example, the internal command generator may be specifically implemented as a processor in the memory in the foregoing embodiment, and the data processor may be embodied as a PIM functional block in the foregoing embodiment.

In response to instructions from the memory controller, the buffer die can generate internal instructions for internal data processing operations, and provide internal instructions generated to the memory cell group through the internal internal processing channel using the internal shared bus. . Moreover, the data processor can perform processing operations on one of the write data from the outside and one of the data read from the one or more core dies. The pre-process data and/or post-process data can be provided to the memory cell group through the internal internal processing channel using the internal shared bus.

The internal shared bus can be connected to a TSV zone by a physical zone having one of the I/O circuits corresponding to the majority of the memory cell groups. Similar to or similar to the foregoing embodiments, the memory device can perform data copying, data exchange, RMW, mask writing, etc. as internal data processing operations without the intervention of the memory controller. Again, the data can be transmitted and received between the majority of the memory cell groups using the internal shared bus through the shared internal processing channel.

Meanwhile, in the embodiment of FIG. 18, an example in which the signal transmission path of the buffer die has an order of the physical region, the TSV region, and the internal shared bus is illustrated. In this case, internal instructions from the internal command generator or data from the data processor may be provided to the core die through the internal shared bus and the TSV's TSVs without passing through the physical area.

19 and 20 are schematic views showing in detail a specific embodiment of the aforementioned buffer die illustrated in Figs. 17 and 18.

Referring to FIG. 19, the buffer die 800A of the memory device can include a TSV region 810, a physical region 820, and an internal shared bus 830. The TSV region 810 can include TSVs having separate signal transmission paths for a plurality of memory cell groups, and can provide, for example, an instruction to the core die through different instructions TSV for each memory cell group, and Different data TSVs for each memory cell group provide information to the core grains. In accordance with an embodiment, as illustrated in FIG. 19, TSV region 810 can include a TSV that delivers signals related to memory operation of a group of memory cells, and can further include use in separate tests (eg, power testing) Extra TSV.

The physical area 820 can also communicate with the external memory controller through different I/O circuits for each memory cell group, and signals from different I/O circuits for each memory cell group can be used. A corresponding TSV is provided to the group of memory cells. Moreover, the internal shared bus 830 can be commonly connected to the I/O circuits of the plurality of memory cell groups of the corresponding physical area 820.

The internal command generator 840 can generate a series of internal instructions for internal data processing operations in the memory device, and can provide the serial internal instructions to the internal shared bus 830. Internal instructions are provided to the core die through physical area 820 and TSV area 810. Further, according to the foregoing embodiment, the data processor 850 can perform data processing operations related to various types of memory operations, such as data copying, data exchange, RMW, mask writing, and the like. According to one embodiment, the data from the data processor 850 is provided to the internal shared bus 830, and the data provided to the internal shared bus 830 is provided to the core die through the physical area 820 and the TSV area 810. Further, the data read from any of the core dies can be provided to the data processor 850 via the internal shared bus 830, and the processed data from the data processor 850 can be provided to the other core dies via the internal shared bus 830. .

Meanwhile, the buffer die 800B of the memory device illustrated in FIG. 20 may have components similar to the aforementioned buffer die 800A illustrated in FIG. 19, and may have an internal shared busbar 830 coupled to the TSV zone 810 therein. Structure. In this case, internal instructions from internal command generator 840 or data from data processor 850 can be provided directly to TSV zone 810 and to the core die.

21 and 22 are block diagrams illustrating a modified embodiment of a buffer die in accordance with several embodiments. In Figures 21 and 22, the illustrated embodiment is used in a bus bar in which the test signal is delivered in the DA region of the buffer die as an internal common bus for sharing internal processing channels.

Referring to FIG. 21, the buffer die may include a physical region interfacing with the memory controller and a TSV region in which a plurality of TSVs are formed to communicate with one or more core dies. Moreover, the buffer die can further include a busbar in which the DA zone is placed in direct communication with the external tester, independent of the memory controller. Signals associated with the tests provided to the DA zone can be delivered to the TSV through the busbars in the DA zone, and test results can be provided to the external tester through the TSV zone and the DA zone.

The test operation using the DA area can be performed on a majority of memory cell groups, and in this case, the bus bars in the test related DA area can be specifically implemented to be shared by most memory cell groups of the memory device. . According to one embodiment, the busbars in the DA zone can be used as internal common busbars for internal data processing operations of the memory device. In addition, an internal command generator for internal data processing operations can generate internal instructions and provide the generated internal instructions to the core die through the bus bars in the DA region. Also, data read from the core die can be provided to the data processor through the busbars in the DA zone, and data from the data processor can be provided to the core die through the busbars in the DA zone.

Meanwhile, referring to FIG. 22, the buffer die may include a physical area and a TSV area, and a DA area including a bus shared by the majority of the memory cell groups may be disposed adjacent to the physical area. Busbars in the DA zone can be used as internal common busbars that provide a common internal processing channel for internal data processing operations. In the foregoing example of FIG. 21, the signal transmitted through the internal shared busbar in the DA zone can be provided to the core die through the TSV zone without passing through the physical zone. On the other hand, in the present embodiment of FIG. 22, internal instructions and data delivered through the internal shared bus can be provided to the core die through the physical area and the TSV area.

Meanwhile, in the illustrated examples of FIGS. 21 and 22, the internal command generator and the data processor are exemplified as being included in the DA area, but the embodiment is not limited thereto. For example, the internal command generator and data processor can be placed outside of the DA area in the buffer die.

23 and 24 are block diagrams illustrating an example of a signal transmission path in the aforementioned buffer die illustrated in Figs. 21 and 22.

Referring to Figure 23, internal instructions and data from the internal shared bus DA BUS in the DA zone can be provided to the TSV zone without passing through the physical zone. For example, the physical area includes independent I/O circuits for each memory cell group, and thus a signal related to the memory cell group A passes through one of the corresponding memory cell groups A in the TSV area. The TSV is delivered to the core grains. Similarly, a signal related to the memory cell group B is delivered to the core crystal by a TSV corresponding to the memory cell group B in the TSV region, and a signal related to the memory cell group C is passed. A TSV corresponding to the memory cell group C in the TSV region is delivered to the core crystal grains.

The internal shared bus DA BUS in the DA zone can be placed into a selector shared by most memory cell groups, and used to select a signal from the physical zone and a signal delivered through the internal shared bus DA BUS (eg, a multiplexer) can be included in the buffer die. For example, when internal instructions/data are independently delivered for each memory cell group, internal instructions and data from the physical area can be selected and delivered to the core die via the TSV. On the other hand, when internal instructions or data are provided to the core die in an internal data processing operation, internal instructions or data are selected and delivered to the core die via the TSV.

Meanwhile, in FIG. 24, an example in which an internal command or a processed data is supplied to a core die through a physical area and a TSV area is exemplified.

Referring to FIG. 24, the internal shared bus DA BUS in the DA area can be placed at the front end of the physical area, and used to select a signal independently provided for each memory cell group and delivered through the internal shared bus DA BUS. A signal selector (eg, a multiplexer) can be placed at the front end of the physical area. For example, instructions/data that are independently delivered for each memory cell group can be received by bumps formed on the outer surface of the memory device. The signals delivered by the bumps can be selected in normal operation in which the signals are independently delivered for each memory cell group through corresponding independent channels, and the signals delivered through the internal shared bus DA BUS can be selected for The internal data processing operation in the foregoing embodiment.

Figure 25 is a configuration diagram illustrating an example of a semiconductor package including an embodiment of a memory device.

Referring to FIG. 25, the semiconductor package 900 can include one or more memory devices 910 and a memory controller 920. The memory device 910 and the memory controller 920 can be mounted on the interposer 930, and the interposer 930 on which the memory device 910 and the memory controller 920 are mounted can be mounted on the package base 940. The memory controller 920 can correspond to a semiconductor device that can perform a memory control function, and for example, the memory controller 920 can be embodied as an application processor (AP).

The memory device 910 can be embodied in various forms, and the memory device 910 according to one embodiment can be a memory device in the form of HBM in which a plurality of layers are stacked. Accordingly, the memory device 910 according to one embodiment may include a plurality of memory cell groups accessible by corresponding independent channels, and an internal shared bus bar is provided for placement by the plurality of memory cell groups. A shared internal processing channel shared. Further, an internal command generator that generates internal instructions for internal data processing operations, and a data processor that processes for writing data and/or reading data may be included in the memory device 910.

Most of the memory devices 910 can be mounted on the interposer, and the memory controller 920 can communicate with most of the memory devices 910. For example, each of the memory device 910 and the memory controller 920 can include a physical area, and communication between the memory device 910 and the memory controller 920 can be performed through the physical areas. Meanwhile, when the memory device 910 includes a DA region, the test signal can be supplied to the memory device 910 through a conductive member (eg, solder ball 950) mounted under the package substrate 940 and the DA region.

Here, the interposer may include an embedded multi-die interconnect bridge (EMIB) that is in an organic or non-TSV manner in the form of a TSV or a printed circuit board (PCB).

In the memory device for performing the internal data processing operation, the memory operation according to one of the instructions from the memory controller can be performed by the internal data processing operation of the memory device without the intervention of the memory controller. Therefore, the access frequency of the system to the memory device can be reduced, and thus the effect of improving the data bandwidth efficiency can be improved.

While the present invention has been described with reference to the preferred embodiments illustrated in the drawings, Further, it is obvious to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the inventive concept.

10A, 10C‧‧‧ memory system
10B‧‧‧Data Processing System
100A, 100C, 920‧‧‧ memory controller
100B‧‧‧Application Processor
110B‧‧‧Memory Control Module
120B‧‧‧Data machine processor
130B‧‧‧Central Processing Unit (CPU)
140B‧‧‧ embedded memory
150B‧‧‧System Bus
200A, 200B, 200C, 300A, 300B, 400, 500, 600, 700, 910‧‧‧ memory devices
201C‧‧‧ memory module
210A, 210B‧‧‧ memory cell array
220A, 220B, 320A, 320B, 350B, 830‧‧‧ internal shared bus
230A, 230B, 330A, 330B, 411, 840‧‧‧ internal command generator
311A-314A, 311B-314B‧‧‧ memory cell group
340A, 340B, 421_2~424_2, 526, 536, 850‧‧‧ data processor
410, 510, 610, 800A‧‧‧buffer die
412, 810‧‧‧TSV area
413, 820‧‧‧ entity (PHY) area
414‧‧‧DA area
420, 421-424, 520, 530, 620, 630‧‧‧ core grains
421_1~424_1, 522, 532, 622, 632‧‧‧ instruction decoder
430‧‧‧through through hole (TSV)
511, 611‧‧‧ Memory in Memory (PIM)
512, 612‧‧ interface
513, 613‧‧‧ path controller
514, 524, 534, 614, 624, 634 ‧ ‧ read data path
515, 523, 533, 615, 623, 633‧‧‧ write data path
516, 616‧‧‧Latch
521, 531, 621, 631‧‧‧ memory cell core or group
525, 535, 625, 635‧‧‧ transceivers
626, 636, 720, 730‧‧‧ PIM functional blocks
900‧‧‧Semiconductor package
930‧‧‧Intermediary
940‧‧‧Package base
950‧‧‧ solder balls
A0, A1, B0, B1‧‧ ‧ switch
A2, B2‧‧‧ buffer
ADD‧‧‧ address
Cell_CH1~4‧‧‧ memory cell group
CH‧‧‧ channel
CMD‧‧ directive
CON‧‧‧ memory controller
DA‧‧‧Direct access
DA BUS‧‧‧Internal shared bus
DATA‧‧‧Information
HOST‧‧‧Host
HBM‧‧‧ high frequency wide memory
ICMD_1~4‧‧‧Internal Directive
I/F‧‧ interface
I/O‧‧‧ Input/Output
Lat1-2, Lat A1-2, Lat B1-2‧‧‧Latch
MUX, MUX A, MUX B‧‧‧ multiplexer
PHY‧‧‧ physical layer
Processor in PIM‧‧‧ memory
RD‧‧‧Read
S11-17, S21-23, S31-34‧‧‧ steps
TSV‧‧‧through through hole (TSV)
WR‧‧‧written

The embodiments of the present invention will be more clearly understood from the following detailed description of the drawings.

1 is a block diagram illustrating one embodiment of a memory system.

2 is a block diagram illustrating another embodiment of a memory system.

3 is a block diagram illustrating an embodiment of the application processor of FIG. 2.

4 is a block diagram illustrating another embodiment of a memory system.

5 and 6 are block diagrams illustrating the configuration of a specific embodiment of a memory device.

7, 8A, and 8B are flow diagrams illustrating a specific embodiment of a method of operating a memory device.

Figure 9 is a block diagram illustrating a memory device having a stacked structure.

Figure 10 is a schematic illustration of an illustration of an internal processing operation illustrated in the memory device of Figure 9.

Figure 11 is a block diagram illustrating an embodiment of a data copying operation performed in one embodiment of a memory device.

12A and 12B are block diagrams illustrating an embodiment of a data exchange operation in one embodiment of a memory device.

13A, 13B, and 13C are block diagrams illustrating an example of reading-correcting-writing (RMW) in a particular embodiment of a memory device.

14A and 14B are block diagrams illustrating an embodiment of a RMW operation performed simultaneously on two or more core dies in one embodiment of a memory device.

15A and 15B are block diagrams illustrating an embodiment in which mask writing is performed in one embodiment of a memory device.

Figure 16 is a block diagram illustrating a modified embodiment of one of the memory devices.

17 and 18 are block diagrams illustrating one embodiment of a buffer die included in one embodiment of a memory device.

19 and 20 are schematic views showing in detail a specific embodiment of the aforementioned buffer die illustrated in Figs. 17 and 18.

21 and 22 are block diagrams illustrating a modified embodiment of a buffer die.

23 and 24 are block diagrams illustrating an example of a signal transmission path in the aforementioned buffer die illustrated in Figs. 21 and 22.

Figure 25 is a configuration diagram illustrating an example of a semiconductor package including a specific embodiment of a memory device.

400‧‧‧ memory device

410‧‧‧buffer die

411‧‧‧Internal Command Generator

412‧‧‧TSV area

413‧‧‧ entity (PHY) area

414‧‧‧DA area

420, 421-424‧‧‧ core grains

430‧‧‧through through hole (TSV)

Claims (21)

A memory device comprising: a buffer die having an internal command generator, the internal command generator being configured to receive from an external memory controller for at least one internal data by the memory device Processing a first external command of the operation, and in response to the receiving, generating at least two internal instructions for causing the memory device to perform a corresponding internal memory operation to perform the at least one An internal data processing operation; a first core die and a second core die stacked with the buffer die, each of the first and second core die having a plurality of dynamic random accesses a memory (DRAM) cell, wherein the DRAM cells are arranged in at least a first memory cell group of the first core die and a second memory cell group of the second core die a plurality of through-via vias (TSVs) extending through the first and second core dies and thereby coupled to the buffer dies; each of the first and second memory cell groups Corresponding to one related At least two independent channels, each of the at least two independent channels including a corresponding set of the TSVs; and the first and second memory cell groups in the first and second core dies A shared internal processing channel shared between groups. The memory device of claim 1, wherein each of the at least two independent channels includes a corresponding independent data bus for the corresponding memory cell group, and wherein the shared internal processing channel includes a system thereof A shared internal data bus shared between the at least two memory cell groups. The memory device of claim 1, wherein each of the at least two independent channels includes a corresponding independent instruction/address bus for the associated memory cell group, and wherein the shared internal The processing channel includes a shared internal instruction/address bus that is shared among the at least two groups of memory cells. The memory device of claim 1, wherein each of the at least two independent channels comprises a corresponding independent instruction/address bus for the associated memory cell group, and the memory device Further comprising at least two independent internal instruction/address signal busbars each associated with one of the at least two memory cell groups. The memory device of claim 1, wherein the shared internal processing channel includes at least some of the TSVs, and when the memory device performs the at least one internal data processing operation, the TSVs of the shared internal processing channel Shared by at least two of the groups of memory cells. The memory device of claim 1, wherein the first core die comprises at least one first data processor associated with the first memory cell group, wherein the second core die comprises the second At least one second data processor associated with the group of memory cells, wherein the data processors are configured to perform the at least one internal data in response to at least one control signal provided by the internal command generator Processing operations. The memory device of claim 6, wherein the at least one internal data processing operation comprises at least one of a data addition operation, a mutual exclusion or operation, a data subtraction operation, and a data multiplication operation. The memory device of claim 1, wherein when the memory device receives a second external command from the memory controller as one of the normal instructions, the normal command is provided to the associated independent channel through the associated independent channel. One of the groups of memory cells. A memory device comprising: a buffer die having an internal command generator, the internal command generator being configured to receive from an external memory controller for at least one internal data by the memory device Processing a first external command of the operation, and in response to the receiving, generating at least two internal instructions for causing the memory device to perform a corresponding internal memory operation to perform the at least one An internal data processing operation; at least one core die stacked with the buffer die, the at least one core die having a plurality of dynamic random access memory (DRAM) cells, and the plurality of dynamic random accesses Memory (DRAM) cells are arranged in a plurality of memory cell groups; a plurality of through-via vias (TSVs) extending through the at least one core die are coupled to the buffer die; and each At least two independent channels associated with a corresponding one of the groups of memory cells, each of the at least two independent channels comprising a corresponding set of the TSVs, When the memory device performs the at least one internal data processing operation, at least some of the TSVs are shared by at least two of the plurality of memory cell groups. The memory device of claim 9, wherein at least some of the TSVs shared by at least two of the plurality of memory cell groups are included in the plurality of memory cell groups A shared internal processing channel. The memory device of claim 9, wherein the first external command comprises at least one of a data copy command, a data exchange command, a read-correct-write command, and a mask-write command. The memory device of claim 9, further comprising a plurality of data processors, each data processor being associated with one of the groups of memory cells, and being disposed in the associated memory cell The meta-groups are identical to a core die, wherein the data processors are configured to perform the at least one internal data processing operation in response to at least one control signal provided by the internal command generator. The memory device of claim 9, wherein the at least one internal data processing operation comprises at least one of a data addition operation, a mutual exclusion or operation, a data subtraction operation, and a data multiplication operation. The memory device of claim 9, wherein when the memory device receives a second instruction from the memory controller as one of the normal instructions, the normal command is provided to the plurality of independent channels through its associated independent channel. One of the memory cell groups. A memory device, comprising: a plurality of dynamic random access memory (DRAM) cells arranged in a plurality of memory cell groups; each corresponding to one of the plurality of memory cell groups An associated plurality of independent channels; an internal command generator configured to receive at least one first external command for performing at least one internal data processing operation by the memory device from an external memory controller, and Responding to the receiving to generate at least two internal instructions for causing the corresponding memory operation to be performed to perform the at least one internal data processing operation; and in the plurality of memory cell groups A shared internal processing channel shared between. The memory device of claim 15, wherein the plurality of independent channels each associated with a corresponding one of the at least two memory cell groups are assembled for the plurality of memories The DRAM cells of the cell group perform normal operations, and the shared internal processing channel is shared among the at least two memory cell groups for the at least two memory cell groups The DRAM cells perform internal data processing operations. The memory device of claim 15, wherein the first external command comprises at least one of a data copy instruction, a data exchange instruction, a read-correction-write instruction, and a mask-write instruction. The memory device of claim 17, further comprising a plurality of data processors associated with one of the groups of memory cells, wherein the data processors are configured to respond to the internal The at least one control signal provided by the instruction generator performs the at least one internal data processing operation on the data for the associated group of memory cells. The memory device of claim 18, wherein the at least one internal data processing operation comprises at least one of a data addition operation, a mutual exclusion or operation, a data subtraction operation, and a data multiplication operation. The memory device of claim 15, wherein when the memory device receives a second external command from the memory controller as one of the normal instructions, the normal command is provided to the same through its associated independent channel. One of a plurality of memory cell groups. The memory device of claim 15, wherein the memory operations are performed in series.