KR102345539B1 - Memory Device performing internal process and Operating Method thereof - Google Patents

Abstract

A memory device for performing an internal process and an operating method thereof are disclosed. A memory device according to the inventive concept includes a plurality of DRAM cells disposed in a plurality of memory cell groups, a plurality of independent channels each associated with a corresponding one of the plurality of memory cell groups, and the memory Receive at least a first external command from an external memory controller for performing at least one internal data processing operation by the device, and in response cause corresponding memory operations to be executed to perform the at least one internal data processing operation and an internal command generator generating at least two internal commands for

Description

A memory device performing an internal process and an operating method thereof

The technical idea of the present invention relates to a memory device, and more particularly, to a memory device for performing an internal process and an operating method thereof.

BACKGROUND ART A semiconductor memory device widely used in high-performance electronic systems has increased in capacity and speed. As an example of a semiconductor memory device, a DRAM is a volatile-memory, a memory that determines data based on a charge stored in a capacitor.

The semiconductor memory device may transmit/receive data to and from an external memory controller through one or more channels. As an example, according to a command type provided from the memory controller, a processing operation may be performed on data provided from the memory controller, or data stored therein may be read and the data may be provided to the memory controller through a processing operation. . In this case, as bandwidth is occupied between the semiconductor memory device and the memory controller, the efficiency of channel use may be reduced, and power consumption may increase.

SUMMARY An object of the present invention is to provide a memory device that performs an internal process capable of improving data processing bandwidth and energy efficiency, and an operating method thereof.

In a memory device according to the inventive concept, a first external command for performing at least one internal data processing operation by the memory device is received from an external memory controller, and the at least one internal data processing operation is performed in response thereto a buffer die including an internal command generator for generating at least two internal commands to cause the memory device to execute corresponding internal memory operations to perform The DRAM cells extend through at least a first core die and a second core die disposed in a first group of memory cells of a first core die and a second group of memory cells of a second core die, and the first and second core dies. a plurality of through silicon vias (TSVs) coupled to the buffer die and at least two independent channels and a common internal processing channel shared between the first and second groups of memory cells of the first and second core dies.

According to the inventive concept, a memory device for performing an internal process and an operating method therefor, a series of memory operations according to a command from a memory controller can be performed through an internal process of the memory device without intervention of the memory controller, so that the system It is possible to reduce the access frequency of the memory device, and thus has the effect of improving the data bandwidth efficiency.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present invention.
2 is a block diagram illustrating another example of an exemplary memory system of the present invention.
3 is a block diagram illustrating an implementation example of the application processor of FIG. 2 .
4 is a block diagram illustrating another example of an exemplary memory system of the present invention.
5 and 6 are block diagrams showing the configuration of a memory device according to an exemplary embodiment of the present invention.
7 and 8A and B are flowcharts illustrating a method of operating a memory device according to an exemplary embodiment of the present invention.
9 is a block diagram illustrating a memory device having a stacked structure according to an exemplary embodiment of the present invention.
FIG. 10 is a diagram illustrating an example of an internal process in the memory device of FIG. 9 .
11 is a block diagram illustrating an example in which data copy is performed in a memory device according to an embodiment of the present invention.
12A and 12B are block diagrams illustrating an example in which data swap is performed in a memory device according to an embodiment of the present invention.
13A, B, and C are block diagrams illustrating an example in which a Read Modify Write (RMW) is performed in a memory device according to an embodiment of the present invention.
14A and 14B are block diagrams illustrating an example in which Read Modify Write (RMW) is simultaneously performed on two or more core dies in a memory device according to an embodiment of the present invention.
15A and 15B are block diagrams illustrating an example in which mask write is performed in a memory device according to an embodiment of the present invention.
16 is a block diagram illustrating a memory device according to a deformable embodiment of the present invention.
17 and 18 are block diagrams illustrating an implementation example of a buffer die included in a memory device according to an embodiment of the present invention.
19 and 20 are diagrams illustrating specific implementation examples of the buffer die illustrated in FIGS. 17 and 18 described above.
21 and 22 are block diagrams illustrating a deformable implementation example of the buffer die of the present invention.
23 and 24 are block diagrams illustrating an example of a signal transmission path in the buffer die illustrated in FIGS. 21 and 22 described above.
25 is a structural diagram illustrating an example of a semiconductor package including a memory device according to embodiments of the present invention.
26 is a block diagram illustrating a computing system including a memory device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention are provided to more completely explain the present invention to those of ordinary skill in the art. Since the present invention may have various changes and may have various forms, specific embodiments will be illustrated in the drawings and described in detail. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention. In describing each figure, like reference numerals are used for like elements. In the accompanying drawings, the dimensions of the structures are enlarged or reduced than the actual size for clarity of the present invention.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate that a feature, number, step, operation, component, part, or a combination thereof described in the specification exists, but one or more other features It should be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Also, terms such as first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be termed a second component, and similarly, a second component may also be termed a first component.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present application. does not

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a memory system 10A may include a memory controller 100A and a memory device 200A. The memory controller 100A includes a memory interface 110A, and provides various signals to the memory device 200A through the memory interface 110A to control memory operations such as writing and reading. For example, the memory controller 100A provides the command CMD and the address ADD to the memory device 200A to access the data DATA of the memory cell array 210A. The command CMD may include a command for a normal memory operation such as writing and reading data. Also, the command CMD may include a command for requesting that the memory device 200A perform an internal process including a series of memory operations.

The memory controller 100A may access the memory device 200A according to a request from the host HOST. The memory controller 100A may communicate with a host using various protocols. For example, the memory controller 100A may include Peripheral Component Interconnect - Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), and PATA. It may communicate with the host using an interface protocol such as (Parallel ATA) or serial attached SCSI (SAS). In addition, various other interface protocols such as Universal Serial Bus (USB), Multi-Media Card (MMC), Enhanced Small Disk Interface (ESD), or Integrated Drive Electronics (IDE) may be applied to the protocol between the host and the memory controller 100A. can

The memory device 200A may include a memory cell array 210A, an internal common bus 220A, and an internal command generator 230A. Also, the memory device 200A may include n channels (eg, n independent channels). In this case, the memory device 200A may include n independent interfaces corresponding to the n channels. can That is, since each channel includes an interface independent from each other, each channel may operate the same as an individual memory device.

According to an embodiment, the memory device 200A may have an independent signal transmission path for each channel, and accordingly, the signal transmission path for transmitting a command/address may be implemented to be independent for each channel. Also, a signal transmission path for transferring data may be implemented to be independent for each channel.

The memory cell array 210A may include a plurality of cell regions (or a plurality of cell groups) corresponding to a plurality of channels. As an example, as the memory device 200A includes n channels, the memory cell array 210A may include n cell regions Cell_CH1 to Cell_CHn.

Meanwhile, when the memory device 200A has a structure in which a plurality of layers are stacked, the memory device 200A may include one or more layers each including memory cells. A layer including memory cells may be referred to as a core die, and each core die may include a separate independent channel or a group of memory cells. Also, one core die may include two or more channels or two or more memory cell groups. In this case, one core die may include a plurality of independent interfaces corresponding to the plurality of channels.

On the other hand, the memory device 200A, such as DDR SDRAM (Double Data Rate Synchronous Dynamic Ramdom Access Memory), LPDDR (Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, RDRAM (Rambus Dynamic Ramdom Access Memory), etc. It may be a dynamic random access memory (DRAM). However, embodiments of the present invention are not limited thereto. As an example, the memory device 200A includes a flash memory, a magnetic RAM (MRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), and a ReRAM. (Resistive RAM) may be implemented as a non-volatile memory.

Meanwhile, the internal common bus 220A may include a bus shared by a plurality of channels or a plurality of memory cell groups. For example, the internal common bus 220A may include a bus for implementing a common internal processing channel shared by a plurality of memory cell groups. Also, as an example, one or more types of signals may be commonly provided to a plurality of channels or memory cell groups through a common internal processing channel provided by the internal common bus 220A. The internal common bus 220A may include a common data bus that commonly provides data to a plurality of channels or groups of memory cells. In addition, the internal common bus 220A may include a common command bus that provides an internal command in common to a plurality of channels or groups of memory cells. According to an embodiment, data of any one channel or memory cell group may be provided to one or more other channels or memory cell groups through the internal common bus 220A.

Hereinafter, an internal operation of the memory device 200A will be described with reference to a channel, but in embodiments of the present invention, a channel may be substituted with the above-described memory cell group.

According to an embodiment, when a bus shared by a plurality of channels does not exist in the memory device 200A, the internal common bus 220A in addition to the existing bus for transferring commands/data in the memory device 200A may be further added. On the other hand, as a direct access (DA) type test block is provided in the memory device 200A, if a bus shared by a plurality of channels already exists in the test block, the internal common bus ( 220A) may correspond to some of the existing buses shared by a plurality of channels.

The internal command generator 230A may generate various types of internal commands related to memory operations and provide the generated internal commands to channels of the memory device 200A. As an example, various types of commands may be defined between the memory controller 100A and the memory device 200A, and commands for requesting execution of normal memory operations such as write and read operations may be defined. According to an embodiment, in the normal memory operation, commands and addresses may be independently transmitted for each channel in the memory device 200A.

Meanwhile, in the case of a specific command, the memory device 200A may perform an internal process of sequentially performing a plurality of memory operations in response to the specific command. The internal command generator 230A may generate a plurality of internal commands to sequentially perform a plurality of memory operations in response to receiving the specific command CMD from the memory controller 100A. In addition, while performing the internal process, at least one of commands and data is transmitted to channels through the internal common bus 220A, and accordingly, the internal common bus 220A is transmitted between a plurality of channels while performing the internal process. It is possible to form an internal command/data transmission path in .

In order to improve the performance of the memory device 200A, various types of internal processes may be performed. As an example, as fragmentation occurs in the cell area of the memory device 200A, a portion of the cell area becomes smaller than the minimum data recording unit, so that a part of the cell area cannot be used. . In this case, a continuous empty memory space may be secured in the cell region of the memory device 200A by performing the data copy operation, thereby increasing memory usage efficiency.

In order to perform the above-described internal process, a command CMD for copying data stored in one location of the memory device 200A to another location may be defined. When the memory device 200A receives the copy command CMD from the memory controller 100A, the internal command generator 230A may generate a series of internal commands for data copying. If the data of the first channel CH1 is copied to the second channel CH2, the memory device 200A uses an internal command for reading data of the first channel CH1 and the read data to the second channel CH2. An internal command to write to channel CH2 can be generated. Also, data read from the first channel CH1 may be transmitted to the second channel CH2 through the internal common bus 220A.

In the conventional case, as the memory device 200A has a general structure in which interfaces are independent for each channel, data read from the first channel CH1 uses a communication path corresponding to the first channel CH1 for a data copy operation. through the memory controller 100A, and the memory controller 100A must provide the received data to the memory device 200A through a communication path corresponding to the second channel CH2. On the other hand, according to an embodiment of the present invention, a series of memory operations for data copy may be performed through an internal process of the memory device 200A without intervention of the memory controller 100A.

Accordingly, in the memory system 10A according to the embodiment of the present invention, data processing bandwidth and energy efficiency may be improved, system performance may be improved, and internal power consumption and operation speed may be improved.

Meanwhile, although the data copy operation is exemplified in the above-described embodiment, the embodiment of the present invention is not limited thereto. For example, data may be transmitted/received between channels in various types of memory operations such as data move, swap, read modify write (RMW), and mask write. may be performed through internal command generation of the memory device 200A and an internal process using an internal common bus.

2 is a block diagram illustrating another example of an exemplary memory system of the present invention. FIG. 2 shows a data processing system 10B including an application processor 100B and a memory device 200B, and the memory control module 110B and the memory device 200B in the application processor 100B are the memory devices. You can configure the system. Also, the memory device 200B may include a memory cell array 210B, an internal common bus 220B, and an internal command generator 230B.

The application processor 100B may perform the function of the host in FIG. 1 . Also, the application processor 100B may be implemented as a system on chip (SoC). The system on chip (SoC) may include a system bus (not shown) to which a protocol having a predetermined standard bus standard is applied, and may include various intellectual properties (IPs) connected to the system bus. As a standard specification of the system bus, the Advanced Microcontroller Bus Architecture (AMBA) protocol of ARM (Advanced RISC Machine) may be applied. The bus type of the AMBA protocol may include Advanced High-Performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI), AXI4, and AXI Coherency Extensions (ACE). In addition, other types of protocols such as uNetwork of SONICs Inc., CoreConnect of IBM, and Open Core Protocol of OCP-IP may be applied.

The memory control module 110B may perform the function of the memory controller in the above-described embodiment. Also, the memory device 200B may perform various types of memory operations through an internal process without the intervention of the memory control module 110B. As an example, the memory device 200B may generate internal commands to perform read and write operations on data, and data may be transmitted/received between a plurality of channels through the internal common bus 220B.

3 is a block diagram illustrating an implementation example of the application processor 100B of FIG. 2 .

2 and 3 , the application processor 100B may include a plurality of IPs connected through a system bus 150B. As an example, the application processor 100B includes a memory control module 110B, a modem. It may include a processor 120B, a central processing unit (CPU, 130B) and an embedded memory 140B. The central processing unit 130B may control operations of various IP cores inside the application processor 100B, and the modem processor 120B is a processor for performing wireless communication with a base station or other communication devices.

Meanwhile, the memory control module 110B may communicate with the memory device 200B disposed outside the application processor 100B through a plurality of independent channels corresponding to a plurality of memory cell groups. In addition, the memory control module 110B may communicate with the embedded memory 140B through the system bus 150B. The embedded memory 140B may also be implemented identically or similarly to the memory device 200B according to the above-described embodiment, and accordingly, the embedded memory 140B may have a common internal processing channel provided by an internal common bus (not shown). and an internal command generator (not shown).

4 is a block diagram illustrating another example of an exemplary memory system of the present invention.

Referring to FIG. 4 , the memory system 10C may include a memory controller 100C and one or more memory modules 201C. The memory module 201C includes a module board on which one or more memory devices 200C according to an embodiment of the present invention are mounted. Also, the memory module 201C may be implemented in the form of a single in-line memory module (SIMM) or a dual inline memory module (DIMM).

The aforementioned channel may be defined in various ways. According to an embodiment, one or more memory modules 201C may configure one or more channels described above. For example, each memory module 201C may constitute one channel. Alternatively, a plurality of memory devices 200C may be mounted on the memory module 201C, and each memory device 200C may constitute one channel. Alternatively, each memory device 200C may include a plurality of cell groups, and each memory device 200C may configure a plurality of channels.

According to one embodiment, the memory system 10C may include an internal common bus (not shown) in the embodiment described above. If each memory module 201C constitutes one channel, a bus shared by a plurality of memory modules 201C will be implemented. Alternatively, when each memory device 200C constitutes one channel, a bus shared by a plurality of memory devices 200C may be implemented in each memory module 201C. Alternatively, when each memory device 200C includes a plurality of channels, a bus shared by a plurality of cell regions may be implemented inside each memory device 200C.

5 and 6 are block diagrams showing the configuration of a memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 5 , the memory device 300A may include a plurality of channels 311A to 314A. Each of the channels 311A to 314A may be defined in various ways, for example, each of the channels 311A to 314A may include a group of cells, and may be defined to further include one or more components related to memory operation. can As an example, each of the channels 311A to 314A may include a row decoder, a column decoder, a sense amplifier, and a command decoder.

Also, the memory device 300A may further include an internal common bus 320A, an internal command generator 330A, and a data processor 340A. The internal common bus 320A has a signal transmission path shared by the plurality of channels 311A to 314A, and may transfer data for the plurality of channels 311A to 314A, for example. For example, the first channel 311A may output the first channel data Data_1 to the internal common bus 320A, and the first channel data Data_1 is provided to another channel through the internal common bus 320A. can be Similarly, the fourth channel 314A may output the fourth channel data Data_4 to the internal common bus 320A, and the fourth channel data Data_4 may be transmitted to another channel through the internal common bus 320A. can be provided as

The internal command generator 330A may generate a plurality of internal commands ICMD_1 to ICMD_4 according to a command CMD from the memory controller. For example, the signal transmission path of the internal command may be independently implemented for the plurality of channels 311A to 314A, and accordingly, the internal command generation unit 330A may transmit the internal commands ICMD_1 to ICMD_4 through independent paths. may be provided as channels 311A to 314A.

Meanwhile, the data processing unit 340A may be connected to the internal common bus 320A, receive data transmitted through the internal common bus 320A, and perform a processing operation thereon. As an example, the data processing unit 340A may perform a latch operation or an arithmetic operation on data, and may output data on which the processing operation is completed to the internal common bus 320A.

The internal command generator 330A may generate various types of internal commands ICMD_1 to ICMD_4 . As an example, the internal command generator 330A may generate internal commands ICMD_1 to ICMD_4 for changing the location of internal data, correcting internal data, and performing a comparison operation. In addition, the internal command generator 330A may generate internal commands ICMD_1 to ICMD_4 for performing Read Modify Write (RMW), data swap between channels, and mask write.

The data processing unit 340A may perform various functions related to the above internal process. For example, during a data copy or swap operation, a function of temporarily storing data read from any one channel may be performed. Alternatively, a bit comparison operation on data may be performed during a read modify write (RMW) or a mask write operation, and the bit comparison operation may be performed by the data processing unit 340A.

If the memory device 300A has a structure in which a buffer die and a core die are stacked, the internal common bus 320A is provided in the buffer die to transmit/receive data between a plurality of channels. Alternatively, a plurality of TSVs for electrically connecting the buffer die and the core die are disposed, and the internal common bus 320A may correspond to one or more TSVs transferring data. Additionally, each group of memory cells on the core die may include an independent channel for communication, and each channel may include corresponding TSVs.

Also, the internal command generation unit 330A and the data processing unit 340A may be implemented according to various methods. As an example, the internal command generator 330A may be provided in the buffer die. In addition, the data processing unit 340A may be provided in the buffer die or may be provided in each core die.

Meanwhile, referring to FIG. 6 , the memory device 300B includes a plurality of channels 311B to 314B, first and second internal common buses 320B and 350B, an internal command generator 330B, and a data processor 340B. ) may be included. The first internal common bus 320B is a bus shared by the plurality of channels 311B to 314B and corresponds to a common data bus, and the second internal common bus 350B is shared by the plurality of channels 311B to 314B. As a bus to be used, it may correspond to a common command bus. Internal commands ICMD<1:4> for the plurality of channels 311B to 314B generated by the internal command generator 330B may be transmitted through the second internal common bus 350B, and the channels Data (Data<1:4>) for 311B to 314B may be transferred through the first internal common bus 320B. Also, the first and second internal common buses 320B and 350B may provide a common internal processing channel for the memory device 300B.

In the embodiment shown in FIG. 6 , the second internal common bus 350B may be implemented in various ways. As an example, the second internal common bus 350B may be provided in the buffer die to transmit/receive internal commands between a plurality of channels. Alternatively, a plurality of TSVs for electrically connecting the buffer die and the core die may be disposed, and the second internal common bus 350B may correspond to one or more TSVs transmitting a command.

7 and 8A and B are flowcharts illustrating a method of operating a memory device according to an exemplary embodiment of the present invention. The memory device includes a plurality of channels corresponding to a plurality of memory cell groups, and according to an embodiment of the present invention, an internal common bus shared by the plurality of channels may be provided in the memory device.

Referring to FIG. 7 , the memory device receives a command from an external memory controller ( S11 ). Various types of commands may be set between the memory controller and the memory device, and some of them may correspond to commands for performing an internal process including two or more internal memory operations.

The memory device may determine whether it is necessary to perform a specific internal process through a decoding operation for the received command (S12). If there is no need for an internal process in which a plurality of memory operations are sequentially performed, the memory device performs a normal memory operation to complete an operation for a command of an external memory controller ( S13 ).

On the other hand, according to a specific command from the memory controller, the memory device may sequentially generate two or more internal commands ( S14 ). Also, a plurality of channels may perform different memory operations according to internal commands, and accordingly, the memory device may generate a channel selection signal corresponding to each internal command ( S15 ).

The internal command and the channel selection signal generated in the memory device may be respectively provided to corresponding channels. The selected channel may perform a memory operation according to the received internal command, and may output a result (eg, data according to a read operation) according to the memory operation ( S16 ). In addition, data according to the memory operation may be transmitted/received between channels through an internal common bus (S17), and as an example, data provided from one channel may be provided to another channel through an internal common bus. The channel receiving the data may perform a memory operation using the received data according to an internal command.

8A and 8B illustrate an example of data transfer when a memory device includes a plurality of layers.

The memory device may include a plurality of layers, and each layer may be a die corresponding to a different channel. For example, the memory device may include one buffer die and a plurality of core dies.

A plurality of internal commands are generated according to a command from the memory controller, and the memory device performs an internal process according to the internal commands. According to any one internal command, an operation of reading data from the first core die may be performed (S21).

In order to perform various types of internal processes such as data copy, swap, RMW and mask write, a processing operation on the read data may be performed ( S22 ). As an example, a temporary latch operation on the read data may be performed as the processing operation. Alternatively, a comparison operation of various types of data such as write data or mask data and the read data may be performed as the processing operation. A circuit for processing data can be implemented in various ways, and as an example, a circuit for processing data (eg, a data processing unit) is implemented separately in each core die, or is implemented in a buffer die so that a plurality of core dies may be shared with

Data on which the processing operation has been completed may be transferred through an internal common bus (or a common internal processing channel provided by the internal common bus), and according to an embodiment, the data on which the processing operation has been completed is transferred to another core die (eg, the second core die). 2 core die) (S23). That is, data may be transmitted/received between different core dies through an internal common bus.

Meanwhile, referring to FIG. 8B , in performing an internal process according to a command from the memory controller, an operation of reading data from the first core die may be performed ( S31 ). In addition, write data for RMW and mask writing may be received from the memory controller ( S32 ), and the memory device may perform arithmetic processing using data read from the first core die and the received write data ( S33 ). ). Similar to the above-described embodiment, the arithmetic processing using the read data and the received write data may be performed in the first core die, or may be performed in another core die or may be performed in the buffer die.

The operation processing result is provided to the first core die through an internal common bus (or a common internal processing channel provided by the internal common bus), or a second core die configuring a channel different from that of the first core die may be provided as (S34). According to the above operation, a series of operations for an internal process may be performed in a plurality of dies, and a result of the operation may be transmitted/received through an internal common bus shared for channels.

Hereinafter, a memory device according to embodiments of the present invention includes a plurality of layers (or a plurality of dies) having a stacked structure, and detailed descriptions of various types of internal processes in a memory device having a stacked structure will be described below. An example is described.

9 is a block diagram illustrating a memory device having a stacked structure according to an exemplary embodiment of the present invention. In FIG. 9 , a high bandwidth memory (HBM) type memory device having an increased bandwidth by including a plurality of channels having mutually independent interfaces is exemplified.

Referring to FIG. 9 , the memory device 400 may include a plurality of layers. As an example, the memory device 400 may include a buffer die 410 and one or more core dies 420 stacked thereon. In the example of FIG. 9 , an example in which the first to fourth core dies 421 to 424 are provided is illustrated, but the number of the core dies may be variously changed.

In addition, each of the core dies 420 may include one or more channels, and in the example of FIG. 9 , as one core die 420 includes two channels, the memory device 400 has 8 channels ( Examples with CH1 to CH8) are shown. For example, the first core die 421 includes a first channel and a third channel (CH1, CH3), the second core die 422 includes a second channel and a fourth channel (CH2, CH4), The third core die 423 may include fifth and seventh channels CH5 and CH7 , and the fourth core die 424 may include sixth and eighth channels CH6 and CH8 .

The buffer die 410 may communicate with the memory controller, receive commands, addresses, and data from the memory controller, and provide the received commands, addresses, and data to the core dies 420 . The buffer die 410 may communicate with the memory controller through conductive means (not shown) such as bumps formed on the outer surface thereof. The buffer die 410 buffers commands, addresses, and data, and accordingly, the memory controller may interface with the core dies 420 by driving only a load of the buffer die 410 .

Also, the memory device 400 may include a plurality of through silicon vias (TSVs) 430 penetrating the layers. The TSVs 430 may be disposed to correspond to a plurality of channels CH1 to CH8, and when each channel has a bandwidth of 128 bits, the TSVs 430 are configured for data input/output of 1024 bits. may include

According to one embodiment, at least some of the TSVs 430 may be used as the internal common bus described in the above embodiment. For example, the TSV 430 is disposed to pass through the first to fourth core dies 421 to 424 , and each of the first to fourth core dies 421 to 424 is a transmitter/receiver connected to the TSV 430 . may include In a normal operation in which data input/output is independently performed for each channel, only the transmitter/receiver of any one core die is enabled for each TSV 430 , so that each TSV 430 is connected to any one core die. (or, only data of any one channel) can be transmitted independently.

On the other hand, when the TSV 430 is used as the above-described internal common bus in an internal process operation such as data copy or swap according to an embodiment of the present invention, the transmitter / of two or more core dies for each TSV 430 . As the receiver is sequentially or simultaneously enabled, data may be transmitted/received between at least two channels.

The buffer die 410 may include an internal command generator 411 , a TSV area 412 , a physical (PHY) area 413 , and direct access areas DA and 414 . The internal command generator 411 may generate an internal command according to the above-described embodiments and provide it to the core dies 420 through the TSVs 430 . The TSV region 412 is a region in which the TSV 430 for communication with the core dies 420 is formed. In addition, the physical (PHY) area 413 is an area including a plurality of input/output circuits for communication with an external memory controller, and various signals from the memory controller are transmitted through the physical (PHY) area 413 to the TSV area ( 412 , and may also be provided to the core dies 420 via TSV 430 .

Meanwhile, the direct access area DA 414 may directly communicate with an external tester through a conductive means disposed on the outer surface of the memory device 400 in a test mode for the memory device 400 . Various signals provided from the tester may be provided to the core dies 420 through the direct access area DA 414 and the TSV area 412 . Alternatively, as a variant embodiment, various signals provided from the tester may be provided to the core dies 420 through the direct access area DA 414 , the physical (PHY) area 413 , and the TSV area 412 . have.

FIG. 10 is a diagram illustrating an example of an internal process in the memory device of FIG. 9 .

9 and 10 , the buffer die 410 includes an internal command generator 411 , and the internal commands from the internal command generator 411 are independently formed for each channel. Command TSV (TSV_cmd) is provided to the core dies 420 through The buffer die 410 may control the memory operation of the core dies 420 by outputting internal commands.

Meanwhile, each of the core dies 420 includes a command decoder 421_1 to 424_1 that decodes an internal command to output an internal control signal, and a data processor 421_2 that performs a processing operation on read data and/or data to be written. ~ 424_2) can be provided.

Referring to any one core die (eg, the first core die 421 ), the first core die 421 performs a memory operation according to the decoding result of the command decoder 421_1 , and as an example, the first core die A plurality of bits of data stored in a cell region inside the die 421 may be read and provided to the data processing unit 421_2 . The data processing unit 421_2 may process a plurality of bits of data in parallel, and may output the parallelly processed data as a plurality of data TSVs TSV_data in parallel.

According to the type of memory operation, the data processing unit 421_2 may temporarily store the read data and may output the stored data as data TSV (TSV_data). Also, under the control of the command decoder 421_1 , data from the data processing unit 421_2 may be provided to at least one of the other core dies through data TSV (TSV_data). If the internal process of copying the data of the first core die 421 to the second core die 422 is performed, the data from the data processing unit 421_2 is transferred to the second core die (TSV_data) through the data TSV(TSV_data). 422) may be provided.

11 is a block diagram illustrating an example in which data copy is performed in a memory device according to an embodiment of the present invention. Hereinafter, operations of one buffer die and two core dies are exemplified for convenience of description. In addition, the in-memory processor shown in the following embodiments may perform the command decoding function in the above embodiments. Also, the in-memory processor may further perform a function of providing a chip select signal (chip_select) for channel selection or chip selection according to an internal process. According to a deformable embodiment, the chip select signal chip_select shown in the drawings below may be implemented to be generated through a command decoder of each core die.

Referring to FIG. 11 , the memory device 500 may include a buffer die 510 and first and second core dies 520 and 530 . The first core die 520 may include an A-th channel CH A, and the second core die 530 may include a B-th channel CH B.

The buffer die 510 communicates with the memory controller, generates internal commands for performing a series of internal processes in response to a specific command from the memory controller, and changes a chip select signal (chip_select) for selecting a core die. Internal commands may be provided to the first and second core dies 520 , 530 . In addition, data may be transmitted/received between the buffer die 510 and the first and second core dies 520 and 530 , and data TSVs for data transmission/reception are the buffer die 510 and the first and second core dies. They may be disposed in common with respect to the ones 520 and 530 .

The buffer die 510 may include a plurality of input/output circuits to perform an independent interface for each channel with the first and second core dies 520 and 530 . For example, the buffer die 510 includes an input/output circuit for a channel A (CH A) that interfaces with the first core die 520 and an input/output circuit for a channel B (CH B) that interfaces with the second core die 530 . may include Various components included in each input/output circuit may be disposed in at least one area of the buffer die 510 , and as an example, components of the input/output circuit may be disposed in a physical (PHY) area.

The buffer die 510 may include an in-memory processor 511 for generating internal commands according to the above-described embodiment. According to an embodiment, the in-memory processor 511 may be configured to be shared by a plurality of channels. In addition, the input/output circuit corresponding to each channel includes an interface unit 512 that interfaces with the memory controller, a path control unit 513 , a read data path 514 , a write data path 515 , and one or more latches 516 . may include

The in-memory processor 511 may sequentially output a plurality of internal commands so that an internal process according to a command from the memory controller is performed. In addition, each core die may perform a specific function according to an internal command, and the in-memory processor 511 may select a core die to perform a function according to the internal command by outputting a chip select signal chip_select . Each of the first and second core dies 520 and 530 may include transceivers 525 and 535 for inputting and outputting data through a TSV, and the transceiver of each core die includes a chip select signal (chip_select). Enable may be controlled by .

Meanwhile, the first core die 520 includes a cell core 521 including a cell region, a command decoder 522 for decoding an internal command, a write data path 523 , a read data path 524 , and a transceiver 525 . ) may be included. Also, the first core die 520 may further include a circuit for performing predetermined processing on data to be written and/or data to be read. As an example, in FIG. 11 , a data processing unit 526 that performs a processing operation for controlling data transfer or temporarily storing data is illustrated. The data processing unit 526 may include a latch and a switch for controlling electrical connection with the data TSV.

The second core die 530 may be implemented the same as or similar to the first core die 520 , so that the second core die 530 includes a cell core 531 , a command decoder 532 , and a write data path. 533 , a read data path 534 , a transceiver 535 , and a data processing unit 536 may be included. The data processing unit 536 may also include a latch and a switch.

According to a command from the external memory controller, an internal process for copying data of the second core die 530 to the first core die 520 is performed, and the internal process is performed in the memory device 500 without intervention of the memory controller ) can be done by creating an internal command inside. For example, the buffer die 510 provides an internal command to the second core die 530 , the second core die 530 reads data in response to the received internal command, and uses the read data as an internal common bus. It may be provided to the first core die 520 through the data TSV. In addition, the buffer die 510 provides an internal command to the first core die 520 , and the first core die 520 writes data received through the data TSV to the cell core 521 in response to the internal command. can do. Accordingly, data of the second core die 530 may be copied to the cell core 521 of the first core die 520 .

According to a deformable embodiment, data read from the second core die 530 is stored in the latch of the data processing unit 536 , and the data stored in the latch of the data processing unit 536 is stored in the latch of the data processing unit 536 through the data TSV. 520) may be provided.

According to the above-described embodiment, even when a memory operation in which data is moved between different core dies is performed, a data copy operation between channels may be performed through a process inside the memory device 500 without intervention of the memory controller. can

12A and 12B are block diagrams illustrating an example in which data swap is performed in a memory device according to an embodiment of the present invention. The configuration of the memory device 500 shown in FIG. 12A is the same as or similar to the configuration of the memory device 500 in the embodiment of FIG. is omitted.

12A and 12B , an internal process for swapping data of the first core die 520 and data of the second core die 530 may be performed according to a command from an external memory controller, and a buffer The die 510 may generate a series of internal commands for data swap and provide it to the first and second core dies 520 and 530 . Also, the in-memory processor 511 may select a core die to perform a function according to an internal command by outputting a chip select signal chip_select.

Referring to FIG. 12B as an example of an internal process for data swapping, first, data of the first core die 520 corresponding to the first channel CH A is read (CH A RD) according to an internal command, and then data is read. The data is stored in a latch of the data processing unit 526 of the first core die 520 . After the data of the first core die 520 is stored in the latch of the data processing unit 526 , the switch of the data processing unit 526 may be turned off to cut off the electrical connection between the latch and the TSV transferring data (CH). A lat_off).

In addition, data from the second core die 530 corresponding to the second channel CH B is read (CH B RD) according to the internal command, and the data read from the second core die 530 is transferred to the internal common bus is provided to the first core die 520 through the TSV. In addition, data provided to the first core die 520 is written to the cell core 521 of the first core die 520 according to an internal command (CH A WR). Thereafter, as the switch of the data processing unit 526 of the first core die 520 is turned on (CH A lat_on), the data read from the first core die 520 is the internal common bus and the second through the data TSV Data provided to the core die 530 and data provided to the second core die 530 are written to the cell core 531 of the second core die 530 according to an internal command (CH B WR).

Even when data of different channels are swapped as described above, data read from one channel can be provided to another channel through the internal common bus without the intervention of the memory controller, thereby increasing the memory access frequency of the system Without this, data swap between channels may be performed through a process inside the memory device.

13A, B, and C are block diagrams illustrating an example in which a Read Modify Write (RMW) is performed in a memory device according to an embodiment of the present invention. The configuration of the memory device 600 shown in FIG. 13A is the same as or similar to the configuration of the memory device 500 in the embodiments of FIGS. 11 and 12A and B described above, and thus each of the components shown in FIG. 13A is Duplicate description of the will be omitted.

13A, B, and C , the memory device 600 may include a buffer die 610 and first and second core dies 620 and 630 as one or more core dies, and first and second The two-core dies 620 and 630 may include different channels Ch A and CH B corresponding to memory cell cores (or cell groups, 621 and 631 ), respectively. Also, the buffer die 610 may include an input/output circuit corresponding to each channel. The buffer die 610 may include an in-memory processor 611 , and each input/output circuit includes an interface unit 612 , a path control unit 613 , a read data path 614 , and a write data path 615 . and one or more latches 616 . The in-memory processor 611 may perform various control functions related to an internal process, and as an example, the in-memory processor 611 may perform an operation of generating an internal command. Also, the in-memory processor 611 may further generate a chip select signal chip_select for selecting a core die on which a memory operation is to be performed according to an internal command.

In addition, the first core die 620 includes a cell core 621 including a cell region, a command decoder 622 for decoding an internal command, a write data path 623 , a read data path 624 , and a transceiver 625 . ) may be included. In addition, the first core die 620 may include a processor in memory (PIM) function block 626 that performs arithmetic processing on data to be written and/or data to be read. Accesses such as writing and reading data to and from the cell core 621 may be performed in parallel with respect to a plurality of bits, and accordingly, a plurality of transceivers 625 and a plurality of PIM function blocks 626 corresponding thereto These may be provided on the first core die 620 .

As an embodiment, the operation of the PIM function block 626 may be controlled according to various methods. For example, the PIM function block 626 may be controlled by a PIM control signal PIM_ctrl according to a decoding result of an internal command. .

In addition, the second core die 630 may be implemented the same or similar to the first core die 620 , so that the second core die 630 includes a cell core 631 , a command decoder 632 , and a write operation. It may include a data path 633 , a read data path 634 , a transceiver 635 , and a PIM function block 636 . Depending on the type of internal command provided to the core die, the PIM function block 626 of the first core die 620 and the PIM function block 636 of the second core die 630 may perform different functions. .

The PIM function blocks 626 and 636 may be implemented in various ways to perform arithmetic processing on data. According to an embodiment, the PIM function blocks 626 and 636 may include a function that performs a boolean operation, and may perform operations such as AND, OR, XOR, and NOT on data. As one implementation example, as shown in FIG. 13B , each of the PIM function blocks 626 and 636 includes one or more switches A0 and A1, one or more latches Lat 1 and Lat 2, an operation unit (Function) and a buffer (Function). A2) may be included. The operation unit (Function) may perform the above-described boolean operation.

As an example of an operation of Read Modify Write (RMW), when data is written to one region of the cell core, after data stored in the one region is read, the bit values of the read data and the data to be written are compared with each other. And, according to the comparison result, data having different bit values of read data and data to be written may be selectively written in one region of the cell core.

Referring to FIG. 13C , when a Read Modify Write (RMW) is performed on one region of the cell core 631 of the second core die 630 , data of one region of the cell core 631 is read (CH B RD), the read data is stored in the latch Lat 1 through the first switch A0 of the PIM function block 636 . After data is stored in the latch Lat 1 , the first switch A0 is turned off (A0 Off), and the second switch A1 is turned on (A1 On).

In addition, write data to be written to one area of the cell core 631 is provided to the second core die 630 through the data TSV as an internal common bus (Data_WR). Since a comparison operation is performed on the write data before the write data is written to the cell core 631 , the receiver (or the write buffer) may have an off state (WR Buf Off). The write data is provided to the operation unit (Function) through the second switch (A1) of the PIM function block (636). The operation unit (Function) compares data read from one area of the cell core 631 and write data. Also, the comparison result is temporarily stored in the latch Lat 2 .

According to the comparison result, only some bits of the write data may be selectively written to one area of the cell core 631 . The second switch A1 is turned off (A1 Off), the buffer A2 is activated (A2 On), and the read data and the data to be written have different bit values through the buffer A2 into the cell. It may be provided as a core 631 . Accordingly, a selective write operation (CH B WR) may be performed on some bits of the write data.

14A and 14B are block diagrams illustrating an example in which Read Modify Write (RMW) is simultaneously performed on two or more core dies in a memory device according to an embodiment of the present invention. Since the configuration of the memory device 600 shown in FIG. 14A is the same as or similar to that of the memory device 600 in the embodiment of FIG. 13A described above, the overlapping description of each of the components shown in FIG. 14A is not is omitted.

Referring to FIGS. 14A and 14B , write data may be written together to the first and second core dies 620 and 630 according to a Read Modify Write (RMW) method, and first, a cell of the second core die 630 . Data of one region of the core 631 may be read (CH B RD). Data read from the cell core 631 is stored in the latch Lat 1 through the first switch A0 of the PIM function block 636 . After data is stored in the latch Lat 1 , the first switch A0 is turned off (CH B A0 Off). Also, data of one region of the cell core 621 of the first core die 620 may be read (CH A RD). Data read from the cell core 621 is stored in the latch Lat 1 through the first switch A0 of the PIM function block 626, and after the data is stored in the latch Lat 1, the first switch A0 is turned off (CH A A0 Off).

Thereafter, the second switches A1 of all channels may be turned on (All CH A1 On), and the receivers (or write buffers) of all channels may be turned off (WR Buf Off). Further, write data is provided to the first core die 620 and the second core die 630 through the data TSV as an internal common bus (Data_WR). As the write data is provided to the operation unit (Function), a comparison operation on the read data and the write data may be performed similarly to the above-described embodiment, and the second switches A1 of all channels may be changed to a turned-off state. Yes (All CH A1 Off).

Thereafter, at least some bits of the write data may be written to the first core die 620 and the second core die 630 according to the comparison result, respectively. As an example, the buffer A2 of the first core die 620 is enabled (CH A A2 On), and at least a portion of the write data is written to the cell core 621 of the first core die 620 ( CH A WR). In addition, the buffer A2 of the second core die 630 is enabled (CH B A2 On), and at least a portion of the write data is written to the cell core 631 of the second core die 630 (CH B WR).

According to the above embodiment, when RMW (Read Modify Write) is performed on at least two core dies, write data may be provided to at least two core dies together through an internal common bus without intervention of a memory controller, , accordingly, Read Modify Write (RMW) may be performed together with respect to the two core dies.

15A and 15B are block diagrams illustrating an example in which mask write is performed in a memory device according to an embodiment of the present invention. 15A and 15B illustrate only the PIM functional blocks provided in the core dies of the memory device for convenience of description.

In the case of a mask write, the memory controller may provide mask data corresponding to the write data together with the write data. As an example, a mask data value may be set to a logic high or a logic low corresponding to each of a plurality of bits included in the write data, and a write operation may be selectively performed only on data whose mask data value corresponds to a logic low. have. In addition, in the case of mask write, an internal read operation may be performed first before a write operation is performed, because a previous write state of some data is maintained according to the value of the mask data.

15A and 15B , the memory device 700 may include a buffer die and one or more core dies (above, not shown), wherein the first core die includes a first PIM function block 720 , The second core die may include a second PIM function block 730 . The first PIM function block 720 may include one or more switches A0 and A1, one or more latches Lat A1 and Lat A2, a buffer A2, and a multiplexer MUX A. Also, the second PIM function block 730 may include one or more switches B0 and B1, one or more latches Lat B1 and Lat B2, a buffer B2, and a multiplexer MUX B.

A case in which mask writing is performed on the second core die corresponding to channel B is exemplified. First, as a mask write command is received from the memory controller, data is read from the cell core of the second core die according to an internal process of the memory device 700 (CH B RD), and the read data is the second PIM function block It may be stored in the latch Lat B1 of 730 . After the read data is stored in the latch Lat B1, the first switch B0 may be turned off (CH B B0 Off).

In addition, the receivers (or write buffers) of all channels are turned off (WR Buf Off), and write data is provided to the memory device (Data_WR). The write data may be provided to the first core die through the data TSV corresponding to the internal common bus, and the write data may be stored in the latch Lat A1 of the first PIM function block 720 . After the write data is stored in the latch Lat A1, the first switch A0 of the first PIM function block 720 may be turned off (CH A A0 Off).

Also, the second switches A1 and B1 of all channels may be turned on (All CH A1, B1 On), and mask data may be provided from the memory controller to the memory device (Data_mask). The mask data may be stored in the latch Lat A2 through the multiplexer MUX A of the first PIM function block 720 , and the mask data may also be stored in the multiplexer MUX B of the second PIM function block 730 . It may be stored in the latch Lat B2. According to an embodiment, for each bit of the mask data, the bit value of the mask data may be inverted in the first PIM function block 720 and stored in the latch Lat A2, and the second PIM function block 730 ), the bit value of the mask data may be stored in the latch Lat B2 without being inverted.

Thereafter, according to the bit value of the mask data, the write data stored in the first PIM function block 720 is provided to the cell core of the second core die to be written, or the read data stored in the second PIM function block 730 is It may serve as the cell core of the second core die to be recorded. For example, the buffer A2 of the first PIM function block 720 may be enabled according to the inverted bit value of the mask data, and the buffer B2 of the second PIM function block 730 is the bit of the mask data. It can be enabled depending on the value.

If the write data is blocked from being written to the cell core when the bit of the mask data has a logic high, the buffer B2 of the second PIM function block 730 is enabled in response to the mask data having a logic high. , accordingly, the read data stored in the second PIM function block 730 is provided to the cell core of the second core die to be written. That is, the write data corresponding to the mask data having a logic high may be blocked from being provided to the cell core of the second core die.

On the other hand, when the bit of the mask data has a logic low, as the buffer A2 of the first PIM function block 720 is activated, the write data provided from the memory controller is transferred to the cell core of the second core die to be written. provided On the other hand, since the buffer B2 of the second PIM function block 730 is disabled, provision of read data to the cell core of the second core die to be written may be blocked.

In the above-described embodiment, an example in which data read from the second core die to be masked is stored in the second PIM function block 730 and write data is stored in the first PIM function block 720 has been described. Examples need not be limited thereto. As an example, data read from the second core die is stored in the first PIM function block 720 , and after the write data is stored in the second PIM function block 730 , write data or The read data may be selectively written to the cell core of the second core die.

According to the above-described embodiment, mask writing may be performed through an internal process in the memory device 700 without intervention of the memory controller. In addition, read data and write data used in an internal process for mask writing can be transmitted and received between core dies through an internal common bus, and thus data bandwidth efficiency is improved as the access frequency of the memory device of the system is reduced can be

16 is a block diagram illustrating a memory device according to a deformable embodiment of the present invention. 16 illustrates an example in which a memory device includes a plurality of layers, at least one of the plurality of layers constitutes a master die, and at least one other constitutes a slave die.

As an example, the master die and the slave die may be stacked on a substrate, and the stacked master die and the slave die may transmit and receive signals to each other through the through silicon via. In addition, the master die and the slave die may be implemented through the same memory process, and the master die and the slave die may each include a cell core for storing data. In addition, the master die may include an input/output circuit (IO) for communicating with an external memory controller.

According to an embodiment of the present invention, the master die may include an in-memory processor that serially generates internal commands for performing an internal process according to a command from the memory controller. In addition, each slave die includes a PIM function block, and various operations on data may be performed within the memory device according to the above-described embodiments by the PIM function block. In addition, at least some of the plurality of TSVs formed in the TSV region are used as an internal common bus inside the memory device, and data may be transmitted/received between the master die and the slave die through the internal common bus.

Hereinafter, an example in which an internal common bus is disposed on a buffer die (or a master die) in a memory device according to an embodiment of the present invention will be described.

17 and 18 are block diagrams illustrating an implementation example of a buffer die included in a memory device according to an embodiment of the present invention.

Similar to the above-described embodiment, the memory device includes a plurality of layers, any one of which may be a buffer die (or a master die) that communicates with an external memory controller. As an example, the memory device may have a high bandwidth memory (HBM) type, and one or more core dies stacked on the buffer die may form channels independent from each other. Also, as an example, each core die may configure two or more channels.

The buffer die may include a physical (PHY) area that interfaces with the memory controller and a TSV area in which a plurality of TSVs are formed for communication with one or more core dies. Also, according to an embodiment, the buffer die may further include an internal common bus shared for a plurality of channels configured by the core dies. Various signals may be provided to a plurality of channels through the internal common bus.

As an embodiment, the buffer die may further include an internal command generator and a data processor. For example, the internal command generation unit may be implemented as the in-memory processor in the above-described embodiments, and the data processing unit may be implemented as the PIM function block in the above-described embodiments.

The buffer die may generate internal commands for an internal process in response to a command from the memory controller and provide the generated internal commands to channels through an internal common bus. In addition, the data processing unit may perform a processing operation on externally written data, and may also perform a processing operation on data read from one or more core dies. Unprocessed data and/or processed data may be provided to channels via an internal common bus.

The internal common bus may be connected to the TSV region through a physical (PHY) region having input/output circuits corresponding to a plurality of channels. Same or similar to the above-described embodiments, the memory device may perform data copy, swap, read modify write (RMW) and mask write as internal processes without intervention of the memory controller. Also, data may be transmitted/received through an internal common bus between multiple channels.

Meanwhile, in the embodiment of FIG. 18 , a case in which a signal transmission path of the buffer die has the order of a physical (PHY) area, a TSV area, and an internal common bus is exemplified. In this case, an internal command from the internal command generating unit or data from the data processing unit may be provided to the core die through the internal common bus and TSV of the TSV area without passing through the physical (PHY) area.

19 and 20 are diagrams illustrating specific implementation examples of the buffer die illustrated in FIGS. 17 and 18 described above.

Referring to FIG. 19 , the buffer die 800A of the memory device may include a TSV area 810 , a physical area 820 , and an internal common bus 830 . The TSV region 810 may include TSVs having independent signal transmission paths for a plurality of channels, and as an example, provides commands to the core dies through different command TSVs for each channel, and also provides each channel with each other. It provides data to the core dies through another data TSV. According to one embodiment, as shown in FIG. 19 , the TSV region 810 includes TSVs that transmit signals related to memory operation of channels, and additionally used for a separate test (eg, a power test). It may further include TSVs.

The physical area 820 may also communicate with an external memory controller through different input/output circuits for each channel, and signals from different input/output circuits for each channel may be provided as TSVs of corresponding channels. Also, the internal common bus 830 may be commonly connected to input/output circuits corresponding to a plurality of channels of the physical area 820 .

The internal command generator 840 generates a series of internal commands for internal processes in the memory device and provides them to the internal common bus 830 . Internal commands are provided to the core dies through physical region 820 and TSV region 810 . In addition, the data processing unit 850 may perform data processing operations related to various types of memory operations, such as data copy, swap, read modified write (RMW), and mask write, according to the above-described embodiments. According to an embodiment, data from the data processing unit 850 is provided to the internal common bus 830 , and data provided to the internal common bus 830 is transmitted through the physical area 820 and the TSV area 810 to the core die. are provided with In addition, data read from one core die is provided to the data processing unit 850 through the internal common bus 830 , and the processed data from the data processing unit 850 is transmitted to another core through the internal common bus 830 . It may be provided as a die.

Meanwhile, the buffer die 800B of the memory device shown in FIG. 20 has a configuration similar to that of the buffer die 800A shown in FIG. 19 , and has a structure in which the internal common bus 830 is connected to the TSV region 810 . have In this case, an internal command from the internal command generation unit 840 or data from the data processing unit 850 may be directly provided to the TSV region 810 and transmitted to the core dies.

21 and 22 are block diagrams illustrating a deformable implementation example of the buffer die of the present invention. 21 and 22 show an example in which a bus for transferring a test signal in the DA area of the buffer die is used as an internal common bus.

Referring to FIG. 21 , the buffer die may include a physical (PHY) area that interfaces with the memory controller and a TSV area in which a plurality of TSVs are formed for communication with one or more core dies. In addition, the buffer die may further include a DA area in which a bus capable of directly communicating with an external tester is disposed regardless of the memory controller. A test-related signal provided to the DA area may be transmitted to TSVs through a bus in the DA area, and a test result may be provided to an external tester through the TSV area and the DA area.

A test operation using the DA area may be performed for a plurality of channels, and in this case, a bus related to a test in the DA area may be implemented to be shared for a plurality of channels of the memory device. According to an embodiment of the present invention, a bus in the DA area may be used as the internal common bus used for an internal process of the memory device. In addition, the internal command generator for the internal process may generate an internal command and provide it to the core dies through a bus in the DA area. In addition, data read from the core dies may be provided to the data processing unit through a bus in the DA area, and data from the data processing unit may be provided to the core dies through a bus in the DA area.

Meanwhile, referring to FIG. 22 , the buffer die may include a physical (PHY) area and a TSV area, and a DA area including a bus common to a plurality of channels may be disposed adjacent to the physical (PHY) area. The bus in the DA area can be used as an internal common bus for internal processes. In the example of FIG. 21 described above, signal transfer through the internal common bus in the DA area may be provided to the core dies through the TSV area without passing through the physical (PHY) area. On the other hand, in the example of FIG. 22 , internal commands and data transferred through an internal common bus may be provided to the core dies through a physical (PHY) region and a TSV region.

Meanwhile, in the examples shown in FIGS. 21 and 22 , the internal command generating unit and the data processing unit are illustrated as being provided in the DA area, but the embodiment of the present invention is not limited thereto. For example, the internal command generating unit and the data processing unit may be disposed outside the DA area in the buffer die.

23 and 24 are block diagrams illustrating an example of a signal transmission path in the buffer die illustrated in FIGS. 21 and 22 described above.

Referring to FIG. 23 , internal commands and data from the internal common bus (DA BUS) in the DA area may be provided to the TSV area without passing through the physical (PHY) area. As an example, the physical (PHY) region includes an independent input/output circuit for each channel, and accordingly, a signal for the channel A is transmitted to the core dies through the TSV corresponding to the channel A in the TSV region. Similarly, the signal for channel B is delivered to the core dies through the TSV corresponding to channel B in the TSV region, and the signal for channel C is delivered to the core dies through the TSV corresponding to channel C in the TSV region. is transmitted to

The internal common bus (DA BUS) in the DA area is disposed in common for a plurality of channels, and a selection unit ( For example, a multiplexer) may be provided on the buffer die. As an example, when internal commands/data are independently transmitted for each channel, internal commands and data from the physical (PHY) area are selected and transmitted to the core dies through the TSV. On the other hand, when an internal command or data is provided to the core dies in the internal process according to the embodiments of the present invention, the internal command or data is selected and transmitted to the core dies through the TSV.

Meanwhile, FIG. 24 shows an example in which an internal command or processed data is provided to core dies through a physical (PHY) region and a TSV region.

Referring to FIG. 24 , the internal common bus (DA BUS) in the DA area may be disposed at the front end of the physical (PHY) area, and a signal independently provided for each channel and a signal transmitted through the internal common bus (DA BUS) A selection unit (eg, a multiplexer) for selecting ? may be disposed at the front end of the physical (PHY) area. For example, commands/data independently transmitted for each channel may be received through bumps formed on the outer surface of the memory device. In the normal operation of independently transmitting signals for each channel, a signal transmitted through a bump is selected, and in the internal process as in the above-described embodiments, a signal transmitted through an internal common bus (DA BUS) is selected. can

25 is a structural diagram illustrating an example of a semiconductor package including a memory device according to embodiments of the present invention.

Referring to FIG. 25 , the semiconductor package 900 may include one or more memory devices 910 and a memory controller 920 . The memory device 910 and the memory controller 920 are mounted on an interposer 930 , and the interposer on which the memory device 910 and the memory controller 920 are mounted is a package substrate 940 . can be mounted on The memory controller 920 may correspond to a semiconductor device capable of performing a memory control function, and as an example, the memory controller 920 may be implemented as an application processor (AP).

The memory device 910 may be implemented in various forms, and according to an embodiment, the memory device 910 may be a high bandwidth memory (HBM) type memory device in which a plurality of layers are stacked. Accordingly, the memory device 910 includes a plurality of channels, and according to an embodiment of the present invention, an internal common bus commonly disposed for the plurality of channels may be provided in the memory device 910 . Also, the memory device 910 may include an internal command generator that generates an internal command for an internal process and a data processor that processes write data and/or read data.

A plurality of memory devices 910 may be mounted on the interposer, and the memory controller 920 may communicate with the plurality of memory devices 910 . As an example, each of the memory devices 910 and the memory controller 920 may include a physical (PHY) area, between the memory devices 910 and the memory controller 920 through the physical (PHY) area. Communication may be performed. On the other hand, when the memory device 910 includes the DA region, the test signal is transmitted into the memory device 910 through the conductive means (eg, solder balls 950 ) mounted under the package substrate 940 and the DA region. can be provided.

Here, the interposer may include an organic or non-TSV type embedded multi-die interconnect bridge (EMIB) in a silicon (TSV) type, a PCB type, or the like.

26 is a block diagram illustrating a computing system including a memory device according to an embodiment of the present invention. The memory device of the present invention may be mounted as the RAM 1020 in the computing system 1000 such as a mobile device or a desktop computer. Any one of the above-described embodiments may be applied to the memory device mounted as the RAM 1020 .

The computing system 1000 according to an embodiment of the present invention includes a central processing unit 1010 , a RAM 1020 , a user interface 1030 , and a nonvolatile memory 1040 , and each of these components includes a bus 1050 . ) is electrically connected to As the nonvolatile memory 1040, a mass storage device such as an SSD or HDD may be used.

As the memory device (or memory system) according to an embodiment of the present invention is applied to the computing system 1000 , the memory device included in the RAM 1020 has a structure in which a plurality of layers are stacked according to the above-described embodiment. may have, at least one of which may correspond to a buffer die and the rest may correspond to a core die. In addition, an internal command generator and a data processor (not shown) may be provided in the RAM 1020 for an internal process of the memory device, and an internal common to a plurality of layers (or a plurality of channels) A common bus may be provided in the RAM 1020 . The internal command may be provided to a plurality of channels through the internal common bus, and data of one channel may be provided to another channel through the internal common bus.

Since the description of the above embodiment is merely an example with reference to the drawings for a more thorough understanding of the present invention, it should not be construed as limiting the present invention. In addition, it will be apparent to those of ordinary skill in the art to which the present invention pertains that various changes and modifications can be made without departing from the basic principles of the present invention.

Claims (20)

A memory device comprising:
In order to receive a first external command for performing at least one internal data processing operation by the memory device from an external memory controller, and perform the at least one internal data processing operation in response thereto, the memory device performs a corresponding internal data processing operation. a buffer die including an internal command generator that generates at least two internal commands to execute memory operations;
a first core die stacked on the buffer die, each including a plurality of DRAM cells, wherein the DRAM cells are disposed in at least a first group of memory cells of a first core die and a second group of memory cells of a second core die; a second core die;
a plurality of through silicon vias (TSV) extending through the first and second core dies and connected to the buffer die;
at least two independent channels each associated with a corresponding one of the first and second groups of memory cells, each channel comprising a corresponding set of TSVs; and
and a common internal processing channel shared between the first and second groups of memory cells of the first and second core dies. According to claim 1,
each of the at least two independent channels includes a corresponding independent data bus for a corresponding group of memory cells, and wherein the common internal processing channel comprises a common internal data bus shared between the at least two groups of memory cells. containing memory devices. The method of claim 1,
each of the at least two independent channels includes a corresponding independent command/address bus for an associated group of memory cells, the common internal processing channel including a common internal command/address bus shared between the at least two groups of memory cells A memory device comprising an address bus. According to claim 1,
each of the at least two independent channels includes a corresponding independent command/address bus for an associated group of memory cells;
wherein the memory device further comprises at least two independent internal command/address signal buses each associated with any one of the at least two memory cell groups. According to claim 1,
The common internal processing channel includes at least some of the plurality of TSVs, and when the memory device performs at least one internal data processing operation, the TSVs of the common internal processing channel are connected to at least two memory cell groups. A memory device shared by The method of claim 1,
wherein the first core die includes at least one first data processor associated with the first group of memory cells, and the second core die includes at least one second data processor associated with the second group of memory cells;
and the first and second data processors perform at least one internal data processing operation in response to at least one control signal provided by the internal command generator. 7. The method of claim 6,
The at least one internal data processing operation includes at least one of a data addition operation, an exclusive OR operation, a data subtraction operation, and a data multiplication operation. The method of claim 1,
When the memory device receives a second external command corresponding to a normal command from the memory controller, the normal command is provided to one of the memory cell groups through a related independent channel. A memory device comprising:
In order to receive a first external command for performing at least one internal data processing operation by the memory device from an external memory controller, and perform the at least one internal data processing operation in response thereto, the memory device performs a corresponding internal data processing operation. a buffer die including an internal command generator that generates at least two internal commands to execute memory operations;
at least one core die stacked on the buffer die and including a plurality of DRAM cells disposed in a plurality of memory cell groups;
a plurality of through silicon vias (TSV) extending through the at least one core die and coupled to the buffer die; and
at least two independent channels each associated with a corresponding one of said groups of memory cells, each channel comprising a corresponding set of TSVs;
At least some of the plurality of TSVs are shared by at least two of the plurality of memory cell groups when the memory device performs the at least one internal data processing operation. 10. The method of claim 9,
and wherein the at least some TSVs shared by the at least two of the plurality of memory cell groups include a common internal processing channel shared between the plurality of memory cell groups. 10. The method of claim 9,
The first external command may include at least one of a data copy command, a data swap command, a Read Modify Write (RMW) command, and a mask write command. 10. The method of claim 9,
Further comprising a plurality of data processors,
each data processor is associated with one of said groups of memory cells and is provided on the same core die as said associated group of memory cells;
The data processors perform the at least one internal data processing operation in response to the at least one control signal provided by the internal command generator. 10. The method of claim 9,
The at least one internal data processing operation includes at least one of a data addition operation, an exclusive OR operation, a data subtraction operation, and a data multiplication operation. 10. The method of claim 9,
When the memory device receives a second external command corresponding to a normal command from the memory controller, the normal command is provided to one of the memory cell groups through a related independent channel. A memory device comprising:
a plurality of DRAM cells disposed in a plurality of memory cell groups;
a plurality of independent channels each associated with a corresponding one of the plurality of memory cell groups;
At least a first external command is received from an external memory controller to perform at least one internal data processing operation by the memory device, and in response, corresponding memory operations are executed to perform the at least one internal data processing operation an internal command generator that generates at least two internal commands to be executed; and
and a common internal processing channel shared among the plurality of groups of memory cells;
The first external command may include at least one of a data copy command, a data swap command, a Read Modify Write (RMW) command, and a mask write command. 16. The method of claim 15,
a plurality of independent channels each associated with a corresponding one of the at least two memory cell groups to perform normal operations on DRAM cells of the plurality of memory cell groups;
The common internal processing channel is shared between the at least two memory cell groups to perform internal data processing operations on DRAM cells of the at least two memory cell groups. delete 16. The method of claim 15,
a plurality of data processors each coupled to one of said groups of memory cells;
and the data processors perform at least one internal data processing operation on the data of the related memory cell group in response to at least one control signal provided by the internal command generator. 19. The method of claim 18,
The at least one internal data processing operation includes at least one of a data addition operation, an exclusive OR operation, a data subtraction operation, and a data multiplication operation. 16. The method of claim 15,
When the memory device receives a second external command corresponding to a normal command from the memory controller, the normal command is provided to one of the plurality of memory cell groups through a related independent channel.

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