TW201740577A - Light-emitting device and manufacturing method thereof - Google Patents

Abstract

A light-emitting device comprising a substrate; a reflective layer on the substrate; a dielectric layer on the reflective layer, wherein the dielectric later has a through hole; a light-emitting stack on the dielectric layer, wherein the light-emitting stack comprises an active layer and a top surface; and an opaque layer covers a first part of the top surface of the light-emitting stack and exposes a second part of the top surface, and the second part is directly above the through hole.

Description

Light-emitting element and method of manufacturing same

The present invention relates to a light-emitting element and a method of manufacturing the same.

Light-Emitting Diode (LED) has characteristics such as low energy consumption, long operating life, shock resistance, small size, fast response speed, and stable wavelength of output light, so it is suitable for various applications. Recently, in addition to general lighting applications, it has been further developed for industrial applications, such as industrial counting, sensors, and the like.

A light-emitting element comprising: a substrate; a reflective layer above the substrate; an insulating layer above the reflective layer, wherein the insulating layer has a first through hole; a light emitting layer is over the insulating layer, the light emitting layer An active area having an upper surface; and an opaque layer covering a first portion of the upper surface of the light emitting laminate to expose a second portion of the upper surface, and wherein the second portion is at the first portion Just above the perforation.

A method of fabricating a light-emitting device, comprising: forming a light-emitting layer, wherein the light-emitting layer comprises an active region; forming an insulating layer over the light-emitting layer, wherein the insulating layer has a first through hole; and forming a reflective layer Above the insulating layer; providing a substrate; bonding the substrate and the light emitting layer, wherein the reflective layer is located between the substrate and the light emitting layer; and forming an opaque layer in the bonding direction of the light emitting layer and the substrate The opposite side covers a first portion of one of the surfaces of the light-emitting laminate and exposes a second portion of the surface, and the second portion is positioned opposite to the first through-hole of the insulating layer.

The present invention will be described with reference to the drawings, in which the same or the same reference numerals are used in the drawings or the description, and in the drawings, the shape or thickness of the elements may be enlarged or reduced. It is to be noted that elements not shown or described in the specification may be in a form known to those skilled in the art.

1A to 1T are views showing a light-emitting element according to a first embodiment of the present invention and a method of manufacturing the same. As shown in FIG. 1A, a growth substrate 101, such as gallium arsenide (GaAs), is first provided, and a buffer layer 102, a first contact layer 103, and a light-emitting layer 104 are sequentially formed thereon. Wherein, the buffer layer 102 can block etching or grow the substrate more difficult to be etched in the subsequent step of removing the growth substrate 101. Therefore, according to the etching method, for example, wet etching, the buffer layer 102 can be selectively used and the growth substrate 101 is larger. The material of the difference in etching rate, for example, when the growth substrate 101 is a gallium arsenide substrate, the material of the buffer layer 102 may be selected from indium gallium phosphide (InGaP) or aluminum gallium arsenide (AlGaAs). In some embodiments of the present invention, if the growth substrate 101 and the first contact layer 103 have significant etch rate differences for the same etchant, for example, the etch rate of the growth substrate 101 is greater than the etch rate of the first contact layer 103 by at least 2 The number of levels, or the etch rate of the first contact layer 103 is greater than the etch rate of the growth substrate 101 by at least 2 orders of magnitude, the buffer layer 102 may not be provided. The first contact layer 103 can provide a low resistance contact, such as less than 10 ^-3 Ω-cm, and the material thereof is, for example, an n-type doped gallium arsenide (GaAs), and its doping concentration can be higher than 1*10 ¹⁸ (/ Cm ³ ). The light emitting laminate 104 includes a first electrical semiconductor layer 104a, a second electrical semiconductor layer 104c, and an active region 104b between the first electrical semiconductor layer 104a and the second electrical semiconductor layer 104c. The first electrical semiconductor layer 104a and the second electrical semiconductor layer 104c are electrically different, for example, the first electrical semiconductor layer 104a is an n-type semiconductor layer, and the second electrical semiconductor layer 104c is a p-type semiconductor layer. The first electrical semiconductor layer 104a, the active region 104b, and the second electrical semiconductor layer 104c are formed of a III-V material, such as an aluminum gallium indium phosphide series ((Al _y Ga( _1-y )) _{1- x} In _x P, where 0≦x≦1; 0≦y≦1) material.

Next, as shown in FIG. 1B, a second contact layer 105 is formed on the light emitting stack 104 to provide a low resistance contact, such as less than 10 ^-3 Ω-cm, such as gallium phosphide (GaP). In this embodiment, the thickness of the second contact layer 105 is not too thick, for example, not more than 1.5 μm; or the thickness of the second contact layer 105 is between 0.1 μm and 0.5 μm. Next, as shown in FIG. 1C, an insulating layer 106 is formed on the second contact layer 105. The refractive index of the insulating layer 106 may be smaller than the equivalent refractive index of the light emitting layer 104. The material of the insulating layer 106 may comprise a material selected from the group consisting of yttrium oxide (SiO _x ), magnesium fluoride (MgF ₂ ), and tantalum nitride (SiN _x ). The thickness of the insulating layer 106 is about 50 nm to 300 nm. The thickness of the insulating layer 106 is between about 100 nm and 200 nm. Next, as shown in FIG. 1D, a first via 106h is formed in the insulating layer 106 through the insulating layer 106 by a yellow light and an etching process. The first via 106h is viewed from the insulating layer 106 toward the light emitting layer 104. It is substantially circular (not shown) and has a diameter D ₁ , a diameter D ₁ of between about 20 μm and 150 μm, or a diameter D ₁ of between about 40 μm and 90 μm.

Next, as shown in FIG. 1E, a first transparent conductive layer 107 is formed on the insulating layer 106 and filled in the first via 106h, so that the first transparent conductive layer 107 and the light emitting layer 104 are formed by the first via 106h. Electrical connection. The magnitude of the current supplied to the light emitting stack 104 can be controlled by adjusting the size of the first via 106h. Then, as shown in FIG. 1F, a second transparent conductive layer 108 is formed on the first transparent conductive layer 107, and the material thereof is different from the material of the first transparent conductive layer 107, or even the forming method may be different. The second transparent conductive layer 108 may have a function of enhancing current spreading in a lateral direction (ie, a direction perpendicular to a stacking direction of the light emitting laminate 104) or a function as a light transmitting layer. Considering the function as a light transmissive layer, the second transparent conductive layer 108 may select a material having a lower refractive index than the light emitting laminate 104. Considering the function of providing lateral current diffusion, the thickness of the second transparent conductive layer 108 may be thicker than the thickness of the first transparent conductive layer 107, for example, viewed from the direction of the insulating layer 106 toward the second transparent conductive layer 108, the first transparent conductive The layer 107 has a thickness between about 25 Å and 200 Å, or between 40 Å and 60 Å, and the second transparent conductive layer 108 has a thickness between about 25 Å and 2000 Å, or between 600 Å and 1000 Å. In other embodiments of the present invention, the second transparent conductive layer 108 may not be formed, but the thickness of the first transparent conductive layer 107 may be thickened to replace the function of the second transparent conductive layer 108. The first transparent conductive layer 107 and the second transparent conductive layer 108 respectively comprise a material selected from the group consisting of Indium Tin Oxide (ITO), Aluminium Zinc Oxide (AZO), cadmium tin oxide, antimony tin oxide, and oxidation. A group consisting of zinc (ZnO), zinc tin oxide, indium zinc oxide (Indium Zinc Oxide, IZO), and graphene (Graphene). In this embodiment, the material of the first transparent conductive layer 107 is Indium Tin Oxide (ITO), and the material of the second transparent conductive layer 108 is Indium Zinc Oxide (IZO). The first transparent conductive layer 107 can be formed using an electron beam gun (E-gun), and the second transparent conductive layer 108 can be formed using sputtering, but the invention is not limited thereto, and another embodiment The first transparent conductive layer 107 and the second transparent conductive layer 108 may also use the same forming method. In addition, the density of the second transparent conductive layer 108 may be the same as or different from the density of the first transparent conductive layer 107. In this embodiment, the second transparent conductive layer 108 is denser than the first transparent conductive layer 107, that is, the second transparent The density of the conductive layer 108 is higher than the density of the first transparent conductive layer 107 to facilitate the lateral current spreading described above.

Next, as shown in FIG. 1G, a reflective layer 109 is formed on the second transparent conductive layer 108 to reflect the light emitted by the light-emitting layer 104. In this embodiment, the reflective layer 109 can be applied to the light-emitting layer. The emitted light has a reflectance greater than 85%, wherein the reflective layer 109 may comprise a metallic material such as gold (Au) or silver (Ag).

Next, as shown in FIG. 1H, the first bonding layer 110a is formed on the reflective layer 109, and the second bonding layer 110b is formed on the first bonding layer 110a. Figure 1I shows the inversion of Figure 1H. Next, as shown in FIG. 1J, a permanent substrate 111 is provided, and a third bonding layer 110c is formed on the permanent substrate 111, and then the third bonding layer 110c is bonded to the second bonding layer 110b, and bonded. The situation is shown in Figure 1K. The first bonding layer 110a, the second bonding layer 110b, and the third bonding layer 110c form a bonding structure 110. The bonding structure 110 may comprise a low temperature fused material having a melting point of less than or equal to 300 ° C, such as indium (In) or tin (Sn). In this embodiment, the material of the first bonding layer 110a is gold (Au), the material of the second bonding layer 110b is low-temperature fusion material indium (In), and the material of the third bonding layer 110c is gold (Au), in one At a low temperature, for example, a temperature less than or equal to 300 ° C, the first bonding layer 110a, the second bonding layer 110b, and the third bonding layer 110c may form an alloy due to a eutectic effect and bond into the bonding structure 110, wherein The bonding structure 110 includes an alloy of indium (In) and gold (Au). In another embodiment, the second bonding layer 110b may be formed on the third bonding layer 110c and then bonded to the first bonding layer 110a to form the bonding structure 110. Next, the growth substrate 101 is removed, as shown in FIG. 1L. In this embodiment, the wet etching etching method is selected to remove the growth substrate 101, and the etching liquid is, for example, an etching liquid containing ammonia water (NH ₃ ·H ₂ O) and hydrogen peroxide (H ₂ O ₂ ), and contains indium gallium phosphide (In The buffer layer 102 of _x Ga _1-x P, where 0 ≦ x ≦ 1) is harder to be etched than the growth substrate 101, so that the process of removing the growth substrate 101 can be controlled without damaging the light-emitting laminate 104. Then, since the buffer layer 102 containing indium gallium phosphide ((In _x Ga _1-x P, where 0 ≦ x ≦ 1) may absorb the light emitted by the light-emitting layer 104, it may be further removed, after removal The situation is as shown in Figure 1M.

Subsequently, as shown in FIG 1N first, a second through hole H is formed on the first contact layer ₁₀₃₁ through the first contact layer 103, a second _{perforation. 1} H concept of a first contact layer 103 to the direction 111 of the permanent substrate It is substantially circular (refer to Figure 2, detailed later) and has a diameter D ₂ . The diameter D ₂ is between about 20 μm and 150 μm, or between about 40 μm and 90 μm. Specifically, the second through hole H ₁ has a cross-sectional area along the line A-A' (ie, a direction perpendicular to the stacking direction of the light-emitting laminate 104). In this embodiment, the second through hole H ₁ is formed by yellow light and an etching method. Subsequently, as shown in FIG first 1O, a contact layer is formed on the first contact layer 103 and 112 penetrating the second through hole H ₁ extending on the contact layer 112. In the present embodiment, the upper contact layer 112 comprises an alloy such as an alloy of three metals of germanium (Ge), gold (Au), and nickel (Ni). Then, as shown in FIG. 10, a portion of the periphery of each layer from the upper contact layer 112 to the second contact layer 105 is removed by a yellow light and etching process and a portion of the insulating layer 106 is exposed. Next, as shown in Fig. 1P, a sidewall insulating layer 113 is formed on the sidewall of the structure formed after removing a portion of the peripheral portion. The sidewall insulating layer 113 comprises an insulating material such as tantalum nitride (Si ₃ N ₄ ) or tantalum oxide (SiO ₂ ). In the embodiment, the sidewall insulating layer 113 comprises tantalum nitride (Si ₃ N ₄ ) and tantalum oxide. a stack of (SiO ₂ ) formed by laminating a layer of tantalum nitride (Si ₃ N ₄ ) and tantalum oxide (SiO ₂ ) on the structure, and then removing a portion thereof by a yellow light and etching process And leaving and forming the sidewall insulating layer 113 on at least the aforementioned sidewalls. As shown in FIG. 1P, in the present embodiment, a sidewall insulating layer 113 is also formed on the exposed insulating layer 106 and on the portion of the upper contact layer 112.

Next, as shown in Fig. 1Q, an upper electrode 114 is formed on the structure as shown in Fig. 1P. The material of the upper electrode 114 comprises a metal material, in this embodiment, a laminate comprising titanium (Ti)/platinum (Pt) formed by an electron beam evaporation (E-beam evaporation) method; in another example, The electrode 114 does not contain platinum (Pt), and the upper electrode 114 is composed of titanium (Ti); in still another embodiment, the upper electrode 114 contains titanium (Ti) and gold (Au). And after formation, substantially corresponds to the titanium (Ti)/platinum (Pt) stack of the second via H ₁ removed portion such that the second via H ₁ extends and penetrates the upper electrode 114. In addition to being an electrode, the upper electrode 114 also serves as an opaque layer that covers one of the present light-emitting elements. Since the upper electrode 114 positioned above the light emitting stack 104, stack 104 for over the light emitting surface, corresponding to the second perforated area H ₁ region of the light emitting element, namely, the light emitting device of the present invention based emitted from light aperture, i.e., the second light perforated H _1, the upper electrode 114 is not covered and the exposed portion of the surface area is the area of the light emitting element of the light emitting stack 104, and the upper electrode 114 while covering the upper surface of the light emitting stack 104 other parts. In addition, the opaque layer formed by the upper electrode 114 further covers the sidewall of the luminescent layer 104, and the sidewall insulating layer 113 is disposed between the opaque layer formed by the upper electrode 114 and the sidewall of the luminescent layer 104. This prevents the light-emitting stack 104 from failing due to a short circuit. Further, in one embodiment, the first predetermined based light hole (i.e., the second through hole H ₁₎ the size, shape, and position of the perforation 106h and the first size, shape, and location of the required second perforated substantially H ₁ correspondence with the first through hole 106h is located directly below the second perforation ₁ H, 106h and the first perforations size and / or shape of the second perforated ₁ H size and / or shape may be designed to be the same. Specifically, before the first perforation 106h is manufactured as shown in FIG. 1D, the parameters of the second perforation H1 (such as the above-mentioned parameters such as size, shape, and position) are preset to determine the first perforation. The corresponding parameters of 106h were manufactured.

In addition, since the material of the upper electrode 114 is less likely to be formed on the sidewall insulating layer 113, the thickness of the upper electrode 114 may be too thin. Therefore, in the embodiment, as shown in FIG. 1R, a metal layer 114S may be formed. The shortage of the thickness of the upper electrode 114 on the sidewall insulating layer 113 is reinforced. The metal layer 114S may be formed on the upper electrode 114 by a plating method, for example, immersing the structure shown in FIG. 1A with a metal-containing material such as gold (Au), silver (Ag), titanium (Ti) or platinum ( Pt), in the solution of gold (Au) in this embodiment, and the metal material layer formed by the action of redox, that is, the metal layer 114S may comprise a gold (Au) layer. Further corresponding to the gold (Au) layer of the second perforation H ₁ removed portion, the second perforation H ₁ extends and penetrates the metal layer 114S. In one embodiment of the invention, the upper electrode 114 has a thickness of at least greater than 100 Å as an opaque layer that covers the light-emitting elements. In this embodiment, the thickness of the gold (Au) layer of the titanium (Ti), the platinum (Pt) and the metal layer 114S of the upper electrode 114 is respectively between about 200 Å and 400 Å, between 2 μm and 4 μm, and between 2000 Å and 4,000 Å. between.

Next, as shown in FIG. 1S, a protective layer 115 is formed on the structure as shown in FIG. 1R. The protective layer 115 along the sidewalls of the second perforations surrounding the fill H ₁ H after _a second perforation, the diameter of the inner diameter of the protective layer 115 composed of pores of D _3. The material of the protective layer 115 is an insulating material such as tantalum nitride (Si ₃ N ₄ ) or yttrium oxide (SiO ₂ ). After the formation, as shown in FIG. 1T, a portion of the protective layer 115 is removed to form a third via 115h, and a lower electrode 111E is formed on the permanent substrate 111. The third via 115h exposes a portion of the metal layer 114S (in the embodiment of the other metal-free layer 114S of the present invention, a portion of the upper electrode 114 is exposed) as a solder pad to allow external power to enter the wiring and The metal layer 114S (or the upper electrode 114) is in contact.

1T is a schematic view of a light-emitting element according to a first embodiment of the present invention, and FIG. 2 is a top view of FIG. 1T. Referring to the two figures, the light-emitting element includes: a permanent substrate 111, and the joint structure 110 is permanently Above the substrate 111, the reflective layer 109 is located above the bonding structure 110, and the insulating layer 106 is located above the reflective layer 109. The insulating layer 106 has a first via 106h, and the first transparent conductive layer 107 is filled in the first via 106h of the insulating layer 106. And electrically connected to the light emitting laminate 104 by the first via 106h being in direct contact with the second contact layer 105. And a first perforation 106h located in the first transparent conductive layer 105 in direct contact with the second contact layer 107 is a current-conducting region, a second current-conducting region which is located on the surface of the perforated H ₁ and the light emitting stack 104, a second portion Directly below, the current conducting region allows current to flow into the light emitting stack 104. Specifically, the contact resistance between the first transparent conductive layer 107 and the second contact layer 105 is smaller than the contact resistance between the insulating layer 106 and the second contact layer 105, for example, less than two orders of magnitude or less than five orders of magnitude. Preferably, the contact resistance between the first transparent conductive layer 107 and the second contact layer 105 is between 10 ^-3 and 10 ^-5 Ω cm ² . The insulating layer 106 of the non-current conducting region surrounds the second contact layer 105. The light emitting layer 104 is disposed above the insulating layer 106. The light emitting layer 104 includes an active region 104b and has an upper surface (refer to FIG. 2, a region formed by a rectangular dotted line), and the opaque layer formed by the upper electrode 114 is located. Above the light-emitting layer, wherein the opaque layer formed by the upper electrode 114 covers a first portion of the upper surface of the light-emitting layer 104, that is, a portion other than the second hole H1 (refer to FIG. 2, outside the circular dotted line constituting region) on one of the exposed surface of the second portion, a second portion that is located directly below the second perforated portion of H ₁ (refer to FIG. 2, the dotted circle formed region). That area, on the surface of the light emitting stack 104 is located directly below the second perforated H ₁ other than the second portion are on opaque layer is composed of the electrode 114 is covered. Light emitted from light emitting stack 104 may be _an escape from the second part of its upper surface and a second perforated H. The ratio of the cross-sectional area of the second perforation H _{1 to} the upper surface area of the light-emitting laminate 104 is about 1.5 to 5%. As shown in FIG. 2, the solder pad is usually formed on the first portion covered by the upper electrode 114, and specifically formed in the third through hole 115h to form an electrical connection with the light emitting laminate 104, and the solder pad is generally rectangular or square. The third through hole 115h is at least 80 μm on either side of the short side of the rectangle or the square. Specifically, the area of the first portion of the upper surface of the light emitting laminate 104 is larger than the area of the second portion. The first transparent conductive layer 107 is filled in the first through hole 106h of the insulating layer 106, and is electrically connected to the light emitting laminate 104 by direct contact with the second contact layer 105. Since the insulating layer 106 of a first substantially perforated 106h cooperate with _a corresponding second perforation H in the size, shape, and position, so that a first cross-sectional area ratio of the surface area of the perforations of the light emitting stack 104 and also approximately 106h 1.5~5%.

3 shows an embodiment of the present invention, when the thickness of the second contact layer 105 of the light-emitting element is 0.2 μm and 1 μm, respectively, under the condition of the diameter of each of the first through holes 106h (horizontal axis), respectively corresponding to the light-emitting elements The case of luminous power (Po, left vertical axis) and forward voltage (Vf, right vertical axis). As shown in FIG. 3, the luminous power and the forward voltage of the light-emitting element vary with the size of the first perforation 106h, that is, the predictability and controllability of the component design, and the first perforation can be adjusted according to different requirements. The size of 106h is achieved. It can be seen from further experimental results that the thickness of the second contact layer 105 is not more than 1.5 μm. When the thickness of the second contact layer 105 is too thick, for example, greater than 1.5 μm, the current blocking effect of the insulating layer 106 does not easily change with the diameter of the first through hole 106h, that is, the light-emitting element is illuminated in this case. The power and forward voltage will not be obvious with the change of the diameter dimension of the first through hole 106h, and it is not easy to control or predict the light emission power and the forward voltage of the light emitting element through the adjustment of the diameter size of the first through hole 106h.

In addition, the light-emitting element can be operated under conditions of a general current value (for example, 50 mA in this embodiment), and depending on the application of the element, part of the application requires the light-emitting element to have a relatively high current value (in this embodiment, for example, The operation is performed under the condition of 300 mA), and the pulse mode is emitted (that is, the light output of the light-emitting element changes with time to be intermittent and discontinuous, rather than continuous). The structure of the light-emitting element of this embodiment can satisfy both of the above situations. 4 shows an embodiment of the present invention in which the active region 104b is a multi-quantum well (MQW)-structured light-emitting element that emits light in the same pulse mode, and the multiple quantum well structures include 18, 38, and 48 well layers, respectively. Under the condition of (well), corresponding to the relatively high current (300 mA) luminous power (Po, right vertical axis) and luminous power ratio (left vertical axis, when the illuminating element is in the same pulse emission mode, the illuminating element is at a relatively high current The case of the ratio of the luminous power under operation to the luminous power under normal current operation). The figure shows that when the multiple quantum well structure contains 38 and 48 well layers respectively, the luminous power ratio can be as high as 2.8 or more. It can be seen from further experimental results that when the multi-quantum well (MQW) structure contains 30 to 50 well layers, the luminous power ratio can reach 2.6 or more.

Fig. 5 is a view showing the phosphide aluminum gallium indium series in the multiple quantum well structure in the light-emitting element of the above embodiment, in which the active region 104b is a multi-quantum well (MQW) light-emitting element emitting light in the same pulse mode (Al _y Ga( _1-y )) _1-x In _x P, where 0≦x<1; 0≦y≦1) The barrier layer of the material contains 30%, 50%, and 70% aluminum, respectively. (Al) (refers to the ratio of aluminum (Al) to the composition of aluminum (Al) and gallium (Ga), which is equivalent to the y) content of the above formula, corresponding to the relatively high current (300 mA) of luminous power (Po, right vertical axis And the ratio of the luminous power (Factor refers to the ratio of the luminous power of the relatively high current to the luminous power of the general current in the same pulse emission pattern, the left vertical axis), wherein the barrier layer has a plurality of layers. The figure shows that the barrier energy of the multi-quantum well structure can be as high as 3.1 or higher under the conditions of 50% and 70% aluminum (Al). Considering the electrical requirements of other illuminating elements, such as the appropriate range of forward voltage, further experiments show that the barrier layers in the multiple quantum well structure contain aluminum (Al) content of about 40% to 60%, respectively. The luminous power ratio and the forward voltage have good performance at the same time. In another embodiment, in the plurality of barrier layers, wherein the two barrier layers have different aluminum contents, and the aluminum content of the barrier layer closer to the first electrical semiconductor layer 104a is lower than the first electrical property. The aluminum content of the barrier layer of the semiconductor layer 104a. Preferably, in the plurality of barrier layers, at least half of the barrier layers adjacent to the first electrical semiconductor layer 104a (ie, the n-type semiconductor layer) have a lower aluminum content than the remaining near the second electrical semiconductor layer 104c ( That is, the barrier layer of the p-type semiconductor layer has an aluminum content. Specifically, the barrier layer adjacent to the first electrical semiconductor layer 104a includes (Al _a Ga _1-a ) _1-b In _b P, and the barrier layer adjacent to the second electrical semiconductor layer 104 _c includes (Al _c Ga _{1- c} ) _1-d In _d P, in the case of b≒d, c>a. In one embodiment, the multiple quantum well structure includes 38 barrier layers, and the first 20 barrier layers closer to the first electrical semiconductor layer 104a include (Al _0.5 Ga _0.5 ) _1-b In _b P The remaining 18 barrier layers away from the first electrical semiconductor layer 104a, that is, the 18 barrier layers closer to the second electrical semiconductor layer 104c include (Al _0.7 Ga _0.3 ) _1-d In _d P, In the example, b and d are approximately equal to 0.5, but are not limited thereto. In one embodiment, the multiple quantum well structure comprises 38 barrier layers, and the first 28 barrier layers closer to the first electrical semiconductor layer 104a comprise (Al _0.5 Ga _0.5 ) _1-b In _b P, closer The first ten barrier layers of the second electric semiconductor layer 104c include (Al _0.7 Ga _0.3 ) _1-d In _d P, and in this embodiment, b and d are approximately equal to 0.5, but are not limited thereto. In one embodiment, the multiple quantum well structure comprises 38 barrier layers, and the first 36 barrier layers closer to the first electrical semiconductor layer 104a comprise (Al _0.5 Ga _0.5 ) _1-b In _b P, closer The two barrier layers of the second electrical semiconductor layer 104c include (Al _0.7 Ga _0.3 ) _1-d In _d P, and in this embodiment, b and d are approximately equal to 0.5, but are not limited thereto. In one embodiment, the aluminum content in the plurality of barrier layers is gradually increased from the n-type semiconductor layer to the p-type semiconductor layer, that is, each is closer to the first electrical semiconductor layer 104a (ie, the n-type semiconductor layer The aluminum content of the barrier layer is lower than the aluminum content of the barrier layer adjacent to the second electrical semiconductor layer 104c (i.e., the p-type semiconductor layer). In one embodiment, the dopant of the second electrical semiconductor layer 104c comprises carbon (C), magnesium (Mg) or zinc (Zn). Preferably, the dopant comprises magnesium. The present disclosure can avoid or reduce the p-type by the barrier layer having different aluminum contents, and the aluminum content of the barrier layer closer to the n-type semiconductor layer is lower than the aluminum content of the barrier layer farther away from the n-type semiconductor. In the case where the p-type dopant in the semiconductor layer diffuses into the active region 104b, the reliability of the light-emitting element is improved and the forward voltage of the light-emitting element is not greatly increased.

Figure 6 is a cross-sectional view showing a light-emitting element of a second embodiment of the present invention. The light-emitting element of the second embodiment of the present disclosure includes substantially the same structure as the first embodiment, and the differences are as follows. As shown in FIG. 6, the light emitting element includes a first semiconductor layer 116 and a second semiconductor layer 117. The first semiconductor layer 116 is located between the first contact layer 103 and the light emitting layer 104, and the second semiconductor layer 117 is located at the second layer. Between the contact layer 105 and the light emitting stack 104. The first semiconductor layer 116 and the second semiconductor layer 117 serve to enhance light extraction and/or enhance current spreading to spread the current across the entire light emitting stack 104. The thickness of the first semiconductor layer 116 is greater than the thickness of the first electrical semiconductor layer 104a. Preferably, the thickness of the first semiconductor layer 116 is greater than 2000 nm, and more preferably between 2500 nm and 7000 nm. The thickness of the second semiconductor layer 117 is greater than the thickness of the second electrical semiconductor layer 104c. Preferably, the thickness of the second semiconductor layer 117 is greater than a thickness of 1000 nm, and more preferably between 1500 nm and 2000 nm. The first semiconductor layer 116 has an energy level which is smaller than the energy level of the first electrical semiconductor layer 104a. The second semiconductor layer 117 has an energy level which is smaller than the energy level of the second electrical semiconductor layer 104c. The energy levels of the first semiconductor layer 116 and the second semiconductor layer 117 are greater than the energy levels of the well layers in the active region 104b. Light emitted by the active region 104b can substantially penetrate the first semiconductor layer 116. The first semiconductor layer 116 and the second semiconductor layer 117 each have a doping concentration higher than 1 ́10 ¹⁷ /cm ³ , and the doping concentration of the first semiconductor layer 116 is smaller than the doping concentration of the first contact layer 103, The doping concentration of the second semiconductor layer 117 is smaller than the doping concentration of the second contact layer 105. Preferably, the doping concentration of the first contact layer 103 is at least twice or more (inclusive) of the doping concentration of the first semiconductor layer 116. The doping concentration of the second contact layer 105 is at least twice or more (inclusive) of the doping concentration of the second semiconductor layer 117. The first semiconductor layer 116, the second semiconductor layer 117, the first contact layer 103, and the second contact layer 105 comprise a tri-five semiconductor material such as AlGaAs or AlGaInP. As shown in FIG. 6, the second contact layer 105 has a width W _1, with the light emitting element of the area than the width of not less than 0.5 and not greater than 1.1, i.e., in the same cross section, the second contact layer 105 The _ratio of the width W ₁ to the width of the region not covered by the upper electrode 114 (i.e., the second portion of the upper surface of the light-emitting laminate 104) is not less than 0.5 and not more than 1.1. In one embodiment, the ratio of the width W _{1 of the} second contact layer 105 to the diameter D ₂ of the second via H ₁ (ie, W ₁ /D ₂ ) is not less than 0.5 and not more than 1.1. Preferably, the ratio of the width W _{1 of the} second contact layer 105 to the width of the light-emitting region of the light-emitting element is not less than 0.55 and not more than 0.8. In one embodiment, the ratio of the width W _{1 of the} second contact layer 105 to the diameter D ₂ of the second via H ₁ (ie, W ₁ /D ₂ ) is not less than 0.55 and not more than 0.8. In addition, in the second embodiment, as shown in FIG. 6, the second contact layer 105 is located directly under the light-emitting region of the light-emitting element, that is, in a region not covered by the upper electrode 114 (ie, above the light-emitting stack 104). Just below the second part of the surface). The contact resistance between the second contact layer 105 and the first transparent conductive layer 107 is much smaller than the contact resistance between the first transparent conductive layer 107 and the second semiconductor layer 117, for example, less than two orders of magnitude or less than five orders of magnitude. Therefore, the second contact layer 105 having the width W ₁ is a current conducting region that allows current to flow into the light emitting stack 104 while the other of the first transparent conductive layer 107 is not in contact with the second contact layer 105 and surrounds the second contact layer. The area of 105 does not allow current to flow or makes it difficult for current to flow into the light emitting stack 104. In the embodiment, the second contact layer 105 is located directly below the second through hole H ₁ . Preferably, the second contact layer 105 does not overlap the upper contact layer 112 and the upper electrode 114 in the stacking direction of the light emitting laminate 104. In the present embodiment, as shown in FIG. 6, the thickness of the portion of the second semiconductor layer 117 is greater than the thickness of the second semiconductor layer 117 of the other portion, and the portion of the second semiconductor layer 117 having a thicker thickness corresponds to the light exit region. That is, the area not covered by the upper electrode 114 (i.e., the second portion of the upper surface of the light-emitting layer 104). In the present embodiment, the thicker portion of the second semiconductor layer 117 corresponds to the second through hole H ₁ . The second contact layer 105 is located on a portion of the second semiconductor layer 117 having a relatively thick thickness. Specifically, the thinner portion of the second semiconductor layer 117 includes a surface 1171 away from the light emitting stack 104, and the second contact layer 105 includes a surface 1051 away from the light emitting layer 104, as compared to the second semiconductor layer 117. The surface 1171 of the thinner portion is thinner than the surface 1051 of the second contact layer 105. Specifically, the height h between the surface 1051 of the second contact layer 105 away from the surface 1051 of the light emitting layer 104 to the surface 1171 of the second semiconductor layer 117 remote from the light emitting layer 104 is not less than 50 nm and not more than 200 nm. In one embodiment, the thickness of the second contact layer 105 is not less than 20 nm and not more than 0.5 μm. Preferably, the thickness of the second contact layer 105 is not less than 20 nm and not more than 0.1 μm. Since the light-emitting element of the second embodiment includes the second contact layer 105 having a width W ₁ and the second contact layer 105 is located directly under the light-emitting region, when current flows through the light-emitting stack 104, current is more likely to concentrate. Corresponding to the area of the second contact layer 105, the current density is greatly increased, thereby increasing the brightness of the light-emitting element.

The manufacturing method of the light-emitting element of the second embodiment of the present disclosure is substantially the same as the manufacturing method of the first embodiment, and the difference includes, before forming the light-emitting layer 104, further comprising forming the first semiconductor layer 116 in the first contact. On the layer 103, and after forming the light-emitting stack 104 and before forming the second contact layer 105, the second semiconductor layer 117 as described above is further formed. After the second contact layer 105 is formed, the second contact layer 105 is patterned by a yellow light and an etching process, so that the second contact layer 105 has a width W ₁ , and then the first transparent layer is formed as in the manufacturing method of the first embodiment. Subsequent steps of the conductive layer 107, the second transparent conductive layer 108, and the like. Compared with the manufacturing method of the first embodiment, the manufacturing method of the present embodiment greatly reduces the cost of the process because the insulating layer 106 is not required to be formed and the yellow light and etching process is not required to form the first via 106h in the insulating layer 106. Increase process simplicity.

In one embodiment immediately below, the light emitting element does not comprise a second perforated H1, having a width W region of the light-emitting element ₁ of the second contact layer 105, i.e. not located on the coverage area of electrode 114 (i.e., the light emitting Directly below the second portion of the upper surface of the laminate 104).

Figure 7 is a cross-sectional view showing a light-emitting element of a third embodiment of the present invention. The light-emitting element of the present embodiment further includes a heat-conducting layer 118 disposed on the second portion of the upper surface of the light-emitting layer 104, as compared with the foregoing embodiments of the present invention. In detail, the thermally conductive layer 118 is disposed on the upper surface of the light emitting stack 104 by a second perforated exposed by H _1, and the thermally conductive layer 118 having a higher thermal conductivity than the light emitting stack 104 (thermal conductivity), the light emitting element in operation, heat generated by the light emitting stack 104 by a thermally conductive layer 118 may be conductive or radiation to escape to the outside, so can reduce the heat accumulated in the second light emitting stack 104 perforation H ₁ below, the emission mitigation The material inside the component decays due to heat and increases the service life and reliability of the light-emitting component. The heat conductive layer 118 may include a material having a thermal conductivity of not less than 100 W/(m Ï K), and may be, for example, diamond, graphene, or aluminum nitride (AlN _X ) having a thermal conductivity of about 140 W/(m Ï K) to 180 W/(m Ï _K ). The invention is not limited thereto. More detail, in the present embodiment, the thermally conductive layer 118 along the second perforation line sidewall ₁ H H ₁ filled in the second perforation, and covers the first layer of the second conductivity type semiconductor exposed by _a perforated H on 104a, and extending to a direction away from the second perforated H ₁ around the light emitting element, and in contact with the metal layer 114S or the upper electrode 114, the light emitting stack 104 to the heat generated is transmitted to the metal layer through the thermally conductive layer 118 or 114S In the upper electrode 114, since the metal layer 114S and the upper electrode 114 are generally selected as metals, the thermal conductivity is high, and heat inside the light-emitting element can be discharged by the heat conductive layer 118 and the metal layer 114s or the upper electrode 114. In some embodiments, the thermally conductive layer 118 may also not be in contact with the metal layer 114S or the upper electrode 114. The heat generated in the light emitting layer 104 may be radiated to the outside via the heat conducting layer 118, or the heat conducting layer 118 may be thermally conductive to the outside. The structure is connected such that heat generated in the light-emitting stack 104 can be conducted to the outside in a conductive manner via the thermally conductive layer 118. Compared with the first embodiment, the light-emitting element in this embodiment includes a protective layer 115 covering the metal layer 114S, and the protective layer 115 is also covered on the heat conductive layer 118. In this embodiment, the protective layer 115 can be completed. Covering the heat conducting layer 118, in detail, the heat conducting layer 118 of the present embodiment has a top surface 118t and a side surface 118s. The top surface 118t is parallel to the upper surface of the light emitting layer 104, and the side surface 118s is connected to the top surface 118t. Parallel to the upper surface of the light-emitting layer 104, and the protective layer 115 covers the top surface 118t and the side surface 118s of the heat-conducting layer 118 at the same time, thereby preventing the material of the heat-conducting layer 118 from being in contact with the external environment when the light-emitting element operates, thereby causing a qualitative change, but The invention is not limited thereto; in another embodiment, the heat conductive layer 118 may be substituted for the protective layer 115 such that the heat conductive layer 118 completely covers the surface of the upper electrode 114 or the metal layer 114S except the position of the third through hole 115h. To increase the heat transfer area of the light-emitting element. In one embodiment, the thermally conductive layer 118 has a high degree of transparency to the light emitted by the light emitting stack 104, for example, the thermally conductive layer 118 comprises a material having a transmittance of greater than 85% for the emitted light of the active region 104b; In another embodiment, the heat conductive layer 118 further has a refractive index greater than 1.5, or 2.1 to 2.5, and the difference in refractive index between the heat conductive layer 118 and the first electrical semiconductor layer 104a does not exceed 1.5, which can be reduced in the first The interface between the electrical semiconductor layer 104a and the heat conductive layer 118 generates a probability of total reflection, and increases the light extraction efficiency of the light emitting element. The thickness of the heat conductive layer 118 may be 300 to 2000 Å. In the embodiment, the thickness of the heat conductive layer 118 is 1000 Å, but not limited thereto. The heat conductive layer 118 may be formed after the upper electrode 114 is formed as shown in FIG. 1Q or after the metal layer 114S is formed as shown in FIG. 1R to cover the upper electrode 114 or the metal layer 114S.

8A to 8B are schematic cross-sectional views and a top view of a light-emitting element according to a fourth embodiment of the present invention. The heat conducting layer 118 of the light emitting device of the present embodiment is disposed in the light emitting layer 104, and the heat conducting layer 118 has a fourth through hole H ₄ substantially opposite to the second through hole H ₁ . In the direction of the light emitting laminate 104, the fourth through hole H _{4 is} first substantially circular (see FIG. 8B), and the upper viewing area of the fourth through hole H ₄ is larger than the second portion of the light emitting laminate 104. The upper viewing area, in other words, the upper viewing area of the fourth perforation H ₄ is larger than the upper viewing area of the second perforation H ₁ . In detail, the heat conducting layer 118 is located between the light emitting layer 104, the first contact layer 103 and the insulating layer 106. More specifically, the heat conducting layer 118 of the present embodiment penetrates the first electrical semiconductor layer of the light emitting layer 104. 104a, active region 104b, second electrical semiconductor layer 104c and second contact layer 105, such that the heat conducting layer 118 is surrounded by the light emitting layer 104, the first contact layer 103 and the insulating layer 106; in another embodiment, the heat conducting layer 118 penetrates the first electrical semiconductor layer 104a, the active region 104b, and the second electrical semiconductor layer 104c without penetrating the second contact layer 105, so that the heat conductive layer 118 is illuminated by the light emitting layer 104, the first contact layer 103, and the second contact layer 105 is surrounded, but the structure of the heat conductive layer 118 is not limited to the above embodiment. The fourth perforation H _{4 of the} thermally conductive layer 118 has a diameter D ₄ greater than the diameter D _{2 of the} second perforation H1 , a diameter D ₄ of between about 30 μm and 200 μm, or a diameter D ₄ of between about 50 μm and 120 μm. As shown in Figure 8B, 118 having an inner contour and an outer contour 118a 118b surrounding the inner contour of the embodiment of the present embodiment thermally conductive layer 118a, 118a of the inner ring to surround the contour of the second perforation H ₁ and the light emitting stack 104 is formed below Fourth perforation H ₄ . Depends on the minimum distance d from the concept of the present embodiment, the shape of the inner contour 118a is circular, and its center is located substantially on the center of the second through hole H _1, the inner contour of the outer profile 118a and 118b is between 10μm to 50μm between. Further, the thermally conductive layer 118 of the present embodiment passes through the second contact layer 105, and in a stacking direction parallel to the light emitting laminate 104, the thermally conductive layer 118 has a thickness W of between 2 μm and 15 μm. Another embodiment, the inner contour of the outer profile 118a and 118b of the center of the thermally conductive layer 118 are located in substantially the center of the second through hole H ₁ of the embodiment.

Figure 9 is a cross-sectional view showing a light-emitting element of a fifth embodiment of the present invention. Compared with the foregoing embodiment, the heat conducting layer 118 of the light emitting element of the present embodiment is located in the light emitting stack 104, and the heat conducting layer 118 has a larger range than the fourth embodiment. In detail, as shown in FIG. 9, the total area of the heat conducting layer 118 of the light emitting element may be larger than the area of the light emitting layer 104, so as to more efficiently transfer the heat generated by the operation of the light emitting element to external. The light-emitting elements of the fourth and fifth embodiments of the present invention may be formed through the steps of FIGS. 1A to 1Q, and after the second contact layer 105 is formed on the light-emitting layer 104, it is intended to be formed at a position where the heat-conductive layer 118 is formed. The portion of the light-emitting layer 104 and the second contact layer 105 thereon are removed by means of inductively coupled plasma (ICP) for reactive ion etching, but not limited thereto. In the fifth embodiment, the area of the light-emitting layer 104 removed by this step is larger than the area of the light-emitting layer 104 removed in the fourth embodiment. In detail, in an embodiment, before the formation of the heat conductive layer 118, the second contact layer 105, the active region 104b, the second electrical semiconductor layer 104c, and the first electrical semiconductor at a position where the heat conductive layer 118 is to be formed may be formed. The light-emitting layer 104 of the layer 104a and the like is removed. In this case, an etch barrier layer (not shown) is further disposed between the first contact layer 103 and the first electrical semiconductor layer 104a to avoid removing portions. The first contact layer 103 is broken when the light-emitting layer 104 is illuminated. Next, the thermally conductive layer 118 is deposited at the location where the light emitting stack 104 has been removed, and in a stacking direction parallel to the light emitting stack 104, the thermally conductive layer 118 has a thickness W, and the thickness W is preferably such that the top of the thermally conductive layer 118 Face 118t is flush with the second portion of the surface of light-emitting laminate 104. The heat conductive layer 118 may be deposited by sputtering or evaporation, for example, by Atomic Layer Chemical Vapor Deposition (ALD) or Electron Beam Physical Vapor Deposition (EBPVD). The thermally conductive layer 118 of the present embodiment is formed by a two-stage growth method in which a first portion of the denser thermally conductive layer 118 is first deposited by atomic layer chemical vapor deposition, and then an electron beam is applied to the first portion of the thermally conductive layer 118. The second portion of the thermally conductive layer 118 continues to be deposited, but the manner in which the thermally conductive layer 118 is formed is not limited thereto.

It is to be noted that the various embodiments of the present invention are intended to be illustrative only and not to limit the scope of the invention. Any obvious modifications or variations of the present invention are possible without departing from the spirit and scope of the invention. The same or similar components in different embodiments, or components having the same reference numbers in different embodiments, have the same physical or chemical properties. In addition, the above-described embodiments of the present invention may be combined or substituted with each other as appropriate, and are not limited to the specific embodiments described. The connection between the specific components and the other components described in detail in the embodiments can also be applied to other embodiments, and all fall within the scope of the scope of the invention as described hereinafter.

101‧‧‧ Growth substrate
102‧‧‧buffer layer
103‧‧‧First contact layer
104‧‧‧Lighting laminate
104a‧‧‧First electrical semiconductor layer
104b‧‧‧Active area
104c‧‧‧Second electrical semiconductor layer
105‧‧‧Second contact layer
106‧‧‧Insulation
106h‧‧‧first perforation
107‧‧‧First transparent conductive layer
108‧‧‧Second transparent conductive layer
109‧‧‧reflective layer
110‧‧‧ joint structure
110a‧‧‧First joint layer
110b‧‧‧Second joint layer
110c‧‧‧ third joint layer
111‧‧‧Permanent substrate
112‧‧‧Upper contact layer
H ₁ ‧‧‧second perforation
H ₄ ‧‧‧fourth perforation
113‧‧‧ sidewall insulation
114‧‧‧Upper electrode
114S‧‧‧ metal layer
115‧‧‧Protective layer
115h‧‧‧ third perforation
111E‧‧‧ lower electrode
D ₁ , D ₂ , D ₃ , D ₄ ‧‧‧ hole diameter
116‧‧‧First semiconductor layer
117‧‧‧Second semiconductor layer
d‧‧‧Minimum distance
W‧‧‧thickness
W ₁ ‧‧‧Width
H‧‧‧height
1051‧‧‧ surface
1071‧‧‧ surface
118‧‧‧thermal layer
118t‧‧‧ top surface
118s‧‧‧ side
118a‧‧‧ inside contour
118b‧‧‧Outer contour

1A to 1T are schematic views showing a light-emitting element and a method of manufacturing the same according to a first embodiment of the present invention.

Fig. 2 is a top plan view showing a light-emitting element according to a first embodiment of the present invention.

Figure 3 is a view showing the first embodiment of the present invention, when the thickness of the second contact layer is 0.2 μm and 1 μm, respectively, under the conditions of the diameter dimensions (horizontal axes) of the various first perforations, respectively corresponding to the illumination of the light-emitting elements Distribution of power (Po, left vertical axis) and forward voltage (Vf, right vertical axis).

FIG. 4 is a view showing a first embodiment of the present invention, in which the light-emitting elements emit light in the same pulse mode, and the multiple quantum well structures respectively correspond to relatively high conditions including 18, 38, and 48 wells. The distribution of the luminous power (Po, right vertical axis) and the luminous power ratio (left vertical axis) of the current (300 mA).

FIG. 5 is a view showing a first embodiment of the present invention, in which the light-emitting element emits light in the same pulse mode, and the barrier layers included in the multiple quantum well structure respectively have corresponding aluminum (Al) content, corresponding to each other. Distribution of high current (300 mA) luminous power (Po, right vertical axis) and luminous power ratio (left vertical axis).

Fig. 6 is a cross-sectional view showing a light-emitting element of a second embodiment of the present invention.

Fig. 7 is a cross-sectional view showing a light-emitting element of a third embodiment of the present invention.

Fig. 8A is a schematic cross-sectional view showing a light-emitting element according to a fourth embodiment of the present invention.

Fig. 8B is a top plan view showing a light-emitting element of a fourth embodiment of the present invention.

Fig. 9 is a cross-sectional view showing a light-emitting element of a fifth embodiment of the present invention.

101‧‧‧ Growth substrate

102‧‧‧buffer layer

103‧‧‧First contact layer

104‧‧‧Lighting laminate

104a‧‧‧First electrical semiconductor layer

104b‧‧‧Active area

104c‧‧‧Second electrical semiconductor layer

105‧‧‧Second contact layer

106‧‧‧Insulation

106h‧‧‧first perforation

107‧‧‧First transparent conductive layer

108‧‧‧Second transparent conductive layer

109‧‧‧reflective layer

110‧‧‧ joint structure

110a‧‧‧First joint layer

110b‧‧‧Second joint layer

110c‧‧‧ third joint layer

111‧‧‧Permanent substrate

112‧‧‧Upper contact layer

H ₁ ‧‧‧second perforation

113‧‧‧ sidewall insulation

114‧‧‧Upper electrode

114S‧‧‧ metal layer

115‧‧‧Protective layer

115h‧‧‧ third perforation

111E‧‧‧ lower electrode

D ₂ , D ₃ ‧‧‧ hole diameter

Claims (27)

A light emitting device comprising: a substrate; an insulating layer above the substrate, wherein the insulating layer comprises a first through hole; a light emitting layer is disposed above the insulating layer, the light emitting layer comprising an active region and an upper surface And an opaque layer covering a first portion of the upper surface of the light emitting laminate to expose a second portion of the upper surface, and the second portion is positioned directly above the first through hole. The illuminating device of claim 1, further comprising a sidewall insulating layer, wherein the opaque layer further covers at least a portion of the sidewall of the luminescent laminate, and the sidewall insulating layer is located in the opaque layer Between the sidewalls of the luminescent stack. The illuminating element of claim 1, wherein the active region comprises a multiple quantum well (MQW) structure, and the multiple quantum well (MQW) structure comprises 30 to 50 well layers. The illuminating element of claim 1, wherein an area of the first portion of the upper surface is larger than an area of the second portion. The light-emitting element of claim 1, wherein a ratio of a cross-sectional area of the first perforation to an area of the upper surface is about 1.5% to 5%. The light-emitting element of claim 1, further comprising a reflective layer and a first transparent conductive layer, the reflective layer being located between the insulating layer and the substrate, wherein the first transparent conductive layer is in the insulating layer The reflective layer is electrically connected to the light-emitting layer by the first through-hole. The light-emitting element of claim 1, further comprising a first contact layer on the light-emitting layer and a second hole penetrating the first contact layer. The illuminating element of claim 7, wherein the second perforation is located directly above the first perforation. The illuminating element of claim 1, further comprising a second through hole penetrating the opaque layer. The light-emitting element of claim 1, wherein the active region comprises a multiple quantum well (MQW) structure, and the multiple quantum well (MQW) structure comprises a plurality of barrier layers, each of the barrier layers A material comprising an indium gallium phosphide series ((Al _y Ga( _1-y )) _1-x In _x P, where 0 ≦ x <1; 0.4 ≦ y ≦ 0.7). The illuminating element of claim 1, further comprising a heat conducting layer disposed on the second portion. The light-emitting element according to claim 11, wherein the heat-conducting layer comprises a material having a thermal conductivity of not less than 100 W/(mÏK). The light-emitting element according to claim 1, further comprising a heat-conducting layer disposed in the light-emitting layer. The light-emitting element according to claim 13, wherein the heat-conducting layer comprises a material having a thermal conductivity of not less than 100 W/(mÏK). The light-emitting element of claim 13, wherein the heat-conducting layer has a pair of perforations located in the first perforation. The illuminating element of claim 15, wherein a top view area of the perforation of the thermally conductive layer is greater than an upper view area of the second portion. The light-emitting element according to claim 13, wherein the area of the heat-conducting layer is larger than the area of the light-emitting layer by a cross-sectional view. A method of fabricating a light-emitting device, comprising: forming a light-emitting layer, the light-emitting layer comprising an active region; forming an insulating layer over the light-emitting layer, wherein the insulating layer comprises a first through hole; providing a substrate; bonding The substrate and the light emitting laminate; and forming an opaque layer on a side opposite to the bonding direction of the light emitting layer and the substrate, and covering a first portion of one surface of the light emitting layer and exposing one of the surfaces And a portion of the second portion is opposite to the first perforated position of the insulating layer. The method for manufacturing a light-emitting device according to claim 11, further comprising forming a sidewall insulating layer on a sidewall of the light-emitting laminate, wherein the opaque layer further covers at least a portion of a sidewall of the light-emitting laminate, and The sidewall insulating layer is between the opaque layer and the luminescent stack. The method of manufacturing a light-emitting element according to claim 11, wherein an area of the first portion of the surface of the light-emitting layer is larger than an area of the second portion. The method of manufacturing a light-emitting device according to claim 11, wherein a ratio of a cross-sectional area of the perforation to an area of the upper surface is about 1.5% to 5%. The method for manufacturing a light-emitting device according to claim 11, further comprising forming a first transparent conductive layer over the insulating layer before bonding the substrate and the light-emitting layer, and the first transparent conductive layer The first through hole is electrically connected to the light emitting layer. The method for manufacturing a light-emitting device according to claim 11, further comprising forming a second through hole penetrating the opaque layer. The method of manufacturing a light-emitting element according to claim 16, wherein the second through hole is located directly above the first through hole. The method of manufacturing a light-emitting device according to claim 11, wherein the active region is a multiple quantum well (MQW) structure, and the multiple quantum well (MQW) structure comprises 30 to 50 well layers. The method of manufacturing a light-emitting device according to claim 11, wherein the active region is a multiple quantum well (MQW) structure, and the multiple quantum well (MQW) structure comprises a plurality of barrier layers, each of which The barrier layer comprises a material of aluminum gallium indium phosphide series ((Al _y Ga( _1-y )) _1-x In _x P, where 0 ≦ x <1; 0.4 ≦ y ≦ 0.7). The method for manufacturing a light-emitting device according to claim 11, further comprising forming a first contact layer before forming the light-emitting layer, and further comprising forming a second after bonding the substrate and the light-emitting layer. A perforation penetrates the first contact layer.