TW201735132A - Fin field effect transistor (FinFET) device and method for forming dielectric layer therein - Google Patents

Abstract

A FinFET device has a dielectric layer with a stacked nitride. The FinFET includes an oxide layer disposed on a substrate. A nitride layer is disposed on the oxide layer. An oxidation layer is disposed on the nitride layer, wherein the oxidation layer at least depletes nitrogen in the nitride layer. A high-K dielectric layer is disposed over the oxidation layer.

Description

Fin field effect transistor element and method of forming a dielectric layer therein

This invention relates to a semiconductor technology, and more particularly to a fin field effect transistor element and a method of forming a dielectric layer therein.

With the demand for shrinking the size of electronic products and increasing functions and operating speeds, the size of semiconductor components such as field effect transistors also needs to shrink. When the size of the field effect transistor is greatly reduced, the size of the gate structure is also reduced. The conventional polysilicon gate structure is no longer applicable, and the gate structure also needs different designs.

Among these developed technologies, Fin Field Effect Transistor (FinFET) elements have also been proposed. The structure of such a FinFET element, the 2D structure of a conventional MOSFET, is changed to the design of a 3D structure in which the source and the drain are formed not in the plane of the germanium substrate but on the surface of the convex fin structure. The gate structure is formed between the source and the drain and spans the convex fin structure. The gate insulating layer is also formed on the surface of the fin structure and covered by the gate structure. As such, the size of the FinFET component can be effectively reduced.

For the FinFET element, since the gate insulating layer is formed on the surface of the fin structure and the fin structure is a convex sheet from the 3D structure, the gate insulating layer is in the top region and bottom of the fin structure in the fin structure. The geometrical structure of the end regions is very different, so it will affect the formation conditions of the gate insulating layer and thus affect its reliability.

For FinFET components, how to manufacture a gate insulating layer with high reliability is one of the factors that need to be considered in design.

The present invention provides a fin field effect transistor element and a method of forming a dielectric layer therein, which can at least improve the reliability of the gate insulating layer.

An embodiment of the invention provides a fin field effect transistor device having a dielectric layer with stacked nitrides. The fin field effect transistor element includes an oxide layer disposed on the substrate. A nitride layer is disposed on the oxide layer. An oxidation generating layer is disposed on the nitride layer, wherein the oxidation generating layer consumes a nitrogen component in the nitride layer. A high-k dielectric layer is located above the oxidation generating layer.

In an embodiment of the fin field effect transistor device, the substrate has a raised structure and the oxide layer is at least on the exposed surface of the protruding structure.

In an embodiment of the aforementioned fin field effect transistor element, the protruding structure is a fin structure.

In an embodiment of the fin field effect transistor device, the oxide layer is a natural oxide layer or a hafnium oxide layer.

In an embodiment of the aforementioned fin field effect transistor device, the nitride layer comprises a tantalum nitride layer, and the oxidation generating layer comprises an oxynitride layer.

In an embodiment of the aforementioned fin field effect transistor device, the oxide layer has a thickness in the range of 5 angstroms to 15 angstroms.

In an embodiment of the aforementioned fin field effect transistor device, the thickness of the nitride layer is in the range of 10 angstroms to 20 angstroms.

In an embodiment of the fin field effect transistor device, the total thickness of the oxide layer, the nitride layer, and the oxidation generating layer is less than or equal to 40 angstroms.

An embodiment of the invention provides a method of also providing a dielectric layer formed in a fin field effect transistor device. The method includes: forming an oxide layer on a substrate; forming a nitride layer on the oxide layer; performing an oxidation process on the nitride layer to form an oxide generating layer; and depositing a high-k dielectric layer on the oxide layer Above the generation layer.

In an embodiment of the foregoing method, the oxidizing process includes introducing oxygen into the nitride layer to form an oxynitride layer.

In an embodiment of the foregoing method, the method further comprises forming a convex structure on the top of the substrate, and the oxide layer is at least on the exposed surface of the protruding structure.

In an embodiment of the aforementioned method, the protruding structure is a fin structure.

In an embodiment of the foregoing method, the oxide layer is formed by natural oxidation or by a deposition process.

In an embodiment of the foregoing method, the nitride layer comprises a tantalum nitride layer, and the oxidation generating layer comprises an oxynitride layer.

In an embodiment of the foregoing method, the oxide layer has a thickness in the range of 5 angstroms to 15 angstroms.

In an embodiment of the foregoing method, the thickness of the nitride layer is in the range of 10 angstroms to 20 angstroms.

In an embodiment of the foregoing method, wherein the total thickness of the oxide layer, the nitride layer, and the oxidation generating layer is less than or equal to 40 angstroms.

Based on the above, the fin field effect transistor element and the method of forming the dielectric layer therefor, for the gate structure of the gate insulating layer, the concentration distribution of the nitrogen component varies with depth, in the fin structure Different regions can achieve a more uniform distribution of nitrogen concentration, thus at least improving the reliability of the gate insulation.

The above described features and advantages of the invention will be apparent from the following description.

The present invention is directed to the formation of a gate insulating layer in a fin field effect transistor device, and proposes related manufacturing techniques to improve reliability.

The following examples are provided to illustrate the invention, but the invention is not limited to the examples.

The present invention is directed to the study of a gate insulating layer of a fin field effect transistor device having a 3D structure, and at least found that for a dielectric layer of a substrate formed on a fin structure for forming a gate insulating layer, if the nitrogen component is The concentration in the depth direction is distributed in different regions of the fin structure, which tends to cause inconsistency and thus affect the reliability of the gate insulating layer.

First, the problems that may occur in the gate insulating layer of the FinFET device are described. 1 is a schematic structural view of a fin field effect transistor device according to an embodiment of the invention. Referring to FIG. 1, the fin field effect transistor component package is based on the substrate 100. One example of the substrate is a tantalum substrate. On the substrate 100, a convex fin structure 100a is formed first by a general semiconductor process. Since the fin structure 100a is thin, it is a structure of a sheet from the viewpoint of the structure of 3D. Moreover, the fin structure 100a is the top structure of the substrate 100, and therefore is also a semiconductor material of germanium. The fin field effect transistor is to be formed on the fin structure 100a, so it is also necessary to form the gate insulating layer 106 on the surface of the fin structure 100a.

Here, the actual structure of the gate insulating layer 106 is formed by stacking a plurality of dielectric layers, which will be described later. The gate insulating layer 106 is only a portion of the surface of the fin structure 100a. The gate insulating layer 106 may have other portions extending over the horizontal surface of the substrate 100 in an embodiment. An inter-dielectric 102 covers a portion of the inner dielectric layer 102.

Structurally, a linear gate structure 108 is disposed over the inner dielectric layer 102 and overlies the fin structure 100a to cover the gate insulating layer 106. On either side of the fin structure 100a that is not covered by the gate structure 108, it utilizes an implantation process to form source/drain electrodes 104a, 104b. Thus, a single fin field effect transistor can be fabricated. In fact, multiple fin field effect transistors can be fabricated tightly together, so multiple fin structures 100a will also form a fin-like architecture.

In fact, multiple fin field effect transistors can be fabricated tightly together, so multiple fin structures 100a will also form a fin-like architecture. 2 is a cross-sectional view of a fin field effect transistor device along a gate line, in accordance with an embodiment of the invention. Referring to FIG. 2, a plurality of fin structures 100a are formed on the top of the substrate 100. The gate insulating layer 106 of FIG. 1 is actually a stack of a plurality of dielectric layers, which typically includes a dielectric layer 120 of the substrate, and a high-k dielectric layer 122. The function of the high-k dielectric layer 122 is to provide a sufficient capacitance value in response to the reduction in component size. For example, the linear gate structure 124 covers the high-k dielectric layer 122 across the fin structure 100a.

A material having a high-k dielectric layer, as is generally known to be higher than the dielectric constant of yttria, is, for example, HfO ₂ , HfSiO ₄ , HfSiON, Al ₂ O ₃ , La ₂ O ₃ , Ta ₂ O ₅ , Y ₂ O ₃ , ZrO ₂ , SrTiO ₃ , ZrSiO ₄ , HfZrO ₄ , SrBi ₂ Ta ₂ O ₉ , PbZrxTi1-xO ₃ , or BaxSr1-xTiO ₃ , but is not limited to the above.

The dielectric layer 120 of the substrate will typically include, for example, nitrogen-containing tantalum nitride. Since the fin structure 100a at the top of the substrate 100 is a structure such as a sheet, for example, the geometry of the region 206a at the bottom of the fin structure 100a, the region 206b of the sidewall, and the region 206c at the top are different, and thus the conditions for deposition may be different. Therefore, the nitrogen concentration in the depth direction in the above different regions may also be inconsistent. This will affect the reliability of the entire gate insulation.

At least in order to improve the reliability of the gate insulating layer, the present invention proposes a method of forming the dielectric layer 120 on the underlying layer, which can have a relatively uniform nitrogen concentration distribution in different regions on the fin structure 100a, thereby improving reliability. .

3A-3E are schematic flow charts showing a cross-sectional structure of a dielectric layer formed in a fin field effect transistor device, in accordance with an embodiment of the invention. Referring to FIG. 3A, the fin structure 100a represents the substrate 100, and the exposed surface of the fin structure 100a has an oxide layer 150. The oxide layer 150 is formed, for example, by natural oxidation in an environment, and may be, for example, a ruthenium oxide layer formed by a process addition, but is not limited to the above. The oxide layer 150 is a substrate layer that functions to prevent nitrogen atoms in subsequent processes from entering the substrate 100, which is the fin structure 100a. The thickness of the oxide layer 150 is, for example, in the range of 5 angstroms to 15 angstroms.

Referring to FIG. 3B, a nitride layer 152 is formed, such as a tantalum nitride layer, which is a barrier effect. The nitride layer 152 is a nitrogen-containing material, and a change in the nitrogen concentration also causes a change in the barrier effect. However, as illustrated in Figure 2, due to the different formation conditions in the different regions 206a, 206b, 206c of the fin structure 100a, the nitrogen concentrations in these regions are inconsistent.

Referring to Figure 3C, at least to mitigate inconsistencies in nitrogen concentration in different regions of the fin structure 100a, the present invention contemplates a further oxidation process 154 of the nitride layer 152, such as by introducing oxygen. In one embodiment, the nitride layer 152 is exemplified by tantalum nitride. After the oxygen is introduced, a part of the tantalum nitride, for example, the upper surface portion is oxidized, and the yttrium oxide layer is changed, so that some of the yttrium oxide layer can be consumed. The nitrogen component causes the nitrogen concentration to have a relatively uniform state on the surface of the fin structure 100a.

Referring to FIG. 3D, after the oxidation process 154 is performed on the nitride layer 152, an oxidation generating layer 156, such as hafnium oxynitride, is formed at least on top of the nitride layer 152. As such, the oxide layer 150, the nitride layer 152, and the oxidation generating layer (156) constitute the dielectric layer 120.

In terms of thickness, as described above, the thickness of the oxide layer 150 is in the range of 5 angstroms to 15 angstroms. The thickness of the nitride layer 152 is, for example, in the range of 10 angstroms to 20 angstroms. Further, the total thickness of the oxide layer 150, the nitride layer 152, and the oxidation generating layer 156 is, for example, 40 angstroms or less.

Referring to FIG. 3E, a high-k dielectric layer 122 may be formed over the oxide-generating layer 156 in accordance with an actual process. The high-k dielectric layer 122 may be formed using an Atom Layer Deposition (ADL) process, but is not limited thereto. The high-k dielectric layer 122, the oxide layer 150, the nitride layer 152, the oxidation generating layer 156, and the like constitute a gate insulating layer 180. Here, the gate insulating layer 180 is not limited to the aforementioned stacked layers. After the gate insulating layer 180 is formed, a gate process 124 is formed on the inner dielectric layer 102 and the gate insulating layer 180 by a multi-pass process including, for example, deposition, definition, and grinding. Here, the gate structure 124 can also be, for example, a stack of multiple layers. Thereafter, the description of the subsequent process of completing the fin field effect transistor can be understood by those skilled in the art, and is not limited to a specific mode, and is omitted here.

In summary, the present invention proposes different structures and corresponding manufacturing methods for the dielectric layers included in the gate insulating layer of the fin field effect transistor. By consuming the nitrogen concentration in the oxidation process, the nitrogen concentration can be made uniform in different regions of the fin structure 100a, which also improves the reliability of the gate insulating layer.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base
100a‧‧‧Fin structure
102‧‧‧Internal dielectric layer
104a, 104b‧‧‧ source/bungee
106‧‧‧gate insulation
108‧‧‧ gate structure
150‧‧‧Oxide layer
152‧‧‧ nitride layer
154‧‧‧Oxidation process
156‧‧‧Oxidation layer
120‧‧‧ dielectric layer
122‧‧‧High dielectric constant dielectric layer
124‧‧‧ gate structure
180‧‧‧ gate insulation
206a, 206b, 206c‧‧‧ areas

1 is a schematic structural view of a fin field effect transistor device according to an embodiment of the invention. 2 is a cross-sectional view of a fin field effect transistor device along a gate line, in accordance with an embodiment of the invention. 3A-3E are schematic flow charts showing a cross-sectional structure of a dielectric layer formed in a fin field effect transistor device, in accordance with an embodiment of the invention.

100a‧‧‧ protruding structure

120‧‧‧ dielectric layer

150‧‧‧Oxide layer

152‧‧‧ nitride layer

156‧‧‧Oxidation layer

Claims (17)

A fin field effect transistor device having a dielectric layer on which a nitride is stacked, comprising: an oxide layer disposed on a substrate; a nitride layer disposed on the oxide layer; and an oxidation generating layer on the nitride layer Wherein the oxidation generating layer consumes a nitrogen component in the nitride layer; and a high-k dielectric layer is disposed over the oxide generating layer. The fin field effect transistor device of claim 1, wherein the substrate has a convex structure, and the oxide layer is at least on an exposed surface of the protruding structure. The fin field effect transistor device of claim 2, wherein the protruding structure is a fin structure. The fin field effect transistor device of claim 1, wherein the oxide layer is a natural oxide layer or a hafnium oxide layer. The fin field effect transistor device of claim 1, wherein the nitride layer comprises a tantalum nitride layer, and the oxidation generating layer comprises an oxynitride layer. The fin field effect transistor device of claim 1, wherein the oxide layer has a thickness in the range of 5 angstroms to 15 angstroms. The fin field effect transistor device of claim 6, wherein the nitride layer has a thickness in the range of 10 angstroms to 20 angstroms. The fin field effect transistor device of claim 7, wherein the total thickness of the oxide layer, the nitride layer, and the oxidation generating layer is less than or equal to 40 angstroms. A method of forming a dielectric layer in a fin field effect transistor device, comprising: forming an oxide layer on a substrate; forming a nitride layer on the oxide layer; performing an oxidation process on the nitride layer to form An oxide generating layer; and depositing a high-k dielectric layer over the oxide generating layer. A method of forming a dielectric layer in a fin field effect transistor device according to claim 9, wherein the oxidizing process comprises introducing oxygen into the nitride layer to form an oxynitride layer. The method of forming a dielectric layer in a fin field effect transistor device according to claim 9, further comprising forming a protruding structure on the top of the substrate, and the oxide layer is at least at the protruding structure The exposed surface. A method of forming a dielectric layer in a fin field effect transistor device according to claim 11, wherein the protruding structure is a fin structure. A method of forming a dielectric layer in a fin field effect transistor device according to claim 9, wherein the oxide layer is formed by natural oxidation or formed by a deposition process. The method of forming a dielectric layer in a fin field effect transistor device according to claim 9, wherein the nitride layer comprises a tantalum nitride layer, and the oxidation generating layer comprises an oxynitride layer. A method of forming a dielectric layer in a fin field effect transistor device according to claim 9, wherein the thickness of the oxide layer is in the range of 5 angstroms to 15 angstroms. A method of forming a dielectric layer in a fin field effect transistor device according to claim 15 wherein the thickness of the nitride layer is in the range of 10 angstroms to 20 angstroms. The method of forming a dielectric layer in a fin field effect transistor device according to claim 16, wherein the total thickness of the oxide layer, the nitride layer, and the oxidation generating layer is less than or equal to 40 angstroms. .