TW201730520A - Capacitive sensor with low parasitic capacitance, sensor array and method of manufacturing the same - Google Patents

Abstract

A capacitive sensor with low parasitic capacitance comprises a semiconductor base and an electrode cover. The semiconductor base has a sensing circuit and a cavity portion disposed above the sensing circuit. The electrode cover disposed on the semiconductor base covers the cavity portion to form a chamber with the semiconductor base. The electrode cover electrically connected to the sensing circuit forms a sense capacitor together with an organism, and forms a parasitic capacitor together with the semiconductor base. The chamber provides a low dielectric coefficient medium to reduce the parasitic capacitor. A sensor array and a method of manufacturing the same are also provided.

Description

Capacitive sensor with low parasitic capacitance, sensor array and manufacturing method thereof

The present invention relates to a capacitive sensor with low parasitic capacitance, a capacitive sensor array, and a method of fabricating the same.

Conventional capacitive sensing technology applied to human skin can be applied to, for example, a fingerprint sensor that senses a fingerprint path or a touchpad or screen that is a capacitive touch. For example, a sensor (fingerprint sensor) applied to the skin of a finger skin, the basic structure of the portion in contact with the skin texture is an array type sensing element, that is, a plurality of identical sensing elements constitute a two-dimensional sense. When the detector is placed on the finger, for example, the ridge of the fingerprint road contacts the sensor directly, and the valley of the fingerprint road is separated from the sensor by each. The sense element is in contact with the peak or forms a gap with the valley, and the hand fingerprint path can be extracted from the two-dimensional capacitance or even the three-dimensional capacitance image, which is the most basic principle of the capacitive skin texture sensor.

The most common sensing element structure, because of the conductive properties in the human body, the skin in contact with the sensor can be regarded as an equipotential electrode plate, and each sensing element is a flat electrode, which can be between the skin and the skin. A capacitor is formed, and a material located between the two electrode plates may have a sensor protective layer disposed on the sensing electrode in contact with the skin in addition to the stratum corneum of the surface layer of the finger skin. The protective layer is a single insulating layer or multiple insulating layers and must have the characteristics of environmental corrosion resistance, impact resistance, wear resistance and electrostatic breakdown resistance.

Therefore, in addition to the sensing capacitance between the sensing electrodes of the capacitive fingerprint sensor, there is a vertical parasitic capacitance seen from the sensing electrode toward the inside of the wafer. In addition, since the sensing device is an array element and has a plurality of sensing elements, a horizontal parasitic capacitance exists between each sensing electrode and each surrounding sensing electrode, and these parasitic capacitances often cause high sensing sensitivity. One of the main reasons. In order to achieve a sensing capability of sensing capacitance less than 1fF, solving the interference of two parasitic capacitances is the most important problem. The vertical parasitic capacitance is far more influential than the horizontal parasitic capacitance because it is directly related to the area of the sensing electrode (or sensing electrode plate), for example, as a fingerprint sensor, each The area of the sensing electrode plate is at least about 50 um (micrometers) * 50 um (micrometers), and the farthest distance between the sensing electrode plate and the bottom conductive layer is in a standard integrated circuit (IC) process (for example, a CMOS process). It is a germanium substrate (for example, an internal N/P well), and the material between the two is mainly an inter-metal dielectric layer (IMD) material having a dielectric constant of about 3 to 4, and the thickness thereof is about 3 to 5 μm. (determined by the process), so the minimum value of the vertical parasitic capacitance is also about 10~20fF (determined by the process), so the sensing capacitance between each sensing electrode and the finger skin is compared to the total parasitic capacitance (horizontal and vertical) The ratio of the parasitic capacitance, especially the vertical parasitic capacitance, is as high as possible. For example, if the sensor is applied to a mobile phone, in order to facilitate integration and take into account the appearance of the mobile phone, a future demand is required for the sensor. Integrated in the underglass of the display cover glass, and the cover The thickness of the glass is about 400 ~ 500um, representative of a sensed capacitance will be less than 0.1 fF, if the applied current design capacitive fingerprint sensors, divided by the parasitic capacitance of the sensing capacitor to the quotient of less than 0.01.

Since the sensing capacitance is a fixed value (determined by the cover glass), the sensitivity of the sensor can be improved if the total parasitic capacitance value can be effectively reduced.

Therefore, an important spirit of the present invention is how to effectively reduce the total parasitic capacitance, especially the vertical parasitic capacitance.

Accordingly, it is an object of the present invention to provide a capacitive sensor with low parasitic capacitance, a capacitive sensor array, and a method of fabricating the same that utilizes a cavity to reduce the effects of parasitic capacitance on the sensing results.

To achieve the above object, the present invention provides a low parasitic capacitance capacitive sensor comprising a semiconductor substrate and an electrode cover. The semiconductor substrate has a sensing circuit and a recessed portion above the sensing circuit. The electrode cover is located on the semiconductor substrate and covers the groove portion to form a chamber with the semiconductor substrate, the electrode cover is electrically connected to the sensing circuit, the electrode cover forms a sensing capacitance with the living body, and the electrode cover and the semiconductor substrate A parasitic capacitance is formed and the chamber provides a low dielectric constant medium to reduce parasitic capacitance.

The invention further provides a capacitive sensor array with low parasitic capacitance, comprising a plurality of capacitive sensors with low parasitic capacitance, wherein the capacitive sensors with low parasitic capacitance are arranged in an array, and the cavity The chambers are isolated from each other or communicate with each other.

The invention further provides a capacitive sensor array with low parasitic capacitance, comprising the above-mentioned low parasitic capacitance capacitive sensor, an adhesive layer and a protective cover layer. These low parasitic capacitance capacitive sensors are arranged in an array. The adhesive layer is located on these low parasitic capacitance capacitive sensors. The protective cover layer is on the adhesive layer and is adhered by the adhesive layer to these low parasitic capacitance capacitive sensors for supporting the living body.

The present invention further provides a method of fabricating a low parasitic capacitance capacitive sensor array, comprising the steps of: providing a semiconductor substrate having a plurality of sensing circuits and a plurality of recesses located above the sensing circuits Providing an electrode cover structure; placing the electrode cover structure on the semiconductor substrate and covering the groove portions; bonding the electrode cover structure and the semiconductor substrate to form a plurality of chambers between the electrode cover structure and the semiconductor substrate; Forming a plurality of electrode covers, wherein a portion of the electrode cover structure is removed to leave a portion of the electrode covers and forming another portion of the electrode covers to electrically connect the electrode covers to the sense In the measuring circuit, each electrode cover forms a sensing capacitance with a living body, and each electrode cover forms a parasitic capacitance with the semiconductor substrate, and each chamber provides a low dielectric constant medium to reduce parasitic capacitance.

Since the dielectric constant of the cavity is approximately equal to 1, the parasitic capacitance can be reduced by using a very low cavity, without increasing the thickness of the inter-metal dielectric (IMD) or interlayer dielectric (ILD) to reduce parasitics. capacitance.

In order to make the above description of the present invention more comprehensible, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

Cp‧‧‧ parasitic capacitance

Cs‧‧‧Sense Capacitance

F‧‧‧ organisms

H‧‧‧ Height

1‧‧‧Capacitive sensor

2‧‧‧Capacitive Sensor Array

3‧‧‧Adhesive layer

4‧‧‧Protective cover layer

10‧‧‧Semiconductor substrate

12‧‧‧Sensor circuit

14‧‧‧ Groove

16‧‧‧Wiring layer group

16A‧‧‧Connecting mat

16B‧‧‧Wiring set

17‧‧‧Interlayer dielectric layer

18‧‧‧First insulation

19‧‧‧ Opening

20‧‧‧electrode cover

30‧‧‧ chamber

110‧‧‧First semiconductor substrate

200‧‧‧electrode cover structure

210‧‧‧Second semiconductor substrate

220‧‧‧Second insulation

225‧‧‧mask layer

226‧‧‧ openings

230‧‧‧ conductor layer

231‧‧‧ openings

240‧‧‧mask layer

241‧‧‧Opening

1 shows a partial cross-sectional view of a low parasitic capacitance capacitive sensor array in accordance with a preferred embodiment of the present invention.

FIG. 2 shows a partial equivalent circuit diagram of FIG. 1.

3 shows a top plan view of a low parasitic capacitance capacitive sensor array in accordance with a preferred embodiment of the present invention.

4A-4I are structural diagrams showing the steps of a method of fabricating a low parasitic capacitance capacitive sensor array in accordance with a preferred embodiment of the present invention.

In order to solve the problem that the ratio of the sensing capacitance to the parasitic capacitance is too low, the most important spirit of the present invention is to provide a sensor structure, which can effectively reduce the parasitic capacitance value, thereby effectively improving the sensing capacitance and parasitic. The ratio of capacitance to improve the sensitivity of the sensor.

1 shows a partial cross-sectional view of a capacitive sensor array 2 of low parasitic capacitance in accordance with a preferred embodiment of the present invention. FIG. 2 shows a partial equivalent circuit diagram of FIG. 1. 3 shows a top plan view of a capacitive sensor array 2 in accordance with a preferred embodiment of the present invention. As shown in FIG. 1 to FIG. 3 , the capacitive sensor array 2 of the present embodiment includes a plurality of capacitive sensors 1 , wherein the capacitive sensors 1 are arranged in an array, such as a two-dimensional array. The biometric information of the finger is sensed, including but not limited to fingerprints, blood vessel patterns, and the like.

In addition, the capacitive sensor array 2 can be a module structure including an adhesive layer 3 and a protective cover layer 4. Adhesive layer 3 is located on these capacitive sensors 1. The protective cover layer 4 is located on the adhesive layer 3 and adhered to the capacitive sensor 1 by the adhesive layer 3 for supporting a living body F. In one example, the organism F is a finger. The capacitive sensor array 2 is a fingerprint for sensing a finger. The protective cover layer 4 is also a protective glass such as a mobile phone or a tablet computer. Of course, it is not limited thereto, and any material having non-conductive properties may be the subject of the present invention.

The capacitive sensor 1 includes a semiconductor substrate 10 and an electrode cover 20. The semiconductor substrate 10 has a sensing circuit 12 and a recess portion 14 above the sensing circuit 12. In one embodiment, the horizontal coverage of the recessed portion 14 is greater than the horizontal coverage of the sensing circuit 12 to provide a better effect of reducing parasitic capacitance. The semiconductor substrate 10 further has a wiring layer group 16, an interlayer dielectric layer group 17, and a first insulating layer 18. The wiring layer group 16 is electrically connected to the sensing circuit 12 and includes a connection pad 16A and a wiring group 16B that are electrically connected together. The interlayer dielectric layer group 17 is located between the wiring layer group 16 and the sensing circuit 12. The first insulating layer 18 is located on the wiring layer group 16 and the interlayer dielectric layer group 17.

The electrode cover 20 is located on the semiconductor substrate 10 and covers the groove portion 14 to form a chamber 30 with the semiconductor substrate 10. Since the electrode cover 20 is in a state of being emptied, it can also be referred to as an acquaintance capacitive sensor in the present invention. Height of chamber 30 H is between 2 and 5 microns, preferably 3 microns. In one example, the chambers 30 are isolated from one another. In another example, the chambers 30 are in communication with each other. Here, the structure of the present invention reveals the most important inventive spirit. Under the sensing electrodes of each capacitive array sensor, an air or vacuum chamber is formed, and since the dielectric constant of air or vacuum is about 1, Compared with 3~4 of IMD, if the height of the chamber is 3um, it is equivalent to the thickness of IMD of 10um, then the vertical parasitic capacitance of 10~20fF can be reduced to about 3~6fF, which improves the sensing. The ratio of capacitance to parasitic capacitance is very helpful. In addition, the chamber of the present invention is used merely as a parasitic capacitance between the reduced capacitance sensing element (electrode) and the bottom substrate (including the circuit), and does not have any physical change itself. In an example, the chamber 30 The height H is not changed (or the volume of the chamber 30 is fixed for a long time), that is, the electrode cover 20 is not moved or deformed, unlike the need to deform or move the sensing electrode to generate the sensing. The sensing principle of the result, such as pressure sensing, in short, the capacitive sensor forms a sensing capacitance with the finger, instead of forming a sensing capacitance with the substrate, such technical application and disclosure are What the prior art does not have.

The electrode cover 20 is electrically connected to the sensing circuit 12 from one or more sides of the groove portion 14. The first insulating layer 18 has one or more openings 19 to expose the connection pads 16A of the wiring layer group 16 as a channel electrically connected to the electrode cover 20. In this embodiment, the electrode cover 20 includes a second insulating layer 220 and a conductor layer 230. Therefore, a portion of the electrode cover 20 (the second insulating layer 220) is located on the first insulating layer 18, and another portion of the electrode cover 20 (the conductor layer 230) passes through the second insulating layer 220 and the first insulating layer 18 to be electrically Connected to the wiring layer group 16. The conductor layer 230 may be a material compatible with CMOS, polysilicon, titanium, titanium alloy, aluminum, copper, etc., which is not limited thereto. In the embodiment, the material is aluminum (including low concentration aluminum). Copper alloy). Further, the insulating layer material is yttrium oxide or tantalum nitride, or a combination of the two, and is of course not limited thereto. Another embodiment may omit the first A second insulating layer, and the conductive layer is tantalum or polycrystalline germanium, and the conductive layer is directly bonded to the first insulating layer 18. Therefore, part or all of the material of the electrode cover is selected from the group consisting of ruthenium, polycrystalline iridium, titanium, titanium alloy, aluminum, and copper.

The electrode cover 20 forms a sensing capacitance Cs with the living body F, the electrode cover 20 forms a parasitic capacitance Cp with the semiconductor substrate 10, and the chamber 30 provides a low dielectric constant medium to reduce the parasitic capacitance Cp. In one example, chamber 30 is in a vacuum or near vacuum. In another example, the chamber 30 contains air. In the above two examples, the dielectric coefficient provided by the vacuum or air medium is close to 1, which is smaller than the dielectric constant of the inter-metal dielectric layer (IMD) or the interlayer dielectric layer (ILD) in the general semiconductor process (about 3 to 4), so the ultra-thin thickness can be used to effectively reduce the parasitic capacitance and improve the sensing sensitivity.

4A-4I are schematic diagrams showing the steps of various steps of a method of fabricating a capacitive sensor and an array in accordance with a preferred embodiment of the present invention. First, as shown in FIG. 4A, a semiconductor substrate 10 is provided. The semiconductor substrate 10 has a plurality of sensing circuits 12 and a plurality of recessed portions 14 located above the sensing circuits 12. In an example, the detailed steps are as follows. First, the sensing circuits 12 are formed on a first semiconductor substrate 110, and each of the sensing circuits 12 includes a MOS device and a connection line. Then, above the first semiconductor substrate 110 and the sensing circuits 12, a plurality of wiring layer groups 16 and an interlayer dielectric layer group 17 between the wiring layer groups 16 and the sensing circuits 12 are formed ( The interlayer dielectric layer layer includes a plurality of interlayer dielectric layers), and the wiring layer groups 16 are electrically connected to the sensing circuits 12, respectively. Then, a portion of the interlayer dielectric layer groups 17 are removed to form the recess portions 14. Then, a first insulating layer 18 is formed on the wiring layer group 16 and the interlayer dielectric layer group 17. Finally, a portion of the first insulating layer 18 is removed to form a plurality of openings 19 to expose portions of the wiring layer group 16.

Next, as shown in FIG. 4B, an electrode cover structure 200 is provided. In an example, the step of providing the electrode cover structure 200 includes: providing a second semiconductor substrate 210; And forming a second insulating layer 220 on the second semiconductor substrate 210, which is yttrium oxide in this embodiment.

Then, as shown in FIG. 4C, the electrode cover structure 200 is placed on the semiconductor substrate 10 and covers the groove portions 14. Next, the electrode cover structure 200 and the semiconductor substrate 10 are bonded, and the electrode cover structure 200 and the semiconductor substrate 10 form a plurality of chambers 30. In one example, both the electrode cover structure 200 and the semiconductor substrate 10 form an interface having a hydrogen bond strength by low temperature fusion bonding. Of course, in order to achieve surface activation before the formation of low temperature bonding, surface plasma treatment may be included, such as exposure to oxygen (O ₂ ) and nitrogen (N ₂ ) plasma environments, and in order to allow the bonded surface to have With good flatness, the surface to be joined can be polished and flattened by chemical mechanical polishing (CMP).

Then, as shown in FIGS. 4D to 4I, the purpose is to form a plurality of electrode covers 20. As shown in FIG. 4D, removing a portion of the electrode cover structure 200 (ie, removing the second semiconductor substrate (eg, the germanium substrate) 210 may be stopped by etching to a second insulating layer (eg, a hafnium oxide layer) 220. The process is performed to leave a portion (second insulating layer 220) of the electrode covers 20 electrically connected to the sensing circuits from one or more sides of the groove portions 14 12. Next, as shown in FIG. 4E, a patterned mask layer 225 is formed on the second insulating layer 220, and the mask layer 225 has a plurality of openings 226. Then, as shown in FIG. 4F, an opening 221 through the second insulating layer 220 is formed through the opening 226 of the mask layer 225 (for example, by an etching process), and a portion of the wiring layer group 16 is opened from the opening 221. Exposed, then the mask layer 225 is removed. That is, the second insulating layer 220 is patterned to form a plurality of openings 221 to expose portions of the wiring layer groups 16. Next, as shown in FIG. 4G, a conductor layer 230 is formed on the second insulating layer 220 and the wiring layer groups 16 as another portion of the electrode covers 20. Then, as shown in FIG. 4H, on the conductor layer 230 A patterned mask layer 240 is formed thereon, and the mask layer 240 has a plurality of openings 241. Then, as shown in FIG. 4I, an opening 231 through the conductor layer 230 is formed through the opening 241 of the mask layer 240 (for example, by an etching process), and then the mask layer 225 is removed. The process of Figures 4H through 4I also patterns the conductor layer 230 to form the electrode caps 20 that are spaced apart. In an example, an insulating layer (not shown) is also disposed over the conductor layer 230 to protect the conductor layer 230.

It should be noted that the chamber 30 can also be formed by sacrificial layer etching, and is not necessarily limited to the above bonding manner. Since the implementation technique of the sacrificial layer can be known to those having ordinary knowledge, it will not be described here.

With the above embodiments of the present invention, the cavity can be utilized to reduce parasitic capacitance, thereby increasing the sensitivity of the capacitive sensor. Since the dielectric constant of air or vacuum is about 1, compared with 3~4 of IMD, there can be about 3 times the parasitic capacitance reduction effect at the same height, which is very helpful for increasing the Cf/Cp value. Otherwise, if the thickness of the IMD is increased to effectively reduce the parasitic capacitance, the manufacturing process becomes complicated and expensive, and the thick IMD will have a large thermal stress effect, resulting in wafer cracking or quality problems, which are difficult to achieve. Manufacturing method. Therefore, the present invention easily achieves the goal of reducing parasitic capacitance by an electrode bottom chamber design, and is relatively easy and inexpensive to manufacture, can greatly overcome the problems of the prior art, and can be applied, for example, to the underside of the glass ( Underglass) product design, quite breakthrough. In addition, the chamber of the present invention is used merely as a parasitic capacitance between the reduced capacitance sensing element (electrode) and the bottom substrate (including the circuit), and has no physical change itself. In one example, the chamber The height H of 30 is not changed, that is, the electrode cover 20 is not moved or deformed, unlike the sensing principle that requires deformation or movement of the sensing electrode to produce a sensing result, such as pressure sensing, simply In other words, the capacitive sensor forms a sensing capacitance with the finger instead of forming a sensing capacitance with the substrate. Such technical application and disclosure are both What the prior art does not have.

Since the dielectric constant of the cavity is approximately equal to 1, the extremely low cavity can be used to reduce the parasitic capacitance without increasing the thickness of the IMD and ILD to reduce the parasitic capacitance.

The specific embodiments of the present invention are intended to be illustrative only and not to limit the invention to the above embodiments, without departing from the spirit of the invention and the following claims. The scope of the invention and the various changes made are within the scope of the invention.

F‧‧‧ organisms

H‧‧‧ Height

1‧‧‧Capacitive sensor

2‧‧‧Capacitive Sensor Array

3‧‧‧Adhesive layer

4‧‧‧Protective cover layer

10‧‧‧Semiconductor substrate

12‧‧‧Sensor circuit

14‧‧‧ Groove

16‧‧‧Wiring layer group

16A‧‧‧Connecting mat

16B‧‧‧Wiring set

17‧‧‧Interlayer dielectric layer

18‧‧‧First insulation

19‧‧‧ Opening

20‧‧‧electrode cover

30‧‧‧ chamber

220‧‧‧Second insulation

230‧‧‧ conductor layer

Claims (12)

A low parasitic capacitance capacitive sensor comprising: a semiconductor substrate having a sensing circuit and a recess portion located above the sensing circuit; and an electrode cover on the semiconductor substrate and covering the The recessed portion forms a chamber with the semiconductor substrate, the electrode cover is electrically connected to the sensing circuit, the electrode cover forms a sensing capacitance with a living body, and the electrode cover forms a parasitic capacitance with the semiconductor substrate The chamber provides a low dielectric constant medium to reduce the parasitic capacitance. The capacitive sensor of the low parasitic capacitance of claim 1, wherein the semiconductor substrate further comprises: a wiring layer group electrically connected to the sensing circuit; and an interlayer dielectric layer located at the wiring Between the layer set and the sensing circuit; and a first insulating layer on the wiring layer group and the interlayer dielectric layer group. The capacitive sensor of low parasitic capacitance according to claim 2, wherein a part of the electrode cover is located on the first insulating layer, and another part of the electrode cover passes through the first insulating layer. Electrically connected to the wiring layer set. The capacitive sensor of low parasitic capacitance according to claim 3, wherein part or all of the material of the electrode cover is selected from the group consisting of tantalum, polycrystalline germanium, titanium, titanium alloy, aluminum and copper. Group. A capacitive sensor of low parasitic capacitance as described in claim 1, wherein a height of the chamber is between 2 and 5 microns. A low parasitic capacitance capacitive sensor array comprising a plurality of low parasitic capacitance capacitive sensors as described in claim 1 wherein the low parasitic capacitance capacitive sensors are arranged in an array And the chambers are isolated from one another. A low parasitic capacitance capacitive sensor array comprising a plurality of low parasitic capacitance capacitive sensors as described in claim 1 wherein the low parasitic capacitance capacitive sensors are arranged in an array And the chambers are in communication with each other. A capacitive sensor array with low parasitic capacitance, comprising: a plurality of capacitive sensors with low parasitic capacitance as described in claim 1 wherein the low parasitic capacitance capacitive sensors are arranged in a An array of adhesive layers on the capacitive sensor of the low parasitic capacitance; and a protective cover layer on the adhesive layer and capacitively attached to the low parasitic capacitance by the adhesive layer Used to support the organism. A method for fabricating a low parasitic capacitance capacitive sensor array, comprising the steps of: providing a semiconductor substrate having a plurality of sensing circuits and a plurality of recess portions located above the sensing circuits; providing a Electrode cover structure; Depositing the electrode cover structure on the semiconductor substrate and covering the groove portions; joining the electrode cover structure and the semiconductor substrate to form the electrode cover structure and the semiconductor substrate to form a plurality of chambers; forming a plurality of An electrode cover, wherein a portion of the electrode cover structure is removed to leave a portion of the electrode cover and form another portion of the electrode cover to electrically connect the electrode covers to the sensing In the circuit, each of the electrode covers forms a sensing capacitance with a living body, and each of the electrode covers forms a parasitic capacitance with the semiconductor substrate, and each of the chambers provides a low dielectric constant medium to reduce the parasitic capacitance. The method for manufacturing a low-parasitic capacitance capacitive sensor array according to claim 9 , wherein the step of providing the semiconductor substrate comprises: forming the sensing circuits on a first semiconductor substrate; a plurality of wiring layer groups and a plurality of interlayer dielectric layer groups between the wiring layer groups and the sensing circuits are formed on a semiconductor substrate and the sensing circuits, wherein the wiring layer groups are respectively electrically connected And the sensing circuit; the portion of the interlayer dielectric layer is removed to form the recess portions; a first insulating layer is formed on the wiring layer group and the interlayer dielectric layer groups; A portion of the first insulating layer is removed to expose a portion of the wiring layer set. The method for manufacturing a low-parasitic capacitance capacitive sensor array according to claim 10, wherein the step of providing the electrode cover structure comprises: forming a second insulating layer on a second semiconductor substrate. The method for manufacturing a capacitive sensor array of low parasitic capacitance according to claim 11, wherein the step of forming the electrode covers comprises the substep of removing the second semiconductor substrate to leave the a second insulating layer; the second insulating layer is patterned to form a plurality of openings to expose portions of the wiring layer groups; and a conductive layer is formed on the second insulating layer and the wiring layer groups as the Another portion of the electrode cover; and patterning the conductor layer to form the spaced apart electrode covers.