TW201729524A - Power conversion apparatus - Google Patents

Abstract

A power conversion apparatus including a power conversion circuit, a synchronous rectification transistor, a synchronous rectification control circuit, a feedback circuit, and a cable loss compensation circuit. The power conversion circuit converts an input voltage into an output voltage and provides it to a load for use. The synchronous rectification transistor is coupled to, in series, a current path in secondary side of the power conversion circuit and switched according to a synchronous rectification control signal. The synchronous rectification control circuit generates the synchronous rectification control signal for controlling the switching of the synchronous rectification transistor. The feedback circuit generates an output indication current related to the output voltage. The cable loss compensation circuit sink a compensation current from the feedback circuit according to the synchronous rectification control signal, so as to compensate the output voltage based on the summation of the compensation current and the output indication current.

Description

Power conversion device

The present invention relates to a power conversion technique, and more particularly to a power conversion apparatus that can compensate for line losses.

The main purpose of the power conversion apparatus is to convert the high-voltage and low-stability input voltage provided by the power company into a low voltage suitable for various electronic devices and has better stability. DC output voltage. Therefore, power conversion devices are widely used in electronic devices such as computers, office automation equipment, industrial control equipment, and communication equipment.

When the power required by the load terminal is large, the power conversion device needs to provide a large output current for the load to be used. At this time, the operating state of the power conversion device is called a heavy load operation. Under heavy-duty operation, a large output current usually causes a voltage drop on the output line, which may cause the voltage supplied to the load terminal to exceed the specification. This phenomenon is generally referred to as cable loss.

In the existing power conversion devices, some line loss compensation mechanisms are usually used to compensate for the output voltage drop caused by line loss during heavy load operation. In the commonly used line loss compensation method, one of them determines the output current by detecting the length of the cutoff period of the power switch, and then determines the compensation amount of the output voltage; the other is to set the output current detection. The circuit directly detects the magnitude of the output current, and then determines the amount of compensation for the output voltage.

However, since the power conversion device operates in a continuous conduction mode (CCM), the off period is fixed and cannot reflect the output current. Therefore, the line loss compensation method according to the cutoff period of the power switch can be applied only to A discontinuous conduction mode (DCM) power conversion device.

On the other hand, since the current detecting mechanism of the general current detecting circuit usually samples the output current, and then causes the sampling current to flow through a specific resistor, the voltage across the resistor is measured to determine the current flowing through the resistor. The magnitude of the sampling current is calculated, and then the output current is calculated according to the sampling current back. Therefore, in the general output current detection mode, it is bound to cause additional power consumption.

In view of this, the present invention provides a power conversion device to solve the problems described in the prior art.

The power conversion device of the present invention includes a power conversion circuit, a synchronous rectification transistor, a synchronous rectification control circuit, a feedback circuit, and a line loss compensation circuit. The power conversion circuit is configured to perform power conversion on the input voltage to generate an output voltage and provide the output voltage to the load. The synchronous rectification transistor is serially connected to the secondary side current path of the power conversion circuit, and is switched to the on state by being controlled by the synchronous rectification control signal. The synchronous rectification control circuit is coupled to the synchronous rectification transistor for generating a synchronous rectification control signal to control switching of the synchronous rectification transistor. The feedback circuit is coupled to the power conversion circuit for generating an output indicating current associated with the output voltage. The line loss compensation circuit is coupled to the synchronous rectification control circuit and the feedback circuit for extracting the compensation current from the feedback circuit according to the synchronous rectification control signal, thereby compensating the output voltage based on the sum of the compensation current and the output indication current.

Based on the above, the present invention provides a power conversion device including a line loss compensation circuit that can utilize a synchronous rectification control signal as a basis for line loss compensation. The line loss compensation circuit may generate a compensation current corresponding to the magnitude of the output current based on the synchronous rectification control signal, and thereby compensate the line loss of the output voltage at the time of heavy load. Since the waveform of the synchronous rectification control signal can indicate the magnitude of the output current under DCM or CCM, the power conversion device of the embodiment of the present invention can effectively perform line loss compensation regardless of whether it is operated under DCM or CCM. It will be limited by the mode of operation of the power conversion device. In addition, since the power conversion device of the embodiment of the present invention does not need to directly detect the output current by using the additional current detection circuit, the overall power loss of the power conversion device can be reduced.

The above described features and advantages of the invention will be apparent from the following description.

In order to make the disclosure of the present disclosure easier to understand, the following specific embodiments are examples of the disclosure that can be implemented. In addition, wherever possible, the same elements, components, and steps in the drawings and embodiments are used to represent the same or similar components.

1 is a schematic diagram of a power conversion device according to an embodiment of the present invention. Referring to FIG. 1 , the power conversion device 100 of the present embodiment includes a power conversion circuit 110 , a synchronous rectification transistor 120 , a synchronous rectification control circuit 130 , a feedback circuit 140 , and a detection auxiliary circuit 130 .

The power conversion circuit 110 can be, for example, a flyback converter having a synchronous rectification function. In the present embodiment, the power conversion circuit 110 is configured to receive the input voltage Vin and perform power conversion on the input voltage Vin to generate a DC output voltage Vout, wherein the output voltage Vout is supplied to the load LD, wherein the load LD can be, for example The present invention is not limited to any type of electronic device.

The synchronous rectification transistor 120 is connected in series to the secondary side current path of the power conversion circuit 110 (the circuit architecture of the subsequent embodiment will be specifically illustrated), and is controlled by the synchronous rectification control signal Ssr generated by the synchronous rectification control circuit 130. Switch the conduction state.

The synchronous rectification control circuit 130 is coupled to the synchronous rectification transistor 120, and cooperates with the power switch (not shown) switching timing of the power conversion circuit 110 to provide a corresponding synchronous rectification control signal Ssr to control the switching of the synchronous rectification transistor 120, so that A secondary side power supply can be provided to the load LD terminal.

The feedback circuit 140 is coupled to the power conversion circuit 110, which can be used to sample the output voltage Vout at the output of the secondary side, and accordingly generate an output indicating current Iic associated with the output voltage Vout. In addition, the feedback circuit 140 also couples the sampled voltage information as a feedback voltage Vfb back to the primary side for supply to the power conversion circuit 110 as a basis for control.

The line loss compensation circuit 150 is coupled to the synchronous rectification control circuit 130 and the feedback circuit 140, and can be used to retrieve the corresponding compensation current Icomp from the feedback circuit 140 according to the synchronous rectification control signal Ssr generated by the synchronous rectification control circuit 130. Thereby, in addition to the voltage originally established in the feedback circuit 140 based on the output indicating current Iic, the line loss compensation circuit 150 establishes an additional voltage in the feedback circuit 140 to compensate the output voltage based on the captured compensation current Icomp. Vout. In other words, the line loss compensation circuit 150 compensates the output voltage Vout based on the sum of the compensation current Icomp outputting the indication current Iic.

Specifically, in the synchronous rectification control circuit 130 applied in this embodiment, the synchronous rectification control signal Ssr generated is operated in a continuous conduction mode (CCM) or a discontinuous conduction mode (discontinuous conduction mode). Under , DCM), there are characteristics that the waveform will vary with the output current Iout/load and weight. The line loss compensation circuit 150 of the present embodiment mainly utilizes the characteristic as a basis for determining the operating state of the power conversion circuit 110, and compensates based on the synchronous rectification control signal Ssr to generate a compensation current Icomp associated with the magnitude of the output current and the change of the load LD. The voltage drop of the output voltage Vout at high current/heavy load.

More specifically, the line loss compensation mode of the present embodiment can be simultaneously applied to the DCM and the CCM without being limited by the power conversion circuit 110, compared to the manner of performing the line loss compensation according to the off period of the power switch. Mode of operation. On the other hand, compared with the direct detection output current Iout and the line loss compensation method, the line loss compensation method of the embodiment can reduce the power loss because the output current Iout is not directly detected. .

The line loss compensation mechanism of this embodiment will be described below with the specific circuit shown in FIG. 2. 2 is a circuit diagram of a power conversion device according to an embodiment of the present invention.

Referring to FIG. 2, the power conversion device 200 of the present embodiment includes a power conversion circuit 210, a synchronous rectification transistor 220, a synchronous rectification control circuit 230, a feedback circuit 240, and a line loss compensation circuit 250. The power conversion circuit 210 includes a transformer T, an input capacitor Cin, a power switch PSW, a control chip CTP, and an output capacitor Cout. The line loss compensation circuit 250 includes resistors R1, R2, and Rb, a capacitor C1, and a transistor Q1. The feedback circuit 240 includes resistors R3, R4 and R5, a capacitor C2, a regulator U1, and an optocoupler PC.

In the power conversion circuit 210, the transformer T has a primary winding Np and a secondary winding Ns. Wherein, the primary side circuit (one side of the primary side winding Np) uses the ground terminal GND1 as a voltage reference point, and the secondary side circuit (the side of the secondary side winding Ns) uses the ground terminal GND2 as a voltage reference point. . The grounding ends GND1 and GND2 may be the same or different grounding surfaces, which are not limited by the present invention.

The common-polarity terminal of the primary winding Np of the transformer T is coupled to the power switch PSW, and the opposite-polarity terminal of the primary winding Np of the transformer T is used. Receive input voltage Vin. The same end of the secondary winding Ns of the transformer T is coupled to the first end of the output capacitor Cout, and the different end of the secondary winding Ns of the transformer T is coupled to the second end of the output capacitor Cout via the synchronous rectification transistor 220. Grounding terminal GND2 on the secondary side.

The control chip CTP is coupled to the control end of the power switch PSW to provide a pulse width modulation signal Spwm to control the switching of the power switch PSW. The power switch PSW is exemplified by, for example, an NMOS. The first end of the power switch PSW (here, the drain, but not limited to, the type of the visible power switch PSW) is coupled to the same end of the primary winding Np of the transformer T, and the second end of the power switch PSW The source is coupled to the ground GND1, and the control terminal of the power switch PSW (here, the gate) is used to receive the pulse width modulation signal Spwm from the control chip 120.

The first end of the input capacitor Cin is coupled to the different end of the primary winding Np, and the second end of the input capacitor Cin is coupled to the ground GND1. The first end of the output capacitor Cout is coupled to the same end of the secondary side winding Ns, and the second end of the output capacitor Cout is coupled to the ground GND2.

The synchronous rectifying transistor 220 is exemplified by, for example, an NMOS. The first end of the synchronous rectifying transistor 220 (here, the drain, but not limited to, the type of the visible synchronous rectifying transistor 220) is coupled to the second end of the output capacitor Cout, and the second of the synchronous rectifying transistor 220 The terminal (here, the source) is coupled to the different-name end of the secondary winding Ns of the transformer T, and the control terminal of the synchronous rectification transistor 220 (here, the gate) is used to receive the synchronous rectification from the synchronous rectification control circuit 23. Control signal Ssr. In other words, the first end and the second end of the synchronous rectifying transistor 220 are connected in series on the current path of the secondary side winding Ns, and thus the conduction state of the synchronous rectifying transistor 220 determines whether the secondary side current path is interrupted.

In the feedback circuit 240, the first end of the resistor R3 is coupled to the first end of the output capacitor Cout. The first end of the resistor R4 is coupled to the second end of the resistor R3, and the second end of the resistor R4 is coupled to the ground GND2. The first end of the resistor R5 is coupled to the second end of the resistor R3 and the first end of the resistor R4. The first end of the capacitor C2 is coupled to the second end of the resistor R5.

The first end of the input side of the optocoupler PC is coupled to the first end of the resistor R3, and the second end of the input side of the optocoupler PC is coupled to the second end of the capacitor C2. The first end of the output side of the optocoupler PC outputs the feedback voltage Vfb, and the second end of the output side of the optocoupler PC is coupled to the ground GND1.

The first end of the voltage regulator U1 is coupled to the second end of the capacitor C2 and the second end of the input side of the optocoupler PC, the second end of the voltage regulator U1 is coupled to the ground GND2, and the regulator U1 is stable. The second end of the resistor R3 is coupled to the first end of the resistor R4 (ie, the node NC), and the voltage on the node NC is regulated.

The optocoupler PC cooperates with the operation of the regulator U1 to generate a feedback voltage Vfb associated with the output voltage Vout on the output side thereof according to the DC output voltage Vout to the control chip CTP, so that the control chip CTP can be based on The voltage Vfb is used as the basis for controlling the power switch PSW.

In the line loss compensation circuit 250, the first end of the resistor R1 is coupled to the signal output end of the synchronous rectification control circuit 230, thereby receiving the synchronous rectification control signal Ssr. The first end of the resistor R2 is coupled to the node NC (ie, the first end of the resistor R4 in the feedback circuit 240). The first end of the capacitor C1 is coupled to the second end of the resistor R1, and the second end of the capacitor C1 is coupled to the ground GND2. The transistor Q1 is exemplified by, for example, BJT. The first end of the transistor Q1 (here, the collector) is coupled to the second end of the resistor R2, the second end of the transistor Q1 (here, the emitter) is coupled to the ground GND2, and the base of the transistor Q1 The second end of the resistor R1 is coupled to the first end of the capacitor C1.

In detail, when the power conversion device 200 is in normal operation, the control chip CTP responds to the power supply demand of the load to correspondingly generate the pulse width modulation signal Spwm to control the operation of the power conversion circuit 210. Under this condition, when the power switch PSW is turned on in response to the pulse width modulation signal Spwm generated by the control chip CTP, the input voltage Vin is connected across the primary side winding Np of the transformer T, so that the transformer T The inductor current of the primary side winding Np linearly increases to store energy. At the same time, the synchronous rectification control circuit 230 generates a disable synchronous rectification control signal Ssr on the secondary side winding Ns side to turn off the synchronous rectification transistor 220. Due to the blocking of the cut-off synchronous rectifying transistor 220, the secondary side winding Ns of the transformer T will pass no current.

When the power switch PSW is turned off in response to the pulse width modulation signal Spwm generated by the control wafer CTP, the energy stored in the primary winding Np of the transformer T is transferred to the secondary of the transformer T based on Lenz's law. Side winding Ns. At the same time, the synchronous rectification control circuit 230 generates an enabled synchronous rectification control signal Ssr on the secondary side winding Ns side to turn on the synchronous rectification transistor 220. Since the synchronous rectifying transistor 220 is turned on, the energy transferred to the secondary side winding Ns of the transformer T will charge the output capacitor Cout, and supply the output voltage Vout to the load (electronic device).

From this, it can be seen that the power conversion device 200 continuously supplies the output voltage Vout by alternately turning on and off the operation mode of the power switch PSW based on the pulse width modulation signal Spwm generated by the control wafer CTP.

On the other hand, in the operation of the line loss compensation circuit 250, in the case where the synchronous rectification control signal Ssr is enabled, the capacitor C1 is charged in response to the voltage level of the synchronous rectification control signal Ssr, so that the node NB is charged. The voltage Vnb is gradually increased during the enable period of the synchronous rectification control signal Ssr, and is held at a specific voltage value by the capacitor C1 when the synchronous rectification control signal Ssr is switched to disabled.

When the voltage across the base and the emitter of the transistor Q1 exceeds the barrier voltage, the transistor Q1 generates an emitter current having a multiple relationship with the base current, that is, a compensation current Icomp flowing through the resistor R2. In the case that the compensation current Icomp has not yet been generated, the output voltage Vout will be equal to the output indicating current Iic multiplied by the resistance value of the resistor R3 (ie, the voltage across the resistor R3) plus the regulated voltage Vu (indicated by the formula, that is, Vout =Iic*R3+Vu). When the compensation current Icomp is generated, since the transistor Q1 draws an additional current from the node Nc, the current flowing through the resistor R3 becomes the output indicating current Iic plus the compensation current Icomp. In other words, in the case where the compensation current Icomp is generated, the output voltage Vout is equal to the sum of the current values of the output indicating current Iic and the compensation current Icomp multiplied by the resistance value of the resistor R3 plus the regulated voltage Vu (indicated by the formula, that is, Vout = (Iic + Icomp) * R3 + Vu).

It can be seen from the above formula that when the line loss compensation circuit 250 reacts with the synchronous rectification control signal Ssr to generate the compensation current Icomp, the output voltage Vout is pulled high, thereby achieving the effect of compensating the output voltage Vout. In addition, since the magnitude of the compensation current Icomp is determined by the voltage Vnb on the node NB, the level of the voltage Vnb is positively correlated with the product of the voltage level and the enable time of the synchronous rectification control signal Ssr, wherein the synchronization The product of the voltage level of the rectification control signal Ssr and the enable time indicates the magnitude of the output current Iout. Therefore, the line loss compensation circuit 250 of the present embodiment can achieve the effect of compensating the output voltage Vout by providing a corresponding compensation value as the output current Iout is large/loaded.

The signal timing of the power conversion device 200 of the present embodiment operating under DCM and CCM will be respectively described below with reference to FIGS. 3 and 4.

The signal timing of the power conversion device 200 operating in the DCM is as shown in FIG. Referring to FIG. 2 and FIG. 3 simultaneously, since the off period of the power switch PSW is not fixed under DCM, the enable period of the synchronous rectification control signal Ssr varies with the off period of the power switch PSW. Further, in the signal waveform of the synchronous rectification control signal Ssr, it has a characteristic that it will attenuate after a certain period of time. In other words, under DCM, the area of the enable waveform of the synchronous rectification control signal Ssr is positively correlated with the magnitude of the output current Iout.

This embodiment illustrates the operation of the power conversion device 200 under different loads in a state where the load is gradually increased. In the period T1, the load is lighter at this time, and the enabling period of the synchronous rectification control signal Ssr is short, so that the base voltage Vb of the transistor Q1 has not exceeded the barrier voltage Vth in the period T1, so the line loss compensation circuit in the period T1 The voltage conversion circuit 210 does not compensate the output voltage Vout, so that the voltage value of the output voltage Vout is substantially maintained at V1 during the period T1.

When the load is increased, such as the operation of the period T2, the enabling period of the synchronous rectification control signal Ssr is increased. Since the capacitor C1 is continuously charged during the enable period of the synchronous rectification control signal Ssr, the base voltage Vb of the transistor Q1 exceeds the barrier voltage Vth. In this case, the voltage difference between the voltage Vnb and the base voltage Vb establishes the base current Ib on the resistor Rb, so that the compensation current Icomp is generated (with a β-fold relationship with the base current Ib). The output voltage Vout is pulled up to the voltage value V2 by the action of the compensation current Icomp, thereby compensating for the voltage drop generated when the load is increased.

Similarly, in the successive period T3, as the output load continues to increase, the base current Ib also increases as the area of the synchronous rectification control signal Ssr is enabled, so that the compensation current Icomp also increases, thereby making the output voltage Vout Then, the voltage value V2 is pulled up to the voltage value V3 to compensate for the voltage drop generated when the load is increased.

The signal timing of the power conversion device 200 operating in the CCM is as shown in FIG. Referring to FIG. 2 and FIG. 4 simultaneously, since the off period of the power switch PSW is fixed under the CCM, the enable period of the synchronous rectification control signal Ssr is also fixed. However, when the output current Iout is large, the synchronous rectification control signal Ssr is slowed down; conversely, when the output current Iout is small, the synchronous rectification control signal Ssr is attenuated earlier. In other words, under CCM, the area of the enable waveform of the synchronous rectification control signal Ssr is also positively correlated with the magnitude of the output current Iout.

This embodiment also illustrates the operation of the power conversion device 200 under different loads in a state where the load is gradually increased. In the period T1, since the load is light at this time, the voltage level of the synchronous rectification control signal Ssr is attenuated earlier, so that the voltage level of the voltage Vnb on the node NB is lower in the period T1, and thus the line loss in the period T1. The compensation current Icomp generated by the compensation circuit 250 is small, so that the voltage value of the output voltage Vout is substantially maintained at V1 during the period T1.

When the load is increased, such as the operation of the period T2, the voltage level of the synchronous rectification control signal Ssr is delayed until it is delayed later, so that the capacitor C1 is charged at a high voltage level for a long time, so that the node NB is charged. The voltage level of the voltage Vnb rises. In this case, since the base current Ib rises with the rise of the voltage Vnb, and the magnitude of the compensation current Icomp has a multiple relationship with the base current Ib, the output voltage Vout can be affected by the compensation current Icomp. The voltage value V1 is pulled up to the voltage value V2 to compensate for the voltage drop generated when the load is increased.

Similarly, in the successive period T3, as the output load continues to increase, the base current Ib also increases as the area of the synchronous rectification control signal Ssr is enabled, so that the compensation current Icomp also increases, thereby making the output voltage Vout Then, the voltage value V2 is pulled up to the voltage value V3 to compensate for the voltage drop generated when the load is increased.

In summary, the present invention provides a power conversion device including a line loss compensation circuit that can utilize a synchronous rectification control signal as a basis for line loss compensation. The line loss compensation circuit may generate a compensation current corresponding to the magnitude of the output current based on the synchronous rectification control signal, and thereby compensate the line loss of the output voltage at the time of heavy load. Since the waveform of the synchronous rectification control signal can indicate the magnitude of the output current under DCM or CCM, the power conversion device of the embodiment of the present invention can effectively perform line loss compensation regardless of whether it is operated under DCM or CCM. It will be limited by the mode of operation of the power conversion device. In addition, since the power conversion device of the embodiment of the present invention does not need to directly detect the output current by using the additional current detection circuit, the overall power loss of the power conversion device can be reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 200‧‧‧ power conversion device
110, 210‧‧‧ power conversion circuit
120, 220‧‧‧ synchronous rectifier crystal
130, 230‧‧‧ synchronous rectification control circuit
140, 240‧‧ ‧ feedback circuit
150, 250‧‧‧Line loss compensation circuit
Ib‧‧‧base current
Iout‧‧‧Output current
Iic‧‧‧Output indicator current
Icomp‧‧‧compensation current
C1, C2‧‧‧ capacitor
Cin‧‧‧ input capacitor
Cout‧‧‧ output capacitor
CTP‧‧‧ control chip
GND1, GND2‧‧‧ Ground
NB, NC‧‧‧ nodes
NP‧‧‧ primary winding
NS‧‧‧ secondary winding
PC‧‧‧Optocoupler
PSW‧‧‧Power Switch
LD‧‧‧ load
Rb, Ri, R1, R2, R3, R4, R5‧‧‧ resistance
Spwm‧‧‧ pulse width modulation signal
Ssr‧‧‧Synchronous Rectifier Control Signal
T‧‧‧Transformer
T1, T2, T3‧‧ cycle
V1, V2, V3, Vb, Vnb‧‧‧ voltage
Vfb‧‧‧ feedback voltage
Vin‧‧‧Input voltage
Vout‧‧‧ output voltage
Vth‧‧ ‧ barrier voltage

1 is a functional block diagram of a power conversion device according to an embodiment of the present invention. 2 is a circuit diagram of a power conversion device according to an embodiment of the present invention. FIG. 3 is a timing diagram of signals of a power conversion device according to an embodiment of the present invention. FIG. 4 is a timing diagram of signals of a power conversion device according to another embodiment of the present invention.

100‧‧‧Power conversion device

110‧‧‧Power conversion circuit

120‧‧‧Synchronous rectifier transistor

130‧‧‧Synchronous rectification control circuit

140‧‧‧Responsive circuit

150‧‧‧Line loss compensation circuit

Iout‧‧‧Output current

Iic‧‧‧Output indicator current

Icomp‧‧‧compensation current

LD‧‧‧ load

Ssr‧‧‧Synchronous Rectifier Control Signal

Vfb‧‧‧ feedback voltage

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Claims (9)

A power conversion device includes: a power conversion circuit for performing power conversion on an input voltage to generate an output voltage, and supplying the output voltage to a load; and a synchronous rectification transistor connected in series to the power conversion a secondary side current path of the circuit, and controlled by a synchronous rectification control signal to switch the conduction state; a synchronous rectification control circuit coupled to the synchronous rectification transistor for generating the synchronous rectification control signal to control the synchronization Switching of a rectifying transistor; a feedback circuit coupled to the power conversion circuit for generating an output indicating current associated with the output voltage; and a line loss compensation circuit coupled to the synchronous rectification control circuit and the feedback circuit And obtaining a compensation current from the feedback circuit according to the synchronous rectification control signal, thereby compensating the output voltage based on a sum of the compensation current and the output indication current. The power conversion device of claim 1, wherein the waveform of the synchronous rectification control signal varies with an output current generated by the power conversion circuit. The power conversion device of claim 1, wherein the magnitude of the compensation current is positively correlated with a product of a coincidence time of the synchronous rectification control signal and a voltage level. The power conversion device of claim 1, wherein the line loss compensation circuit comprises: a first resistor, the first end of which is coupled to the synchronous rectification control circuit, thereby receiving the synchronous rectification control signal; a resistor having a first end coupled to the feedback circuit; a first capacitor having a first end coupled to the second end of the first resistor and a second end coupled to a secondary ground; and a transistor having a first end coupled to the second end of the second resistor, a second end coupled to the ground, and a control end coupled to the second end of the first resistor and the first capacitor One end. The power conversion device of claim 4, wherein the current flowing through the second resistor is the compensation current. The power conversion device of claim 4, wherein the power conversion circuit comprises: a transformer having a primary side winding and a secondary side winding, wherein the opposite end of the primary side winding receives the input voltage; An input terminal having a first end coupled to the opposite end of the primary winding and a second end coupled to a primary side ground; a power switch having a first end coupled to the same end of the primary winding The second end is coupled to the primary side grounding end; a control chip coupled to the control end of the power switch to provide a pulse width modulation signal to control switching of the power switch; and an output capacitor, the first The end is coupled to the end of the same name of the secondary winding, and the second end is coupled to the secondary ground. The power conversion device of claim 6, wherein the first end of the synchronous rectifying transistor is coupled to the second end of the output capacitor, and the second end of the synchronous rectifying transistor is coupled to the secondary winding The opposite end of the synchronous rectification transistor is coupled to the synchronous rectification control circuit. The power conversion device of claim 6, wherein the feedback circuit comprises: a third resistor having a first end coupled to the first end of the output capacitor and a second end coupled to the second end a first end of the resistor; a first end coupled to the first end of the second resistor and the second end of the third resistor, and a second end coupled to the second side ground end; a fifth resistor, the first end of which is coupled to the second end of the third resistor and the first end of the fourth resistor; a second capacitor, the first end of which is coupled to the second end of the fifth resistor; a voltage regulator having a first end coupled to the second end of the second capacitor, a second end coupled to the second side ground, and a voltage stabilizing end coupled to the second end of the third resistor The first end of the four resistors. The power conversion device of claim 8, wherein the current flowing through the fourth resistor is the output indicating current, and the current flowing through the third resistor is the sum of the output indicating current and the compensation current.