TW201727869A - Thin film resistor, semiconductor device and method of fabricating the same - Google Patents

Abstract

Provided is a semiconductor device having a thin film resistor. The semiconductor device includes a substrate having a first region and a second region. At least one MOS transistor is disposed on the second region. The first region includes a plurality of first conductive structures, a first dielectric layer, a resistor layer, a second dielectric layer, and a plurality of contacts. The first conductive structures are located on the substrate of the first region. The first dielectric layer overlays the first conductive structures, so that the first conductive structures are electrically isolated from each other. The resistor layer is located on the first dielectric layer. The second dielectric layer is located on the resistor layer. The contacts at least pass through the second dielectric layer and electrically connect with the resistor layer respectively.

Description

Thin film resistor, semiconductor element and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a thin film resistor and a method of fabricating the same.

In general, electronic components can be easily divided into active components and passive components. An element capable of performing data operations and data processing in a circuit is referred to as an active element. A passive component generally refers to a component that does not have a signal amplification function, and may include a resistor, a capacitor, and an inductor.

With the evolution of semiconductor technology, various electronic components are moving toward high speed, high efficiency, and light and thin, and under this trend, the miniaturization of the above passive components is based on Thin Film Resistors (TFR). For example, it will gradually receive attention. However, since the thickness of the thin film resistor is too thin, it is difficult to precisely control the depth of the contact window opening by the conventional etching process, so that the electrical connection between the subsequently formed contact window and the thin film resistor is poor, which leads to a decrease in yield and no Steady co-efficient of resistivity (TCR). Therefore, how to form a semiconductor device having a thin film resistor under the premise of improving the yield and maintaining the temperature coefficient of resistance will be one of the important issues in the future.

The present invention provides a semiconductor element having a thin film resistor and a method of manufacturing the same, which have a low temperature coefficient of resistance and can be applied to electronic products in a wide temperature range.

The present invention provides a semiconductor device having a thin film resistor and a method of fabricating the same, which can increase the process window and improve the yield of the semiconductor element without increasing the manufacturing process and process cost.

The present invention provides a semiconductor component having a thin film resistor including a substrate having a first region and a second region. The second zone is provided with at least one gold oxide half field effect transistor. The first region includes a plurality of first conductor structures, a first dielectric layer, a resistive layer, a second dielectric layer, and a plurality of contact windows. The first conductor structure is located on the substrate of the first zone. The first dielectric layer covers the first conductor structure to electrically isolate the first conductor structure. The resistive layer is on the first dielectric layer. The second dielectric layer is on the resistive layer. The contact window extends through at least the second dielectric layer and is electrically connected to the resistive layer.

The present invention provides a thin film resistor comprising at least two first conductor structures, a dielectric layer, a resistive layer, and at least two contact windows. The first conductor structure is on the substrate. The first conductor structure has a first resistance value. The dielectric layer covers the first conductor structure to electrically isolate the first conductor structure. The resistive layer is embedded in the dielectric layer and is not in contact with the first conductor structure. The resistance layer has a second resistance value, and the second resistance value is different from the first resistance value. The contact window penetrates a portion of the dielectric layer and the resistive layer to respectively contact the first conductor structure. One of the contact windows is electrically connected to the other of the contact windows by a resistive layer.

The present invention provides a method of manufacturing a semiconductor device, the steps of which are as follows. A substrate having a first zone and a second zone is provided. A plurality of first conductor structures are formed on the substrate of the first region. Forming a first dielectric layer on the first conductor structure to electrically isolate the first conductor structure. A resistive layer is formed on the first dielectric layer. A second dielectric layer is formed on the resistive layer. A plurality of contact windows are formed through at least the second dielectric layer, wherein the contact windows are electrically connected to the resistive layer, respectively.

The above described features and advantages of the invention will be apparent from the following description.

The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not be repeated.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 1, the semiconductor device 10 of the first embodiment includes a substrate 100 having a first region R1 and a second region R2, wherein the isolation structure 102 is buried in the substrate 100 of the first region R1. In an embodiment, the first region R1 may be, for example, an inactive element region, the inactive element region includes a passive element (eg, a thin film resistor) setting region; and the second region R2 may be, for example, an active device region, The active device region includes a transistor placement region. The substrate 100 may be a semiconductor substrate having a conductivity type, such as an N-type or P-type substrate. The material of the semiconductor substrate is, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. Substrate 100 can also be an undoped epitaxial (Non-EPI) layer, a doped epitaxial layer, a blanket insulating (SOI) substrate, or a combination thereof. The material of the isolation structure 102 can be, for example, doped or undoped cerium oxide, high density plasma oxide, cerium oxynitride or a combination thereof. In an embodiment, the isolation structure 102 can be, for example, a shallow trench isolation structure (STI), a field oxide layer (FOX), or a combination thereof.

In detail, the first region R1 includes a plurality of first conductor structures 104, a first dielectric layer 106, a resistance layer 108b, a second dielectric layer 110, a plurality of contact windows 114a, 114b, and a plurality of second conductor structures 116a. , 116b.

The first conductor structure 104 is located on the substrate 100 of the first region R1. The first conductor structures 104 are disposed apart from each other without being connected to each other. In an embodiment, the material of the first conductor structure 104 may be, for example, a polysilicon. The first conductor structure 104 has a first resistance value between 2 Ω/ and 20 Ω/, wherein is expressed as a unit area.

The first dielectric layer 106 covers the first conductor structure 104 such that the first conductor structures 104 are electrically isolated from one another. In an embodiment, the material of the first dielectric layer 106 may be, for example, tetraethoxysilane (TEOS) cerium oxide, borophosphoquinone glass (BPSG), phosphoric bismuth glass (PSG), hydrogenated sesquioxide. (HSQ), fluorocarbon glass (FSG), undoped bismuth glass (USG), tantalum nitride, bismuth oxynitride, low dielectric materials having a dielectric constant of less than 4, or combinations thereof.

The resistive layer 108b is located on the first dielectric layer 106 and correspondingly covers the first conductor structure 104. In this embodiment, the resistive layer 108b may be, for example, a thin film resistive layer, and the material thereof may be, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), chromium telluride (CrSi), nickel-chromium alloy ( NiCr) or a combination thereof. The resistance layer 108b has a second resistance value ranging from 30 Ω/ to 120 Ω/. However, the present invention is not limited thereto, and the designer can select any resistor value and a lower temperature coefficient of resistance (TCR) material of the resistor layer 108b, so that the thin film resistor of the embodiment can be applied to a wider temperature range. For example, electronic products ranging from -25 ° C to 100 ° C or more, such as power supplies, rechargeable batteries, electronic motor drivers, LED drivers, and the like. In addition, in the embodiment, the thickness of the resistance layer 108b may be between 200 Å and 800 Å. However, the present invention is not limited thereto. In other embodiments, the designer can adjust the resistance value of the thin film resistor by changing the thickness of the resistance layer 108b.

The second dielectric layer 110 is on the resistive layer 108b. The material of the second dielectric layer 110 may be, for example, borophosphoquinone glass (BPSG), tetraethoxy decane (TEOS) cerium oxide, phosphoric silicate glass (PSG), hydrogenated sesquioxide (HSQ), fluorinated glass. (FSG), undoped bismuth glass (USG), tantalum nitride, bismuth oxynitride, low dielectric materials having a dielectric constant of less than 4, or combinations thereof. In an embodiment, the materials of the second dielectric layer 110 and the first dielectric layer 106 may be the same or different, and the invention is not limited thereto.

The contact windows 114a, 114b penetrate the second dielectric layer 110, the resistive layer 108b, and a portion of the first dielectric layer 106, and are in contact with the first conductor structure 104, respectively. It is noted that since the first conductor structures 104 are not connected to each other, the resistance value thereof is greater than the second resistance value of the resistance layer 108b. Therefore, even if the contact windows 114a, 114b are in contact with the first conductor structure 104, the contact window 114a will still be borrowed. The resistor layer 108b is electrically connected to the contact window 114b. In an embodiment, the material of the contact windows 114a, 114b may be, for example, tungsten, titanium, tantalum, aluminum, copper, or alloys thereof.

The second conductor structures 116a, 116b are located on the second dielectric layer 110 to be electrically connected to the contact windows 114a, 114b, respectively. In an embodiment, the material of the second conductor structures 116a, 116b may be, for example, aluminum, copper, or alloys thereof.

On the other hand, the second region R2 is provided with at least one MOS field effect transistor 202. It is noted that the gate structure 204 of the gold oxide half field effect transistor 202 can be formed simultaneously with the first conductor structure 104. Thus, in one embodiment, the gate structure 204 of the gold oxide half field effect transistor 202 and the first conductor structure 104 can be, for example, at the same level. In another embodiment, the material of the gate structure 204 of the gold oxide half field effect transistor 202 may be the same as the material of the first conductor structure 104. For example, in an exemplary embodiment, the first conductor structure 104 may be formed in the first region R1 by the step of forming the gate structure 204 of the gold oxide half field effect transistor 202 in the second region R2. This simplifies process steps and costs. At this time, the material of the gate structure 204 and the first conductor structure 104 may be, for example, polysilicon.

In another exemplary embodiment, the first conductor structure 104 may be formed in the first region R1 by the step of forming a dummy gate of the metal oxide half field effect transistor 202 in the second region R2. This simplifies process steps and costs. The dummy gate can then be replaced by a metal gate structure 204 by a replacement metal gate (RMG) process. Thus, the subsequently formed gold oxide half field effect transistor 202 can include a metal gate structure 204, a spacer 206, and a source/drain region 207 (shown in FIG. 1). In detail, the metal gate structure 204 includes a gate dielectric layer 204a composed of a high dielectric constant material and a gate conductor layer 204b composed of a metal material. The so-called high dielectric constant material can be regarded as a material having a dielectric constant of more than 4, which includes a metal oxide. The metal oxide may be selected from Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, An oxide of at least one of the group consisting of Tm, Yb, and Lu. In an embodiment, the gate conductor layer 204b may be, for example, a single layer structure, and the material thereof may be a low resistivity metal material such as tungsten or aluminum. In another embodiment, the gate conductor layer 204b can be, for example, a multilayer structure (not shown) including a work function layer, a low resistance metal layer, or a combination thereof. The material of the work function layer may be, for example, TiN, TaC, TaCNO, TaCN, TiAl _x , TaN, or a combination thereof. The material of the low-impedance metal layer may be, for example, Ti, TiAl _x , Ti-rich TiN, Al or a combination thereof, where x is any possible value.

The spacers 206 are located on either side of the metal gate structure 204, and the material thereof includes hafnium oxide, tantalum nitride or a combination thereof. Source/drain regions 207 are located in the substrate 100 on either side of the metal gate structure 204. The source/drain regions 207 can be, for example, regions formed by a doping process or an epitaxial process or other suitable process. In addition, the second region R2 further includes a dielectric layer 210 covering the gold oxide half field effect transistor 202. The material of the dielectric layer 210 may be, for example, tetraethoxy decane (TEOS) cerium oxide, borophosphoquinone glass (BPSG), phosphoric bismuth glass (PSG), hydrogenated sesquioxide (HSQ), fluorocarbon glass (FSG). ), undoped bismuth glass (USG), tantalum nitride, bismuth oxynitride, low dielectric materials having a dielectric constant of less than 4, or combinations thereof. In an embodiment, the dielectric layer 210 can be, for example, a one-, two-, or multi-layer structure. For example, when the dielectric layer 210 is a two-layer structure, it can be formed simultaneously with the first dielectric layer 106 and the second dielectric layer 110 in the first region R1.

Since the second region R2 (e.g., the active device region) can be configured with different kinds of transistors, and the manufacturing process thereof is well known to those skilled in the art, it will not be described in detail herein. The manufacturing flow of the first region R1 of FIG. 1 (for example, an inactive component region) will be described in detail below.

2A to 2G are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with a second embodiment of the present invention.

Referring to FIG. 2A, first, an isolation structure 102 is formed in the substrate 100. Next, a plurality of first conductor structures 104 are formed on the substrate 100, wherein the isolation structures 102 are located between the first conductor structures 104 and the substrate 100. The materials of the substrate 100, the isolation structure 102, and the first conductor structure 104 have been described in the above paragraphs and will not be described again. It should be noted that this embodiment can utilize the step of forming a dummy gate of the MOS field-effect transistor 202 of FIG. 1 while forming the first conductor structure 104, thereby simplifying the process steps and costs. The first conductor structure 104 is formed by first forming a first conductive material layer (not shown) on the substrate 100. Next, the first conductive material layer is patterned to simultaneously form the first conductor structure 104 of the first region R1 and the dummy gate (not shown) of the second region R2.

Thereafter, referring to FIG. 2B, a first dielectric layer 106 is formed on the first conductor structure 104. The first dielectric layer 106 covers the surface of the first conductor structure 104 to electrically isolate the first conductor structures 104 that are separated from each other. The material of the first dielectric layer 106 may be, for example, tetraethoxy decane (TEOS) ruthenium oxide, which may be formed, for example, by chemical vapor deposition.

Next, referring to FIG. 2C, a resistive material layer 108 is formed on the first dielectric layer 106. The material of the resistive material layer 108 may be, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), chromium telluride (CrSi), nickel-chromium alloy (NiCr), or a combination thereof, and the forming method thereof may be, for example, Physical vapor deposition (which can be, for example, sputtering) or chemical vapor deposition.

Then, referring to FIG. 2D, the resistive material layer 108 is patterned to expose a portion of the top surface of the first dielectric layer 106, thereby forming the resistive layer 108a. The patterning step is to define a region of the thin film resistor, and the patterning step can be, for example, a lithography process and an etch process.

Referring to FIG. 2E, a second dielectric layer 110 is formed on the substrate 100. The second dielectric layer 110 covers a portion of the top surface of the first dielectric layer 106 and the surface of the resistive layer 108a. The material of the second dielectric layer 110 may be, for example, borophosphon glass (BPSG), and the formation method thereof may be, for example, a chemical vapor deposition method or a spin-on-glass method (SOG).

Thereafter, referring to FIG. 2F, a plurality of contact opening 112a, 112b are formed in the second dielectric layer 110, the resistive layer 108b, and a portion of the first dielectric layer 106. Contact window openings 112a, 112b expose the top surface of first conductor structure 104. In one embodiment, the method of forming the contact opening 112a, 112b includes an anisotropic etch, which may be a dry etch, such as reactive ion etching (RIE).

Referring to FIG. 2F and FIG. 2G simultaneously, contact windows (or conductive plugs) 114a, 114b are formed in the contact opening 112a, 112b. In an implementation, the contact window (or conductive plug) 114a, 114b includes the following steps. A layer of conductive material (not shown) is formed on the substrate 100, and a layer of conductive material is filled into the contact openings 112a, 112b. Thereafter, a planarization process is performed to remove excess conductive material layers to expose the top surface of the second dielectric layer 110. In an embodiment, the planarization process can be, for example, a chemical mechanical polishing (CMP) process, an etch back process, or a combination thereof. In an embodiment, the material of the conductive material layer may be, for example, tungsten, titanium, tantalum, aluminum, copper or an alloy thereof, and the forming method thereof may be, for example, physical vapor deposition or chemical vapor deposition.

Thereafter, second conductor structures 116a, 116b are formed on the contact windows 114a, 114b. In an embodiment, the method of forming the contact windows 114a, 114b includes the following steps. A second conductor material layer (not shown) is formed on the substrate 100. The second layer of conductor material is then patterned using a lithography and etching process. In one embodiment, the material of the second conductor material layer may be, for example, aluminum, copper or an alloy thereof, and the formation method thereof may be, for example, physical vapor deposition or chemical vapor deposition.

It should be noted that the semiconductor device 20 of the second embodiment can utilize the first conductor structure 104 as an etch stop layer when the contact openings 112a, 112b are formed (as shown in FIG. 2F). Therefore, the present invention can avoid the resistance layer. The thickness of 108a is too thin, resulting in the contact window opening not being accurately stopped on the resistance layer 108a, which may damage the surface of the isolation structure 102 or the substrate 100; or, avoiding the subsequent formation of the contact windows 114a, 114b and the resistance layer 108b. The problem of poor electrical connection between the two. Therefore, the first conductor structure 104 of the present invention can be used to increase the process wide range and improve the yield of semiconductor components. On the other hand, the present invention can form the first conductor structure 104 in the first region R1 by the step of forming the dummy gate of the gold oxide half field effect transistor in the second region R2, thereby simplifying the process steps and costs. .

According to the third embodiment and the fourth embodiment of the present invention, the depth of the contact window is different. Figure 3 is a cross-sectional view showing a semiconductor device in accordance with a third embodiment of the present invention. Figure 4 is a cross-sectional view showing a semiconductor device in accordance with a fourth embodiment of the present invention.

Referring first to FIG. 3, the semiconductor device 30 of the third embodiment is substantially similar to the semiconductor device 20 of the second embodiment, and the difference is that the contact windows 214a, 214b of the semiconductor device 30 of the third embodiment are only penetrated. The second dielectric layer 110 is in contact with the resistive layer 208, respectively. The contact windows 214a, 214b are formed by first forming a plurality of contact openings 212a, 212b in the second dielectric layer 110 to expose the top surface of the resistive layer 208. Next, a layer of conductive material (not shown) is formed on the substrate 100 and filled into the contact openings 212a, 212b. Thereafter, a planarization process is performed to remove excess conductive material layers to expose the top surface of the second dielectric layer 110.

Referring first to FIG. 4, the semiconductor device 40 of the fourth embodiment is substantially similar to the semiconductor device 20 of the second embodiment, and the difference is that the contact windows 314a, 314b of the semiconductor device 40 of the fourth embodiment are only penetrated. The second dielectric layer 110 and the resistive layer 308, and some portions extend into the first dielectric layer 106 and are in contact with the resistive layer 308, respectively. The contact windows 314a, 314b are formed by first forming a plurality of contact opening 312a, 312b in the second dielectric layer 110 and the resistive layer 308 to expose the top surface of the resistive layer 308. Next, a layer of conductive material (not shown) is formed on the substrate 100 and filled into the contact openings 312a, 312b. Thereafter, a planarization process is performed to remove excess conductive material layers to expose the top surface of the second dielectric layer 110. Although the bottom surfaces of the contact windows 314a, 314b shown in FIG. 4 are slightly lower than the bottom surface of the resistance layer 308, the invention is not limited thereto. In other embodiments, the bottom surfaces of the contact windows 314a, 314b and the bottom surface of the resistive layer 308 can be substantially coplanar.

In summary, in an embodiment, the first conductor structure can be utilized as an etch stop layer for forming a contact opening, which can avoid damage to the isolation structure or substrate surface underneath due to the thickness of the resistance layer being too thin. The problem. Therefore, the first conductor structure of the present embodiment can be used to increase the process wide range and improve the yield of the semiconductor element. In addition, in one embodiment, the first conductor structure can be formed in the first region by the step of forming a dummy gate of the metal oxide half field effect transistor in the second region, thereby simplifying the process steps and costs.

In addition, the thin film resistor of an embodiment can be formed not only in combination with a thin film, lithography, and etching of a semiconductor process, but also has a low temperature coefficient of resistance (TCR). In other words, the thin film resistor of an embodiment can be applied to an electronic product in a wide temperature range (which can be, for example, between -25 ° C and 100 ° C or more), such as a power supply, a rechargeable battery, Electronic motor driver, LED driver, etc.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10, 20, 30, 40‧‧‧ semiconductor components
100‧‧‧Base
102‧‧‧Isolation structure
104‧‧‧First conductor structure
106‧‧‧First dielectric layer
108‧‧‧Resistive material layer
108a, 108b, 208, 308‧‧‧ resistance layer
110‧‧‧Second dielectric layer
112a, 112b, 212a, 212b, 312a, 312b‧‧‧ contact window opening
114a, 114b, 214a, 214b, 314a, 314b‧‧‧ contact windows
116a, 116b, 216a, 216b, 316a, 316b‧‧‧ second conductor structure
202‧‧‧Gold oxygen half-field effect transistor
204‧‧‧Metal gate structure
204a‧‧‧gate dielectric layer
204b‧‧‧ gate conductor layer
206‧‧‧ spacer
207‧‧‧Source/Bungee Area
210‧‧‧Dielectric layer
R1‧‧‧ first district
R2‧‧‧Second District

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a semiconductor device in accordance with a first embodiment of the present invention. 2A to 2G are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with a second embodiment of the present invention. Figure 3 is a cross-sectional view showing a semiconductor device in accordance with a third embodiment of the present invention. Figure 4 is a cross-sectional view showing a semiconductor device in accordance with a fourth embodiment of the present invention.

10‧‧‧Semiconductor components

100‧‧‧Base

102‧‧‧Isolation structure

104‧‧‧First conductor structure

106‧‧‧First dielectric layer

108b‧‧‧resistance layer

110‧‧‧Second dielectric layer

114a, 114b‧‧‧Contact window

116a, 116b‧‧‧second conductor structure

202‧‧‧Gold oxygen half-field effect transistor

204‧‧‧Metal gate structure

204a‧‧‧gate dielectric layer

204b‧‧‧ gate conductor layer

206‧‧‧ spacer

207‧‧‧Source/Bungee Area

210‧‧‧Dielectric layer

R1‧‧‧ first district

R2‧‧‧Second District

Claims (12)

A semiconductor device comprising: a substrate having a first region and a second region, the second region being configured with at least one MOS field effect transistor, the first region comprising: a plurality of first conductor structures located at the a first dielectric layer covering the first conductor structures to electrically isolate the first conductor structures; a resistive layer on the first dielectric layer; a second a dielectric layer on the resistive layer; and a plurality of contact windows extending through the second dielectric layer and electrically connected to the resistive layer. The semiconductor device of claim 1, wherein the contact windows further extend through the resistive layer. The semiconductor device of claim 2, wherein the contact windows further extend through the portion of the first dielectric layer to be electrically connected to the first conductor structures, respectively. The semiconductor device of claim 1, further comprising a plurality of second conductor structures on the second dielectric layer for electrically connecting to the contact windows. The semiconductor device according to claim 1, wherein the resistive layer is a thin film resistive layer, and the material of the thin film resistive layer comprises titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), and bismuth. Chromium (CrSi), nickel-chromium alloy (NiCr) or a combination thereof. The semiconductor device of claim 1, wherein the first region is an inactive device region and the second region is an active device region. The semiconductor device of claim 1, wherein the first conductor structures are at the same level as one of the gate structures of the MOS field-effect transistor. The semiconductor device of claim 1, wherein the material of the first conductor structure is the same as the material of one of the gate structures of the MOS field-effect transistor. A thin film resistor comprising: at least two first conductor structures on a substrate, the first conductor structures having a first resistance value; a dielectric layer covering the first conductor structures to electrically isolate The first conductor structure; a resistive layer embedded in the dielectric layer and not in contact with the first conductor structures, wherein the resistive layer has a second resistance value, and the second resistance value and the first The resistance values are different; and at least two contact windows penetrate the portion of the dielectric layer and the resistance layer to respectively contact the first conductor structures, wherein one of the contact windows and the contact windows Another electrical connection. A method of fabricating a semiconductor device, comprising: providing a substrate having a first region and a second region; forming a plurality of first conductor structures on the substrate of the first region; forming a first dielectric layer thereon The first conductor structure electrically isolates the first conductor structures; forms a resistive layer on the first dielectric layer; forms a second dielectric layer on the resistive layer; and forms at least a plurality of contact windows of the two dielectric layers, wherein the contact windows are electrically connected to the resistance layer respectively. The method of manufacturing the semiconductor device of claim 10, wherein the forming the contact windows comprises: forming a plurality of contact openings in the second dielectric layer to expose a top surface of the resistive layer; And filling a plurality of conductive plugs into the contact window openings respectively to form the contact windows penetrating the second dielectric layer. The method for fabricating a semiconductor device according to claim 10, further comprising forming a MOS field effect transistor on the second region, wherein the gate structure of the MOS field effect transistor and the first A conductor structure is formed simultaneously.