TW201727758A - A semiconductor device and a method for fabricating the same - Google Patents

Abstract

A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.

Description

Semiconductor device and method of manufacturing same

The present disclosure relates to a method of fabricating a semiconductor device, and more particularly to a structure in which a conductive layer is located on a gate and a source/drain region and a method of fabricating the same.

As the semiconductor industry introduces high-performance and high-performance new generation integrated circuits (ICs), the industry has begun to set up multi-layer wiring structures on electronic devices such as transistors. In order to meet the needs of high speed and high reliability, advanced metal wire structures and their formation methods must be developed.

The present disclosure includes a semiconductor device including a fin field effect transistor. The semiconductor device includes: a first gate electrode; a first source/drain region disposed adjacent to the first gate electrode; and a first source/drain contact disposed on the first source/drain region; a spacer layer disposed between the first gate electrode and the first source/drain region; the first contact layer contacting the first gate electrode and the first source/drain contact; the first circuit layer, Formed integrally with the first contact layer; wherein there is no interface between the first contact layer and the first circuit layer in a cross-sectional view, and the first contact layer has a smaller area than the first circuit layer in plan view.

The disclosure also includes a semiconductor device including a fin field effect transistor. The semiconductor device includes: a first gate electrode; a first gate contact layer disposed over the first gate electrode; and a first source/drain region disposed adjacent to the first gate electrode; the first source/ a drain contact is disposed on the first source/drain region; a first spacer layer is disposed between the first gate electrode and the first source/drain region; and the first contact layer contacts the first gate a pole contact and a first source/drain contact; and a first circuit layer integrally formed with the first contact layer; wherein, in the cross-sectional view, there is no interface between the first contact layer and the first circuit layer, and in a top view The first contact layer has a smaller area than the first circuit layer.

The present disclosure also includes a method of fabricating a semiconductor device including a fin field effect transistor. The method includes: forming a gate structure on the fin structure, the gate structure comprises a gate electrode layer and an insulating cap layer; forming a source/drain contact layer on the source/drain structure; forming an interlayer dielectric layer; Forming a first contact layer and a first circuit layer by a damascene technique; wherein the contact layer is electrically connected to the gate electrode layer and the source/drain contact layer and overlaps the gate electrode in a top view and Source/drain contact layer.

3‧‧‧Isolation insulation

5‧‧‧Fin structure

10‧‧‧Metal gate structure

12‧‧‧ gate dielectric layer

14‧‧‧Work function adjustment layer

16‧‧‧Metal material layer

20‧‧‧Insulation cover

25‧‧ ‧ gate opening

30‧‧‧ sidewall spacers

40‧‧‧First interlayer dielectric layer

45‧‧‧ openings

50‧‧‧Source/bungee area

55‧‧‧ Telluride layer

60, 66, 66S‧‧‧ source/drain contact

65‧‧‧ gate contact

67‧‧‧gate conductive plug

70‧‧‧Second interlayer dielectric layer

72‧‧‧Contact etch stop layer

73, 73S, 73G, 75, 75S, 75G, 77, 77S, 77G, 78, 78S, 78G‧‧‧ contact openings

80, 80S, 80G, 82, 82S, 82G, 83, 83S, 83G‧‧‧ contact layer

85, 85S, 85G, 87, 87S, 87G, 88, 88S, 88G‧‧‧ circuit layer

90‧‧‧ Third interlayer dielectric layer

92‧‧‧Second contact etch stop layer

300‧‧‧Substrate

310‧‧‧Fin structure

315‧‧‧Channel area

320‧‧‧Isolation insulation

330‧‧‧Metal gate structure

340‧‧‧Insulation cover

350‧‧‧ sidewall spacers

360‧‧‧Source/Bungee Area

370‧‧‧Interlayer dielectric layer

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly represent the features of the present disclosure.

In accordance with an embodiment of the present disclosure, FIG. 1A illustrates an exemplary top view (viewed from above) for illustrating one of the various steps of a sequential semiconductor device fabrication process. Figure 1B along the line in Figure 1A X1-X1 shows an exemplary cross-sectional view. Figure 1C is an enlarged view of the gate structure. In accordance with an embodiment of the present disclosure, FIG. 1D illustrates an exemplary perspective view for explaining one of the various steps of a semiconductor device manufacturing process.

In accordance with an embodiment of the present disclosure, FIGS. 2-5, 6A-6B illustrate an exemplary cross-sectional view corresponding to line segment X1-X1 of FIG. 1A for illustrating various steps in a semiconductor device manufacturing process.

In accordance with another embodiment of the present disclosure, FIGS. 7-10, 11A-11B illustrate an exemplary cross-sectional view.

In accordance with another embodiment of the present disclosure, FIGS. 12-17, 18A-18B illustrate an exemplary cross-sectional view.

The various features of the present disclosure are disclosed in the following, and various embodiments of the present invention are described. The embodiments are for illustrative purposes only, and are not intended to limit the scope of the disclosure. For example, the dimensions of the components are not limited to the disclosed ranges or values, but may be adjusted depending on process conditions and/or expected device properties. Furthermore, it is mentioned in the specification that the first feature is formed on the second feature, which includes an embodiment in which the first feature is in direct contact with the second feature, and additionally includes another feature between the first feature and the second feature. An embodiment of the feature, that is, the first feature is not in direct contact with the second feature. In addition, different features may be arbitrarily drawn in different sizes for simplicity and clarity.

In addition, space-related terms such as "below," "below," "lower," "above," "higher," and similar terms may be used. Word system for easy description of one of the illustrations The relationship between a component or feature and another component or feature, such spatially related terms, includes the different orientations of the device in use or operation, and the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientation), the spatially related adjectives used therein will also be interpreted in terms of the orientation after the turn. Further, "formed by" may mean "including..." or "consisting of."

In accordance with an embodiment of the present disclosure, FIGS. 1A and 1B illustrate one of the steps of a sequential semiconductor device fabrication process. FIG. 1A depicts a top view (or top view), and FIG. 1B shows a cross-sectional view along line X1-X1 of FIG. 1A.

FIGS. 1A and 1B illustrate the structure of a semiconductor device after forming a metal gate structure. In FIGS. 1A and 1B, a metal gate structure 10 is formed over the channel layer (eg, a portion of the fin structure 5), and an insulating cap layer 20 is disposed over the metal gate structure 10. The fin structure 5 is disposed on the substrate 1 and protrudes from the isolation insulating layer 3. In the second and subsequent figures, the substrate 1 and the isolation insulating layer 3 will be omitted. In some embodiments, the metal gate structure 10 has a thickness of 15 nm to 50 nm. In some embodiments, the insulating cap layer 20 has a thickness of 10 nm to 30 nm, and in other embodiments, 15 nm to 20 nm. Sidewall spacers 30 are provided on the sidewalls of the metal gate structure 10 and the insulating cap layer 20. In some embodiments, the sidewall spacer 30 has a film thickness of 3 nm to 15 nm at its bottom and 4 nm to 10 nm in other embodiments. The combination of the metal gate structure 10, the insulating cap layer 20, and the sidewall spacers 30 may be collectively referred to as a gate structure. In addition, the source/drain region 50 is formed adjacent to the gate structure, and a space between the gate structures is filled in a first interlayer dielectric layer (ILD) 40. A vaporized layer 55 is further formed on the source/drain region 50. In the present disclosure, the source and the drain are interchangeable in use, and There is no substantial difference in the structure of the two. The term "source/bungee" refers to one of the source and the bungee.

The telluride layer 55 includes one or more components of cobalt telluride, titanium telluride, nickel telluride, copper telluride, tungsten telluride, and molybdenum telluride.

Figure 1C is an enlarged view of the gate structure. The metal gate structure 10 includes one or more layers of metal material 16, such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, and other conductive materials. The gate dielectric layer 12 disposed between the channel layer 5 and the metal gate includes one or more layers of a metal oxide (eg, a high dielectric constant metal oxide). For example, metal oxides for high-k dielectric materials include Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, An oxide of Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and/or combinations thereof.

In some embodiments, one or more work function adjustment layers 14 are interposed between the gate dielectric layer 12 and the metal material 16. The work function adjusting layer 14 is formed of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a plurality of two or more of the above materials. Layer (multilayer). In the case of an n-channel fin field effect transistor, one or more components of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi may be used as a work function adjustment layer to p-channel fin field effect electric For the crystal, one or more components of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co may be used as the work function adjusting layer.

The insulating cap layer 20 includes one or more layers of insulating material (eg, a material based on tantalum nitride, including SiN, SiCN, and SiOCN). The sidewall spacers 30 are formed of a material different from the insulating cap layer 20 and include one or more layers of insulation. Materials (eg, materials based on tantalum nitride, including SiN, SiON, SiCN, and SiOCN). The sidewall spacers 30 may be formed of the same material as the insulating cap layer 20. The first interlayer dielectric layer 40 includes one or more layers of yttrium oxide, SiOC, SiOCN or SiCN or other low dielectric constant material, or a porous material. The first interlayer dielectric layer 40 may be formed by low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (plasma-CVD) or other suitable thin film formation methods.

In some embodiments, the material of the sidewall spacers 30, the material of the insulating cap layer 20, and the material of the first interlayer dielectric layer 40 are different from each other, so that the respective film layers can be selectively etched. In one embodiment, sidewall spacers 30 are formed with SiOCN, SiCN or SiON, insulating cap layer 20 is formed with SiN, and first interlayer dielectric layer 40 is formed with SiO ₂ . In some other embodiments, at least two of the sidewall spacers 30, the insulating cap layer 20, and the first interlayer dielectric layer 40 are formed of the same material.

In this embodiment, a fin field effect transistor fabricated by a gate replacement process is used.

FIG. 1D depicts an exemplary perspective view of a fin field effect transistor structure. The fin field effect transistor structure described above can be fabricated by the following steps.

First, a fin structure 310 is formed over the substrate 300. The above fin structure includes a bottom region and an upper region as the channel region 315. For example, the substrate is a p-type germanium substrate having an impurity concentration of about 1*10 ¹⁵ cm ^-3 to 1*10 ¹⁸ cm ^-3 . In other embodiments, the substrate is an n-type germanium substrate having an impurity concentration of about 1*10 ¹⁵ cm ^-3 to 1*10 ¹⁸ cm ^-3 . Alternatively, the substrate may include other elemental semiconductors (eg, germanium), compound semiconductors, including group IV-IV compound semiconductors (eg, SiC and SiGe), and III-V compound semiconductors (eg, GaAs, GaP). GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP), or a combination thereof. In one embodiment, the substrate is a germanium film layer of a silicon-on-insulator (SOI) substrate.

After the fin structure 310 is formed, an isolation insulating layer 320 is formed over the fin structure 310. The isolation insulating layer 320 includes one or more layers of insulating materials, such as yttrium oxide and nitrogen oxide formed by low pressure chemical vapor deposition, plasma chemical vapor deposition or flowable CVD. Tantalum or tantalum nitride. The above-mentioned isolating insulating layer may be formed by one or more layers of spin-on-glass (SOG), SiO, SiON, SiOCN, and/or fluorine-doped silicate glass (FSG).

After the isolation insulating layer 320 is formed on the fin structure 310, a planarization step is performed to remove a portion of the isolation insulating layer 320. The planarization step described above may include a chemical mechanical polishing (CMP) and/or an etch-back step. Next, the isolation insulating layer 320 is further removed (or recessed) to expose the upper portion of the fin structure.

A dummy gate structure is formed on the exposed fin structure. The dummy gate structure includes a dummy gate electrode formed of polysilicon and a dummy gate dielectric layer. Sidewall spacers 350 comprising one or more layers of insulating material are also formed on the sidewalls of the dummy gate electrode layer. After the dummy gate structure is formed, the fin structure not covered by the dummy gate structure is recessed to be lower than the upper surface of the isolation insulating layer 320. Next, a source/drain region 360 is formed over the recessed fin structure by epitaxial growth. The source/drain regions may include strained materials that stress the channel region 315 (strain material).

Next, an interlayer dielectric layer 370 is formed over the dummy gate structure and the source/drain regions. The interlayer dielectric layer 370 includes one or more layers of yttrium oxide, SiOC, SiOCN or SiCN or other low dielectric constant material, or a porous material. After a planarization step, the dummy gate structure is removed to form a gate space. Then, a metal gate structure 330 including a metal gate electrode and a gate dielectric layer (eg, a high-k dielectric material layer) is formed in the gate space. In addition, an insulating cap layer 340 is formed over the metal gate structure 330 to form a fin field effect transistor structure as shown in FIG. 1D. In FIG. 1D, a portion of the metal gate structure 330, the insulating cap layer 340, the sidewall spacers 350, and the interlayer dielectric layer 370 are slit to present the underlying structure.

The metal gate structure 330, the insulating cap layer 340, the sidewall spacers 350, the source/drain electrodes 360, and the interlayer dielectric layer 370 in FIG. 1D substantially correspond to the metal gate structures 10 in FIGS. 1A and 1B, respectively. The insulating cap layer 20, the sidewall spacers 30, the source/drain regions 50, and the first interlayer dielectric layer 40.

In accordance with an embodiment of the present disclosure, FIGS. 2-6B exemplarily illustrate cross-sectional views corresponding to line segments X1-X1 of FIG. 1A for explaining various steps in a manufacturing process of a semiconductor device. It should be understood that additional steps may be provided before, during, and after the processes illustrated in Figures 2-6B, and in other embodiments of the above methods, some of the following steps may be replaced or removed. . The order of the steps/processes can be exchanged.

As shown in FIG. 2, the first interlayer dielectric layer 40 on the source/drain regions is etched by a photolithography process and a dry etching process to form openings 45. In FIG. 2, the first interlayer dielectric layer 40 remains on the wall of the opening 45. In some embodiments The first interlayer dielectric layer 40 on the source/drain region is completely removed. In some embodiments, an additional interlayer dielectric layer is formed over the first interlayer dielectric layer 40, and then an opening 45 is formed.

Next, as shown in FIG. 3, a source/drain contact 60 is formed in the opening 45 to contact the vaporized layer 55 of the source/drain region. After the opening 45 is formed, a blanket layer of a conductive material is formed over the structure of FIG. The above conductive material layer comprises one or more layers of conductive materials such as Co, W, Ni, Mo or Cu. In an embodiment, tungsten (W) is used. The above-described conductive material layer may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD, including sputtering), atomic layer deposition (ALD), electroplating, or a combination thereof, or other suitable film formation methods.

In some embodiments, an adhesive layer is formed prior to forming a layer of conductive material. The adhesion layer comprises one or more layers of electrically conductive materials such as TiN and Ti. The adhesion layer can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or a combination thereof, or other suitable film formation methods. The adhesion layer is used to prevent the conductive material from falling off.

After forming a "thick" layer of conductive material, a planarization step such as chemical mechanical polishing (CMP) or etch back is performed to remove the layer of conductive material deposited on the upper surface of the first interlayer dielectric layer 40 to form The source/drain contacts 60 shown in Figure 3.

After the source/drain contact 60 is formed, a second interlayer dielectric layer 70 is formed over the structure of FIG. The material and formation method of the second interlayer dielectric layer 70 is similar to that of the first interlayer dielectric layer 40. In some embodiments, a contact etch stop layer 72 (referred to as CESL, for example, SiN, SiC or SiCN) is formed on the first interlayer dielectric layer 40 and the second interlayer dielectric layer. Between 70.

Next, a contact layer and a wiring layer are formed by a damascene technique. The above mosaic technology can be a single damascene technique or a dual damascene technique. As shown in FIG. 5, contact openings 73, 73G and 73S are formed in the first and second interlayer dielectric layers and the insulating cap layer to at least partially expose the source/drain contact 60 and the metal of the gate structure. The upper surface of the gate 10. A contact opening 73 is formed to expose the source/drain contact 60 and the metal gate 10, and a contact opening 73S is formed to expose the upper surface of the source/drain contact 60 to form a contact opening 73G to expose the upper surface of the metal gate 10.

As shown in Fig. 5, the contact openings 73, 73G, and 73S are each included as an upper portion of the wiring layer and as a lower portion of the contact layer. In some embodiments, the upper portion is formed in the second interlayer dielectric layer 70 by a photolithography step and a dry etching step, and then the lower portion is formed by a photolithography step and a dry etching step.

After forming the contact openings 73, 73G and 73S, a thick second conductive material layer is formed on the structure of FIG. 5, and a planarization step such as chemical mechanical polishing is performed to form as shown in FIGS. 6A and 6B. The structure. Fig. 6B is a plan view, and Fig. 6A corresponds to a line segment X1-X1 of Fig. 6B.

The second conductive material layer comprises one or more conductive materials formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition or electroplating or other suitable methods, such as TiN, Ti, Cu, Al, W or alloys thereof. Or other suitable materials.

The contact layer 80 and the wiring layer 85 are formed by filling the contact opening 73 with a second conductive material, and the contact layer 80 and the wiring layer 85 constitute an integrally formed structure. (integrally formed structure).

The contact layer 80 contacts the metal gate 10 and the source/drain contacts 60 to electrically connect the metal gate 10 and the source/drain regions 50. The contact opening 80G is filled with the second conductive material to form the contact layer 80G and the wiring layer 85G. The contact layer 80G contacts the metal gate 10. The contact opening 80S is filled with the second conductive material to form the contact layer 80S and the wiring layer 85S. Contact layer 80S contacts source/drain contact 60.

As shown in FIG. 6B, the contact layer 80 and the wiring layer 85 overlap the fin structure 5. The contact layer 80S and the wiring layer 85S also overlap the fin structure 5, but the contact layer 80G and the wiring layer 85G do not overlap the fin structure 5.

In the cross-sectional view, there is no interface or boundary between the contact layer 80, 80G or 80S and the circuit layer 85, 85G or 85S. Further, in plan view, the areas of the contact layers 80, 80G or 80S are each smaller than the wiring layers 85, 85G or 85S.

In accordance with another embodiment of the present disclosure, FIGS. 7-11B exemplarily illustrate a cross-sectional view corresponding to line segment X1-X1 of FIG. 1A for explaining various steps in a manufacturing process of a semiconductor device. It should be understood that additional steps may be provided before, during, and after the processes illustrated in Figures 7-11B, and in other embodiments of the above methods, some of the following steps may be replaced or removed. . The order of the steps/processes can be exchanged. In the following embodiments, configurations, structures, materials, processes, and/or steps similar or identical to those of the foregoing embodiments detailed in FIGS. 2-6B may be used, and thus detailed description thereof may be omitted.

After the structure of Fig. 3 is formed, the insulating cap layer 20 is removed to form the gate space 25 as shown in Fig. 7. In Fig. 7, the insulating cap layer 20 is completely removed to expose the metal gate 10. In other embodiments, a portion of the insulating cover is removed Layer 20 exposes metal gate 10 such that insulating cap layer 20 remains on the walls of gate opening 25. In some embodiments, an additional interlayer dielectric layer is formed over the first interlayer dielectric layer 40, and a gate opening 25 is formed through the additional interlayer dielectric layer.

After forming the gate opening 25, as shown in Fig. 8, a gate contact 65 is formed over the exposed metal gate 10. A blanket layer of conductive material is formed over the structure of Figure 7. The above conductive material layer comprises one or more layers of conductive materials such as Co, W, Ni, Mo or Cu. In an embodiment, tungsten (W) is used. The conductive material layer described above may be formed by chemical vapor deposition, physical vapor deposition (including sputtering), atomic layer deposition, electroplating, or a combination thereof, or other suitable film formation methods.

In some embodiments, an adhesive layer is formed prior to forming a layer of conductive material. The adhesion layer comprises one or more layers of electrically conductive materials such as TiN and Ti. The adhesion layer can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or a combination thereof, or other suitable film formation methods. The adhesion layer is used to prevent the conductive material from falling off.

After forming a "thick" layer of conductive material, a planarization step such as chemical mechanical polishing (CMP) or etch back is performed to remove the layer of conductive material deposited on the upper surface of the first interlayer dielectric layer 40 to form The gate contact shown in Figure 8 is 65.

Similar to FIG. 4, after the gate contact 65 is formed, as shown in FIG. 9, a second interlayer dielectric layer 70 and a contact etch stop layer 72 are formed.

Next, similar to FIG. 5, as shown in FIG. 10, contact openings 75, 75G, and 75S are formed in the second interlayer dielectric layer to at least partially expose the gate. The pole contact 65 and the source/drain contact 60. A contact opening 75 is formed to expose the source/drain contact 60 and the gate contact 65, forming a contact opening 75S to expose the upper surface of the source/drain contact 60, forming a contact opening 75G to expose the upper surface of the gate contact 65.

Similar to FIGS. 6A and 6B, after forming the contact openings 75, 75G, and 75S, a thick second conductive material layer is formed over the structure of FIG. 10, and a planarization step such as chemical mechanical polishing is performed to form The structure shown in Figures 11A and 11B. Fig. 11B is a plan view, and Fig. 11A corresponds to the line segment X1-X1 in Fig. 11B.

The contact opening 82 and the wiring layer 87 are formed by filling the contact opening 75 with a second conductive material. The contact layer 82 contacts the gate contact 65 and the source/drain contact 60 to electrically connect the metal gate 10 and the source/drain regions 50. The contact opening 75G is filled with the second conductive material to form the contact layer 82G and the wiring layer 87G. Contact layer 82G contacts gate contact 65. The contact opening 82S is filled with the second conductive material to form the contact layer 82S and the wiring layer 87S. Contact layer 82S contacts source/drain contact 60.

As shown in FIG. 11B, the contact layer 82 and the wiring layer 87 do not overlap the fin structure 5. The contact layer 82S and the wiring layer 87S overlap the fin structure 5, but the contact layer 82G and the wiring layer 87G do not overlap the fin structure 5.

In the cross-sectional view, there is no interface or boundary between the contact layer 82, 82G or 82S and the circuit layer 87, 87G or 87S. Further, in plan view, the areas of the contact layers 82, 82G or 82S are each smaller than the wiring layers 87, 87G or 87S. As shown in FIG. 11A, the bottoms of the contact layers 82, 82G, and 82S are located on substantially the same plane, wherein the height difference of the bottom portion is within about 2 nm.

According to another embodiment of the present disclosure, FIGS. 12-18B exemplarily illustrate a cross-sectional view corresponding to the line segment X1-X1 in FIG. 1A for illustrating a continuation of the semi-guide. The various steps in the body device manufacturing process. It should be understood that additional steps may be provided before, during, and after the processes illustrated in Figures 12-18B, and in other embodiments of the above methods, some of the following steps may be replaced or removed. . The order of the steps/processes can be exchanged. In the following embodiments, configurations, structures, materials, processes, and/or steps similar or equivalent to those of the foregoing embodiments described in detail in FIGS. 2-6B may be used, and thus detailed description thereof may be omitted.

After the structure of FIG. 3 is formed, as shown in FIG. 12, the second interlayer dielectric layer 70 and the contact etch stop layer 72 are formed.

Next, as shown in FIG. 13, the second interlayer dielectric layer 70, the contact etch stop layer 72, and the first interlayer dielectric layer 40 are etched on the source/drain regions to form contact openings 77 and 77S.

Similar to Fig. 3, as shown in Fig. 14, source/drain contacts 66 and 66S are formed in openings 77 and 77S to contact the germanide layer 55 of the source/drain regions.

After forming the structure of FIG. 14, as shown in FIG. 15, the second interlayer dielectric layer 70, the contact etch stop layer 72, and the insulating cap layer 20 are etched to form the gate contact opening 77G.

Similar to the third or 14th figure, a gate contact plug 67 is formed in the opening 77G to contact the metal gate 10. Further, as shown in Fig. 16, a third interlayer dielectric layer 90 is formed. In some embodiments, a second contact etch stop layer 92 is formed between the second interlayer dielectric layer 70 and the third interlayer dielectric layer 90.

Next, similar to FIG. 5, as shown in FIG. 17, contact openings 78, 78G, and 78S are formed in the first, second, and third interlayer dielectric layers and the insulating cap layer to at least partially expose the source/ Bungee contact 66, and source/drain contact The 66S and the gate contact the upper surface of the plug 67. As shown in FIG. 17, a contact opening 78 is formed to expose the source/drain contact 66 and the metal gate 10, and a contact opening 78S is formed to expose the upper surface of the source/drain contact 66S to form a contact opening 78G. The gate is exposed to contact the upper surface of the plug 67.

After forming the contact openings 78, 78G and 78S, a thick second conductive material layer is formed over the structure of FIG. 17, and a planarization step such as chemical mechanical polishing is performed to form as shown in FIGS. 18A and 18B. The structure. Fig. 18B is a plan view, and Fig. 18A corresponds to a line segment X1-X1 in Fig. 18B.

The contact layer 83 and the wiring layer 88 are formed by filling the contact opening 78 with a second conductive material. The contact layer 83 contacts the metal gate 10 and the source/drain contact 66 to electrically connect the metal gate 10 and the source/drain region 50. The contact opening 83G is filled with the second conductive material to form the contact layer 83G and the wiring layer 88G. The contact layer 83G contacts the gate contact plug 67. The contact opening 83S is filled with the second conductive material to form the contact layer 83S and the wiring layer 88S. Contact layer 83S contacts source/drain contact 66S.

As shown in FIG. 18B, the contact layer 83 and the wiring layer 88 overlap the fin structure 5. The contact layer 83S and the wiring layer 88S also overlap the fin structure 5, but the contact layer 83G and the wiring layer 88G do not overlap the fin structure 5.

In the cross-sectional view, there is no interface or boundary between the contact layer 83, 83G or 83S and the circuit layer 88, 88G or 88S. Further, in plan view, the areas of the contact layers 83, 83G or 83S are each smaller than the wiring layers 88, 88G or 88S. As shown in Fig. 18A, the source/drain contacts 66 and 66S and the upper surface of the gate contact plug 67 are located on substantially the same plane, and the height difference is within about 2 nm.

It should be noted that the structures and manufacturing steps similar to those of Figures 7-11B can be applied to the embodiment of Figures 12-18B. In such a case, the line is formed The layer 87 and the contact layer 82 are in the second and third interlayer dielectric layers, and the contact layer 82 contacts the upper surface of the gate contact layer 65 and the source/drain contact layer 60.

It should be understood that other complementary MOS field-effect transistor processes can be performed on the devices shown in Figures 6A and 6B, 11A and 11B, and 18A and 18B to form various features (eg, interconnect metal layers, Dielectric layer, passivation layer, etc.).

The different embodiments or examples detailed herein have many advantages over the prior art. For example, in the present disclosure, the contact layer formed by the damascene technique is used to directly connect the gate electrode and the source/drain contact layer formed on the source/drain region, thereby improving the flexibility of the line pattern design. .

It should be understood that not all advantages have been described in detail herein. Not all embodiments or examples must share certain advantages. Other embodiments or examples may provide different advantages.

In accordance with one aspect of the present disclosure, a semiconductor device includes a fin field effect transistor. The semiconductor device includes: a first gate electrode; a first source/drain region disposed adjacent to the first gate electrode; and a first source/drain contact disposed on the first source/drain region; a spacer layer disposed between the first gate electrode and the first source/drain region; the first contact layer contacting the first gate electrode and the first source/drain contact; the first circuit layer, Formed integrally with the first contact layer. There is no interface between the first contact layer and the first circuit layer in the cross-sectional view, and the first contact layer has a smaller area than the first circuit layer in plan view.

In accordance with another aspect of the present disclosure, a semiconductor device includes a fin field effect transistor. The semiconductor device includes: a first gate electrode; a first gate contact layer disposed over the first gate electrode; and a first source/drain region disposed adjacent to the first gate electrode; the first source/ Bungee contact, set at the first source / a first spacer layer disposed between the first gate electrode and the first source/drain region; the first contact layer contacting the first gate contact and the first source/drain contact And a first circuit layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first circuit layer in the cross-sectional view, and the first contact layer has a smaller area than the first circuit layer in plan view.

According to still another aspect of the present disclosure, a method of fabricating a semiconductor device including a fin field effect transistor. A gate structure is formed on the fin structure in the above method. The gate structure includes a gate electrode layer and an insulating cap layer. A source/drain contact layer is formed on the source/drain structure. An interlayer dielectric layer is formed. The first contact layer and the first wiring layer are formed by a damascene technique. The contact layer is electrically connected to the gate electrode layer and the source/drain contact layer and overlaps the gate electrode and the source/drain contact layer in a plan view.

The above summary is a summary of the features of the various embodiments, and thus, those of ordinary skill in the art can be understood. Other processes and structures may be designed or modified to achieve the same objectives and/or the same advantages as the embodiments of the present disclosure, without departing from the scope of the present disclosure. It is to be understood by those of ordinary skill in the art that the present invention may be practiced without departing from the spirit and scope of the disclosure.

3‧‧‧Isolation insulation

5‧‧‧Fin structure

10‧‧‧Metal gate structure

20‧‧‧Insulation cover

30‧‧‧ sidewall spacers

40‧‧‧First interlayer dielectric layer

50‧‧‧Source/bungee area

55‧‧‧ Telluride layer

60‧‧‧Source/bungee contact

70‧‧‧Second interlayer dielectric layer

72‧‧‧Contact etch stop layer

80, 80S, 80G‧‧‧ contact layer

85, 85S, 85G‧‧‧ circuit layer

Claims (10)

A semiconductor device comprising a fin field effect transistor, the semiconductor device comprising: a first gate electrode; a first source/drain region disposed adjacent to the first gate electrode; a first source/汲a first contact layer is disposed between the first gate electrode and the first source/drain region; a first contact layer is disposed on the first source/drain region; Contacting the first gate electrode and the first source/drain contact; and a first circuit layer integrally formed with the first contact layer; wherein the first contact layer and the first portion are in a cross-sectional view There is no interface between a circuit layer, and the first contact layer has a smaller area than the first circuit layer in a plan view. The semiconductor device of claim 1, further comprising: a first gate insulating cap layer formed on the gate electrode; wherein a side surface of the first contact layer contacts the first gate Insulating cover. The semiconductor device of claim 2, further comprising: a first source/drain insulating layer formed on the source/drain region; wherein a lower surface of the first contact layer contacts the lower surface The first source/drain insulation layer. The semiconductor device of claim 2, further comprising: a first interlayer dielectric layer disposed on the first insulating cap layer; wherein the first circuit layer is buried in the first layer In an upper portion of the dielectric layer, and the first contact layer passes through a lower portion of the first interlayer dielectric layer and the first gate Insulating cover. The semiconductor device of claim 4, further comprising: a second gate electrode; a gate contact plug disposed on the second gate electrode; and a second contact layer contacting the gate a pole contact plug; and a second circuit layer integrally formed with the second contact layer; wherein, in a cross-sectional view, there is no interface between the second contact layer and the second circuit layer, the second circuit layer Buried in the upper portion of the first interlayer dielectric layer, and the second contact layer passes through the lower portion of the first interlayer dielectric layer and the second gate insulating cap layer. The semiconductor device of claim 5, further comprising: a second source/drain region; a second source/drain contact disposed on the second source/drain region; a third contact layer contacting the second source/drain contact; and a third circuit layer integrally formed with the third contact layer; wherein the third contact layer and the third line are in a cross-sectional view There is no interface between the layers, the third circuit layer is buried in the upper portion of the first interlayer dielectric layer, and the third contact layer passes through the lower portion of the first interlayer dielectric layer. The semiconductor device of claim 6, further comprising: a fin structure; wherein the first contact layer and the third contact layer are disposed on the fin structure in a top view, and the second contact layer The top surface is not disposed on the fin structure, and the first source/drain contact, the second source/drain contact, and the upper surface of the gate contact plug are located on a substantially same plane. on. A method of fabricating a semiconductor device, the semiconductor device comprising a fin field effect transistor, the method comprising: forming a gate structure on a fin structure, the gate structure comprising a gate electrode layer and an insulating cap layer; forming a source/drain contact layer on a source/drain structure; forming an interlayer dielectric layer; and forming a first contact layer and a first circuit layer by a damascene technique; wherein The contact layer is electrically connected to the gate electrode layer and the source/drain contact layer and overlaps the gate electrode and the source/drain contact layer in a plan view. The method of fabricating a semiconductor device according to claim 8, wherein the contact layer contacts the gate electrode and the source/drain contact layer. The method of fabricating a semiconductor device according to claim 8, wherein the step of forming the first contact layer and the first wiring layer comprises etching the interlayer dielectric layer to expose an upper surface of the gate electrode and One of the source/drain contact layers.