TW201717366A - Integrated circuit - Google Patents

Abstract

An integrated circuit is provided. The integrated circuit includes at least one main chip and an input and output interface chip. The main chip has a plurality of pads. The input and output interface chip includes a clock signal generator. The clock signal generator generates at least one clock signal. Wherein, the clock signal generator provides the clock signal to the main chip to be an operation clock signal of the main chip. The main chip is a multi-cell chip. A separation space is existed between any adjacent two of the cells. The plurality of signal transmission line sets respectively configured to perform signal transmission between at least part of adjacent cells. The multi-cell chip is operable and may be cleaved into a plurality of sub-chips by cutting parts of the separation spaces, wherein parts of the plurality of sub-chips may still be operable.

Description

Integrated circuit

The present invention relates to an integrated circuit, and more particularly to an integrated integrated circuit.

As the demand for electronic products increases, so does the demand for computing power in microcontrollers in electronic products. In the conventional art, microcontrollers, memories, input and output interface circuits, and other analog circuits (such as voltage generators, clock generators) are commonly integrated in a single wafer.

Under the above premise, if a high-order process is used to design the integrated circuit of the microcontroller, although the circuit area of the digital circuit portion can be reduced, in order to provide a conformable electrical characteristic (such as a drive) in the design of the analog circuit. Current, withstand voltage, etc.) often require a larger circuit area. And it causes a waste of costs. In addition, regarding the electrostatic discharge protection circuit, the integrated circuit produced by the high-order process must be able to provide a sufficiently large electrostatic discharge protection capability, and the required circuit area is also large, which also greatly increases the cost. That is to say, in the conventional technical field, it is an important and difficult subject to balance the performance and cost of the microcontroller.

The invention provides an integrated circuit, which can effectively reduce the production cost.

The integrated circuit of the present invention includes at least one main wafer and an input/output interface wafer. The main wafer has a plurality of pads. The input and output interface chip includes a clock signal generator and is used to generate at least one clock signal. The clock signal generator of the input/output interface chip provides a clock signal to the main wafer to serve as a working clock signal of the main wafer. The above main wafer is a polycrystalline wafer. Wherein, the poly unit cell wafer comprises a semiconductor substrate, a plurality of unit cells and a plurality of signal transmission line groups. The unit cells are arranged on the semiconductor substrate, and each unit cell has at least one space between the adjacent unit cells. Each signal transmission line group is disposed in a space between adjacent cells and is used for signal transmission between at least some of the adjacent cells. Wherein the poly unit cell wafer is usable, and the poly unit cell wafer is cut through a portion of the space to cut off part of the signal transmission line group, so that the poly unit cell wafer is divided into a plurality of sub-wafers, wherein at least a portion after cutting The sub-wafer can still be used.

In an embodiment of the invention, the input/output interface chip further includes a voltage generator. The voltage generator is coupled to the main wafer, generates at least one power supply voltage, and supplies a power supply voltage to the main wafer to operate as an operating power source for the main wafer.

In an embodiment of the invention, the input/output interface chip further includes a plurality of connection pads. The connection pads are respectively coupled to the pads on the main wafer.

In an embodiment of the invention, the input/output interface chip further includes at least one peripheral circuit and an external package interface circuit. The peripheral circuit is coupled to the voltage generator and the clock signal generator. The package outer connection interface circuit is for connecting to an external electronic device outside the semiconductor device.

In an embodiment of the invention, the integrated circuit further includes a package carrier, wherein the main chip and the input/output interface chip are disposed on the package carrier.

In an embodiment of the invention, the integrated circuit further includes a plurality of inner leads and a plurality of outer pins. The inner leads are disposed on the package carrier and the pads are coupled to the input and output interface chips. The external pin is coupled to the external connection interface circuit of the package. The external pins are used to connect to external electronic devices.

In an embodiment of the invention, the package carrier is provided with a plurality of solder pads and a plurality of electrostatic discharge protection circuits respectively corresponding to the pads, wherein the external pins are respectively coupled to the pads on the package carrier.

In an embodiment of the invention, the main wafer is disposed on the input/output interface chip and partially covers the input/output interface chip.

In an embodiment of the invention, the input/output interface chip is coupled to the pad through a plurality of conductive bumps, and the input/output interface chip is coupled to the external electronic device through a plurality of external pins.

In one embodiment of the invention, the process level for fabricating the master wafer described above is higher than the process level for fabricating the input and output interface wafers described above.

Based on the above, the present invention integrates at least one main wafer and an input/output interface chip into an integrated circuit. The input/output interface chip is used to generate a clock signal and provide a clock signal to the main chip as a working clock signal of the main chip. Therefore, it is not necessary to provide a related circuit for generating a working clock signal in the main chip, and an appropriate high-order process can be selected without being limited to the relevant circuit that generates the working clock signal. In addition, the I/O interface chip can select a process different from the main die for consideration of the clock signal generator and the peripheral interface function to be performed. In this way, each of the wafers in the integrated circuit is fabricated using an optimally selected process, and the production cost is minimized without affecting the performance of the integrated circuit.

The above described features and advantages of the invention will be apparent from the following description.

DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to the exemplary embodiments embodiments In addition, wherever possible, the same reference numerals in the drawings

Please refer to FIG. 1. FIG. 1 is a schematic diagram of an integrated circuit according to an embodiment of the present invention. The integrated circuit 100 includes a main wafer 110 and an input and output interface wafer 120. The input/output interface chip 120 is coupled to the main chip 110 and serves as an input/output interface of the main chip 110 and an external electronic device (not shown) outside the integrated circuit 100. The main wafer 110 and the input/output interface chip 120 belong to different wafers. In an embodiment of the invention, the wafer 110 and the input/output interface wafer 120 are respectively fabricated by using two different processes. The main wafer 110 is a polycrystalline wafer, and the details of the implementation of the polycrystalline wafer will be described in detail in the following embodiments.

The input and output interface chip 120 includes a clock signal generator 121. The clock signal generator 121 is used to generate the clock signal CK and supply the clock signal CK to the main wafer 110 as the working clock signal of the main wafer 110. It is worth mentioning that the clock signal required in the main chip 110 can be generated according to the clock signal CK. The main wafer 110 does not need to be provided with associated circuitry that independently generates a clock signal.

In other embodiments of the present invention, when the main wafer 110 requires operating pulse signals of different frequencies, the clock signal generator 121 can provide a plurality of different frequency clock signals CK to the main wafer 110 as the working time of the main wafer 110. Pulse signal.

In another aspect, the input and output interface die 120 can have an off-package interface OPI. The input/output interface chip 120 can be connected to an external electronic device outside the integrated circuit 100 through the package external interface OPI, and can perform signal transmission with the connected external electronic device through the external connection interface OPI.

Based on the above, the signal transmission operation between the main wafer 110 and the external electronic device is performed through the input/output interface wafer 120. Therefore, the main wafer 110 is not designed to be designed in accordance with the electrical characteristics of the external electronic device. Specifically, in this embodiment, the signal output end of the main wafer 110 may not need to provide a large output voltage and output current to communicate with an external electronic device, and a higher order process may be used to perform the main wafer 110. Manufacturing. In addition, the input and output interface chip 120 is used to provide signals of suitable electrical characteristics for signal transmission with external electronic devices. Thus, the input and output interface die 120 can be fabricated using a lower order process.

Peripheral circuits, such as the clock signal generator 121 and/or various analog circuits, which are more suitable for fabrication using a low-order process, may be disposed in the input-output interface chip 120. The main wafer 110 mainly includes high-density logic circuits and can reduce the area of the wafer through a high-order process. As a result, the overall area of the integrated circuit 100 can be effectively reduced, and the production cost will be low.

In an embodiment of the present invention, the main wafer 110 may have a plurality of pads, and the input/output interface chip 120 may have a plurality of connection pads. pad. The connection pads on the input and output interface wafers 120 can be coupled to the pads on the main wafer 110, respectively. The form of the coupling is not limited, and the connection bonding pad may be coupled to the bonding pad on the main wafer 110 by using a package bonding wire, or may be formed on the bonding pad on the bonding pad and/or the main wafer 110. The bumps are first coupled to each other through the conductive bumps. In fact, inter-wafer connection techniques well known to those of ordinary skill in the art can be applied to the present invention without fixed limitations.

In addition, in other embodiments of the present invention, the number of the main crystals 110 may be plural. The plurality of main crystals 110 can collectively transmit signals to and from the external electronic device through the input/output interface chip 120. One master wafer 110 illustrated in FIG. 1 is merely an example and is not intended to limit the scope of the invention.

Regarding the implementation details of the package outer interface OPI, the package outer interface OPI can be applied to a signal transmission interface well known to those skilled in the art, such as a serial and/or parallel transmission interface, without limitation.

Referring to FIG. 2, FIG. 2 is a schematic diagram of an integrated circuit 200 according to another embodiment of the present invention. The integrated circuit 200 includes a main wafer 210 and an input and output interface wafer 220. The integrated circuit 200 is coupled to the external electronic device 230 through the input/output interface chip 220. The input and output interface chip 220 includes a clock signal generator 221, a voltage generator 222, a peripheral circuit 223, and an outer package connection interface circuit 224. The package outer connection interface circuit 224 performs signal transmission with the external electronic device 230 through the package outer connection interface OPI.

In the present embodiment, the clock signal generator 221 generates the clock signal CK and supplies the clock signal CK to the main wafer 210 as the operating clock signal of the main wafer 210. In addition, the voltage generator 222 generates a power supply voltage VDD and supplies the power supply voltage VDD to the main wafer 210 as an operating power source for the main wafer 210. That is to say, it is not necessary to provide a related analog circuit for generating the working clock signal and the operating power source in the main wafer 210. In the main wafer 210 using the high-order process, the area of the wafer can be effectively reduced.

In other embodiments of the invention, the number of supply voltages VDD may be more than one. The voltage generator 222 can also generate a plurality of different supply voltages VDD and supply a plurality of different voltage value supply voltages VDD to the main wafer 210.

The peripheral circuit 223 can be designed according to the peripheral requirements of the main wafer 210, and can be, for example, a peripheral circuit such as a timer or an input/output circuit.

Please refer to FIG. 3, which is a schematic diagram of a package structure of an integrated circuit according to an embodiment of the present invention. The integrated circuit 300 includes a main wafer 310, an input/output interface chip 320, and a package carrier 330. The main wafer 310 and the input and output interface wafers 320 are all disposed on the package carrier 330. The main wafer 310 has a plurality of pads thereon, and a plurality of conductive bumps BP1 are respectively formed on the pads. These conductive bumps BP1 are respectively connected to the plurality of inner leads ILB through the flip chip package. The input/output interface chip 320 has a plurality of connection pads, and a plurality of conductive bumps BP2 are respectively formed on the connection pads. A portion of the conductive bumps BP2 are coupled to the inner leads ILB and coupled to the pads of the main wafer 310 via the inner leads ILB. The other portion of the conductive bump BP2 is coupled to the plurality of external pins OLB.

In an embodiment of the invention, the inner lead ILB and the outer lead OLB may be disposed on the package carrier 330. In addition, the package carrier may be configured with a plurality of pads PAD1, PAD2 and the external pins OLB coupled to the pads PAD1, PAD2. Corresponding to the pads PAD1, PAD2, the electrostatic discharge protection circuits ESD1 and ESD2 may be respectively disposed on the package carrier 330. In addition, the pads PAD1, PAD2 can be connected to the external electronic device through the package wires WIR1 and WIR2, respectively.

It is worth mentioning that in an embodiment of the invention, the package carrier 330 can be implemented using a lower order process wafer. As a result, the ESD1 and the ESD2 having a high degree of protection on the package carrier 330 do not require a large production cost. Moreover, in the integrated circuit 300, only the pads PAD1 and PAD2 on the package carrier 330 are directly in contact with the external electronic device, and therefore, the main wafer 310 and the input/output interface chip 320 do not require a high level of electrostatic discharge protection. The ability to effectively reduce the cost of the ESD protection circuit.

In an embodiment of the invention, the integrated circuit 300 can be implemented by means of a chip on board (COB) on the circuit board, or can be performed by other methods. The integrated circuit 300 may also be provided with a package cover on the package carrier 330 to cover the main wafer 310 and the input/output interface chip 320.

Referring to FIG. 4, FIG. 4 is a schematic diagram of a package structure of an integrated circuit according to another embodiment of the present invention. In the embodiment of FIG. 4, integrated circuit 400 includes a main crystal 410 and an input and output interface die 420. The input and output interface die 420 can serve as a package carrier and cover the main wafer 410 on the input and output interface die 420 and partially cover the input and output interface die 420 without requiring an additional package carrier. Through the flip chip package, conductive bumps may be formed on the pads on the main wafer 410, and the conductive bumps are coupled to the interface pads on the input/output interface chip 420. In addition, a plurality of pads PAD3 and PAD4 may be formed on the input/output interface chip 420, and pads PAD3 and PAD4 are provided to be coupled to the external electronic device through the package wires WIR3 and WIR4.

It is worth mentioning that, corresponding to the pads PAD3 and PAD4, the input and output interface chip 420 can form a high-capacity electrostatic discharge protection circuit ESD3 and ESD4. Therefore, it can be known that the protection levels of the ESD protection circuit on the main wafer 410 and the ESD protection circuit of the input/output interface chip 420 in the embodiment of the present invention can be designed to be lower than that of the ESD protection circuit ESD3 and ESD4. Grade to reduce the wafer area and to meet the cost reduction requirements.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of an embodiment of a main wafer of the present invention. In the present embodiment, the main wafer 500 may be a dicable polycrystalline wafer. The main wafer 500 includes a semiconductor substrate SUB, a plurality of cell CELLs, and a plurality of signal transmission line groups OCI. The cell CELL and the signal transmission line group OCI are all disposed on the semiconductor substrate SUB. Regarding the arrangement of the unit cell CELL, each of the unit cells CELL and the adjacent unit cells CELL are arranged to have at least one space therebetween. The signal transmission line group OCI is disposed on a space between adjacent cells CELL. The signal transmission line group OCI can be formed by using a patterned metal layer on the semiconductor substrate SUB and used to perform a signal transmission operation between adjacent unit cells CELL.

In an embodiment of the invention, the CELL on each unit cell may have a plurality of pads. Through these pads, the cell CELL on the main wafer 500 can be connected to a wafer outside the main wafer 500 (for example, a peripheral interface chip is input). The input peripheral chip can transmit signal to the cell CELL through the pad PD on one or more cell CELLs on the main chip 500.

In an embodiment of the invention, the signal transmission between the cells CELL is performed only through the signal transmission line group OCI between the cells, and does not pass through the pad PD on the cell CELL.

Each of the unit cells CELL in the main wafer 500 may be a chip such as a microcontroller or a memory. Generally speaking, each cell CELL is constructed by a high-density logic circuit, and the area of each cell CELL can be effectively reduced under the premise of using a high-order process. Wherein, the poly unit cell wafer of the embodiment of the invention is usable, and the multi-cell wafer is cut through a portion of the space to cut off part of the signal transmission line group OCI, so that the poly unit wafer is divided into a plurality of sub-wafers, At least a portion of the sub-wafer after cutting can still be used.

In other embodiments of the present invention, the space between the cell CELLs in the main wafer 500 can be provided as a dicing street and can be diced into a plurality of wafers. For example, if the main wafer 500 originally includes a cell CELL of a plurality of microprocessors, and when the external electronic device at the application end does not require so many cell CELLs of the microprocessor, the main wafer 500 can be cut into two. One or more wafers. Moreover, all wafers after cutting can maintain normal working ability.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 300, 400‧‧‧ ‧ integrated circuits
110, 210, 310, 410, 500‧‧‧ main wafer
120, 220, 320, 420‧‧‧ input and output interface chip
330‧‧‧Package carrier
CK‧‧‧ clock signal
121, 221‧‧‧ clock signal generator
OPI‧‧‧ package external interface
222‧‧‧Voltage generator
224‧‧‧Package external interface circuit
223‧‧‧ peripheral circuits
VDD‧‧‧Power supply voltage
BP1, BP2‧‧‧ conductive bumps
ILB‧‧‧Internal wire
OLB‧‧‧ external pin
PAD1, PAD2, PD, PAD3, PAD4‧‧‧ pads
ESD1, ESD2‧‧‧ Electrostatic discharge protection circuit
WIR1, WIR2, WIR3, WIR4‧‧‧ package wire
SUB‧‧‧Semiconductor substrate
CELL‧‧‧ unit cell
OCI‧‧‧Signal transmission line set

The following drawings are a part of the specification of the invention, and illustrate the embodiments of the invention FIG. 1 is a schematic diagram of an integrated circuit according to an embodiment of the invention. FIG. 2 is a schematic diagram of an integrated circuit 200 according to another embodiment of the present invention. FIG. 3 is a schematic diagram showing a package structure of an integrated circuit according to an embodiment of the present invention. 4 is a schematic diagram showing a package structure of an integrated circuit according to another embodiment of the present invention. Figure 5 is a schematic illustration of an embodiment of a master wafer of the present invention.

100‧‧‧ integrated circuit

110‧‧‧ main chip

120‧‧‧Input and output interface chip

CK‧‧‧ clock signal

121‧‧‧clock signal generator

OPI‧‧‧ package external interface

Claims (10)

An integrated circuit comprising: at least one main wafer having a plurality of pads, wherein the main wafer is a poly unit wafer, wherein the poly unit wafer comprises: a semiconductor substrate; a plurality of unit cells disposed therein a semiconductor substrate having a space between any two adjacent cells; and a plurality of signal transmission line groups respectively disposed on at least a portion of the spaced spaces and respectively used Performing signal transmission between at least a portion of adjacent cells, wherein the poly unit wafer is usable, and the poly unit wafer is cut through a portion of the spaced spaces to cut off portions of the signal transmission lines. Causing the multi-cell wafer to be divided into a plurality of sub-wafers, wherein the diced portions of the sub-wafers are still usable; and an input-output interface chip, including a clock signal generator, generating at least one clock signal; wherein The clock signal generator of the input and output interface chip provides the clock signal to the main wafer as a working clock signal of the main wafer. The integrated circuit of claim 1, wherein the input/output interface chip further comprises: a voltage generator coupled to the main chip, the voltage generator generating at least one power supply voltage, and providing the power supply voltage to The main wafer serves as an operating power source for the main wafer. The integrated circuit of claim 1, wherein the input/output interface chip further comprises: a plurality of connection pads, wherein the connection pads are respectively coupled to the pads on the main wafer. The integrated circuit of claim 2, wherein the input/output interface chip further comprises: at least one peripheral circuit coupled to the voltage generator and the clock signal generator; and an external package interface circuit, An external electronic device for connecting to the outside of the semiconductor device. The integrated circuit of claim 1, further comprising: a package carrier, wherein the main wafer and the input/output interface chip are disposed on the package carrier. The integrated circuit of claim 5, further comprising: a plurality of inner leads disposed on the package carrier and coupling the pads on the main wafer to the input/output interface chip; A plurality of external pins are disposed on the package carrier and coupled to the package external connection interface circuit, wherein the external pins are used to connect to the external electronic device. The integrated circuit of claim 6, wherein the package carrier is provided with a plurality of pads and a plurality of electrostatic discharge protection circuits respectively corresponding to the pads, wherein the external pins are respectively coupled to The pads on the package carrier. The integrated circuit of claim 1, wherein the main wafer is disposed on the input/output interface chip and partially covers the input/output interface chip. The integrated circuit of claim 8, wherein the input/output interface chip is coupled to the pads through a plurality of conductive bumps, and the input/output interface chip is coupled to an external portion through a plurality of external pins. Electronic device. The integrated circuit of claim 1, wherein the process level for fabricating the main wafer is higher than the process level for fabricating the input/output interface wafer.