TW201715642A - Semiconductor structure and method for manufacturing the same - Google Patents

Abstract

A semiconductor structure is provided, which includes a first high voltage MOS device region having a first light doping region in a substrate, wherein a conductive type of the substrate and a conductive type of the first light doping region are same; and a first well in the substrate, wherein the first well substantially contacts a side of the first light doping region and not extends under the first light doping region, and a conductive type of the first well and a conductive type of the first light doping region are opposite. A first gate stack is disposed on a part of the first light doping region and a first well. A first heavy doping region disposed in the first well and the first light doping region at two sides of the first gate stack, wherein a conductive type of the first heavy doping region and a conductive type of the first light doping region are opposite. The first light doping region between the first well and the first heavy doping region is a channel region of the first high voltage MOS device region.

Description

Semiconductor structure and method of forming same

The present invention relates to semiconductor structures, and more particularly to structures having a low voltage and high voltage MOS device and methods of forming the same.

In order to make the product have extended functions and low prices, the manufacture of electronic products has been under pressure. In the case of mobile phones, the competition between manufacturers and resellers keeps them low, even if the phone functions are significantly larger than previous products. In fact, in addition to sending and receiving words, today's mobile phones also include e-mail, web browsing, text communication, music storage, photography, and video playback.

In order to expand the functionality of the device at a low price, manufacturers must develop new processors and algorithms, as well as develop new semiconductor technologies that are low cost and more closely integrated. However, high device integration typically requires incompatible techniques to be incorporated into a common device substrate.

Many electronic devices, such as cell phones, use low voltage CMOS devices in a variety of circuits, such as data encryption and decryption. However, other circuits of the same electronic device (such as modulators/demodulators and power amplifiers) use relatively high voltage devices. Unfortunately, low voltages do not effectively operate high voltage devices, while high voltages can damage low voltage devices. The above contradictions often lead to the use of different independent circuits in the prior art, some being low voltage devices and others being high voltage devices. However, the above Different types of devices cannot meet the requirements of high integration density and low cost.

To overcome the above problems, many technical solutions have been developed. However, existing technical solutions usually require multiple masks and lithography processes. In summary, there is a need for new structures to reduce the number of reticle and lithography processes.

A semiconductor structure according to an embodiment of the present invention includes: a first high voltage MOS device region, wherein: the first lightly doped region is located in the substrate, and the substrate and the first lightly doped region have the same conductivity type; a well region is located in the substrate, substantially contacting a side of the first lightly doped region and not extending below the first light hybrid region, wherein the first well region is opposite to the conductivity type of the first lightly doped region; a gate stack is disposed on a portion of the first lightly doped region and a portion of the first well region; and the first heavily doped region is respectively located at the first well region and the first lightly doped region on both sides of the first gate stack Wherein the first heavily doped region is opposite to the conductivity type of the first lightly doped region, wherein the first lightly doped region between the first well region and the first heavily doped region is the first high voltage gold The passage area of the oxygen half device area.

A method for forming a semiconductor structure according to an embodiment of the present invention includes: forming a first well region in a substrate, wherein the first well region is opposite to a conductivity type of the substrate; forming a lightly doped region in the substrate, wherein the first well The region substantially contacts the side of the first lightly doped region and does not extend below the first lightly doped region, and the first well region is opposite to the conductive pattern of the first lightly doped region; forming the first gate stack on the portion a first lightly doped region and a portion of the first well region; implanting dopants into the first well region and the first lightly doped region that are not covered by the first gate stack to form a first heavily doped region a region, wherein the first heavily doped region is opposite to the conductivity pattern of the first lightly doped region, wherein the first lightly doped region between the first well region and the first heavily doped region is a first high voltage gold oxygen The channel area of the half device area.

100‧‧‧Substrate

103, 105‧‧‧High voltage gold oxide half device area

107, 109‧‧‧Low voltage gold oxide half device area

111‧‧‧Isolation structure

113A, 113B, 113C‧‧‧ well area

117A, 117B, 117C‧‧‧lightly doped areas

119A, 119B, 119C‧‧ ‧ gate stacking

120‧‧‧ spacers

121A, 121B, 123A, 123B‧‧‧ heavily doped areas

125‧‧‧Contacts

1 to 4 are cross-sectional views showing a process of a semiconductor structure in an embodiment.

1 to 4 are cross-sectional views showing a process of a semiconductor structure in an embodiment. First, as shown in Fig. 1, a p-type substrate 100 is provided. The substrate 100 may be a germanium substrate, a germanium-on-insulator (SOI) substrate, or the like. In an embodiment of the invention, the substrate 100 can be implanted with a p-type dopant after the substrate 100 is first provided. In another embodiment of the present invention, the p-type dopant may be doped in the field when the substrate 100 is epitaxially formed. In an embodiment of the invention, the doping concentration of the substrate 100 is between 7e13 atoms/cm ³ and 7e15 atoms/cm ³ .

Next, an isolation structure 111 is formed in the substrate 100 to separate and define a plurality of device regions such as a p-type high voltage MOS half device region 103, an n-type high voltage MOS half device region 105, and a p-type low voltage gold oxide. The half device region 107 and the n-type low voltage MOS half device region 109. The isolation structure 111 shown in FIG. 1 is a shallow trench isolation (STI), and the method for forming the same includes, but is not limited to, forming a mask layer on the substrate 100, and patterning the mask layer by a lithography and etching process to expose the portion. The substrate 100 etches the exposed portion of the substrate 100 to form a trench, fill an insulating material such as yttrium oxide into the trench, and remove the patterned mask layer. In other embodiments, the isolation structure 111 may be a local oxide ruthenium (LOCOS), and the formation method thereof includes, but is not limited to, depositing a mask layer such as a tantalum nitride layer on the substrate 100, and patterning the mask by a lithography and etching process. The layer exposes a portion of the substrate 100, thermally oxidizes the exposed portion of the substrate 100 to form a hafnium oxide layer, and removes the patterned mask layer. The yttrium oxide layer formed above is LOCOS.

Then, an n-type well region 113A is formed in the high voltage MOS half device region 103, an n-type well region 113B is formed in the partial high voltage MOS half device region 105, and an n-type well region 113C is formed at a low voltage. In the gold oxide half device area 107. In an embodiment of the invention, the method for forming the well regions 113A, 113B, and 113C includes, but is not limited to, forming a mask pattern (not shown) with a lithography process and an etching process to cover a portion of the high voltage metal oxide half device region. 105 and the low voltage MOS half device region 109, and then implanting the n-type dopant into the high voltage MOS half device region 103, the portion of the high voltage MOS device 105, and the low voltage MOS device region 107, The well regions 113A, 113B, and 113C are defined, and the mask pattern is removed. In an embodiment of the invention, the doping concentrations of the well regions 113A, 113B, and 113C are the same, ranging from 5e14 atoms/cm ³ to 1e17 atoms/cm ³ . As shown in Fig. 1, the well regions 113A, 113B, and 113C have the same depth.

Next, as shown in FIG. 2, a p-type lightly doped region 117A is formed in a portion of the well region 113A to form a p-type lightly doped region 117B in a portion of the high voltage MOS half device region 105, and A p-type lightly doped region 117C is formed in the low voltage MOS half device region 109. In an embodiment of the invention, the method for forming the lightly doped regions 117A, 117B, and 117C includes, but is not limited to, forming a mask pattern (not shown) to cover a portion of the high voltage MOS half by a lithography process and an etch process. The device region 103, the portion of the high voltage MOS half device region 105, and the low voltage MOS half device region 107, and the p-type dopant are implanted into the partial well region 113A and the partial high voltage MOS half device region 105. And the low voltage MOS half device region 109, to define the lightly doped regions 117A, 117B, and 117C, and then remove the mask pattern. In an embodiment of the invention, the doped concentrations of the lightly doped regions 117A, 117B, and 117C are the same, ranging from 1e15 atoms/cm ³ to 1e17 atoms/cm ³ . As shown in FIG. 2, the lightly doped regions 117A, 117B, and 117C have the same depth and are smaller than the depths of the well regions 113A, 113B, and 113C, so as to avoid the same doping type of the well region 113A and the substrate to cause the source. Leakage current to the substrate. It is noted that the well region 113B in the high voltage MOS half device region 105 only substantially contacts the sidewall of the lightly doped region 117B and does not extend below the lightly doped region 117B. If the well region 113B traverses the entire high voltage MOS half device region 105 as well as the well region 113A, the doping concentration of the lightly doped region 117B needs to be increased. As a result, the doping concentration of the lightly doped regions 117A and 117C is also increased, that is, the threshold voltage of the device is increased. In one embodiment of the invention, the sides of the lightly doped region 117B are slightly overlapped with the sides of the well region 113B or are not separated by a distance. In principle, however, the sides of the lightly doped region 117B substantially contact the sides of the well region 113B.

Next, as shown in FIG. 3, gate stacks 119A, 119B, 119C, and 119D are respectively formed in the high voltage MOS half device region 103, the high voltage MOS half device region 105, the low voltage MOS half device region 107, and Low voltage MOS half device area 109. The gate stack 119A covers a portion of the well region 113A and a portion of the lightly doped region 117A, and the gate stack 119B covers a portion of the well region 113B and a portion of the lightly doped region 117B. In an embodiment of the invention, the method for forming the gate stacks 119A, 119B, 119C, and 119D includes, but is not limited to, forming a gate dielectric layer on the structure of FIG. 2, forming a gate layer on the gate dielectric. On the layer, a mask pattern (not shown) is formed on the layer to form a mask pattern (not shown) to cover part of the gate layer, and then the gate layer not covered by the mask pattern and the gate dielectric layer below it are removed to define the gate. Stacks 119A, 119B, 119C, and 119D. In an embodiment of the invention, the gate dielectric layer may be yttrium oxide (SiO2), tantalum nitride, hafnium oxynitride, a high dielectric constant material, any other suitable material, or a combination thereof, and the gate material may be An amorphous germanium, a polycrystalline germanium, one or more metals, a metal nitride, a conductive metal oxide, or the like combination.

It should be noted that the order of FIG. 2 and FIG. 3 can be reversed, that is, the gate stack can be formed first to form lightly doped regions 117A, 117B, and 117C. However, if the process of forming the gate stack is used first, the spacers 120 are formed on the sidewalls of the gate stack after forming the lightly doped regions 117A, 117B, and 117C, so that the heavily doped regions 121A and 113A are formed later. The lightly doped region 117A (or 117B) is interposed (either between the heavily doped region 123A and the well region 113B).

As shown in FIG. 4, spacers 120 are formed on the sidewalls of the gate stacks 119A, 119B, 119C, and 119D as appropriate. In an embodiment of the invention, the method for forming the spacers 120 includes, but is not limited to, forming a spacer layer on the gate stack and the exposed doped region, and then removing the spacer layer by anisotropic etching to The spacers 120 are retained on the sidewalls of the gate stack. The spacer layer may be, for example, hafnium oxide, tantalum nitride, hafnium oxynitride, or a multilayer structure as described above. In another embodiment of the invention, the spacers 120 may be omitted.

As shown in FIG. 4, a p-type heavily doped region 121A is formed in the well region 113A and the lightly doped region 117A on both sides of the gate stack 119A, and an n-type heavily doped region 123A is formed on the gate stack 119B. In the side well region 113B and the lightly doped region 117B, a p-type heavily doped region 121B is formed in the well region 113C on both sides of the gate stack 119C, and an n-type heavily doped region 123B is formed in the gate stack 119D. In the lightly doped region 117C on both sides. In an embodiment of the invention, the method for forming the heavily doped regions 121A and 121B includes, but is not limited to, forming a mask pattern (not shown) by a lithography process and an etching process to cover the high voltage MOS device region 105 and the low portion. After the voltage MOS half device region 109, the gate stacks 119A and 119C are used as the implant mask, and the p-type dopant is used to implant the high voltage MOS half device region 103 and the low voltage MOS half device region 107 to define the heavy doping. The miscellaneous regions 121A and 121B are then removed from the mask pattern. In an embodiment of the invention, the doping concentrations of the heavily doped regions 121A and 121B are the same, ranging from 5e17 atoms/cm ³ to 2e20 atoms/cm ³ . As shown in FIG. 4, the depths of the heavily doped regions 121A and 121B are the same, and the depth of the heavily doped region 121A is smaller than the depth of the lightly doped region 117A. The p-type lightly doped region 117A sandwiched between the n-type well region 113A and the right heavily doped region 121A, that is, the drift region of the high voltage MOS half device region 103, is sandwiched between the p-type weight The n-type well region 113A between the doped region 121A and the p-type lightly doped region 117A, that is, the channel region of the high voltage MOS half device region 103. In the above structure, as long as the thickness of the spacer 120 is changed, the width of the gate stack 119A and the spacer 120 covering the lightly doped region 117A can be changed. In this way, the same reticle and implantation process can be used to form the structure of Figures 1-4, and the length of the drift region of the high voltage MOS half device region 103 can be changed by simply changing the thickness of the spacer 120.

In an embodiment of the present invention, the method for forming the heavily doped regions 123A and 123B includes, but is not limited to, forming a mask pattern (not shown) with a lithography process and an etching process to cover the high voltage MOS device region 103 and the low portion. After the voltage MOS half device region 107, the gate stacks 119B and 119D are used as the implant mask, and the n-type dopant is implanted with the high voltage MOS half device region 105 and the low voltage MOS device region 109 to define the heavy doping. Miscellaneous areas 123A and 123B, and then the mask pattern is removed. In an embodiment of the invention, the doping concentrations of the heavily doped regions 123A and 123B are the same, ranging from 1e17 atoms/cm ³ to 5e19 atoms/cm ³ . As shown in FIG. 4, the depths of the heavily doped regions 123A and 123B are the same, and the depth of the heavily doped region 123A is smaller than the depth of the lightly doped region 117B. A p-type lightly doped region 117B between the n-type well region 113B and the right heavily doped region 123A, that is, the channel region of the high voltage MOS half device region 105. In the above structure, as long as the thickness of the spacer 120 is changed, the gate stack 119B and the spacer 120 are changed to cover the width of the lightly doped region 117B. In this way, the same reticle and implantation process can be used to form the structure of FIGS. 1-4, and the length of the channel region of the high voltage MOS device region 105 can be changed by changing the thickness of the spacer 120. Drive voltage. In other words, in the above embodiment, the driving voltage of the high voltage MOS half device region can be simply adjusted without adjusting the doping concentration of the doping region or changing the reticle design. It can be understood that the heavily doped regions 121A and 123B can be formed after the heavily doped regions 121A and 121B are formed. In another embodiment, the heavily doped regions 123A and 123B may be formed before the heavily doped regions 121A and 121B are formed.

The n-type well region 113C between the p-type heavily doped regions 121B, that is, the channel region of the low voltage MOS half device region 107. A p-type lightly doped region 117C between the n-type heavily doped regions 123B, i.e., a channel region of the low voltage MOS half device region 109. It can be understood that the heavily doped region 121A on both sides of the gate stack 119A is the source/drain region of the high voltage MOS device region 103, and the heavily doped region 123A on both sides of the gate stack 119B is a high voltage gold. The source/drain region of the oxygen half device region 105, the heavily doped region 121B on both sides of the gate stack 119C is the source/drain region of the low voltage MOS device region 107, and the gate stack 119D is on both sides. The heavily doped region 123B is the source/drain region of the low voltage MOS half device region 109. An interlayer dielectric layer (not shown) can then be formed over the structure, and contacts 125 are formed through the interlayer dielectric layer to contact the heavily doped regions 121A, 121B, 123A, and 123B, respectively.

In the above embodiment, the substrate 100, the high voltage MOS half device region 103, the low voltage MOS half device region 107, the lightly doped regions 117A, 117B, and 117C, and the heavily doped regions 121A and 121B are p-type. The high voltage MOS half device region 105, the low voltage MOS half device region 109, the well regions 113A, 113B, and 113C, and the heavily doped regions 123A and 123B are n-type. In another embodiment, the substrate 100, the high voltage MOS half device region 103, the low voltage MOS half device region 107, the lightly doped regions 117A, 117B, and 117C, and the heavily doped regions 121A and 121B are n-type. The high voltage MOS half device region 105, the low voltage MOS half device region 109, the well regions 113A, 113B, and 113C, and the heavily doped regions 123A and 123B are p-type. It will be appreciated that the n-type dopant may be phosphorus, arsenic, or antimony, and the p-type dopant may be boron or BF ₂ .

The present invention has been disclosed in the above several embodiments, and is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧Substrate

103, 105‧‧‧High voltage gold oxide half device area

107, 109‧‧‧Low voltage gold oxide half device area

111‧‧‧Isolation structure

113A, 113B, 113C‧‧‧ well area

117A, 117B, 117C‧‧‧lightly doped areas

119A, 119B, 119C, 119D‧‧ ‧ gate stacking

120‧‧‧ spacers

121A, 121B, 123A, 123B‧‧‧ heavily doped areas

125‧‧‧Contacts

Claims (10)

A semiconductor structure comprising: a first high voltage MOS device region, comprising: a first lightly doped region in a substrate; and the substrate and the first lightly doped region have the same conductivity type; a well region is located in the substrate, substantially contacting a side of the first lightly doped region and not extending below the first light hybrid region, wherein the first well region and the first lightly doped region are of a conductivity type The first gate stack is located on a portion of the first lightly doped region and a portion of the first well region; the first heavily doped region is located on each side of the first gate stack a well region and the first lightly doped region, wherein the first heavily doped regions are opposite to the first lightly doped region; wherein the first well region and the first heavily doped region The first lightly doped region between the regions is the channel region of the first high voltage MOS half device region. The semiconductor structure of claim 1, further comprising: a first low voltage MOS device region, comprising: a second lightly doped region in the substrate, wherein the second lightly doped region and The first lightly doped regions have the same conductivity type, doping concentration, and depth; a second gate stack is located on a portion of the second lightly doped region; and the second heavily doped regions are respectively located The second lightly doped region on both sides of the second gate stack, wherein the second heavily doped region and the first heavily doped region have the same conductivity type, doping concentration, and depth. For example, the semiconductor structure described in claim 1 of the patent scope further includes: a second high voltage MOS half device region, comprising: a second well region located in the substrate, wherein the second well region and the first well region have the same conductivity type, doping concentration, and depth; a third lightly doped region is located in a portion of the second well region, and the third lightly doped region and the first lightly doped region have the same conductivity type, doping concentration, and depth; a gate stack disposed on a portion of the third lightly doped region and a portion of the second well region; a third heavily doped region located in the second well region on both sides of the third gate stack and the first And a third lightly doped region, wherein the third heavily doped region is opposite to the conductive type of the first lightly doped region; wherein the third portion is between the second well region and the third heavily doped region a lightly doped region, that is, a drift region of the second high voltage MOS half device region; wherein the second well region between the third heavily doped region and the third lightly doped region, that is, the second The channel area of the high voltage MOS half device area. The semiconductor structure of claim 3, further comprising: a second low voltage MOS half device region, comprising: a third well region located in the substrate, wherein the third well region and the first well The regions have the same conductivity type, doping concentration, and depth; a fourth gate stack is located on a portion of the third well region; and a fourth heavily doped region is respectively located on both sides of the fourth gate stack In the third well region, wherein the fourth heavily doped region has the same conductivity type, doping concentration, and depth as the third heavily doped region. For example, the semiconductor structure described in claim 1 of the patent scope further includes: A spacer is located on a sidewall of the first gate stack. A method of forming a semiconductor structure, comprising: forming a first well region in a substrate, wherein the first well region is opposite to a conductivity type of the substrate; forming a lightly doped region in the substrate, wherein the first The well region substantially contacts the side of the first lightly doped region without extending below the first lightly doped region, and the first well region is opposite to the conductive pattern of the first lightly doped region; forming a first a gate is stacked on a portion of the first lightly doped region and a portion of the first well region; the dopant is implanted to the first well region uncovered by the first gate stack and the first lightly doped Forming a plurality of first heavily doped regions, wherein the first heavily doped regions are opposite to the conductive patterns of the first lightly doped regions; wherein the first well regions are located with the first heavily doped regions The first lightly doped region between the regions is a channel region of a first high voltage MOS half device region. The method for forming a semiconductor structure according to claim 6, wherein the step of forming the first lightly doped region further forms a second lightly doped region of the first low voltage MOS device region on the substrate Forming the first gate stack also forming a second gate of the first low voltage MOS device stacked on a portion of the second lightly doped region; and forming the first heavily doped regions The step of forming a region also forms a plurality of second heavily doped regions of the first low voltage MOS device in the second lightly doped region on either side of the second gate stack. The method for forming a semiconductor structure according to claim 6, wherein the step of forming the first well region also forms a second high voltage metal oxide half device region. a second well region is in the substrate; the step of forming the first lightly doped region also forms a third lightly doped region of the second high voltage MOS half device in a portion of the second well region; Forming the first gate stack also forms a third gate of the second high voltage MOS device stacked on a portion of the third lightly doped region and a portion of the second well region; The method includes: forming a plurality of third heavily doped regions in the second well region and the third lightly doped region on both sides of the third gate stack, wherein the third heavily doped region and the first lightly doped region The conductive pattern of the impurity region is opposite; wherein the third lightly doped region between the second well region and the third heavily doped region is a drift region of the second high voltage MOS half device region; The second well region between the third heavily doped region and the third lightly doped region, that is, the channel region of the second high voltage MOS half device region. The method for forming a semiconductor structure according to claim 8, wherein the step of forming the first well region further forms a third well region of the second low voltage MOS device in the substrate; forming the first a step of stacking the gates also forms a fourth gate of the second low voltage MOS device stacked on a portion of the third well region; the steps of forming the third heavily doped regions also form a plurality of A quadruple doped region is in the third well region on either side of the fourth gate stack. The method for forming a semiconductor structure according to claim 6, further comprising: forming a spacer on a sidewall of the first gate stack.