TW201712864A - Cell grid architecture for FinFET technology - Google Patents

Abstract

A structure of a cell grid comprises a plurality of polycrystalline silicon (POLY) lines in the cell gird, and a plurality of fin-shaped oxide diffused (OD) regions in the cell gird. The POLY lines are arranged horizontally and evenly spaced with a pitch X. The fin-shaped OD regions are arranged vertically and evenly spaced with a pitch Y. The pitch Y of the fin-shaped OD regions defines width of the cell grid. The structure of the cell grid further comprises a plurality of PMOS transistors and NMOS transistors in the cell grid. The PMOS transistors and NMOS transistors have their source nodes and drain nodes formed in the fin-shaped OD regions and their gates connected to the POLY lines. The plurality of PMOS transistors and NMOS transistors are connected together to form one or more CMOS devices in the cell grid.

Description

Component lattice structure of fin field effect transistor

The present disclosure is generally directed to a semiconductor process, and more particularly to a component cell structure for fin field effect transistors (FinFETs).

With the rapid advancement of the semiconductor manufacturing industry, complementary metal oxide semiconductor (CMOS) fin field-effect transistor (FinFET) devices are popular in many logic and other applications. Therefore, fin field effect transistor (FinFET) devices are nowadays incorporated in various forms and fabricated semiconductor devices. Fin field effect transistor devices generally comprise a plurality of fin-shaped oxide diffused (OD) regions of high aperture ratio. The fin-shaped oxidized diffusion region is formed perpendicular to the upper surface of the substrate. The fin-shaped oxidized diffusion region defines an active region. The active region is formed with a channel of a CMOS transistor and a source/drain region. In general, the fin-shaped oxidized diffusion region is an insulated and raised three-dimensional (3D) structure. A gate of a CMOS FinFET device is formed over the fin and along the sides of the fin to take advantage of the increased surface area of the channel and source/gate regions to produce a faster, more reliable, and better controlled semiconductor transistor device. . Polycrystalline germanium A (Polycrystalline silicon; POLY) line is used to carry the control signal to the gate of the CMOS transistor. In some embodiments, the gate can also be fabricated in POLY.

The component cell is an element structure that implements various CMOS transistors in the circuit using the fin OD region and the POLY line. The fin-shaped OD region and the POLY line are formed in different layers on the semiconductor substrate in an orthogonal direction. In the process of circuit design, the height of the component grid is appropriately selected according to the circuit, and the width of the component cell is determined according to the number of CMOS devices in the component cell. The larger the number of CMOS devices, the larger the width of the component grid, and the larger the area of the component grid.

An embodiment of the present disclosure is directed to a component cell structure comprising a plurality of polysilicon lines in a cell, a plurality of fin-shaped oxide diffusion regions in the cell, and a plurality of P-type metals in the cell An oxide semiconductor transistor and an N-type metal oxide semiconductor transistor. The polysilicon lines are arranged in a first direction and are evenly spaced at a first pitch. The fin-shaped oxidized diffusion regions are arranged in a second direction and are equally spaced at a second pitch. The second pitch of the fin-shaped oxidized diffusion region defines the width of the component grid. The P-type metal oxide semiconductor transistor and the N-type metal oxide semiconductor transistor have a source node and a drain node formed in the corresponding fin-shaped oxide diffusion region, and a gate connected to the corresponding polysilicon line. The P-type metal oxide semiconductor transistors are connected to the N-type metal oxide semiconductor transistor Forming one or more complementary metal oxide semiconductor devices in the component cell.

The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood.

102‧‧‧Polyline

102_1, 102_2, 102_3, 102_4, 102_5, 102_6, 102_7‧‧‧ polycrystalline germanium

104‧‧‧Fin-shaped oxidized diffusion zone

104_1, 104_2, 104_3, 104_4, 104_5, 104_6, 104_7, 104_8‧‧‧ Fin-shaped oxidized diffusion regions

106‧‧‧N type materials

108‧‧‧P type material

109‧‧‧ separate line

110‧‧‧ points

112, 114‧‧‧Power line

116, 116_1, 116_2, 116_3, 116_4, 116_5‧‧‧ metal lines

118‧‧‧Cut polycrystalline tantalum wire

120, 132‧‧‧P type metal oxide semiconductor device

122, 134‧‧‧N type metal oxide semiconductor device

124_1, 124_2, 124_3, 124_4, 124_5, 124_6‧‧‧ metal wires

126, 126_1, 126_2, 126_3, 126_4, 126_5, 126_6, 126_7, 126_8, 128‧‧‧ perforation

130, 136‧‧‧Complementary Metal Oxide Semiconductor Devices

X‧‧‧ pitch

Y‧‧‧ pitch

VDD, VSS‧‧‧ voltage source

PMOS-1, PMOS-2, PMOS-3, PMOS-4‧‧‧P type metal oxide semiconductor device

NMOS-1, NMOS-2, NMOS-3, NMOS-4‧‧‧N type metal oxide semiconductor device

700‧‧‧ method

702, 704, 706, 708, 710‧ ‧ steps

The one or more embodiments are illustrated by way of example and not by way of limitation. It is emphasized that the construction of standard practices based on multiple characteristics of the industry may not be drawn to scale, but for illustrative purposes only. In fact, the dimensions of the various types of feature constructs in the schema can be arbitrarily increased or decreased for clarity of discussion.

1A-1B are exemplary plan views of two different component cell layouts in accordance with some embodiments of the present disclosure, wherein the width of the component cell layout is defined by the pitch of the POLY line; 2A-2B A plan view of a different example of two component cell layouts of Figures 1A-1B, respectively, in accordance with some embodiments of the present disclosure, wherein the width of the component cell is determined by the fin OD region rather than the pitch of the POLY line. Definitions; FIGS. 3A-3B are different expanded (unfolded) diagrams of an exemplary component layout of FIG. 2A in accordance with some embodiments of the present disclosure; FIGS. 4A-4B are diagrams in accordance with the present disclosure Different development views of another exemplary layout of the component of the 3A-3B diagram of the embodiment, wherein the devices are connected together to form a CMOS inverter; 5A-5B are different developments of an exemplary layout of the component cells of FIG. 1A, in which adjacent fin OD regions are horizontally staggered and at a particular distance from one another, in accordance with some embodiments of the present disclosure. 6A-6B are different development views of another exemplary layout of the component cells of FIGS. 5A-5B according to some embodiments of the present disclosure, wherein the devices are all connected together to form a CMOS. Inverter; and Figure 7 is a flow diagram of a method of forming a component cell using one or more FinFET devices, wherein the width of the component cell is segmented by a fin shaped OD region, in accordance with some embodiments of the present disclosure The pitch is defined instead of the pitch of the POLY line.

The following disclosure provides many different embodiments, such as implementing different features of the disclosed subject matter. Specific examples of components and permutations are set forth below to simplify the disclosure and are not intended to limit the disclosure. For example, forming a first feature in the following description on the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include other features formed between the first and second features to Embodiments in which the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or words in different examples. This repetition is for the purpose of simplicity and clarity and is not a limitation of the various embodiments and/

In addition, space-related terms such as "under", "below", "below", "above", "above", etc. The relationship of elements and/or features in the figures to the other element(s) and/or features may be used. These spatially related terms encompass different orientations of the device in use and/or operation in addition to the orientation shown in the drawings. The device may be otherwise oriented (eg, rotated 90 degrees or in other directions) and the spatially related descriptors used herein are interpreted accordingly. It will be appreciated that when an element is referred to as being "connected" or "coupled" to another element, this may be directly connected or coupled to the other element, or one or more intervening elements.

According to some embodiments, the finned oxide diffused (OD) regions and the polycrystalline silicon (POLY) lines used in the cell structure are evenly and evenly spaced. The spacing of a pair of adjacent fin-shaped OD regions or the spacing between a pair of adjacent POLY lines is referred to as the pitch of the fin-shaped OD regions or the pitch of the POLY lines, respectively. In an embodiment, the width of the component grid may be defined by the pitch of the POLY line multiplied by the number of POLY lines in the component cell, or by the pitch of the fin OD region multiplied by the number of fin OD regions in the component cell. The definition is as discussed in detail below. As semiconductor process technology advances, the pitch of the fin OD regions continues to decrease, and in some embodiments, the pitch of the fin OD regions is less than the pitch of the POLY lines.

According to some embodiments, a cell structure whose width is defined by a fin OD region can be used to lay out and fabricate a semiconductor cell grid/circuit. Semiconductor component cell/circuit has multiple uses A complementary metal oxide semiconductor (CMOS) device fabricated by a FinFET process. Here, the width of the component grid is determined by the pitch of the fin OD region multiplied by the number of fin OD regions in the component cell. When the pitch of the fin-shaped OD region is smaller than the pitch of the POLY line, if the same number of CMOS devices are implemented in the component cell, the width of the component cell defined by the pitch of the fin-shaped OD region is smaller than the pitch of the POLY line. The width of the defined component cell. As a result, since the height of the component cell is fixed in the circuit design, the layout area of the component cell is reduced by using the component cell defined by the pitch of the fin-shaped OD region.

For example, FIGS. 1A-1B are plan views of two different component grid layouts according to a fin field-effect transistor (FinFET) device layout technique, the width of the component grid layout being the section of the POLY line. Distance defined.

In the example of FIGS. 1A and 1B, each of the component cells includes a plurality of polycrystalline silicon (POLY) lines 102 equally spaced, and a plurality of evenly spaced finned oxide diffusion (OD) regions 104. The POLY line 102 is configured in a first direction (eg, vertical). The fin OD region 104 is configured in a second direction (eg, horizontal). The POLY line 102 and the fin OD region 104 are substantially disposed in different layers of the semiconductor substrate in an orthogonal direction (eg, a vertical direction with respect to a horizontal direction). Each component cell includes an N-type material 106 and a P-type material 108. N-type material 106 is used to form a plurality of PMOS devices. P-type material 108 is used to form a plurality of NMOS devices. Two types of materials are shown on the upper and lower portions of the component grid and separated by a dividing line 109. Take pictures 1A and 1B For example, the pitch of the POLY line 102 is the distance between the lines of two adjacent POLY lines 102 and is represented by X. Similarly, the pitch of the fin OD regions 104 is the distance between the lines of the two adjacent fin OD regions 104 and is represented by Y. In the examples of FIGS. 1A and 1B, the ratio between X and Y is X=2Y. That is, the pitch of the fin OD regions 104 is half the pitch of the POLY line 102.

In the example of FIG. 1A, the height of the component cell is determined during the circuit design process and is generally not changed during the layout of the component cell, and the height of the component cell is equal to the pitch Y of the fin OD region 104. The number of fin-shaped OD regions 104 that are equally spaced in the upper cell. In the example of Figure 1A, the height of the component grid is 12Y (11 intervals between the 8 fin OD regions 104 and the 4 unoccupied points 110, plus 2 are located on the top and bottom of the component grid 1/2 spacing of the sides to provide a total of 12Y). Note that certain points/sites 110 may not be occupied by the fin-shaped OD region 104 (that is, not diffused by the oxide) based on design rules and/or the location of the devices in the component cell. The width of the component cell in Figure 1A is equal to the pitch of the POLY line 102 multiplied by the number of POLY lines 102 in the component cell. In this example, it is equal to 3X (2 intervals between 3 POLY lines 102, plus 2 1/2 intervals on the left and right sides of the cell to provide a total of 3 intervals or pitches), such as Figure 1A shows. Thus, since X = 2Y in this example, the area of the component cell in Fig. 1A is 3X x 12Y = 18X ² .

For a different (different) example of the component grid layout as shown in Figure 1B, although there are fewer numbers in the component grid based on the number and/or height of the devices in the component cell (four in this example) The fin OD area 104, the height of the component grid is predetermined and can still be calculated as 12Y (11 intervals between the 8 fin OD areas 104 and the 4 unoccupied points 110, plus 2 The upper edge of the component cell and the 1/2 spacing of the bottom edge provide a total of 12Y). The width of the component grid can also be determined to be 3X according to the number of POLY lines 102 in the component cell (two intervals between three POLY lines 102, plus two 1/2 intervals on the left and right sides of the component grid, A total of 3 intervals or pitches are provided, as shown in Figure 1B. Thus, even in this example, there are a small number of fin-shaped OD regions 104 (this example is 4, and the example of FIG. 1A is 8), and the area of the component cell in the first panel is the same as the area of the component cell in the first panel AA. It is 3X×12Y=18X ² .

Figure 2A shows an example layout of the same component grid as Figure 1A, but the width of the component grid is defined by the pitch Y of the fin OD region 104 rather than the pitch X of the POLY line 102. The component cell of Fig. 2A realizes the same transistor and device as the component group of Fig. 1A. However, unlike the layout of the component cells of FIG. 1A, in the present example, the fin-shaped OD regions 104 are vertically arranged and staggered. The fin-shaped OD region 104 is vertically arranged in the horizontal direction (for example, the X-axis direction). The POLY line 102 is disposed orthogonally (for example, the Y-axis direction) than the fin-shaped OD region 104 (for example, the X-axis direction) in the horizontal direction. With this layout, the height of the component cells remains the same and is equal to the pitch of the POLY line 102 multiplied by the number of pitches between the POLY lines 102 in the component cell (this example is 6). That is, 6X shown in Figure 2. However, the width of the component grid is now determined by the pitch Y of the fin OD region 104 multiplied by the number of locations or points in the component cell that are occupied by one or more fin OD regions 104. The width of each point along the horizontal direction is equal to the width of one fin OD area 104. In the example of FIG. 2A, the cell width defined by the fin OD region 104 is equal to 4Y (that is, 3 intervals between the 4 staggered OD regions 104, plus 2 in the component grid The left and right 1/2 intervals to provide a total of 4 intervals or pitch). Each location is occupied by two vertically aligned OD regions 104 to form a total of eight fin OD regions 104. Two vertically aligned OD regions 104 form a group. The two OD regions 104 of each group are relatively offset from the two vertically aligned OD regions 104 of another adjacent group. Thus, based on X = 2Y, the area of the component cell in Fig. 2A is 6X × 4Y = 12X ² . This is significantly smaller than the layout area of the same component of Figure 1A (18X ² versus 12X ² ).

In the example of FIG. 2A, when the height of the component cell is predetermined and is generally not changed during the layout of the component cell, the cell width and the fin shape OD are defined by the pitch of the fin OD region 104. The pitch of the regions 104 may be less than the pitch of the POLY lines 102, and the layout area of the component cells may have a significant reduction. The plurality of fin OD regions 104 may be staggered at the same horizontal position to save space in point 1A that is not occupied by the fin OD region 104. In another example, Figure 2B shows an example layout of the same component grid as Figure 1B, but the width of the component grid is taken at the pitch Y of the fin OD region 104 instead of the pitch X of the POLY line 102. definition. Since the example of the layout of the component grid shown in FIG. 2B has a smaller number (4 vs. 8) of the fin-shaped OD region 104 than the example in FIG. 2A, the component lattice defined by the fin-shaped OD region 104 The width is equal to 2Y (that is, 1 interval between 2 staggered OD regions 104, plus 2 1/2 spacing on the left and right sides of the component grid to provide a total of 2 intervals or pitch) . Thus, when X = 2Y, the area of the component cell is now equal to 6X x 2Y = 12X ² . This results in a considerable reduction in the layout area of the component grid (18X ² versus 6X ² ) compared to the layout of the same component grid in Figure 1B.

Figures 3A and 3B show different expanded (unfolded) views of an exemplary layout of the component cells of Figure 2A. The width of each component cell is defined by the pitch Y of the fin OD region 104. Figure 3A shows a layout of the component cell, which contains the POLY line, the OD area, the cut POLY (POL-POLY), and the vertical metal line in the component cell. As shown in FIG. 3A, the POLY lines 102_1 to 102_7 are arranged across the element grid as an evenly spaced horizontal line segment. The fin-shaped OD regions 104_1 to 104_4 are vertically disposed across the component grid and are staggered in a plurality of horizontal positions. The power lines 112 and 114 are vertical metal lines respectively connected to the high voltage source VDD and the low voltage source VSS. Vertical metal lines 116 are used to connect different devices in the cell.

Figure 3B further shows a plurality of p-type metal oxide semiconductor (PMOS) devices 120 implemented in (or staggered) in the component cell and a plurality of N-type metal oxide semiconductors (n-type metal) Oxide device 122. Since a plurality of PMOS or NMOS devices can share the same POLY line 102, as in FIG. 3B, a plurality of dicing POLY (CPOs) 118 cut the POLY line 102 shared by a plurality of PMOS devices or NMOS devices. A plurality of unconnected line segments are formed such that each PMOS device 120 or NMOS device 122 becomes a separate device having its own POLY line segment in the component cell. The CPOs 118 are POLY for cutting components for sharing by a plurality of devices. Each POLY line 102 is cut into separate segments. As shown in Figure 3B, each The PMOS device 120 and the NMOS device 122 have their gates connected to one of the POLY lines (eg, 102_2, 102_3, 102_5, and 102_6, respectively), which carry the input signals to the corresponding gates. Sources and drains of the respective PMOS and NMOS devices are formed in the respective fin OD regions 104_1 to 104_8. In some embodiments, the OD regions of the PMOS and the drain of the NMOS device are connected by the POLY lines 102_1, 102_4, and 102_7, respectively. In some embodiments, one or more PMOS devices 120 (eg, PMOS-3) and one or more NMOS devices 122 (eg, NMOS-1) can be connected together to form one CMOS device 130. For one non-limiting example, as shown in FIG. 3B, the two OD regions 104 are connected to the POLY line 102_4 by contact vias 128, and the drain of the PMOS device 120 (eg, PMOS-3) is connected to the NMOS device 122 (eg, : NMOS-1) bungee. The drain of the PMOS device 120 (PMOS-3) is formed in the corresponding OD region 104_1. The drain of the NMOS device 120 (for example, PMOS-3) is formed in the corresponding OD region 104_1. The drain of the NMOS device 122 (NMOS-1) is formed in the corresponding OD region 104_6. In some embodiments, the POLY lines 102_3 and 102_5 carry the input signals to the gates of PMOS-3 and NMOS-1, respectively. The POLY lines 102_3 and 102_5 can also be connected by a connecting line (not shown) so that the two devices can share the same input. In this manner, PMOS-3 and NMOS-1 can be formed into CMOS device 130 by connecting their drains and connecting their gate inputs. The source of the PMOS-3 device and the source of the NMOS-1 device are insulated from each other by a corresponding CPO 118. The source of the PMOS-3 device is formed on the OD above the PMOS-4 device Area 104_1. The source of the NMOS-1 device is formed in the OD region 104_6 below the NMOS-1 device. In some embodiments, the source of PMOS-3 and the source of NMOS-1 are coupled to VDD and VSS, respectively, through conductive line segments or lines (not shown). Additional CMOS devices 130 may be formed in a similar manner between other pairs of PMOS devices 120 and NMOS devices 122 (eg, PMOS-4 and NMOS-2). Additionally, it is understood that different connections between the PMOS device 120 and the drain, source, and/or gate of the NMOS device 122 can form different forms of CMOS devices as desired.

4A-4B show different development views of another embodiment of the layout of the component cells of FIGS. 3A-3B to illustrate how two or more PMOS devices can be connected in parallel to form one Larger PMOS devices, and how two or more NMOS devices can be connected together in parallel to form a larger NMOS device. The POLY lines 102_1 to 102_7 and the OD areas 104_1 to 104_8 in FIGS. 4A to 4B are the same as those shown in FIGS. 3A to 3B. Figure 4A is a layout diagram showing a component cell in accordance with an embodiment. Compared to the layout shown in the example of FIG. 3A, the layout illustrated in FIG. 4A further includes horizontal metal lines 124_1 to 124_6 which are in different metal layers from the vertical metal lines 112, 114 and 116 and can be made of metal. Contact/perforation 126 is connected to vertical metal lines 112, 114, and 116. As shown in FIG. 4A, the metal line 116_1 is connected to the POLY lines 102_2, 102_3, 102_5, and 102_6 through the through holes 126_1 to 126_4, respectively. These POLY lines carry the gates input to the PMOS devices 120 and the NMOS devices 122. As such, all PMOS devices 120 and NMOS devices 122 share the same input. Similarly, the metal line 116_2 passes through the through hole 126_5 to 126_8 connects the horizontal metal lines 124_1, 124_3, 124_4, and 124_6, respectively. In some embodiments, these horizontal metal lines carry output from the PMOS device 120 and the drain of the NMOS device 122 in accordance with circuit design/layout rules. As such, all PMOS devices 120 and NMOS devices 122 share the same output. The horizontal metal lines 124_2 and 124_5 are connected to VDD and VSS through the vertical metal line 112 and the vertical metal line 114, respectively. CPOs (Cut-POLYs) 118 are used to terminate a particular POLY line 102 that is shared by multiple devices. Since the plurality of PMOS devices 120 and NMOS devices 122 now share the same input, Figures 4A and 4B require a smaller number of CPOs (4 CPOs) than the examples of Figures 3A-3B (8 CPOs). ).

Figure 4B shows a plurality of PMOS devices 120 and NMOS devices 122 implemented (and staggered) in the component cell, plus the POLY line 102, the fin OD region 104, and the cut POLYs 118 in Figure 4A. In some embodiments, the drains of two or more PMOS devices (eg, PMOS-3 and PMOS-4) formed in their respective fin OD regions 104_1 and 104_3 may be perforated through the contact via the POLY line 102_4. The 128s are electrically coupled to each other such that the PMOS devices share the same drain (the source of which can be connected to the VDD via, eg, the horizontal metal line 124_2 shown in FIG. 4A). Since PMOS devices 120 also share the same inputs and outputs, as discussed above for Figure 4A, they are now connected in parallel (that is, they share the same source, drain/output, and gate/input). To form a larger PMOS device 132. The width of the PMOS device 132 is several times the width of a single PMOS device 120. Note that it is replaced In various embodiments, various alternative connections between PMOS device 120 and NMOS device 122 may be substituted for circuits and/or devices as desired, which are different than the particular connections depicted in FIG. 4B. For example, the drains of additional PMOS devices (eg, PMOS-1 and PMOS-2 and/or additional PMOS devices not shown) can also be coupled through additional (plural) connection components (not shown). The drains to PMOS-3 and PMOS-4 allow all PMOS devices to share the same drain.

For example, in one embodiment, by extending the length of the OD region 104_2 under the POLY line 102_3, or alternatively by providing a conductive line segment (not shown) to electrically connect the POLY line 102_3 to 102_4, The drain of PMOS-1 can be connected to the drains of PMOS-3 and PMOS-4. The drain of the PMOS-1 is formed in the lower half of the fin OD region 104_2 crossing the POLY line 102_3. In this example, since the drain of PMOS-1 is also connected to the gates of PMOS-3 and PMOS-4, the drain of PMOS-1 is connected to the gate of PMOS-3 and PMOS-4. The drain of 3 is connected to the gate, and the drain of PMOS-4 can also be connected to the gate, so that PMOS-3 and PMOS-4 act as diodes. If such a diode configuration is not required, a dicing-POLY 118 (not shown) may be formed around the intersection of the OD region 104_2 and the POLY line 102_3 to insulate the PMOS-1 gate from the PMOS-3 gate. With the gate of PMOS-4, so that the gate of PMOS-1 and the gate of PMOS-4 are not connected to their respective drains, the drain of PMOS-1 is connected to the PMOS-3. Extremely poles with PMOS-4. Similarly, the drain of PMOS-2 is formed in the fin OD region crossing the POLY line 102_3. The lower half of the field 104_4. The PMOS-2 drain can be connected by extending the length of the OD region 104_4 under the POLY line 102_3, or alternatively by connecting a POLY line 102_3 to the POLY line 102_4 by providing a wire segment (not shown). The drain to PMOS-3 and PMOS-4. Note that, as shown in FIG. 4B, the drain of the PMOS-2 is insulated from the gates of the PMOS-3 and the PMOS-4 by the cut-POLY 118 at the intersection of the POLY line 102_3 around the fin OD region 104_4. Thus, the drain connecting PMOS-2 to PMOS-3 and the drain of PMOS-4 does not connect PMOS-3 to the diode configuration with the corresponding drain and gate of PMOS-4. The above discussion describes only exemplary connections, which may vary depending on various alternative embodiments. It is to be understood that the various embodiments are not limited to the specific connections described above or are not limited to those shown in FIG. 4B.

Similarly, two or more NMOS devices 122 may also be connected in parallel to form a larger NMOS device 134 in a manner similar to the PMOS device 120 discussed above. In some embodiments, the POLY line 102_4 connects the fin OD regions 104_1, 104_3, 104_6, and 104_8. The drain of PMOS device 120 and the drain of NMOS device 122 are formed by vias 128 such that all PMOS devices 120 and all NMOS devices 122 share the same drain. As a result, the two larger PMOS devices 132 and NMOS devices 134 can form a CMOS device 136 having the same inputs and outputs with their drains connected together.

In addition to occupying too much space in the component grid, the example of the layout of the component grids depicted in Figures 1A-1B may encounter another problem. this The cause of the problem is that the fin-shaped OD regions 104 are arranged horizontally to each other in an extremely close manner. The pitch of the fin OD regions 104 is too small for different elements in the component cell to be cut or separated.

Figs. 5A to 5B are diagrams showing different developments of an example of the layout of the component cell of Fig. 1A for solving the above problem. The width of the component grid is defined by the pitch X of the POLY line 102. Figure 5A is a layout showing the component grid in accordance with some embodiments. In this example, the POLY lines 102_1 to 102_4 are vertically arranged and equally spaced, and the plurality of fin OD areas are in two adjacent groups (104_1, 104_3, 104_5, and 104_7) and (104_2, 104_4, 104_6, and 104_8) Configurations, each of which is staggered and horizontally spaced apart from each other by a distance (eg, pitch 2Y) as shown in FIG. 5A. With the fin-type OD region 104 having such horizontal displacement, gap/separation at a position along the horizontal direction between any two similar fin-shaped OD regions (eg, 104_1 and 104_3, or 104_2 and 104_4) At least 2Y instead of Y, as shown in Figure 5A. Since there is more space between the fin OD regions (eg, 104_1 and 104_3), the CPO 118 is disposed in this space between the fin OD regions to cut the POLY line (eg, 102_2) into a plurality of unconnected Fragments are possible. The POLY line (e.g., 102_2) is shared by a plurality of PMOS devices 120 or a plurality of NMOS devices 122. As shown in FIG. 5A, such horizontal displacement of the fin OD region 104 does not cause an increase in the width of the component grid defined by the pitch of the POLY line 102, and is equal to 3X as shown in FIG. 5A, which is the same as The width of the layout in Figure 1A.

Figure 5B shows PMOS/NMOS device 120/122 and additional POLY line 102, fin OD area 104 as shown in Figure 5A, and Cut-POLY118. As shown in FIG. 5B, each of the PMOS device 120 and the NMOS device 122 has its gate, source, and drain. The gate is connected to one of the POLY lines (for example: 102_2 and 102_3, respectively). The source and the drain are formed in one of the fin-shaped OD regions 104_1 to 104_8. In some embodiments, the OD regions formed by the drains of the PMOS and the NMOS are connected by the POLY lines 102_1 and 102_4, respectively. Cut-POLYs (CPOs) 118 cut the POLY line 102_1 shared by a plurality of PMOS or NMOS devices into a plurality of line segments such that each PMOS device 120 or NMOS device 122 becomes a separate device. The standalone device has its own line of diagonal lines for the input signal. In some embodiments, one or more PMOS devices 120 (eg, PMOS-3) and one or more NMOS devices 122 (eg, NMOS-1) can be connected together to form one CMOS device 130. For a non-limiting example, as shown in FIG. 5B, by connecting the two OD regions 104_3 and 104_5 to the POLY line 102_1 through the contact via 128, the PMOS device 120 (eg, PMOS-3) is formed at the corresponding OD. The drain of the region 104_3 is connected to the drain of the NMOS device 122 (eg, NMOS-1) formed in the corresponding OD region 104_5. In addition, in some embodiments, the PMOS-1 and the drains of the NMOS-3 in FIG. 5B are also connected to each other and connected to the PMOS-3 by correspondingly connecting the fin OD region 104_1 to the POLY line 102_1 at 104_7. And the NMOS-1 bungee.

In some embodiments, the line segments of the POLY line 102_2 carry the input signals to the gates of PMOS-3 and NMOS-1, respectively. The line segment of the POLY line 102_2 can also be connected through the connecting line segment (picture position), so that two Devices can share the same input. In this way, the PMOS-3 is connected to the drain of NMOS-1 through the connection line segment (not shown), the PMOS-3 is connected to the gate input of NMOS-1, and the PMOS-3 is connected. The sources of NMOS-1 are connected to VDD and VSS, respectively, and PMOS-3 and NMOS-1 can form a CMOS device 130. Additional CMOS devices 130 may be formed in a similar manner to other pairs of PMOS devices 120 and NMOS devices 122 (eg, PMOS-4 and NMOS-2). As discussed above with respect to FIGS. 3B and 4B, in accordance with various alternative embodiments, two or more PMOS devices 120 may be connected to each other, and two or more NMOS devices 122 may be connected to each other, or one or More PMOS devices can be connected to one or more NMOS devices 122 to create various types of CMOS devices and circuits in a variety of ways. It is to be understood that the various embodiments are not limited to the specific exemplary connections discussed or illustrated herein.

Figures 6A-6B show various developments of another embodiment of the layout of the elements in Figures 5A-5B, showing how two or more PMOS devices are connected together in a parallel manner to form a larger PMOS. The device, and how two or more NMOS devices are connected together in a parallel manner to form a larger NMOS device. The layout of the POLY lines 102_1 to 102_4 and the OD areas 104_1 to 104_8 in FIGS. 6A to 6B is the same as that shown in FIGS. 5A to 5B. Figure 6A shows a layout of the component cells in accordance with an embodiment. Compared to the layout of the example of FIG. 5A, the layout illustrated in FIG. 6A further includes vertical metal lines 116_1 to 116_5 located on the metal layer different from the horizontal metal line 124 and can be connected to the via/perforation 126 to Level Metal line 124 and POLY line 102. As shown in FIG. 6A, the metal line 124_5 is connected to the POLY lines 102_2 and 102_3 through the vias 126, which carry the gates input to the PMOS device 120 and the gates of the NMOS device 122. As such, PMOS device 120 and NMOS 122 share the same input. Similarly, the vertical metal line 116_5 is connected to a horizontal metal line (eg, one or more of 124_2 to 124_4 and 124_6 to 124_8). The horizontal metal lines carry the output from the drain of the PMOS device 120 and the drain of the NMOS device 122. As such, PMOS device 120 and NMOS device 122 can share the same output/drain. The horizontal metal lines 124_1 to 124_9 are connected to the VDD vertical metal lines 116_1/116_2 and the VSS vertical metal lines 116_3/116_4, respectively. Cut-POLYs 118 is utilized to cut off the POLY line 102_1 or 102_2 shared by a plurality of devices. Since multiple PMOS devices 120 and/or multiple NMOS devices 122 now share the same input, the examples of Figures 6A-6B require a smaller number of CPOs 118 than the examples of Figures 5A-B (8 CPOs). 2 CPO).

Figure 6B shows a plurality of PMOS/NMOS devices additionally with a POLY line 102, a fin OD region 104, a cut POLY 118, and a vertical metal line 116 as shown in Figure 6A. In some embodiments, the drains of the two or more PMOS devices (eg, PMOS_1 and PMOS_3) formed in the respective fin OD regions 104_1 and 104_3 can be electrically coupled to each other through the contact via 128 through the POLY line 102_1. So that the PMOS devices share the same drain. As discussed above in relation to Figure 5B, its source is connected to VDD. Since the PMOS devices 120 also share the same input/gate and output/drain, as described above in relation to FIG. The PMOS devices 120 are now connected in a parallel manner (that is, they share the same source, drain/output, and gate/input) to form a larger PMOS device 132. The width of the PMOS device 132 is many times the width of a single PMOS device 120. The NMOS devices 122 can also be connected in a similar manner and in a parallel manner to form a larger NMOS device 134. In some embodiments, the POLY line 102_1 is connected to the fin OD region (eg, 104_1, 104_3, 104_5 to 104_7), wherein the drains of the PMOS devices are connected together by the contact vias 128 such that the devices share the same Bungee jumping. As such, the two larger PMOS devices 132 and NMOS devices 134 can form a CMOS device 136 having the same input and output with their drains connected together.

Figure 7 is a flow diagram of a method 700 for forming a cell, the width of the cell being defined by the pitch of the fin OD region rather than the POLY line. Although the reference symbols of the elements shown in FIGS. 2A to B and 3A to B are used in the following non-limiting examples to describe the steps in FIG. 7, the method 700 is not limited to these examples or is not limited. The specific order of these steps.

At step 702, a plurality of polycrystalline germanium (POLY) lines 102 are formed in the element grid, and the POLY lines 102 are horizontally formed and equally spaced by a pitch X.

At step 704, a plurality of fin-shaped oxidized diffusion (OD) regions 104 are formed on the element grid, and fin-shaped OD regions 104 are formed vertically and equally spaced by a pitch Y. The pitch Y of the fin OD region 104 defines the width of the component grid.

At step 706, at least a portion of the vertically formed fin OD regions 104 are vertically offset along a same location in the horizontal direction.

At step 708, a plurality of PMOS transistors 120 and NMOS transistors 122 are formed in the cell. The PMOS transistor 120 and the NMOS transistor 122 have their source node, drain node, and gate. A source node and a drain node of the PMOS 120 transistor and the NMOS transistor 122 are formed in the fin OD region 104. The PMOS 120 transistor and the gate of NMOS transistor 122 are connected to respective POL line 102.

At step 710, the PMOS transistors 120 and the NMOS transistors 122 are coupled together to form one or more CMOS devices in the component cell.

In some embodiments, a component cell structure includes a plurality of polycrystalline (POLY) lines in a cell and a plurality of fin oxidized diffusion (OD) regions in the cell. The polysilicon lines are arranged in a first direction and are evenly spaced at a first pitch. The fin-shaped oxidized diffusion regions are arranged in the second direction and are equally spaced at the second pitch. The second pitch of the fin-shaped oxidized diffusion region defines the width of the component grid. The component cell structure further includes a plurality of PMOS transistors and NMOS transistors in the cell. The PMOS transistors and NMOS transistors have a source node and a drain node formed in the fin-shaped oxide diffusion region, and a gate connected to the corresponding polysilicon line. The PMOS transistors are coupled to an NMOS transistor to form one or more CMOS devices in the component cell.

In some embodiments, the second pitch of the fin OD region is less than the first pitch of the POLY line.

In some embodiments, the width of the component grid is determined by the second pitch of the fin OD region multiplied by the number of fin OD regions in the component cell.

In some embodiments, the height of the component grid is predetermined.

In some embodiments, at least a portion of the fin OD regions are staggered in the second direction at the same location in the first direction.

In some embodiments, each CMOS device is connected to a drain of at least one PMOS device and a drain of at least one NMOS device, and a gate input connected to the at least one PMOS device and the at least one NMOS device Formed by a gate input.

In some embodiments, the component cell structure further comprises at least one POLY wire cutting component. The POLY wire cutting element is configured to cut at least one of the plurality of POLY lines such that at least one PMOS device or NMOS device becomes a separate device in the component cell. The POLY line is shared by multiple PMOS or NMOS devices.

In some embodiments, two or more PMOS devices are connected in parallel to form one larger PMOS device. Two or more NMOS devices are connected in parallel to form one larger NMOS device.

In some embodiments, the parallel connected PMOS devices and NMOS devices form a larger CMOS device.

In some embodiments, a component cell structure includes a plurality of polycrystalline (POLY) lines in a cell and a plurality of fin oxidized diffusion (OD) regions in the cell. The polysilicon lines are arranged in a second direction and are evenly spaced at a first pitch. The fin-shaped oxidized diffusion regions are arranged in a first direction and are equally spaced at a second pitch. Adjacent fin-shaped oxidized diffusion regions are staggered and horizontally spaced apart from one another. The component cell structure further includes a plurality of PMOS transistors and NMOS transistors in the cell. The PMOS transistors and The NMOS transistor has a source node and a drain node formed in the fin-shaped oxide diffusion region, and a gate connected to the corresponding polysilicon line. The PMOS transistors and NMOS transistors are connected together to form one or more CMOS devices in the cell.

In some embodiments, the space between any two of the closest fin OD regions at any point in the first direction is at least twice the second pitch.

In some embodiments, one or more POLY wire cutting elements are disposed between the two closest fin OD regions and are used to cut the POLY shared by the plurality of PMOS devices or NMOS devices such that the devices Become a completely separate device.

In some embodiments, two or more PMOS devices are connected together to form one larger PMOS device. Two or more NMOS devices are connected in parallel to form one larger NMOS device.

In some embodiments, the parallel connected PMOS devices and NMOS devices form a larger CMOS device.

In some embodiments, a method includes forming a plurality of polycrystalline (POLY) lines in a cell and forming a plurality of fin-shaped oxidized diffusion (OD) regions in the cell. The polysilicon lines are arranged in a first direction and are evenly spaced at a first pitch. The fin-shaped oxidized diffusion regions are arranged in the second direction and are equally spaced at the second pitch. The second pitch of the fin-shaped oxidized diffusion region defines the width of the cell, and the second pitch of the fin-shaped oxidized diffusion region is less than the first pitch of the POLY line. The method further includes forming a plurality of PMOS transistors and NMOS transistors in the component grid and connecting the PMOS transistors The NMOS transistor is formed to form a plurality of CMOS devices separated in the cell. The PMOS transistors and NMOS transistors have a source node and a drain node formed in the fin-shaped oxide diffusion region, and a gate connected to the corresponding polysilicon line.

In some embodiments, the method further comprises determining the width of the component grid by multiplying the second pitch of the fin OD region by the number of fin OD regions in the component cell.

In some embodiments, the method further comprises: staggering at least a portion of the fin OD regions in the second direction at the same location in the first direction.

In some embodiments, the method further includes: connecting a corresponding gate input of the at least one PMOS device with a corresponding gate input of the at least one NMOS device, and connecting a corresponding drain node of the at least one PMOS device with the At least one corresponding gate buck node of the NMOS device.

In some embodiments, the method further comprises: forming at least one POLY wire cutting element. The POLY wire cutting element is used to cut at least one of the POLY wires. The POLY line is shared by a plurality of PMOS or NMOS devices such that at least one of the PMOS or NMOS devices becomes a separate device in the component cell.

In some embodiments, the method further includes: connecting the inputs of the PMOS devices in a parallel manner and connecting the outputs of the PMOS devices in a parallel manner to form a larger PMOS device; connecting the plurality of PMOS devices in a parallel manner The inputs of the NMOS devices and the outputs of the NMOS devices are connected in a parallel manner to form a larger NMOS device.

Although the present disclosure has been described in terms of exemplary embodiments, the disclosure is not limited thereto. Rather, the scope of the appended claims may be broadly interpreted by those of ordinary skill in the art without departing from the scope of the disclosure and the scope of the disclosure.

102‧‧‧Polyline

104‧‧‧Fin-shaped oxidized diffusion zone

106‧‧‧N type materials

108‧‧‧P type material

109‧‧‧ separate line

X‧‧‧ pitch

Y‧‧‧ pitch

Claims (1)

A component cell structure comprising: a plurality of polycrystalline (POLY) lines in the cell, wherein the polysilicon lines are arranged in a first direction and equally spaced by a first pitch; a plurality of cells are in the cell a fin-shaped oxidized diffusion (OD) region, wherein the fin-shaped oxidized diffusion regions are disposed in a second direction and are equally spaced by a second pitch, wherein the second pitch definition of the fin-shaped oxidized diffusion regions a width of the cell; and a plurality of P-type metal oxide semiconductor (PMOS) transistors and N-type metal oxide semiconductor (NMOS) transistors in the cell, wherein the P-type metal oxide semiconductors The crystal and the N-type metal oxide semiconductor transistors have a source node and a drain node formed in the corresponding fin-shaped oxide diffusion region, and a gate connected to the corresponding polysilicon line, wherein the P-type metal oxide A semiconductor transistor is coupled to the N-type metal oxide semiconductor transistors to form one or more complementary metal oxide semiconductor (CMOS) devices in the cell.