TW201711161A - An electrical fuse and making method thereof - Google Patents

An electrical fuse and making method thereof Download PDF

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TW201711161A
TW201711161A TW104129827A TW104129827A TW201711161A TW 201711161 A TW201711161 A TW 201711161A TW 104129827 A TW104129827 A TW 104129827A TW 104129827 A TW104129827 A TW 104129827A TW 201711161 A TW201711161 A TW 201711161A
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layer
metal
electrical fuse
doped
metal layer
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TW104129827A
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TWI666756B (en
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杜懷甫
翁彰鍵
李崇銘
白啟宏
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聯華電子股份有限公司
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Abstract

The present invention provides an electrical fuse structure comprises: a substrate; a doping layer on the substrate; a isolation structure in-between the doping layer; a silicide layer on the doping layer; a pure metal layer on the isolation structure; a first metal layer on a side of the silicide layer; a second metal layer on the other side of the silicide layer; a first contact plug electrically connected to the side of the silicide layer and the first metal layer; and a second contact plug electrically connected to the other side of the silicide layer and the second metal layer. The present invention also provides a making method thereof.

Description

一種電熔絲結構及其製造方法 Electric fuse structure and manufacturing method thereof

本發明是有關於一種電熔絲結構及其製造方法,尤其是關於一種具有良好熔斷效果之電熔絲結構及其製造方法。 The present invention relates to an electrical fuse structure and a method of fabricating the same, and more particularly to an electrical fuse structure having a good fuse effect and a method of fabricating the same.

在製造半導體裝置時,執行在晶圓表面形成導電性膜,藉微影、蝕刻等形成佈線層之製程、佈線層上形成層間絕緣膜之製程等,透過這些製程,在晶圓表面產生由金屬等之導電體或絕緣體構成之凹凸。近年來,以半導體積體電路之高密度化為目的,佈線微細化或多層佈線化正進展中,但就因如此,將晶圓表面之凹凸平坦化之技術漸趨重要。 In the manufacture of a semiconductor device, a process of forming a conductive film on a surface of a wafer, a process of forming a wiring layer by lithography, etching, or the like, and a process of forming an interlayer insulating film on a wiring layer are performed, and a metal is generated on the surface of the wafer through these processes. Concavities and convexities formed by electric conductors or insulators. In recent years, in order to increase the density of semiconductor integrated circuits, wiring is becoming finer or multilayer wiring is progressing. However, the technique of flattening the unevenness on the surface of wafers is becoming more and more important.

一般來說隨著半導體製程的微小化以及複雜度的提高,半導體元件也變得更容易受各式缺陷或雜質所影響,因此在製作金屬連線、二極體或電晶體元件之外,還會額外在積體電路中形成一些可熔斷的連接線(fusible links),也就是電熔絲(efuse),以確保積體電路的可利用性。 In general, as semiconductor processes become more compact and more complex, semiconductor components become more susceptible to various types of defects or impurities, so in addition to metal wiring, diodes or transistor components, Additional fusible links, ie, efuse, are formed in the integrated circuit to ensure the availability of the integrated circuit.

電熔絲之應用例如可以連接積體電路中的冗餘電路(redundancy circuit),一旦檢測發現電路具有缺陷時,這些連接線就可用於修復(repairing)或取代有缺陷的電路。以記憶體(memory)的結構為例,習知製程會於結構的最上層製作 一些熔絲的結構,其作用在於當記憶體完成時,若其中有部分記憶胞、字元線(word line)或導線之功能有問題時,就可以利用熔絲跳接另一些冗餘的(redundant cells)的記憶胞、字元線或導線來取代之。另外,目前的熔絲設計更可以提供程式化(programming elements)的功能,以使各種客戶可依不同的功能設計來程式化電路。例如,為了節省研發與製作成本,晶圓廠便可以利用金屬連線與記憶陣列內每個電晶體相連接,並在連接線中增加一個程式化連結性元件,待半導體晶片製作完成後,再由外部進行資料輸入,以獨特化各個標準晶片成各式產品晶片。 The application of the electric fuse can, for example, be connected to a redundancy circuit in the integrated circuit, and these connections can be used to repair or replace the defective circuit once the circuit is found to be defective. Taking the structure of the memory as an example, the conventional process will be made on the top layer of the structure. The structure of some fuses, when the memory is completed, if some of the memory cells, the word line or the function of the wires have problems, the fuses can be used to jump to other redundant ones ( Replace cells, memory cells, word lines or wires to replace them. In addition, the current fuse design can provide programming elements, so that various customers can program the circuit according to different functions. For example, in order to save R&D and manufacturing costs, the fab can use metal wires to connect to each transistor in the memory array and add a stylized connectivity component to the cable. After the semiconductor wafer is fabricated, Data input is performed externally to uniqueize each standard wafer into a variety of product wafers.

以目前應用來說,晶片會在低電壓的環境下進行操作,如何在低電壓操作下使晶片電熔絲使用時能否具有適當的電阻值,並且在熔斷(blow)時是否能有效阻斷電路,對於產品的效能與應用有著絕對的關係。而以目前習知的製程與結構來看,尚有需要改善的地方。 In the current application, the chip will operate in a low voltage environment, how to make the chip electric fuse use appropriate resistance value under low voltage operation, and whether it can effectively block when it is blown. Circuits have an absolute relationship with the performance and application of the product. From the current well-known process and structure, there is still room for improvement.

本發明提供一種電熔絲結構,包含:基材;摻雜層,位於基材上;隔離結構,位於基材上與摻雜層之間;金屬矽化物層,位於摻雜層上;純金屬層,位於隔離結構上;第一金屬層,位於金屬矽化物層之第一側上;第二金屬層,位於金屬矽化物層之遠離第一側之第二側上,其中第一側與第二測係以純金屬層分界;第一接觸插塞,位於第一金屬層與金屬矽化物層之間,電性連接金屬矽化物層之第一側與第一金屬層;以及第二接觸插塞,位於第一金屬層與金屬矽化物層之間,電性連接金屬矽化物層之第二側與第二金屬層。 The present invention provides an electrical fuse structure comprising: a substrate; a doped layer on the substrate; an isolation structure between the substrate and the doped layer; a metal telluride layer on the doped layer; a layer on the isolation structure; a first metal layer on the first side of the metal telluride layer; and a second metal layer on the second side of the metal telluride layer away from the first side, wherein the first side The second test system is delimited by a pure metal layer; the first contact plug is located between the first metal layer and the metal telluride layer, electrically connecting the first side of the metal telluride layer and the first metal layer; and the second contact plug Between the first metal layer and the metal telluride layer, electrically connecting the second side of the metal telluride layer and the second metal layer.

在本發明的較佳實施例中,上述之基材包含元件 層以及氧化層,位於元件層上、元件層與摻雜層之間。 In a preferred embodiment of the invention, the substrate comprises a component The layer and the oxide layer are located on the element layer, between the element layer and the doped layer.

在本發明的較佳實施例中,上述之摻雜層可以包含不同之摻雜型。 In a preferred embodiment of the invention, the doped layers described above may comprise different doping types.

在本發明的較佳實施例中,上述之摻雜層之不同摻雜型分別位於隔離結構靠近第一接觸插塞之部分摻雜層,以及位於隔離結構靠近第二接觸插塞之間之部分摻雜層。 In a preferred embodiment of the present invention, the different doping types of the doped layers are respectively located in a portion of the doping layer of the isolation structure close to the first contact plug, and a portion between the isolation structure and the second contact plug. Doped layer.

在本發明的較佳實施例中,上述之純金屬層僅覆蓋隔離結構。 In a preferred embodiment of the invention, the pure metal layer described above covers only the isolation structure.

在本發明的較佳實施例中,上述之純金屬層覆蓋隔離結構以及部分金屬矽化物層。 In a preferred embodiment of the invention, the pure metal layer described above covers the isolation structure and a portion of the metal halide layer.

在本發明的較佳實施例中,上述之純金屬層所含之金屬成分與金屬矽化物層所含之金屬成分相同。 In a preferred embodiment of the invention, the metal component contained in the pure metal layer is the same as the metal component contained in the metal telluride layer.

在本發明的較佳實施例中,上述之第一接觸插塞為單數個,且第二接觸插塞為複數個。 In a preferred embodiment of the invention, the first contact plugs are singular and the second contact plugs are plural.

在本發明的較佳實施例中,上述之金屬矽化物層與金屬層共同形成電熔絲,並且電熔絲僅覆蓋部分之摻雜層。 In a preferred embodiment of the invention, the metal halide layer and the metal layer together form an electrical fuse, and the electrical fuse covers only a portion of the doped layer.

在本發明的較佳實施例中,上述之金屬矽化物層與金屬層共同形成電熔絲,並且電熔絲完整覆蓋摻雜層。 In a preferred embodiment of the invention, the metal halide layer and the metal layer together form an electrical fuse, and the electrical fuse completely covers the doped layer.

在本發明的較佳實施例中,上述之電熔絲結構還包含外側隔離結構,位於該基材上、該摻雜層之相對兩側。 In a preferred embodiment of the invention, the electrical fuse structure further includes an outer isolation structure on the substrate and opposite sides of the doped layer.

本發明還提供一種電熔絲結構的製造方法,步驟包含:提供基材;形成摻雜層與隔離結構於基材上,其中隔離結構位於摻雜層之間;形成純金屬層於隔離結構上與金屬矽化物層於摻雜層上;形成第一接觸插塞與第二接觸插塞,分別電性連結於金屬矽化物層之第一側與遠離第一側之一第二側,其中第一側與第二側以隔離結構做分界;以及形成第一金屬層與第二金屬層,其中第一接觸插塞電性連接金屬矽化物層之第一側與第一金屬層,第二接觸插塞電性連接金屬 矽化物層之第二側與第二金屬層。 The invention also provides a method for manufacturing an electric fuse structure, the method comprising: providing a substrate; forming a doping layer and an isolation structure on the substrate, wherein the isolation structure is located between the doped layers; forming a pure metal layer on the isolation structure And forming a first contact plug and a second contact plug electrically connected to the first side of the metal telluride layer and the second side away from the first side, wherein The first side and the second side are separated by an isolation structure; and the first metal layer and the second metal layer are formed, wherein the first contact plug electrically connects the first side of the metal telluride layer with the first metal layer, and the second contact Plug electrical connection metal a second side of the telluride layer and a second metal layer.

在本發明的較佳實施例中,上述之基材包含元件層以及氧化層,形成於元件層上、元件層與摻雜層之間。 In a preferred embodiment of the invention, the substrate comprises an element layer and an oxide layer formed on the element layer, between the element layer and the doped layer.

在本發明的較佳實施例中,上述之摻雜層之形成方法,包含步驟:形成多晶矽層於基材上;圖案化多晶矽層,形成一具有一暴露基材之開口之圖案化多晶矽層;以及對圖案化多晶矽層進行離子佈植步驟。 In a preferred embodiment of the present invention, the method for forming a doped layer includes the steps of: forming a polysilicon layer on a substrate; patterning the polysilicon layer to form a patterned polysilicon layer having an opening exposing the substrate; And performing an ion implantation step on the patterned polysilicon layer.

在本發明的較佳實施例中,上述之離子佈植步驟包含:進行第一離子佈植步驟,使第一部份之該摻雜層為第一摻雜型;以及進行第二離子佈植步驟,使第二部份之該摻雜層為第二摻雜型。 In a preferred embodiment of the present invention, the ion implantation step includes: performing a first ion implantation step to make the first portion of the doped layer a first doped type; and performing a second ion implantation In the step, the doped layer of the second portion is of a second doping type.

在本發明的較佳實施例中,上述之第一部份係位於摻雜層之第一側與開口之間,第二部份係位於摻雜層之第二側與開口之間。 In a preferred embodiment of the invention, the first portion is between the first side of the doped layer and the opening, and the second portion is between the second side of the doped layer and the opening.

在本發明的較佳實施例中,上述之摻雜層含矽,並且形成純金屬層與金屬矽化物層之方法包含步驟:沉積形成原金屬層於摻雜層與隔離結構上;以及進行熱處理步驟,使位於摻雜層上之部分原金屬層與摻雜層中之矽反應,形成金屬矽化物層,並且同時形成該純金屬層於隔離結構上。 In a preferred embodiment of the present invention, the doped layer contains germanium, and the method of forming a pure metal layer and a metal germanide layer comprises the steps of: depositing a raw metal layer on the doped layer and the isolation structure; and performing heat treatment The step of reacting a portion of the original metal layer on the doped layer with the germanium in the doped layer to form a metal germanide layer and simultaneously forming the pure metal layer on the isolation structure.

在本發明的較佳實施例中,上述之摻雜層含矽,並且形成純金屬層與金屬矽化物層之方法包含步驟:沉積形成原金屬層於摻雜層與隔離結構上;進行熱處理步驟,使位於摻雜層上之部分原金屬層與摻雜層中之矽反應,形成金屬矽化物層;移除未反應之部分原金屬層;以及形成純金屬層覆蓋隔離結構。 In a preferred embodiment of the present invention, the doped layer contains germanium, and the method of forming the pure metal layer and the metal germanide layer comprises the steps of: depositing a raw metal layer on the doped layer and the isolation structure; and performing a heat treatment step And reacting a portion of the original metal layer on the doped layer with the germanium in the doped layer to form a metal germanide layer; removing an unreacted portion of the original metal layer; and forming a pure metal layer to cover the isolation structure.

在本發明的較佳實施例中,上述之形成第一接觸插塞與第二接觸插塞之前,還包含步驟:形成中介層於隔離結構、純金屬層與金屬矽化物層上;蝕刻形成複數個通孔於 中介層中;以及形成第一接觸插塞與第二接觸插塞於複數個通孔中。 In a preferred embodiment of the present invention, before the forming the first contact plug and the second contact plug, the method further comprises the steps of: forming an interposer on the isolation structure, the pure metal layer and the metal telluride layer; and etching to form a plurality Through hole And forming a first contact plug and a second contact plug in the plurality of through holes.

在本發明的較佳實施例中,上述之電熔絲結構的製程方法,其還包含步驟:形成一保護層於該第一金屬層與該第二金屬層上,其中該保護層之材質可以為低常數介電材質或是超低常數介電材質。 In a preferred embodiment of the present invention, the method for manufacturing the electrical fuse structure further includes the steps of: forming a protective layer on the first metal layer and the second metal layer, wherein the material of the protective layer is It is a low constant dielectric material or an ultra low constant dielectric material.

在本發明的較佳實施例中,上述之金屬矽化物層與金屬層共同形成電熔絲,並且電熔絲僅覆蓋部分之摻雜層。 In a preferred embodiment of the invention, the metal halide layer and the metal layer together form an electrical fuse, and the electrical fuse covers only a portion of the doped layer.

在本發明的較佳實施例中,上述之金屬矽化物層與金屬層共同形成電熔絲,並且電熔絲完整覆蓋摻雜層。 In a preferred embodiment of the invention, the metal halide layer and the metal layer together form an electrical fuse, and the electrical fuse completely covers the doped layer.

因此本發明能提供一種電熔絲結構與其製造方法,以提供較佳之熔斷效果。依據本發明提供之電熔絲,能在低電壓操作條件下,尤其是操作電壓介於2.5~3伏特之間時,熔斷後有效避免金屬離子殘留,因此能達到較佳之熔斷效果,使熔斷後電阻值至少大於10,000歐姆(Ω),提供良好之電路阻斷效果。 Accordingly, the present invention can provide an electrical fuse structure and a method of fabricating the same to provide a better fuse effect. The electric fuse provided by the invention can effectively avoid metal ion residual after the low voltage operation condition, especially when the operating voltage is between 2.5 and 3 volts, so that a better melting effect can be achieved, and after the fuse is blown A resistance value of at least 10,000 ohms (Ω) provides good circuit blocking.

1‧‧‧基材 1‧‧‧Substrate

2‧‧‧多晶矽層 2‧‧‧Polysilicon layer

3、31、32‧‧‧隔離結構 3, 31, 32‧‧‧ isolation structure

4、8、81、82‧‧‧金屬層 4, 8, 81, 82‧‧‧ metal layers

5‧‧‧純金屬層 5‧‧‧Pure metal layer

6‧‧‧中介層 6‧‧‧Intermediary

7、71、72‧‧‧接觸插塞 7, 71, 72‧‧‧ contact plugs

9‧‧‧保護層 9‧‧‧Protective layer

11‧‧‧元件層 11‧‧‧Component layer

12‧‧‧氧化層 12‧‧‧Oxide layer

21‧‧‧圖案化多晶矽層 21‧‧‧ patterned polycrystalline layer

22‧‧‧摻雜層 22‧‧‧Doped layer

41‧‧‧金屬矽化物層 41‧‧‧metal telluride layer

H1‧‧‧開口 H1‧‧‧ openings

為讓本發明之上述和其他目的、特徵和優點能更明顯易懂,下文特舉數個較佳實施例,並配合所附圖式,作詳細說明如下:圖1-5係依據本發明一實施例所繪製,製程步驟之剖面結構圖;圖5a係依據本發明之一實施例所繪製,圖6之俯視結構示意圖;圖5b係依據本發明之一實施例所繪製,圖6之俯視結構示意圖;圖6係依據本發明之一實施例所繪製,圖6所示實施例之後 續製程步驟之剖面結構圖;圖6a係依據本發明之一實施例所繪製,圖6所示實施例之後續製程步驟之剖面結構圖;圖6b係依據本發明之一實施例所繪製,圖6所示實施例之後續製程步驟之剖面結構圖;圖6c係依據本發明之一實施例所繪製,圖7之俯視結構示意圖;圖6d係依據本發明之一實施例所繪製,圖7之俯視結構示意圖;圖6e係依據本發明之一實施例所繪製,圖7b之俯視結構示意圖;圖7-10係依據本發明之一實施例所繪製,圖7所示實施例之後續製程步驟之剖面結構圖;圖10a係依據本發明之一實施例所繪製之電熔絲結構剖面示意圖;以及圖10b係依據本發明之一實施例所繪製之電熔絲結構剖面示意圖。 The above and other objects, features, and advantages of the present invention will become more apparent and understood. FIG. 5a is a cross-sectional structural view of a process step; FIG. 5a is a schematic view of a top view of FIG. 6; FIG. 5b is a plan view of FIG. Schematic; FIG. 6 is drawn in accordance with an embodiment of the present invention, after the embodiment shown in FIG. FIG. 6a is a cross-sectional structural view of a subsequent process step of the embodiment shown in FIG. 6; FIG. 6b is drawn according to an embodiment of the present invention; FIG. 6 is a cross-sectional structural view of a subsequent process step of the embodiment shown in FIG. 6; FIG. 6c is a schematic plan view of FIG. 7 according to an embodiment of the present invention; FIG. 6d is drawn according to an embodiment of the present invention, FIG. Figure 6e is a schematic view of a top view of the embodiment of the present invention; Figure 7-10 is a schematic view of the structure of Figure 7b; Figure 7-10 is drawn according to an embodiment of the present invention, and the subsequent process steps of the embodiment shown in Figure 7 FIG. 10a is a schematic cross-sectional view of an electrical fuse structure according to an embodiment of the present invention; and FIG. 10b is a schematic cross-sectional view of an electrical fuse structure according to an embodiment of the present invention.

本發明是在提供一種電熔絲結構與其製造方法,以提供較佳之熔斷效果。依據本發明提供之電熔絲,能在低電壓操作條件下,尤其是操作電壓介於2.5~3伏特之間時,熔斷後有效避免金屬離子殘留,因此能達到較佳之熔斷效果,使熔斷後電阻值至少大於10,000歐姆(Ω),提供良好之電路阻斷效果。為讓本發明之上述和其他目的、特徵和優點能更明顯易懂,下文以實施例配合所附圖式,做詳細說明。 SUMMARY OF THE INVENTION The present invention is directed to an electrical fuse structure and method of making the same to provide a better blown effect. The electric fuse provided by the invention can effectively avoid metal ion residual after the low voltage operation condition, especially when the operating voltage is between 2.5 and 3 volts, so that a better melting effect can be achieved, and after the fuse is blown A resistance value of at least 10,000 ohms (Ω) provides good circuit blocking. The above and other objects, features, and advantages of the present invention will become more apparent and understood.

圖1-10所示為依據本發明一實施例所繪製,不同製 程步驟之剖面結構圖;並且圖5a-5b、圖6a-6e以及圖10a-10b為依據相同製程步驟所提供之不同實施例的剖面與/或俯視結構示意圖。 1-10 illustrate different systems in accordance with an embodiment of the present invention. Cross-sectional structural views of the steps; and Figures 5a-5b, 6a-6e, and 10a-10b are schematic cross-sectional and/or top-rise structural views of different embodiments provided in accordance with the same process steps.

首先,如圖1所示,提供一基材1,並形成一多晶矽層2於基材1上。基材1可以包含元件層11與位於元件層上之氧化層12,而元件層11可以包含複數個電晶體(transistor)、F-RAM或是其他半導體元件。此實施例雖然同時具有元件層11與氧化層12,但於其他實施例中基材1也可以僅包含元件層11。之後如圖2所示,圖案化上述多晶矽層2以形成圖案化多晶矽層21,其具有一暴露基材1之開口H1以使圖案化多晶矽層21分為不同之部分(此實施例如圖2所示,左邊之圖案化多晶矽層21與右邊之圖案化多晶矽層21)。並且開口H1於多晶矽層21中之水平位置可以依據不同實施例做調整,可以較靠近左側或右側,此實施例則是位於約略中間之位置。如圖3所示,於開口H1中形成隔離結構3,並對圖案化多晶矽層21進行離子佈植,以形成摻雜層22。上述離子佈植製程可以進行於隔離結構3形成之前或是之後,並且不同部份之圖案化多晶矽層21可以具有不同之摻雜型或是相同之摻雜型(因情況需求進行一次或多次離子佈植)。在此實施例中使用相同之P摻雜型。接著如圖4所示,於摻雜層22與隔離結構3遠離基材1之表面上形成原金屬層4,原金屬層4可以為鈷(Co)、鎳(Ni)或其他適合之金屬。接著進行熱處理製程,使原金屬層4與下方之摻雜層22中之矽反應,以形成金屬矽化物層41於摻雜層22上,而位於隔離結構3上方之部分原金屬層4則不會反應形成金屬矽化物。此實施利中,該未反應之部分原金屬層4於熱處理製程後,與其餘未反應之原金屬層4被移除,形成如圖5所示之剖面結構,金屬矽化物層41可以包含多個部分之金屬矽化物層41。於其他實施利中,該未反應之部分原金屬層4可以被保留,直接用做部份之電熔絲結構來使用。並且為方便製程,原金屬層4在可以全面 沉積於基材1上,配合不移除未反應之部分原金屬層4的製程選擇下,需移除電熔絲結構以外之部分原金屬層4,僅保留所需導通之部分來形成電熔絲結構。 First, as shown in FIG. 1, a substrate 1 is provided, and a polycrystalline germanium layer 2 is formed on the substrate 1. The substrate 1 may comprise an element layer 11 and an oxide layer 12 on the element layer, and the element layer 11 may comprise a plurality of transistors, F-RAM or other semiconductor elements. Although this embodiment has both the element layer 11 and the oxide layer 12, in other embodiments the substrate 1 may also include only the element layer 11. Thereafter, as shown in FIG. 2, the polysilicon layer 2 is patterned to form a patterned polysilicon layer 21 having an opening H1 exposing the substrate 1 to divide the patterned polysilicon layer 21 into different portions (this embodiment is shown in FIG. Shown, the patterned polycrystalline germanium layer 21 on the left and the patterned polycrystalline germanium layer 21 on the right. Moreover, the horizontal position of the opening H1 in the polysilicon layer 21 can be adjusted according to different embodiments, and can be closer to the left side or the right side. This embodiment is located approximately in the middle. As shown in FIG. 3, an isolation structure 3 is formed in the opening H1, and the patterned polysilicon layer 21 is ion implanted to form a doped layer 22. The ion implantation process may be performed before or after the isolation structure 3 is formed, and different portions of the patterned polysilicon layer 21 may have different doping types or the same doping type (one or more times depending on the situation) Ion implantation). The same P doping type is used in this embodiment. Next, as shown in FIG. 4, a raw metal layer 4 is formed on the surface of the doped layer 22 and the isolation structure 3 away from the substrate 1. The original metal layer 4 may be cobalt (Co), nickel (Ni) or other suitable metal. Then, a heat treatment process is performed to react the original metal layer 4 with the germanium in the underlying doped layer 22 to form the metal germanide layer 41 on the doped layer 22, and a portion of the original metal layer 4 above the isolation structure 3 is not. Will react to form a metal halide. In this implementation, the unreacted portion of the original metal layer 4 is removed from the remaining unreacted primary metal layer 4 after the heat treatment process to form a cross-sectional structure as shown in FIG. 5, and the metal telluride layer 41 may contain more A portion of the metal telluride layer 41. In other implementations, the unreacted portion of the original metal layer 4 can be retained for use as part of the electrical fuse structure. And for the convenience of the process, the original metal layer 4 can be comprehensive Deposited on the substrate 1 in combination with the process of removing the unreacted portion of the original metal layer 4, a portion of the original metal layer 4 other than the electric fuse structure is removed, and only the portion to be turned on is formed to form the fused layer. Silk structure.

前述說明之摻雜層22與金屬矽化物層41係用以電性連接基材1中之不同元件,因此兩者的形狀較佳為長條型,其可以為直線、折線或是曲線等。並且摻雜層22僅覆蓋部份之基材1,而金屬矽化物層41之寬度可以等於或小於摻雜層22之寬度(可使用遮罩或是熱處理後進行移除等方式來調整金屬矽化物層41之寬度)。圖5a-5b為依據本發明不同實施例所繪製,相對應於製程步驟剖面圖圖5之結構俯視圖。本發明之此實施例所形成之金屬矽化物層41完整覆蓋摻雜層22,如圖5a所示;而本發明之另一實施例如圖5b所示,金屬矽化物層41之寬度小於摻雜層22之寬度,亦即金屬矽化物層41僅覆蓋部份之摻雜層22。為簡化說明,將以圖5a之上述實施例進行後續製程說明以及圖式之繪示。 The doped layer 22 and the metal telluride layer 41 described above are used to electrically connect different elements in the substrate 1. Therefore, the shape of both is preferably a strip shape, which may be a straight line, a broken line or a curved line. And the doping layer 22 covers only a part of the substrate 1 , and the width of the metal telluride layer 41 may be equal to or smaller than the width of the doping layer 22 (the mask may be removed by using a mask or heat treatment to adjust the metal deuteration). The width of the object layer 41). Figures 5a-5b are plan views of the structure of Figure 5, taken in accordance with various embodiments of the present invention, corresponding to a cross-sectional view of the process steps. The metal telluride layer 41 formed by this embodiment of the present invention completely covers the doped layer 22, as shown in FIG. 5a; and another embodiment of the present invention, as shown in FIG. 5b, the metal telluride layer 41 has a width smaller than that of the doping. The width of the layer 22, that is, the metal telluride layer 41 covers only a portion of the doped layer 22. In order to simplify the description, the subsequent process description and the drawing of the drawings will be made in the above embodiment of FIG. 5a.

接著如圖6所示,於隔離結構3上形成純金屬層5。純金屬層5之材料可以為鈷(Co)、鎳(Ni)或其他適合之金屬。本發明之上述實施例中,純金屬層5之材料與金屬矽化物層41之金屬成份相同。於本發明另一實施例中,純金屬層5之材料選用適合之任意金屬。另外,純金屬層5覆蓋的範圍可以依需求做調整,只要能將不同部分之金屬矽化物層41做連接,使不同部分之金屬矽化物層41能藉由純金屬層5達到電性連接之效果,純金屬層5與金屬矽化物層41的相對寬度與長度皆可做調整。此實施例中,純金屬層5如圖6所示,僅形成於隔離結構3上,並與金屬矽化物層41相接觸。但依據本發明不同之實施例,純金屬層5在與金屬矽化物41之相同延伸方向上的長度可以做調整。如圖6a所示之本發明一實施例,為確保純金屬層5與金屬矽化物層41之接觸,純金屬層5形成並覆蓋於隔離結構3以及與隔離結構3相鄰之部份金屬矽化物層41上,並且純金屬層5可能因覆蓋之表面不 平整,導致純金屬層5之上表面對應於隔離結構3之部分有些微凹陷;又另一實施例如圖6b所示,純金屬層5形成並完整覆蓋於隔離結構3與金屬矽化物層41上,並且純金屬層5可能因覆蓋之表面不平整,導致純金屬層5之上表面對應於隔離結構3之部分有些微凹陷。此外,形成純金屬層5後可以選擇性地進行一平坦化製程,以使圖6中之純金屬層5與金屬矽化物層41之上表面共平面,或於圖6a與6b所示的實施例中,進行平坦化製程使純金屬層5之上表面平坦化。另一方面,純金屬層5在與金屬矽化物41之延伸方向垂直之方向上的長度(即純金屬層5的寬度)來說,可以小於或等於金屬矽化物層41。本發明之上述實施例中如圖6c所示,純金屬層5僅位於隔離結構3上,並且純金屬層5寬度等於金屬矽化物層41之俯視結構圖;而本發明之其他實施例中,純金屬層5僅位於隔離結構3上,並且如圖6d所示之俯視結構圖,純金屬層5寬度小於金屬矽化物層41;又本發明另一實施例中如圖6e所示,純金屬層5覆蓋於隔離結構3與金屬矽化物層41上,並且寬度小於金屬矽化物層41。其他變化可依本發明提供之概念推知,在此不再做敘述。 Next, as shown in FIG. 6, a pure metal layer 5 is formed on the isolation structure 3. The material of the pure metal layer 5 may be cobalt (Co), nickel (Ni) or other suitable metal. In the above embodiment of the invention, the material of the pure metal layer 5 is the same as the metal composition of the metal telluride layer 41. In another embodiment of the invention, the material of the pure metal layer 5 is selected from any suitable metal. In addition, the coverage of the pure metal layer 5 can be adjusted according to requirements, as long as different portions of the metal telluride layer 41 can be connected, so that different portions of the metal telluride layer 41 can be electrically connected by the pure metal layer 5. As a result, the relative width and length of the pure metal layer 5 and the metal telluride layer 41 can be adjusted. In this embodiment, the pure metal layer 5 is formed only on the isolation structure 3 as shown in FIG. 6, and is in contact with the metal telluride layer 41. However, in accordance with various embodiments of the present invention, the length of the pure metal layer 5 in the same direction of extension as the metal telluride 41 can be adjusted. In an embodiment of the invention as shown in FIG. 6a, in order to ensure the contact of the pure metal layer 5 with the metal telluride layer 41, the pure metal layer 5 is formed and covers the isolation structure 3 and a portion of the metal adjacent to the isolation structure 3 On the object layer 41, and the pure metal layer 5 may not be covered by the surface Flattening, causing the upper surface of the pure metal layer 5 to be slightly recessed corresponding to the portion of the isolation structure 3; yet another embodiment, as shown in FIG. 6b, the pure metal layer 5 is formed and completely covered on the isolation structure 3 and the metal telluride layer 41. And the pure metal layer 5 may be uneven due to the surface of the cover, resulting in a slight depression of the upper surface of the pure metal layer 5 corresponding to the portion of the isolation structure 3. In addition, after forming the pure metal layer 5, a planarization process may be selectively performed to make the pure metal layer 5 in FIG. 6 coplanar with the upper surface of the metal telluride layer 41, or the implementation shown in FIGS. 6a and 6b. In the example, a planarization process is performed to planarize the upper surface of the pure metal layer 5. On the other hand, the length of the pure metal layer 5 in the direction perpendicular to the extending direction of the metal telluride 41 (i.e., the width of the pure metal layer 5) may be less than or equal to the metal telluride layer 41. In the above embodiment of the present invention, as shown in FIG. 6c, the pure metal layer 5 is only located on the isolation structure 3, and the width of the pure metal layer 5 is equal to the top view of the metal halide layer 41. In other embodiments of the present invention, The pure metal layer 5 is only located on the isolation structure 3, and as shown in the top view of FIG. 6d, the pure metal layer 5 has a smaller width than the metal telluride layer 41; and in another embodiment of the invention, as shown in FIG. 6e, the pure metal The layer 5 covers the isolation structure 3 and the metal telluride layer 41 and has a smaller width than the metal halide layer 41. Other variations can be inferred from the concepts provided by the present invention and will not be described herein.

為方便理解,後續製程步驟剖面圖僅以圖6所示之實施例做後續製程的說明,但本案所提供之圖式並非用以限制本發明。在符合本發明概念的前提下,本文所述之元件結構與形狀皆可依需求做適當調整。 For ease of understanding, the subsequent process step profiles are only illustrated by the embodiment shown in FIG. 6, but the drawings provided in the present invention are not intended to limit the present invention. The components and shapes described herein can be appropriately adjusted according to the requirements on the premise of conforming to the concept of the present invention.

如圖7所示,形成中介層6於該金屬矽化物層41與該純金屬層5上,之後如圖8所示,於中介層6中形成複數個接觸插塞7。複數個接觸插塞7中,包含至少一個第一接觸插塞71與至少一個第二接觸插塞72,用以於使用時分別連接陰極與陽極。如圖9所示之實施例,其具有一個第一接觸插塞71用以電性連接陰極,並且具有二個第二接觸插塞72用以電性連接陽極。於本發明其他實施例中,第一接觸插塞71與第二接觸插塞72皆為 複數個,也可以皆為單數個。且為使陰極與陽極之間能形成通路,第一接觸插塞71電性連接於金屬矽化物層41(圖中之左側),第二接觸插塞72電性連接於金屬矽化物層41之遠離第一側之第二側(圖中之右側),其中金屬矽化物層41之第一側與第二側係以純金屬層5做為分界。接觸插塞7形成的方法可以為慣用之做法,例如是先形成中介層6於該隔離結構3、該純金屬5層與該金屬矽化物層41上,之後蝕刻形成複數個通孔於該中介層6中,並且形成第一接觸插塞71與第二接觸插塞72於該複數個通孔中。 As shown in FIG. 7, an interposer 6 is formed on the metal silicide layer 41 and the pure metal layer 5, and then a plurality of contact plugs 7 are formed in the interposer 6 as shown in FIG. The plurality of contact plugs 7 includes at least one first contact plug 71 and at least one second contact plug 72 for respectively connecting the cathode and the anode in use. The embodiment shown in FIG. 9 has a first contact plug 71 for electrically connecting the cathode and two second contact plugs 72 for electrically connecting the anode. In other embodiments of the present invention, the first contact plug 71 and the second contact plug 72 are both A plurality of them can also be singular. In order to form a path between the cathode and the anode, the first contact plug 71 is electrically connected to the metal telluride layer 41 (on the left side in the drawing), and the second contact plug 72 is electrically connected to the metal telluride layer 41. Along from the second side of the first side (the right side in the figure), the first side and the second side of the metal telluride layer 41 are delimited by the pure metal layer 5. The method of forming the contact plug 7 may be a conventional method, for example, first forming an interposer 6 on the isolation structure 3, the pure metal 5 layer and the metal telluride layer 41, and then etching to form a plurality of via holes in the intermediary. In the layer 6, and forming a first contact plug 71 and a second contact plug 72 in the plurality of through holes.

最後如圖9-10所示,圖9中於接觸插塞7上形成金屬層8,其包含第一金屬層81與第二金屬82。第一金屬層81形成於第一接觸插塞71上,以電性連接第一接觸插塞71;並於第二接觸插塞72上形成第二金屬層82,以電性連接第二接觸插塞72。之後如圖10所示,形成保護層9於第一金屬層81、第二金屬層82與中介層6上。上述中介層6與保護層9可依需要使用低介電(low k)或是超低介電(ultra-low k)常數材料。 Finally, as shown in FIGS. 9-10, a metal layer 8 is formed on the contact plug 7 in FIG. 9, which comprises a first metal layer 81 and a second metal 82. The first metal layer 81 is formed on the first contact plug 71 to electrically connect the first contact plug 71, and the second metal layer 82 is formed on the second contact plug 72 to electrically connect the second contact plug. Plug 72. Thereafter, as shown in FIG. 10, a protective layer 9 is formed on the first metal layer 81, the second metal layer 82, and the interposer 6. The interposer 6 and the protective layer 9 may use a low dielectric (low k) or ultra-low k constant material as needed.

本發明所提供之電熔絲係由金屬矽化物層41與純金屬層5共同組成。當提供電壓至本發明提供之電熔絲結構時,因電遷移效用(electromigration)使電熔絲中之金屬離子從陰極被推往陽極,導致電熔絲之電阻值升高,形成斷路。測試結果顯示,金屬矽化物層41形成於摻雜層22上之產品表現優於形成於未摻雜之多晶矽層2上。並且為避免金屬矽化物層41中之金屬離子殘留於摻雜層22上,造成熔斷後可能產生的少量電流導通問題,造成電阻值的下降,摻雜層41中間以隔離結構3做分離,同時形成純金屬層5於隔離結構3上、陰陽極之間,加強電遷移效用所產生的金屬離子推移效果,以確保電熔絲完整熔斷(此處完整熔斷非限定在結構上的斷開,只要熔斷後電阻值能升高到一預設值即可)。 The electric fuse provided by the present invention is composed of a metal telluride layer 41 and a pure metal layer 5. When a voltage is supplied to the electric fuse structure provided by the present invention, metal ions in the electric fuse are pushed from the cathode to the anode due to electromigration, resulting in an increase in the resistance value of the electric fuse to form an open circuit. The test results show that the product in which the metal telluride layer 41 is formed on the doped layer 22 performs better than the undoped polysilicon layer 2. In order to prevent the metal ions in the metal telluride layer 41 from remaining on the doped layer 22, a small amount of current conduction problem may occur after the fuse is caused, causing a decrease in the resistance value, and the doping layer 41 is separated by the isolation structure 3 at the same time. Forming a pure metal layer 5 on the isolation structure 3, between the anode and the cathode, enhancing the metal ion shifting effect produced by the electromigration effect to ensure complete melting of the electric fuse (where the complete fuse is not limited to the structural disconnection, as long as After the fuse, the resistance value can be raised to a preset value).

另外,在實際產品應用上,摻雜層22可能需要與其 他元件隔離,因此還可能包含外側隔離結構,位於摻雜層22兩側,並且寬度上與摻雜層22相同或寬於摻雜層22。如圖10a與10b所是,外側隔離結構31與32位於基材1上、摻雜層22兩側,其形成可以是與隔離結構3同時,因此形成如圖10a所示之外側隔離結構31;於本發明另一實施例中,其可以是形成於金屬矽化物層41形成之後,因此會形成如圖10b所示之外側隔離結構32。外側隔離結構之形成步驟順序可依不同製程做調整,只要其能有效達到隔離摻雜層22之功效,皆不脫離本發明之概念。再者,如前所說明,隔離結構3位於摻雜層22之間之水平位置可以調整,並且考慮電遷移效應以及產生熔斷的可能位置,可以將隔離結構3設置在較靠近陽極之一側。 In addition, in practical product applications, doped layer 22 may need to be The elements are isolated and thus may also comprise outer isolation structures on either side of the doped layer 22 and are the same width or wider than the doped layer 22 in the doped layer 22. 10a and 10b, the outer isolation structures 31 and 32 are located on the substrate 1, on both sides of the doping layer 22, which may be formed simultaneously with the isolation structure 3, thus forming an outer side isolation structure 31 as shown in Figure 10a; In another embodiment of the invention, it may be formed after the formation of the metal telluride layer 41, thus forming an outer side isolation structure 32 as shown in FIG. 10b. The order of forming the outer isolation structure may be adjusted according to different processes, as long as it can effectively achieve the effect of isolating the doped layer 22 without departing from the concept of the present invention. Furthermore, as explained above, the horizontal position of the isolation structure 3 between the doped layers 22 can be adjusted, and the isolation structure 3 can be disposed closer to one side of the anode in consideration of the electromigration effect and the possible position at which the fuse is generated.

本發明是在提供一種電熔絲結構與其製造方法,以提供較佳之熔斷效果。依據本發明提供之電熔絲,能在低電壓操作條件下,尤其是操作電壓介於2.5~3伏特之間時,熔斷後有效避免習知技術中金屬離子殘留,因此能達到較佳之熔斷效果,使熔斷後電阻值至少大於10,000歐姆(Ω),提供良好之電路阻斷效果。 SUMMARY OF THE INVENTION The present invention is directed to an electrical fuse structure and method of making the same to provide a better blown effect. The electric fuse provided by the invention can effectively avoid metal ion residue in the prior art under the condition of low voltage operation, especially when the operating voltage is between 2.5 and 3 volts, so that a better melting effect can be achieved. The resistance value after fusing is at least greater than 10,000 ohms (Ω), providing a good circuit blocking effect.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明。任何該領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed above by way of example, it is not intended to limit the invention. Anyone having ordinary knowledge in the field can make some changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

1‧‧‧基材 1‧‧‧Substrate

3‧‧‧隔離結構 3‧‧‧Isolation structure

5‧‧‧純金屬層 5‧‧‧Pure metal layer

6‧‧‧中介層 6‧‧‧Intermediary

7、71、72‧‧‧接觸插塞 7, 71, 72‧‧‧ contact plugs

8、81、82‧‧‧金屬層 8, 81, 82‧‧‧ metal layers

9‧‧‧保護層 9‧‧‧Protective layer

11‧‧‧元件層 11‧‧‧Component layer

12‧‧‧氧化層 12‧‧‧Oxide layer

22‧‧‧摻雜層 22‧‧‧Doped layer

41‧‧‧金屬矽化物層 41‧‧‧metal telluride layer

Claims (22)

一種電熔絲結構,其包含:一基材;一摻雜層,位於該基材上;一隔離結構,位於該基材上與該摻雜層之間;一金屬矽化物層,位於該摻雜層上;一純金屬層,位於該隔離結構上;一第一金屬層,位於該金屬矽化物層之一第一側上;一第二金屬層,位於該金屬矽化物層之遠離該第一側之一第二側上,其中該第一側與該第二測係以該純金屬層為分界;一第一接觸插塞,位於該第一金屬層與該金屬矽化物層之間,電性連接該金屬矽化物層之該第一側與該第一金屬層;以及一第二接觸插塞,位於該第一金屬層與該金屬矽化物層之間,電性連接該金屬矽化物層之該第二側與該第二金屬層。 An electric fuse structure comprising: a substrate; a doped layer on the substrate; an isolation structure between the substrate and the doped layer; a metal telluride layer located in the doped a layer of a pure metal on the isolation structure; a first metal layer on a first side of the metallization layer; and a second metal layer on the metallization layer away from the first layer a second side of one of the sides, wherein the first side and the second test system are bounded by the pure metal layer; a first contact plug is located between the first metal layer and the metal telluride layer, Electrically connecting the first side of the metal telluride layer to the first metal layer; and a second contact plug between the first metal layer and the metal telluride layer, electrically connecting the metal telluride The second side of the layer and the second metal layer. 如申請專利範圍第1項所述之電熔絲結構,其中該基材包含:一元件層;以及一氧化層,位於該元件層上、該元件層與該摻雜層之間。 The electrical fuse structure of claim 1, wherein the substrate comprises: an element layer; and an oxide layer on the element layer, between the element layer and the doped layer. 如申請專利範圍第1項所述之電熔絲結構,其中該摻雜層包含不同之摻雜型。 The electrical fuse structure of claim 1, wherein the doped layer comprises a different doping type. 如申請專利範圍第3項所述之電熔絲結構,其中該摻雜層之不同摻雜型分 別位於該隔離結構靠近該第一接觸插塞之部分該摻雜層,以及位於該隔離結構靠近該第二接觸插塞之間之部分該摻雜層。 The electric fuse structure according to claim 3, wherein the doping layer has different doping types The doped layer is located in a portion of the isolation structure adjacent to the first contact plug, and a portion of the doped layer is located between the isolation structure and the second contact plug. 如申請專利範圍第1項所述之電熔絲結構,其中該純金屬層僅覆蓋該隔離結構。 The electrical fuse structure of claim 1, wherein the pure metal layer covers only the isolation structure. 如申請專利範圍第1項所述之電熔絲結構,其中該純金屬層覆蓋該隔離結構以及部分該金屬矽化物層。 The electrical fuse structure of claim 1, wherein the pure metal layer covers the isolation structure and a portion of the metal halide layer. 如申請專利範圍第1項所述之電熔絲結構,其中該純金屬層所含之金屬成分與該金屬矽化物層所含之金屬成分相同。 The electric fuse structure according to claim 1, wherein the pure metal layer contains the same metal component as the metal halide layer. 如申請專利範圍第1項所述之電熔絲結構,其中該第一接觸插塞為單數個,且該第二接觸插塞為複數個。 The electrical fuse structure of claim 1, wherein the first contact plugs are singular and the second contact plugs are plural. 如申請專利範圍第1項所述之電熔絲結構,其中該金屬矽化物層與該金屬層共同形成一電熔絲,並且該電熔絲僅覆蓋部分之該摻雜層。 The electrical fuse structure of claim 1, wherein the metal halide layer and the metal layer together form an electrical fuse, and the electrical fuse covers only a portion of the doped layer. 如申請專利範圍第1項所述之電熔絲結構,其中該金屬矽化物層與該金屬層共同形成一電熔絲,並且該電熔絲完整覆蓋該摻雜層。 The electrical fuse structure of claim 1, wherein the metal halide layer and the metal layer together form an electrical fuse, and the electrical fuse completely covers the doped layer. 如申請專利範圍第1項所述之電熔絲結構,其還包含:一外側隔離結構,位於該基材上、該摻雜層之相對兩側。 The electrical fuse structure of claim 1, further comprising: an outer isolation structure on the substrate and opposite sides of the doped layer. 一種電熔絲結構的製造方法,步驟包含:提供一基材; 形成一摻雜層與一隔離結構於該基材上,其中該隔離結構位於該摻雜層之間;形成一純金屬層於該隔離結構上與一金屬矽化物層於該摻雜層上;形成一第一接觸插塞與一第二接觸插塞,分別電性連結於該金屬矽化物層之一第一側與遠離該第一側之一第二側,其中該第一側與該第二側以該隔離結構做分界;以及形成一第一金屬層與一第二金屬層,其中該第一接觸插塞電性連接該金屬矽化物層之該第一側與該第一金屬層,該第二接觸插塞電性連接該金屬矽化物層之該第二側與該第二金屬層。 A method of manufacturing an electrical fuse structure, the method comprising: providing a substrate; Forming a doped layer and an isolation structure on the substrate, wherein the isolation structure is between the doped layers; forming a pure metal layer on the isolation structure and a metal halide layer on the doped layer; Forming a first contact plug and a second contact plug electrically connected to a first side of the metal halide layer and a second side away from the first side, wherein the first side and the first side Forming a first metal layer and a second metal layer, wherein the first contact plug electrically connects the first side of the metal telluride layer and the first metal layer, The second contact plug is electrically connected to the second side of the metal telluride layer and the second metal layer. 如申請專利範圍第12項所述之電熔絲結構的製程方法,其中該基材包含:一元件層;以及一氧化層,形成於該元件層上、該元件層與該摻雜層之間。 The method of manufacturing an electrical fuse structure according to claim 12, wherein the substrate comprises: an element layer; and an oxide layer formed on the element layer, between the element layer and the doped layer . 如申請專利範圍第12項所述之電熔絲結構的製程方法,其中該摻雜層之形成方法,包含步驟:形成一多晶矽層於該基材上;圖案化該多晶矽層,形成一具有一暴露該基材之開口之圖案化多晶矽層;以及對該圖案化多晶矽層進行一離子佈植步驟。 The method for manufacturing an electrical fuse structure according to claim 12, wherein the method for forming the doped layer comprises the steps of: forming a polysilicon layer on the substrate; patterning the polysilicon layer to form a a patterned polycrystalline germanium layer exposing the opening of the substrate; and an ion implantation step of the patterned polycrystalline germanium layer. 如申請專利範圍第14項所述之電熔絲結構的製程方法,其中該離子佈植 步驟包含:進行一第一離子佈植步驟,使一第一部份之該摻雜層為第一摻雜型;以及進行一第二離子佈植步驟,使一第二部份之該摻雜層為第二摻雜型。 The method for manufacturing an electric fuse structure according to claim 14, wherein the ion implantation The method includes: performing a first ion implantation step to make a first portion of the doped layer a first doping type; and performing a second ion implantation step to do the doping of a second portion The layer is of a second doping type. 如申請專利範圍第15項所述之電熔絲結構的製程方法,其中該第一部份係位於該摻雜層之一第一側與該開口之間,該第二部份係位於該摻雜層之一第二側與該開口之間。 The method of manufacturing an electrical fuse structure according to claim 15, wherein the first portion is located between a first side of the doped layer and the opening, and the second portion is located in the blending One of the second side of the hybrid layer is between the opening. 如申請專利範圍第12項所述之電熔絲結構的製程方法,其中該摻雜層含矽,並且形成該純金屬層與該金屬矽化物層之方法包含步驟:沉積形成一原金屬層於該摻雜層與該隔離結構上;以及進行一熱處理步驟,使位於該摻雜層上之部分該原金屬層與該摻雜層中之矽反應,形成該金屬矽化物層,並且同時形成該純金屬層於該隔離結構上。 The method of manufacturing an electrical fuse structure according to claim 12, wherein the doped layer contains germanium, and the method of forming the pure metal layer and the metal germanide layer comprises the steps of: depositing a raw metal layer to form The doping layer and the isolation structure; and performing a heat treatment step of reacting a portion of the original metal layer on the doped layer with germanium in the doped layer to form the metal germanide layer, and simultaneously forming the A layer of pure metal is on the isolation structure. 如申請專利範圍第12項所述之電熔絲結構的製程方法,其中該摻雜層含矽,並且形成該純金屬層與該金屬矽化物層之方法包含步驟:沉積形成一原金屬層於該摻雜層與該隔離結構上;進行一熱處理步驟,使位於該摻雜層上之部分該原金屬層與該摻雜層中之矽反應,形成該金屬矽化物層;移除未反應之部分該原金屬層;以及形成該純金屬層覆蓋該隔離結構。 The method of manufacturing an electrical fuse structure according to claim 12, wherein the doped layer contains germanium, and the method of forming the pure metal layer and the metal germanide layer comprises the steps of: depositing a raw metal layer to form Depositing a doped layer with the isolation structure; performing a heat treatment step of reacting a portion of the original metal layer on the doped layer with germanium in the doped layer to form the metal telluride layer; removing unreacted a portion of the original metal layer; and forming the pure metal layer to cover the isolation structure. 如申請專利範圍第12項所述之電熔絲結構的製程方法,其中形成該第一接觸插塞與該第二接觸插塞之前,還包含步驟:形成一中介層於該隔離結構、該純金屬層與該金屬矽化物層上;蝕刻形成複數個通孔於該中介層中;以及形成該第一接觸插塞與該第二接觸插塞於該複數個通孔中。 The method for manufacturing an electric fuse structure according to claim 12, wherein before the forming the first contact plug and the second contact plug, the method further comprises the steps of: forming an interposer in the isolation structure, the pure Forming a plurality of vias in the interposer; and forming the first contact plug and the second contact plug in the plurality of vias. 如申請專利範圍第12項所述之電熔絲結構的製程方法,其還包含步驟:形成一保護層於該第一金屬層與該第二金屬層上,其中該保護層之材質可以為低常數介電材質或是超低常數介電材質。 The method for manufacturing an electrical fuse structure according to claim 12, further comprising the steps of: forming a protective layer on the first metal layer and the second metal layer, wherein the material of the protective layer can be low Constant dielectric material or ultra low constant dielectric material. 如申請專利範圍第12項所述之電熔絲結構,其中該金屬矽化物層與該金屬層共同形成一電熔絲,並且該電熔絲僅覆蓋部分之該摻雜層。 The electrical fuse structure of claim 12, wherein the metal halide layer and the metal layer together form an electrical fuse, and the electrical fuse covers only a portion of the doped layer. 如申請專利範圍第12項所述之電熔絲結構,其中該金屬矽化物層與該金屬層共同形成一電熔絲,並且該電熔絲完整覆蓋該摻雜層。 The electrical fuse structure of claim 12, wherein the metal halide layer and the metal layer together form an electrical fuse, and the electrical fuse completely covers the doped layer.
TW104129827A 2015-09-09 2015-09-09 An electrical fuse and making method thereof TWI666756B (en)

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