TW201706844A - Power failure detection system and method thereof - Google Patents

Abstract

A power failure monitoring system and a method thereof are disclosed herein, where the power failure monitoring system includes a motherboard, a board, a complex programmable logic device (CPLD) and a baseboard management controller (BMC) module, where the motherboard includes a central processing unit (CPU) power and a non-CPU power, the board includes a board power, and the BMC module includes a register that is electrically coupled to the CPLD. The CPLD is configured to execute a shutdown process when power failure happens, identify a power failure type, and determine whether to execute a restart process according to the power failure type. If the restart process is executed and a time of the restart process exceeds a predetermined time, the CPLD records a lock message in the register. The BMC module is configured to record the time of the restart process, and execute a lock process according to the lock message.

Description

Power failure detection system and method thereof

The invention is a detection technology, and in particular relates to a power failure detection system and a method thereof.

When there is a problem with the internal power supply of the server (for example, the power cannot be turned on, the power is turned off, the power is turned off after the switch button is pressed, etc.), it is necessary to use an oscilloscope (Oscilloscope) or a three-meter ( Multimeter) sequentially measures the Power-on sequence and the Enable signal and other related signals to determine which power supply is causing the power problem and cannot be turned on.

However, after the server is formed into a system, since the host is already installed inside the chassis, if the above problem occurs, it is difficult to measure the boot timing signal by using an oscilloscope or a three-meter, so that it is impossible to judge which power problem occurs in a short time. Whether the power supply, or power supply problem is a false power fault, such as an error caused by other system configurations.

In order to identify the power problem that occurs in the server system and to process it in time to eliminate the inability to power on due to a false power failure, one aspect of the present disclosure is to provide a power failure detection system including a motherboard (Motherboard) and a board. Card, Complex Programmable Logic Device (CPLD) and Baseboard Management Controller (BMC) modules, wherein the motherboard includes a central processing unit (CPU) power supply and decentralized The processing unit power supply, the board includes the board power supply, and the base management controller module includes a register, and the temporary register is electrically coupled with the complex programmable logic device. The complex programmable logic device is configured to perform a Shutdown program when a power failure occurs; identify a power failure type, and determine whether to perform a restart procedure according to the power failure type, and the power failure type indicates that the power failure occurs in the center. Processing unit power, non-central processing unit power or board power; if the restart procedure is executed, when the number of restarts reaches a preset number, the lock message is recorded in the register. The baseboard management controller module is configured to record the number of times of the restarting process, and execute the locking procedure according to the lock message.

In an embodiment of the present disclosure, when the complex programmable logic device records the lock message in the register, the location information of the buffer is transferred to the substrate management controller module, and the substrate management controller module is The location message reads the lock message of the scratchpad.

In one embodiment of the present disclosure, the complex programmable logic device records the lock message in the register when the power failure type indicates that a power failure occurred at the central processing unit power supply.

In one embodiment of the present disclosure, the complex programmable logic device performs a restart procedure when the power failure type indicates that a power failure occurs at the power of the board or the power of the non-central processing unit.

In one embodiment of the present disclosure, the complex programmable logic device is configured to record, via the power scan program, that a power failure occurs at a power failure location within the central processing unit power supply, the non-central processing unit power supply, or the board power supply.

Another aspect of the present invention provides a power failure detection method, comprising the steps of: performing a shutdown procedure when a power failure occurs; identifying a power failure type, and determining whether to execute a restart procedure according to a power failure type, wherein the power failure occurs The type indicates that the power failure occurs in the central processing unit power of the motherboard, the non-central processing unit power of the motherboard, or the power of the board; if the restart procedure is executed, when the number of restarts reaches a preset number, the lock message is recorded in the register. And recording the number of restarting procedures through the baseboard management controller module; and performing a locking procedure according to the locked message by the baseboard management controller module.

In an embodiment of the present disclosure, the method further includes: when the record lock message is in the temporary register, transmitting the location information of the temporary register to the substrate management controller module, and the substrate management controller module reads the temporary information according to the location information. The lock message of the memory.

In an embodiment of the present disclosure, the method further includes: recording a lock message in the temporary register when the power failure type indicates that the power failure occurs in the central processing unit power supply.

In an embodiment of the present disclosure, the method further includes: performing a restart procedure when the power failure type indicates that the power failure occurs in the power supply of the card or the power of the non-central processing unit.

In an embodiment of the present disclosure, the method further includes: recording, by the power supply scanning program, a power failure occurs in a power failure position of the central processing unit power supply, the non-central processing unit power supply, or the board power supply.

In summary, the disclosure can identify the power supply failure of the server system, and does not need to measure the power-on sequence of the power supply one by one, and perform corresponding subsequent processing according to the different failed power supplies to eliminate false power failures. An event, that is, a confirmation of a true power failure event. Further reduce maintenance costs due to false power failure events. On the other hand, if the power failure cannot be eliminated through the restart procedure, the information about the power failure can be used to improve the error analysis and fault repair process of the server system power failure.

The above description will be described in detail in the following embodiments, and further explanation of the technical solutions of the present disclosure is provided.

To make the description of the present disclosure more detailed and complete, reference is made to the drawings and the various embodiments described below. The examples are not intended to limit the scope of the invention; the description of the steps is not intended to limit the order of execution thereof, and any device having equal efficiency resulting from recombination is covered by the present invention. range.

In the scope of the embodiments and claims, "one" and "the" may mean a single or plural unless the context specifically dictates the articles.

In addition, as used herein, "coupled" and "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other. "Connected" may also mean that two or more elements operate or interact with each other.

As shown in FIG. 1 , FIG. 1 is a schematic diagram of a power failure detection system 100 according to an embodiment of the disclosure. The power failure detection system 100 includes a Motherboard 140, a board 150, a Complex Programmable Logic Device (CPLD), and a Baseboard Management Controller (BMC) module 130. The motherboard 140 includes a central processing unit (CPU) power supply 142 and a non-central processing unit power supply 144. The board 150 includes a board power supply 152. The baseboard management controller module 130 includes a register 120 (Register). The register 120 is electrically coupled to the complex programmable logic device 110.

The complex programmable logic device 110 instantly detects the operation of various power sources within the server system. For example, the main power applied to the motherboard 140 includes P12V, P5V, P3V3, PVDDQ, PVCCIN, etc., and the standby (by-by) power supply includes P12V_STBY, P5V_STBY, P3V3_STBY, P1V8_STBY, P1V_STBY, and the like. In this embodiment, the power applied to the motherboard can be divided into a central processing unit power supply 142 (eg, PVCCIN), and a non-central processing unit power supply 144 (eg, power supplies P12V, P5V, P3V3, PVDDQ supplied to the memory of the motherboard). And the standby power supply P12V_STBY, P5V_STBY, P3V3_STBY, P1V8_STBY, P1V_STBY). The board power supply 152 is, for example, supplied to a power supply of a server backboard, which includes a backup power source and a main power source.

In one embodiment, the complex programmable logic device 110 instantly detects whether the central processing unit power supply 142 and the non-central processing unit power supply 144 supplied to the motherboard 140 and the power supply to the board power supply 152 supplied to the card are powered. Invalid. When a power failure occurs in any of the above power supplies, the complex programmable logic device 110 immediately performs a Shutdown procedure to identify the type of power failure. The complex programmable logic device 110 further determines whether to execute a restart procedure based on the type of power failure. If the complex programmable logic device 110 executes the restart procedure and restarts smoothly, it indicates that the power failure is a false power failure and no maintenance is required. If the complex programmable logic device 110 fails to boot smoothly, the restart process is repeatedly executed. When the number of restarts of the program reaches a preset number of times (for example, the preset number of times is 3), a lock message is recorded in the register 120 to indicate that the power failure cannot be eliminated by rebooting. The baseboard management controller module 130 is configured to perform a locking procedure according to the lock message to lock the server system to prevent the server system from causing secondary damage due to malfunction before the power failure problem is eliminated. In addition, the substrate management controller module 130 is also used to record the number of restart procedures. Therefore, the complex programmable logic device 110 identifies the type of power failure when the server system fails, and can further determine whether to perform a restart procedure according to the type of power failure to eliminate a false power failure event, that is, to confirm the true Power failure event. The foregoing preset times may be designed according to actual needs, and are not intended to limit the disclosure, and other suitable preset times are also included in the scope of the present disclosure.

The following is a detailed description of whether or not to execute a restart procedure for different power failure types according to the complex programmable logic device 110. In one embodiment, when the power failure type is a failure of the central processing unit power supply 142, the complex programmable logic device 110 directly records the lock message in the scratchpad 120 without performing a restart procedure. The baseboard management controller module 130 executes a locking procedure based on the lock message to lock the server system such that the server system fails to power on before the central processing unit power supply 142 failure issue is eliminated. Since the central processing unit power failure is a fatal power failure, the complex programmable logic device 110 directly records the lock message in the scratchpad 120 without performing a restart procedure on the server system. The baseboard management controller module 130 is configured to execute a locking procedure of the server system to avoid secondary damage caused by a malfunction.

Alternatively, in another embodiment, the complex programmable logic device 110 when the power failure type is a power failure of the motherboard 140 and not the central processing unit power supply 142 fails (ie, the non-central processing unit power supply 144 fails). Perform a restart procedure to try to troubleshoot the above power failure. If the complex programmable logic device 110 is successfully restarted, it indicates that the power failure is a false power failure and no maintenance is required. If the complex programmable logic device 110 fails to boot smoothly, the restart process is repeatedly executed. When the number of restarts of the program reaches a preset number of times (for example, the preset number of times is 3), the record lock message is recorded in the register 120, indicating that the power failure cannot be eliminated by restarting. The foregoing preset times may be designed according to actual needs, and are not intended to limit the disclosure, and other suitable preset times are also included in the scope of the present disclosure.

Alternatively, in another embodiment, when the power failure type is a failure of the board power supply 152 (including the standby power failure of the board and the main power failure of the board), the complex programmable logic device 110 performs a restart procedure to try Eliminate the above power failure. If the complex programmable logic device 110 is successfully restarted, it indicates that the power failure is a false power failure and no maintenance is required. If the complex programmable logic device 110 fails to boot smoothly, the restart process is repeatedly executed. When the number of restarts of the program reaches a preset number of times (for example, the preset number of times is 3), the record lock message is recorded in the register 120, indicating that the power failure cannot be eliminated by restarting. The foregoing preset times may be designed according to actual needs, and are not intended to limit the disclosure, and other suitable preset times are also included in the scope of the present disclosure. In one embodiment, when the power failure type is that the board power supply 152 fails (including the standby power failure of the board and the main power failure of the board), an alert is sent through the display device. For example, red light is emitted through the light device, but the disclosure is not limited thereto.

In one embodiment, when the complex programmable logic device 110 records the lock message in the register 120, the location information of the register 120 is transferred to the baseboard management controller module 130. The baseboard management controller module 130 reads the lock message of the register 120 according to the location information to execute the lock procedure.

In one embodiment, the complex programmable logic component 210 defines a power scan program through the code to record a power failure occurring at a power failure location within the central processing unit power supply 142, the non-central processing unit power supply 144, or the board power supply 152. Therefore, the error analysis and fault repair process of the server system power failure are improved. For example, when the board power supply 152 fails, the complex programmable logic device 110 uses a power scanning program to record which power source on the board the power failure occurred. Therefore, if the power failure problem cannot be eliminated by the restart procedure, the time for checking the power failure position can be effectively saved. When the central processing unit power supply 142 fails, or the non-central processing unit power supply 144 (or the board power supply 152) fails and the number of restarts reaches a preset number of times, the complex programmable logic element 210 records the lock message in the failed state. The corresponding pin of the power source is connected to the register 120, and the position information of the register 120 is transmitted to the substrate management controller module 130.

2 is a flow chart illustrating a power failure detection method 200 in accordance with another embodiment of the present disclosure. The power failure detection method 200 includes a plurality of steps S202-S208, which can be applied to the power failure detection system 100 as shown in FIG. 1, but those skilled in the art should understand that the reference in this embodiment is mentioned. The steps can be adjusted according to actual needs, except for the order in which they are specifically stated, or even simultaneously or partially.

The following description uses the power supply of the server system as an example. Instantly detect the operation status of each power supply inside the server system. For example, the main power supply applied to the motherboard includes P12V, P5V, P3V3, PVDDQ, PVCCIN, etc., and the standby power supply includes P12V_STBY, P5V_STBY, P3V3_STBY, P1V8_STBY, P1V_STBY, and the like. In this embodiment, the power applied to the motherboard can be divided into a central processing unit power supply (eg, PVCCIN), and a non-central processing unit power supply (eg, power supplies P12V, P5V, P3V3, PVDDQ supplied to the memory of the motherboard), and Prepare the power supply P12V_STBY, P5V_STBY, P3V3_STBY, P1V8_STBY, P1V_STBY). The board power supply, for example, is supplied to a power supply of the server backplane, which includes a backup power source and a main power source.

In one embodiment, the central processing unit power supply to the motherboard and the power of the non-central processing unit, and the power supply to the board, are detected immediately. In step S202, when any of the above power sources fails, the shutdown procedure is immediately executed. In step S204, the power failure type is identified, and whether the restart procedure is executed is determined according to the power failure type. If the restart program is executed and the power is turned back on, it indicates that the power failure is a false power failure and no maintenance is required. If the boot fails, the restart procedure will be executed repeatedly. In step S206, if the restarting of the program is performed and when the number of restarting the program reaches a preset number of times (for example, the preset number of times is 3), the lock information is recorded in the register to indicate that the power failure cannot be eliminated by restarting. In addition, the number of restart procedures is also recorded through the baseboard management controller module. In step S208, the substrate management controller module executes a locking procedure according to the lock message to lock the server system to prevent the server system from causing secondary damage due to malfunction before the power failure problem is eliminated. Therefore, when a power failure occurs in the server system, the type of power failure is identified, and it is further determined whether to perform a restart procedure according to the type of power failure to eliminate a false power failure event, that is, to confirm a true power failure event. The foregoing preset times may be designed according to actual needs, and are not intended to limit the disclosure, and other suitable preset times are also included in the scope of the present disclosure.

The following is a detailed description of whether to perform a restart procedure based on different power failure types. In one embodiment, when the power failure type is a failure of the central processing unit power supply, the lock information is directly recorded in the temporary memory without performing a restart procedure. The locking process is executed by the baseboard management controller module according to the lock message to lock the server system, so that the server system cannot be turned on before the central processing unit power failure problem is eliminated. Since the central processing unit power failure is a fatal power failure, the lock message is directly recorded in the scratchpad without performing a restart procedure on the server system. The locking program of the server system is executed through the baseboard management controller module to avoid secondary damage caused by malfunction.

Alternatively, in another embodiment, when the power failure type is a motherboard power failure and not the central processing unit power failure (ie, the non-central processing unit power failure), a restart procedure is performed to attempt to eliminate the power failure described above. If the power is turned back on, it indicates that the power failure is a false power failure and no maintenance is required. If the boot fails, the restart procedure will be executed repeatedly. When the number of restarts of the program reaches a preset number of times (for example, the preset number of times is 3), the record lock message is recorded in the scratchpad, indicating that the power failure cannot be eliminated by restarting. The foregoing preset times may be designed according to actual needs, and are not intended to limit the disclosure, and other suitable preset times are also included in the scope of the present disclosure.

Alternatively, in another embodiment, when the power failure type is a board power failure (including the backup power failure of the board and the main power failure of the board), a restart procedure is performed to try to eliminate the power failure described above. If the power is turned back on, it indicates that the power failure is a false power failure and no maintenance is required. If the boot fails, the restart procedure will be executed repeatedly. When the number of restarts of the program reaches a preset number of times (for example, the preset number of times is 3), the record lock message is recorded in the scratchpad, indicating that the power failure cannot be eliminated by restarting. The foregoing preset times may be designed according to actual needs, and are not intended to limit the disclosure, and other suitable preset times are also included in the scope of the present disclosure. In an embodiment, when the power failure type is a failure of the power supply of the board (including the failure of the standby power supply of the board and the failure of the main power supply of the board), an alert is sent through the display device. For example, the warning light is emitted through the light device, but the disclosure is not limited thereto.

In one embodiment, when the record lock message is in the register, the location information of the register is transferred to the baseboard management controller module. The baseboard management controller module reads the lock message of the register according to the position information to execute the lock program.

In one embodiment, the power supply scanning program defined by the code is used to record a power failure occurring in a power failure position of the central processing unit power supply, the non-central processing unit power supply, or the board power supply, thereby improving the error analysis of the server system power failure. With the fault repair process. For example, when a board power failure occurs, a power scan procedure is used to record which power supply of the board occurs in the power failure. Therefore, if the power failure problem cannot be eliminated by the restart procedure, the time for checking the power failure position can be effectively saved. When the central processing unit power failure occurs, or the non-central processing unit power supply (or board power supply) fails and the number of restarts reaches a preset number of times, the complex programmable logic element records the lock message to the corresponding pin of the failed power supply. The bit is connected to the scratchpad and transmits the location information of the temporary register to the baseboard management controller module.

In summary, the disclosure can identify the power supply failure of the server system through the above embodiments, without measuring the power-on sequence of the power supply one by one, and performing corresponding subsequent processing according to the different failed power supplies to eliminate A false power failure event, that is, a true power failure event is confirmed. Further reduce maintenance costs due to false power failure events. On the other hand, if the power failure cannot be eliminated through the restart procedure, the information about the power failure can be used to improve the error analysis and fault repair process of the server system power failure.

Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the invention, and the present invention may be modified and retouched without departing from the spirit and scope of the present disclosure. The scope of protection is subject to the definition of the scope of patent application.

The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood.
100‧‧‧Power Failure Detection System
110‧‧‧Complex programmable logic devices
120‧‧‧ register
130‧‧‧Baseboard Management Controller Module
140‧‧‧ motherboard
142‧‧‧Central Processing Unit Power Supply
144‧‧‧Uncentralized processing unit power supply
150‧‧‧ boards
152‧‧‧ board power supply
200‧‧‧Power failure detection method
S202～S208‧‧‧Steps

The above and other objects, features, advantages and embodiments of the present disclosure will be apparent from the accompanying drawings. FIG. 1 is a schematic diagram showing a power failure detection system according to an embodiment of the present disclosure; And FIG. 2 is a flow chart illustrating a power failure detection method according to another embodiment of the present disclosure.

100‧‧‧Power Failure Detection System

110‧‧‧Complex programmable logic devices

120‧‧‧ register

130‧‧‧Baseboard Management Controller Module

140‧‧‧ motherboard

142‧‧‧Central Processing Unit Power Supply

144‧‧‧Uncentralized processing unit power supply

150‧‧‧ boards

152‧‧‧ board power supply

Claims (10)

A power failure detection system comprising: a motherboard comprising: a central processing unit (CPU) power supply; and a non-central processing unit power supply; a card comprising a card power supply; A Programmable Logic Device (CPLD) is configured to perform a shutdown procedure when a power failure occurs, identify a power failure type, and determine whether to execute a restart procedure according to the power failure type, the power failure type indication The power failure occurs in the central processing unit power supply, the non-central processing unit power supply or the board power supply; and a baseboard management controller (BMC) module, including: a temporary storage device electrically coupled to the complex a programmable logic device; wherein if the complex programmable logic device executes the restarting program, when the number of restarting programs reaches a preset number of times, a lock message is recorded in the temporary register; the substrate management control The module is used to record the number of restarts, and is executed according to the lock message Lock program. The power failure detection system of claim 1, wherein when the complex programmable logic device records the lock message in the register, transmitting a location message of the register to the baseboard management controller module The group management controller module reads the lock message of the register according to the location information. The power failure detection system of claim 1, wherein the complex programmable logic device records the lock message in the register when the power failure type indicates that a power failure occurs at the central processing unit power supply. The power failure detection system of claim 1, wherein the complex programmable logic device executes the restart procedure when the power failure type indicates that a power failure occurs at the power of the board or the power of the non-central processing unit. The power failure detection system of claim 1, wherein the complex programmable logic device is configured to record, via a power scanning program, that a power failure occurs in the central processing unit power supply, the non-central processing unit power supply, or the board power supply. One of the power failure locations. A power failure detection method includes: performing a shutdown procedure when a power failure occurs; identifying a power failure type, and determining whether to execute a restart procedure according to the power failure type, wherein the power failure type indicates that the power failure occurs in a One central processing unit power supply of the motherboard, one of the motherboards is not a central processing unit power supply or a board power supply; if the restarting process is executed, when the number of restarting programs reaches a preset number of times, a lock message is recorded And in the register, the number of times of restarting the program is recorded by a baseboard management controller module; and a locking program is executed according to the lock message through the baseboard management controller module. The power failure detection method of claim 6, further comprising: transmitting a location information of the temporary storage device to the baseboard management controller module when the locking information is recorded in the temporary storage, the substrate management control The module reads the lock message of the register according to the location information. The power failure detection method of claim 6, further comprising: recording the lock message in the temporary memory when the power failure type indicates that a power failure occurs in the central processing unit power supply. The power failure detection method of claim 6, further comprising: performing the restart procedure when the power failure type indicates that a power failure occurs at the power of the board or the power of the non-central processing unit. The power failure detection method of claim 6, further comprising: recording, by a power scanning program, that the power failure occurs at a power failure position of the central processing unit power supply, the non-central processing unit power supply, or the board power supply.