TW201705815A - Light emitting diode driver - Google Patents

Abstract

A driver circuit for driving light emitting diodes (LEDs). The driver circuit includes: a string of LEDs divided into n groups, the n groups of LEDs being electrically connected to each other in series, a downstream end of group m-1 being electrically connected to the upstream end of group m, where m is a positive number equal to or less than n. The driver circuit also includes a plurality of current regulating circuits, each of the current regulating circuits being coupled to the downstream end of a corresponding group at one end and coupled to the ground at the other end and including a sensor amplifier and a cascode having first and second transistors, each sensor amplifier being coupled to a different voltage source for providing a different reference voltage thereto.

Description

LED driver [Comparative Reference]

This application is a partial continuation of the application number 13/244,873 filed on September 26, 2011. It is also a part of the serial file of application number 13/244,892 filed on September 26, 2011, and also in 2011. Part of the continuation of the application No. 13/244,900 filed on September 26, the above-mentioned case, the benefit of the US Provisional Application No. 61/422,128 filed on December 11, 2010, with all of its contents The references in this are incorporated herein.

The present invention relates to driving a light emitting diode (LED) driver and, more particularly, to circuitry for driving a string of light emitting diodes (LEDs).

Due to the concept of low energy consumption, LED lights are prevailing and are seen as lighting practices in the era of energy shortages. Typically, the LED lamp includes a string of LEDs to provide the desired light output. The string of LEDs can be connected in parallel or in series A combination of the two or a combination of the two. Regardless of the configuration type, it is necessary to provide the correct voltage and/or current for efficient operation of the LEDs.

In power cycle applications, the LED driver should be able to convert the time-varying voltage to the correct voltage and/or current level. Typically, voltage conversion is implemented by circuitry that is generally known as an AC/DC converter. These converters, which utilize inductors or transformers, capacitors, and/or other components, are large in size and short in life, which results in an objectionable form factor, high manufacturing cost, and reduced system reliability in lamp design. Therefore, there is a need for an LED driver that is reliable and has a small form factor, thereby reducing manufacturing costs.

In an embodiment of the present disclosure, a method for driving light emitting diodes (LEDs) includes: providing a series of LEDs divided into groups, the groups being electrically connected to each other in series; providing a power source, electrically connected to the string of LEDs Each of the sets is connected to ground by a separate current regulating circuit comprising a cascode structure having first and second transistors; different reference voltages are applied to each The set of separate current regulating circuits; and increasing the input voltage from the power source to sequentially turn the groups on downstream.

In another embodiment of the present disclosure, a driving circuit for driving light emitting diodes (LEDs) includes: a series of LEDs divided into n groups, the n groups of LEDs are electrically connected in series, group m-1 The downstream end is electrically connected to the upstream end of the group m, where m is equal to or less than n a positive number; and a plurality of current regulating circuits each connected to a downstream end of a corresponding group at one end and to a ground at the other end, and including a sensor amplifier and having first and second The gates of the transistors are cascodes, each of which is connected to a different voltage source for providing a different reference voltage thereto.

In another embodiment of the present disclosure, a method for driving light emitting diodes (LEDs) includes: providing a series of LEDs divided into groups, the groups being electrically connected to each other in series; providing a power source, electrically connected to the string LEDs; each set of the sets is connected to ground by a separate current regulating circuit comprising a transistor and a sensor amplifier, the output pin of the sensor amplifier being connected to the gate of the transistor Applying different reference voltages to each of the set of sensor amplifiers; and increasing the input voltage from the power supply to turn the groups on in downstream order.

In another embodiment of the present disclosure, a driving circuit for driving light emitting diodes (LEDs) includes: a series of LEDs divided into n groups, the n groups of LEDs are electrically connected in series, group m-1 The downstream end is electrically connected to the upstream end of the group m, wherein m is a positive number equal to or smaller than n; and a plurality of current regulating circuits each connected to the downstream end of the corresponding group at one end and Connected to ground at the other end, and includes a sensor amplifier and a transistor whose output pins are connected to different voltage sources for providing different reference voltages thereto.

In another embodiment of the present disclosure, a method for driving light emitting diodes (LEDs) includes: providing a string of LEDs divided into groups, The groups are electrically connected in series; a power source is provided, electrically connected to the string of LEDs; and each group of the groups is connected to a ground through a corresponding one of the current regulating circuits, each of the groups being connected to a different voltage source Used to provide different reference voltages thereto; measure the phase of the voltage waveform of the power supply; and turn on the groups in a downstream order based on the measured phase.

In another embodiment of the present disclosure, a driving circuit for driving light emitting diodes (LEDs) includes: a series of LEDs divided into n groups, the n groups of LEDs are electrically connected in series, group m-1 The downstream end is electrically connected to the upstream end of the group m, wherein m is a positive number equal to or less than n, the upstream end of the group 1 is configured to be connected to a power supply that provides an input voltage; a complex current regulating circuit, the current regulating circuit Each is connected to a downstream end of a corresponding group at one end and to a ground at the other end, and includes a sensor amplifier and a cathode amplifier having first and second transistors, the current regulating circuit Each is coupled to a different voltage source; and phase control logic for transmitting signals to each of the current regulating circuits, thereby controlling current through each of the current regulating circuits.

11] In another embodiment of the present disclosure, a method for driving light emitting diodes (LEDs) includes: providing a series of LEDs divided into groups, the groups being electrically connected to each other in series; providing power, electrically connected to The string of LEDs; each set of the groups is connected to ground by a separate current regulating circuit comprising a stacked structure having first and second transistors and the same as the second transistor a three-electrode, the gate of the second transistor is directly connected to the gate of the third transistor, thereby forming Forming a current mirror; applying different currents to each of the third transistors of the group; and increasing an input voltage from the power source to sequentially turn the groups on downstream.

In another embodiment of the present disclosure, a driving circuit for driving light emitting diodes (LEDs) includes: a series of LEDs divided into n groups, the n groups of LEDs are electrically connected in series, group m-1 The downstream end is electrically connected to the upstream end of the group m, wherein m is a positive number equal to or smaller than n; and a plurality of current regulating circuits each connected to the downstream end of the corresponding group at one end and Connected to the ground at the other end, and includes a cathode amplifier having first and second transistors and a third transistor identical to the second transistor, the gate of the second transistor being directly connected to The gate of the third transistor, thereby forming a current mirror.

These and other features, aspects and advantages of the present invention will become better understood from the following description, appended claims.

10‧‧‧LED drive circuit, driver

100‧‧‧LED drive circuit

102‧‧‧ Phase Control Logic

110‧‧‧LED drive circuit

112‧‧‧ Phase Control Logic

113‧‧‧Detector

114‧‧‧clock counter

115‧‧‧frequency selector

116‧‧‧Oscillator

117‧‧‧Detector

118‧‧‧clock counter

119‧‧‧ label selector

120‧‧‧ label

150‧‧‧ Circuit

151‧‧‧dotted line

152‧‧‧ Circuitry

154‧‧‧ Circuitry

155a-155d‧‧‧dotted line

162‧‧‧Overvoltage detector

164‧‧‧Detector

20‧‧‧LED drive circuit

200‧‧‧ input generator

202‧‧‧Rectifier

204‧‧‧Transformers

210‧‧‧Input generator

212‧‧‧Rectifier

214‧‧‧Transformers

30‧‧‧LED drive circuit

40‧‧‧LED drive circuit

50‧‧‧LED drive circuit

60‧‧‧LED drive circuit

70‧‧‧LED drive circuit

80‧‧‧LED drive circuit

90‧‧‧LED drive circuit

I1-i4‧‧‧current

Iref1-Iref4‧‧‧reference current

M‧‧‧Adjusting the crystal

M1‧‧‧Second transistor, conditioning transistor

M2‧‧‧ Adjusting the crystal

M3‧‧‧ Adjusting the crystal

M4‧‧‧Adjusting the crystal

N1‧‧‧ node

N2‧‧‧ node

N3‧‧‧ node

N4‧‧‧ node

P1-P8‧‧‧ points

Pd‧‧‧ grounding level

R‧‧‧Sense Resistors

Rs‧‧‧ Current Sensing Resistors

SA‧‧‧Sensor Amplifier

SA1-SA4‧‧‧Sensor Amplifier

T1ra, T1rb, T1fa, T1fb‧‧ points

T2ra, T2rb, T2fa, T2fb‧‧ points

T3ra, T3rb, T3fa, T3fb‧‧ points

UHV1‧‧‧first transistor, protective transistor

UHV2‧‧‧ protective transistor

UHV3‧‧‧protective transistor

UHV4‧‧‧Protective transistor

UHVs‧‧‧protective crystal

Vcc2‧‧‧ Constant voltage, constant gate voltage

VCC2‧‧‧ Constant voltage

VCC2‧‧‧ gate voltage

Vrect‧‧‧ rectified voltage

Vref‧‧‧reference voltage

Vref1-Vref4‧‧‧ reference voltage

Vref1-Vref4‧‧‧ reference voltage

Vs‧‧‧ voltage

Z1‧‧‧ node

1 shows a schematic diagram of an LED driving circuit according to an embodiment of the present invention; FIG. 2 shows a schematic diagram of an LED driving circuit according to another embodiment of the present invention; and FIG. 3 shows an LED driving circuit according to another embodiment of the present invention. FIG. 4 is a schematic diagram showing an LED driving circuit according to another embodiment of the present invention; FIG. 5 is a schematic diagram of an LED driving circuit according to another embodiment of the present invention; FIG. 6 is a schematic diagram showing an LED driving circuit according to another embodiment of the present invention; and FIG. 7 is a diagram showing an LED driving according to another embodiment of the present invention. FIG. 8 is a schematic diagram showing an LED driving circuit according to another embodiment of the present invention; FIG. 9 is a schematic diagram showing an LED driving circuit according to another embodiment of the present invention; and FIG. 10 is a view showing another embodiment according to the present invention. 1 is a schematic diagram of an LED driving circuit according to another embodiment of the present invention; and FIGS. 12A-12C show different waveforms of a rectified voltage that can be input to the driver of FIGS. 1-11; 12D shows a schematic diagram of the frequency detector and phase control logic of Figures 10 and 11; Figures 13A-13B show different waveforms of the rectified voltage that can be input to the driver of Figures 1-11; Figures 14A-14F show the waveforms of Figures 10 and 11 Output signal of frequency detector and phase control logic; Figures 15A-15C show schematic diagrams of circuitry for controlling current flow through a transistor in accordance with another embodiment of the present invention; Figure 16 shows a schematic diagram of an overvoltage detector in accordance with another embodiment of the present invention; and Figures 17A-17B show schematic diagrams of an input generator in accordance with another embodiment of the present invention.

Referring now to Figure 1, a schematic diagram of an LED drive circuit (or ephemeral drive) 10 in accordance with an embodiment of the present invention is shown. As shown in the figure. The driver 10 is propelled by a power source such as an alternating current (AC) power source. The current from the AC source is rectified by the rectifier circuit. The rectifier circuit can be any suitable rectifier circuit, such as a bridge diode rectifier, capable of rectifying an AC circuit from an AC power source. The rectified voltage Vrect is then applied to a string of light emitting diodes (LEDs). If desired, the AC power source and rectifier can be replaced by a DC circuit power supply.

LEDs as described herein are used in general terms for many different types of light-emitting diodes, such as conventional LEDs, super bright LEDs, high brightness LEDs, organic LEDs, and the like. The driver of the present invention is applicable to all kinds of LEDs.

As shown in Figure 1, a string of LEDs is electrically connected to a power source and divided into four groups. However, it will be apparent to those skilled in the art that the string of LEDs can be driven in any suitable number of groups. The LEDs in each group can be the same or a combination of different kinds, such as different colors. They can be connected in series or in parallel or a mixture of both. Moreover, one or more resistors can be included on the inside of each group, such as LED1.

A separate current regulating circuit (or a short adjustment power system is connected to the downstream end of each LED group, wherein the current regulating circuit collectively means a set of elements for current regulation, such as i1, and includes a first transistor (eg UHV1) ), a second transistor (eg M1) and a sensor amplifier (eg SA1). Hereinafter, the term "transistor" means an N-channel MOSFET, a P-channel MOSFET, an NPN-bipolar transistor, a PNP- Bipolar transistor, insulated gate bipolar transistor (IGBT), analog switch or relay.

The first and second electro-crystalline systems are electrically connected in series to form a stacked structure. The first electro-crystalline system is capable of protecting the second transistor from high voltages. As such, in the following, the first transistor is referred to as a protective transistor, even though its function is not limited to protecting the second transistor. The main function of the second transistor includes adjusting the current i1; and as such, the second transistor is hereinafter referred to as an adjustment transistor. The protective transistor may be an ultra high voltage (UHV) transistor having a high breakdown voltage of 500V, for example, and the conditioning transistor M1 may be a low voltage (LV), medium voltage (MV) or high voltage (HV) transistor. And has a lower breakdown voltage than the protective transistor. A node, such as N1, means that the point of the source of the guard transistor is connected to the drain of the conditioning transistor.

The voltage Vs can be expressed by the following equation: Vs = (i1 + i2 + i3 + i4) * Rs, where Rs means a current sensing resistor.

The sensor amplifier SA1, which may be an operational amplifier, compares the voltage Vs with the reference voltage Vref1, and outputs the input to the adjustment transistor The signal of the gate of the body, thereby forming a feedback control of the current i1 flowing through the gate ground amplifier and the resistor Rs. The gate voltage of the guard transistor can be set to a constant voltage Vcc2. (The following Vcc2 means constant voltage Vcc2). Mechanisms for generating a constant gate voltage Vcc2 are well known in the art, and a detailed description of the mechanism is not described herein.

As described above, each current regulating circuit is electrically connected to the downstream end of the corresponding LED group at one end and to the other end via the current sensing resistor Rs. The adjustment transistors M1, M2, M3, and M4 have a common sensor voltage Vs. Hereinafter, the terms "common sensor voltage" and "common source voltage" mean the voltage Vs.

The reference voltages Vref1, Vref2, Vref3, and Vref4 are set to different values. For example, the reference voltage may satisfy the condition that Vref1 < Vref2 < Vref3 < Vref4, so that the driver 10 can successfully turn on/off each group of LEDs when the level of the Vrect changes. When the voltage of the power supply begins to increase from zero, Vrect may not be high enough to allow current to flow through the LEDs. At this stage, Vs is lower than the reference voltages Vref1-Vref4, and therefore, the sensor amplifiers SA1, SA2, SA3, and SA4 turn on the regulating transistors M1, M2, M3, and M4, respectively.

When the voltage of the power supply is increased enough to turn on the first LED group, LED1 (or Group 1), it is immediately downstream of the power supply, and the first regulating circuit, that is, UHV1, M1 and SA1 are conductive, and the current i1 flows. To ground. It is noted that the first conditioning circuit can be turned on before, during or after the rectified voltage Vrect is sufficient to activate the LED 1. The same analogy applies to other conditioning circuits corresponding to Groups 2-4. When the Vrect system is high enough When the LED 1 is activated but insufficient to turn on the LED 2, the sensor amplifier SA1 compares the voltage level Vs with the reference voltage Vref1 and transmits a control signal to the adjustment transistor M1. More specifically, the output signal of the sensor amplifier SA1 is input to the gate of the adjustment transistor M1.

As Vrect increases, it reaches a level sufficient to activate LED1 and LED2. Then, the second regulating circuits (i.e., UHV2, M2, and SA2) are electrically conductive, and the LEDs 1 and 2 are turned on. As described above, the second conditioning circuit can be turned on before, during or after the Vrect reaches a level sufficient to activate LED1 and LED2. The sensor amplifier SA2 compares the voltage levels Vs and Vref2 and transmits a control signal to the adjustment transistor M2.

When the second current regulating circuit is turned on, if the current i1 is turned off (or set to the minimum level), the overall efficiency of the driver 10 will be enhanced. This is because LED2 will generate more light if current flows through it, and shutting down (or decreasing) current i1 will cause current i1 to redirect to LED2. In the driver 10, when the current i2 starts to flow, the voltage Vs further increases at a certain point in time and exceeds Vref1. At this point, SA1 transmits a signal to M1, thereby reducing current i1.

When Vrect is further increased, the current i2 is further increased. Moreover, the current i1 is further reduced. When Vref1 is less than Vs, current i1 is finally completely blocked by sensor amplifier SA1, where Vs is represented by the equation Vs=i2*Rs. At this point, only current i2 flows through LED1 and LED2 and is regulated by sensor amplifier SA2.

The same analogy is applied to subsequent groups. In general, when downstream When the LED group is turned on and the current regulating circuit associated with the downstream group is conducting, the current regulating circuit associated with the upstream group can be turned off (or the current flowing through the regulating circuit is set to a minimum level) to enhance the overall efficiency of the driving circuit 10. .

Once the source voltage (or rectified voltage Vrect) reaches its peak and begins to fall, the above process is reversed such that the first current regulating circuit finally returns to turn-on. It is noted that when the source voltages are reduced to a level that is insufficient to continue the downstream group turn-on, the downstream group is naturally turned off even though its associated regulation circuit may be on.

As described above, each of the adjustment circuits includes two transistors, such as UHV1 and M1, arranged in series to form a spliced structure. A spliced structure, which is implemented as a current sink, has different advantages compared to a single transistor current slot. First, it has enhanced current drive capability. When operating in its saturation region, which is expected for current sinks, the current drive capability (Idrv) of the LV/MV/HV NMOS is much better than the UHV NMOS. For example, the Idrv of a typical LV NMOS is 500 μA/μm, and the Idrv of a typical UHV NMOS is 10-20 μA/μm. Therefore, to adjust the same amount of current, the desired projection area of the UHV NMOS on the wafer is at least 20 times larger than the desired projection area of the LV NMOS. Moreover, a typical UHV NMOS has a minimum channel length of 20 μm, while a typical LV NMOS has a minimum channel length of 0.5 μm. However, typical LV NMOSs need to provide protection against high voltage protection. In the spliced structure, the first transistor, preferably a UHV NMOS, operates as a guard transistor, and the second transistor, preferably an LV/MV/HV NMOS, operates as a current regulator to provide enhanced current drive. ability. The protective transistor does not operate in the following example A saturation region in which a single UHV NMOS is used as a current sink and operates in a linear region. In other words, the current drive capability Idrv is not a decisive design factor; rather, the resistance of the protection transistor Rdson is an important factor in designing the UHV NMOS of the cascode amplifier.

Second, due to the series configuration of the spliced structure, the required voltage (a.k.a voltage compliance) of the voltage (headspace) of the spliced structure can be higher than the single UHV NMOS configuration. As for the LED driver example, however, the power loss due to the required voltage is very much less than the power loss due to the LED drive voltage. For example, in the AC-driven LED driver example, the LED drive voltage (voltage on the LED positive) ranges from 100Vmrs to 250Vrms. For example, the required voltage for a single UHV NMOS is 2V and the required voltage for the stacked structure is 5V. In this case, the efficiencies are 98 to 99% and 95 to 98%, respectively. Of course, Rdson can be lowered such that the desired voltage of the stacked structure can be about the same as the desired voltage of a single UHV NMOS. The important point is that the additional power consumed by the spliced structure is a minor drawback. If efficiency is a decisive design factor, the spliced structure can be designed in a current mirror configuration, while the current mirror configuration using two UHV NMOS transistors is practically not feasible due to the large area on the wafer.

Third, because the UHV NMOS and the LV/MV/HV NMOS are separately controlled, the on/off current slot is easier to overlap. In a single UHV NMOS current sink, both current regulation and switching must be accomplished by controlling the gate of the UHV NMOS, which has the characteristics of a large capacitor. In contrast, in the spliced structure, current regulation can be accomplished by controlling the LV/MV/HV NMOS, and the switching action can be performed by UHV. Completed by the NMOS, the UHV NMOS only requires logic operation on the gate.

Fourth, the speed of the switch in the single UHV NMOS configuration is more smoothly controlled in the spliced structure. In a single UHV NMOS configuration, linear control of the current cannot be easily achieved by controlling the gate voltage because of the square function of the current system gate voltage. In contrast, in the spliced structure, when the gate of the LV/MV/HV NMOS is controlled, the current control (rotation) becomes smoother because the current control system operates as a resistor, and the resistor system gate voltage The inverse of the function.

Fifth, the spliced structure provides better noise immunity. Noise from the power source can propagate through the LEDs and can then be coupled to the current conditioning circuit. More specifically, the noise is introduced into the feedback loop of the current regulating circuit. In a single UHV NMOS configuration, this noise is directly coupled to this loop, however, in a spliced configuration. The noise is the ratio of the Rdson of the UHV NMOS to the effective resistance of the LV/MV/HV NMOS.

Sixth, the noise structure generated by the stacked structure is lower than that of the single UHV NMOS configuration. In the spliced configuration, current control is primarily implemented by the conditioning transistor, however, in a single UHV NMOS configuration, current control is implemented by the UHV NMOS. Because the gate capacitance of the LV/MV/HV NMOS is lower than the UHV NMOS, the noise structure generated by the stacked structure is lower than that of the single UHV NMOS configuration.

It is noted that the protective transistors UHV1-UHV4 may be the same or different from each other. Likewise, the conditioning transistors M1-M4 may be the same or different from each other. Specifications for protective and regulating transistors can be selected to match The purpose of the meter.

2 shows a schematic diagram of an LED drive circuit 20 in accordance with another embodiment of the present invention. As described, the drive circuit 20 is similar to the drive circuit 10 of FIG. 1, with the difference that in one embodiment, the detector 1, the detector 2, and the detector 3 are used to detect the nodes N2, N3, and N4, respectively. Voltage. Each detector can be, for example, an operational amplifier, an inverter (logic gate) or a Schmitt trigger. Each detector transmits a signal to a sensor amplifier associated with the upstream LED group, thereby controlling the current flowing through the current regulating circuit. For example, when the rectified voltage Vrect is high enough to turn on LED1 and LED2, detector 1 monitors the voltage level at node N2. When the voltage at the node N2 further increases to reach the preset voltage level, the detector 1 transmits a signal to the sensor amplifier SA1. Next, the sensor amplifier SA1 can turn off the current i1 (or the current i1 is set to the minimum level) by controlling the gate voltage of the adjustment transistor M2. Once Vrect reaches its peak level and falls, the above process reverses.

The same analogy applies to other detectors. For example, detector 2 monitors the voltage level at node 3 and transmits a signal to sensor amplifier SA2 to control current i2. It is noted that the sensor amplifier SA2 also compares the reference voltage Vref2 with the voltage Vs to control the gate voltage of the adjustment transistor M2. Therefore, the sensor amplifier SA2 takes three input voltages to control the current i2; the voltage of the node N3, the voltage Vs of the transistor M2 (ie, the source voltage), and the reference voltage Vref2.

FIG. 3 shows a schematic diagram of an LED drive circuit 30 in accordance with another embodiment of the present invention. As mentioned, the drive circuit 30 is similar to the drive Circuit 10 differs in that the output signal of the sensor amplifier, such as SA2, is input to an upstream sensor amplifier, such as SA1. For example, when the voltage Vs reaches a preset level, the sensor amplifier SA2 transmits a signal to the sensor amplifier SA1, and then, the sensor amplifier SA1 can reduce its output voltage level, so that the adjustment transistor M1 turns off the current. I1. Therefore, the sensor amplifier SA1 takes three input voltages to control the current i1; the output from the sensor amplifier SA2, the voltage Vs (ie, the source voltage) of the adjustment transistor M1, and the reference voltage Vref1.

4 shows a schematic diagram of an LED driver circuit 40 in accordance with another embodiment of the present invention. As noted, the drive circuit 40 is similar to the drive circuit 20 of FIG. 2, with the difference that the output pin of each detector is coupled to the gate of the first transistor of the upstream current regulation circuit. Each detector transmits an output signal to the gate of the first (or guard) transistor associated with the upstream LED group, thereby controlling the current flowing through the current regulating circuit. For example, when the rectified voltage Vrect is high enough to turn on LED1 and LED2, detector 1 monitors the voltage level at node N2. When the voltage at the node N2 further increases to reach a preset voltage level, the detector 1 transmits an output signal to the gate of UHV1. Next, UHV1 turns off current i1 (or sets current i1 to the minimum level).

The same analog application is applied to other detectors. For example, detector 2 monitors the voltage level at node 3 and transmits an output signal to UHV2 to control current i2. It is noted that UHV4, the first transistor of the current regulating circuit associated with LED4 (the last LED group), has a constant gate voltage Vcc2.

FIG. 5 shows a schematic diagram of an LED driver circuit 50 in accordance with another embodiment of the present invention. As described, the drive circuit 50 is similar to the drive circuit 10 of FIG. 1 except that the output pin of the sensor amplifier is connected to the gate of the first transistor of the upstream current regulation circuit, thereby controlling the flow through Current of the upstream current regulating circuit. For example, when the rectified voltage Vrect is sufficiently high to turn on the LED 1 and the LED 2, the sensor amplifier SA2 transmits an output signal to the gate of UHV1, thereby reducing the current i1. When Vrect is further increased, UHV1 turns off current i1 (or sets current i1 to the minimum level).

The same analog application is applied to other sensor amplifiers. For example, sensor amplifier SA3 transmits an output signal to UHV2 to control current i2. It is noted that UHV4, the first transistor of the current regulating circuit associated with LED4 (the last LED group), has a constant gate voltage Vcc2.

FIG. 6 shows a schematic diagram of an LED driver circuit 60 in accordance with another embodiment of the present invention. As described, the drive circuit 60 is similar to the drive circuit 10 of FIG. 1, with the difference that the detector 1, the detector 2, and the detector 3 are used to detect the voltages at the nodes N1, N2, and N3, respectively. Each detector can be, for example, an operational amplifier, an inverter (logic gate) or a Schmitt trigger. Each detector transmits a signal to a sensor amplifier associated with the downstream LED group, thereby controlling the current flowing through the current regulating circuit.

When the voltage level at each node, such as N1, is below a predetermined threshold level, detector 1 transmits its output signal to sensor amplifier SA2, causing sensor amplifier SA2 to be disabled, and the result Tune The power saver M2 is disconnected. Vs is lower than the reference voltage Vref1, and therefore, the sensor amplifier SA1 is energized. Moreover, the energized sensor amplifier SA1 outputs an output signal of a high energy state to turn on the adjustment transistor M1. More specifically, the output pin of the sensor amplifier SA1 is directly connected to the gate of the regulating transistor M1, and the high-energy state output signal turns on the regulating transistor M1. Therefore, in this early stage, only the first regulating transistor M1 is turned on, and therefore, only the first current regulating circuit conducts current, and the other current regulating circuits are turned off.

As Vrect increases, current i1 flows through the first set of LEDs 1, causing LED 1 to illuminate. Current i1 then flows through transistors UHV1, M1 and current sense resistor Rs to ground. When the voltage level at the node N1 reaches a preset level, the detector 1 transmits an output signal to the sensor amplifier SA2 to cause the sensor amplifier SA2 to turn on the regulating transistor M2 and the current i2 to flow through the LED 2. Therefore, in this phase, both currents i1 and i2 flow through LED1 and LED2, respectively.

When Vrect is further increased to a level at which the voltage Vs is higher than Vref1, the sensor amplifier SA1 transmits a low-energy state output signal to the adjustment transistor M1, thereby turning off the adjustment transistor M1. In this phase, only current i2 flows through LED1 and LED2. When the current i1 is cut off (or set to the minimum level), the overall efficiency of the driver 60 is increased. This is because LED2 will produce more light if more current flows through it, and shutting (or reducing) current i1 will cause current i1 to redirect to LED2.

The same analog application is applied to other current regulating circuits corresponding to Groups 2-4. For example, the current regulating circuit for LED3 is disconnected. Until the detector 2 transmits a high energy state output signal to the sensor amplifier SA3. Moreover, when the Vs is higher than Vref3, the current regulating circuit for the LED 3 is turned off.

When the source voltage (or the rectified voltage Vrect) reaches its peak value, the current regulating circuits for LED1, LED2, and LED3 are turned off. When Vrect begins to fall, the above process reverses causing the first current regulating circuit to finally return to turn-on.

FIG. 7 shows a schematic diagram of an LED driver circuit 70 in accordance with another embodiment of the present invention. As noted, the driver circuit 70 is similar to the driver circuit 60, with the difference that the driver 70 does not include a detector and a sensor amplifier, such as the output signal of SA1 being input to a downstream sensor amplifier, such as SA2. For example, when the Vrect is at the ground level, the current regulation circuits of LED2, LED3, and LED4 are turned off. When the voltage Vs reaches a preset level, the sensor amplifier SA1 transmits an output signal to the sensor amplifier SA2 such that the sensor amplifier SA2 turns on the regulating transistor M2 to allow the current i2 to flow through the LED 2. Therefore, in this phase, both currents i1 and i2 flow through LED1 and LED2, respectively.

When Vrect is further increased to a level at which the voltage Vs is higher than Vref1, the sensor amplifier SA1 transmits a low-energy state output signal to the adjustment transistor M1, thereby turning off the adjustment transistor M1. In this phase, only current i2 flows through LED1 and LED2.

The same analog application is applied to other current regulating circuits corresponding to Groups 2-4. For example, the current regulation circuit for LED3 remains in the disabled state until the sensor amplifier SA2 transmits a high energy state output signal. To sensor amplifier SA3. Moreover, when the Vs is higher than Vref3, the current regulating circuit for the LED 3 is turned off (or, disabled). The sensor amplifier SA3 has three inputs; a source voltage Vs of M3, a reference voltage Vref3, and an output signal from SA2.

FIG. 8 shows a schematic diagram of an LED driver circuit 80 in accordance with another embodiment of the present invention. As described, the drive circuit 80 is similar to the drive circuit 70 of FIG. 7, except that the output pin of each sensor amplifier is connected to the gate of the guard transistor of the downstream current regulation circuit, thereby controlling the flow. The current through the downstream current regulating circuit. For example, when the Vrect is at the ground level, the guard transistors UHV2, UHV2, and UHV3 are disconnected and the UHV1 is turned "on". When the voltage Vs is increased to a preset level, the sensor amplifier SA1 transmits an output signal to the gate of the guard transistor UHV2, thereby turning on the transistor UHV2.

When Vrect is further increased to a level at which the voltage Vs is higher than Vref1, the sensor amplifier SA1 transmits a low-energy state output signal to the adjustment transistor M1, thereby turning off the adjustment transistor M1. In this phase, only current i2 flows through LED1 and LED2.

The same analog application is applied to other current regulation circuits. It is noted that the gate of the first guard transistor UHV1 is maintained at a constant level such that the current regulation circuit of the LED 1 is turned on when the Vrect is at the ground level.

FIG. 9 shows a schematic diagram of an LED driver circuit 90 in accordance with another embodiment of the present invention. As mentioned, each current regulating circuit includes a transistor (eg, UHV1) and a sensor amplifier (eg, SA1). As above The spliced structure of Figures 1-8, which is implemented as a current sink, has different advantages over a single transistor current sink. However, single transistor current sinks have the advantage of being less expensive to manufacture than stacked structures.

When the voltage of the power supply is increased enough to turn on the LED 1, the current i1 flows through the transistors UHV1 and Rs to ground. It is noted that the first current regulating circuit can be turned on before, during or after the rectified voltage Vrect reaches a level sufficient to activate the LED 1. The same analog application is applied to other current regulating circuits corresponding to Groups 2-4. When the Vrect is high enough to activate the LED 1 but not enough to turn on the LED 2, the sensor amplifier SA1 compares the voltage Vs with the reference voltage Vref1 and transmits a control signal to the transistor UHV1 to adjust the current i1. More specifically, the output signal of the sensor amplifier SA1 is input to the gate of the adjustment transistor UHV1.

As Vrect increases, it reaches a level sufficient to activate LED1 and LED2. Then, the second adjustment transistors (i.e., UHV2 and SA2) are conducted, and the LEDs 1 and 2 are turned on. As described above, the second current regulating circuit can be turned on before, during, or after the Vrect reaches a level sufficient to activate LED1 and LED2. The sensor amplifier SA2 compares the voltage levels Vs and Vref2 and transmits a control signal to the transistor UHV2.

When the second current regulating circuit is turned on, if the current i1 is cut off (or set to the minimum level), the overall efficiency of the driver 90 will be enhanced. This is because LED2 will produce more light if current flows through it, and shutting (or reducing) current i1 will cause current i1 to redirect to LED2. In the driver 90, when the current i2 starts to flow, the voltage Vs Further increase and timely exceed Vref1 at a certain point. At this point, SA1 transmits a signal to UHV1, thereby cutting off current i1.

The same analogy is applied to subsequent groups. In general, when the downstream LED group is turned on and the current regulating circuit associated with the downstream group is conducting, the current regulating circuit associated with the upstream group can be turned off (or the current through the regulating circuit is set to a minimum level). The overall efficiency of the drive circuit 90 is enhanced.

Once the source voltage (or rectified voltage Vrect) reaches its peak and begins to fall, the above process reverses causing the first current regulating circuit to finally return to turn-on. It is noted that when the source voltage is reduced to a level that is insufficient to maintain the downstream group turn-on, the downstream group is naturally turned off even though its associated regulation circuit may be on.

FIG. 10 shows a schematic diagram of an LED drive circuit 100 in accordance with another embodiment of the present invention. As noted, the driver circuit 100 is similar to the driver 10 of FIG. 1 with the difference that the frequency detector and phase control logic (or, in short, phase control logic) 102 transmits signals to UHV1-UHV4. The driver 100 can sequentially turn on/off each group of LEDs in accordance with a signal received from the phase control logic 102. For example, phase control logic 102 transmits a signal to the gate of guard transistor UHV1 to turn it on, while other guard transistors UHV2-UHV4 are turned off. As described in connection with Figures 14A-14F, phase control logic 102 can transmit output signals to guard transistors UHV1-UHV4 to control them at different timings.

In another example, phase control logic 102 transmits signals to a plurality of guard transistors, such as UHV1 and UHV2, to turn on a plurality of guard transistors, such as UHV1 and UHV2.

The sensor amplifiers SA1-SA4 control the gates of the conditioning transistors M1-M4 in a similar manner as described in connection with the driver 10. Thus, the current flowing through each current regulating circuit, such as i1, is controlled by either sensor amplifier SA1 or phase control logic 102 or both.

Figure 11 shows a schematic diagram of an LED driver circuit 110 in accordance with another embodiment of the present invention. As noted, the driver circuit 110 is similar to the driver circuit 100 of FIG. 10, with the difference that the phase control logic 112 transmits signals to SA1-SA4.

The driver 110 can sequentially turn on/off each group of LEDs in accordance with a signal received from the phase control logic 112. For example, phase control logic 112 transmits a signal to sensor amplifier SA1 to turn on regulation transistor M1, while other adjustment transistors M2-M4 are off. As described in connection with Figures 14A-14F, phase control logic 112 can transmit output signals to sensor amplifiers SA1-SA4 at different timings to control conditioning transistors M1-M4.

In another example, phase control logic 112 transmits signals to a plurality of sensor amplifiers, such as SA1 and SA2, to turn on a plurality of conditioning transistors, such as M1 and M2. When the Vrect is increased from the ground level, the current flows only through the first LED group, that is, only the current i1 flows. When Vrect is further increased enough to turn on the first and second LED groups, LED1 and LED2 (or Group 1 and Group 2), current i2 begins to flow through the second current regulating circuit. At the same time, Vs instantly increases further at one point and exceeds Vref1. At this point, the feedback loop control mechanism cuts off the current i1, that is, the sensor amplifier SA1 compares the voltage level Vs with the reference voltage Vref1 and transmits a control signal to the adjustment transistor M1. More specifically, when the Vs is higher than At Vref1, the sensor amplifier SA1 transmits a low-energy state output signal to the adjustment transistor M1, thereby turning off the adjustment transistor M1.

In another example, the sensor amplifier SA1 controls the adjustment transistor M1 based only on the output signal of the phase control logic 112. Thus, each sensor signal has 3 inputs; Vs, Vref and the signal from phase control logic 112.

The same analog application is applied to other current regulating circuits corresponding to Groups 2-4. For example, current i3 is controlled by sensor amplifier SA3 based on the output signal of phase control logic 112 or Vs/Vref3 or both. When the source voltage (or rectified voltage Vrect) reaches its peak and Vrect begins to fall, the above process reverses to cause the first current regulating circuit to finally return to turn-on.

As described above, phase control logic 102 and 112 respectively transmit signals to guard transistors UHV1-UHV4 and sensor amplifiers SA1-SA4. Because the phase control logic 102 and 112 have similar structures and operating mechanisms, only the phase control logic 112 is detailed. The operation of phase control logic 112 includes measuring the AC 1⁄2 cycle time, where AC 1⁄2 cycle time means half of the cycle time of the AC signal. Figure 12A shows the waveform of the rectified voltage input to driver 110 as a function of time, where AC 1⁄2 cycle time is the time interval between T1ra and T1rb or between T1fa and T1fb. FIG. 12D shows a schematic diagram of phase control logic 112 of FIG. As shown in FIG. 12D, when Vrect rises to a preset level such as Vva1, the detector 113 monitors the voltage level of the Vrect and transmits a signal, energizing 1. For example, detector 113 transmits a first enable signal at T1ra. Then, when The clock counter 114 begins counting the clock signals received from the oscillator 116. When Vrect rises to Vva1 at T1rb, detector 113 transmits a second enable signal to clock counter 114 and clock counter 114 stops counting the clock signal. Next, the measurement counter value is transferred (or loaded) to the frequency selector 115 to determine the frequency (or Vrect) of the AC input. Upon shifting the measured counter value, the clock counter 114 resets the counter value and begins counting again to maintain monitoring of the rectified AC voltage frequency.

Based on the determined frequency, the frequency selector 115 selects a preset time interval of the switch tag (or, in short, the tag). The driver 110 (shown in FIG. 11) includes four tags corresponding to the input pins of the sensor amplifiers SA1-SA4, and the frequency selector 115 specifies a preset time interval to each tag, wherein the preset time interval means a reference The time interval between the point (such as T1ra) and the time at which the signal will be transmitted to the corresponding tag (such as P1 in Figure 12A).

When Vrect falls (or rises) to a predetermined voltage level such as Vva1, detector 117 monitors the level of Vrect falling (or rising) and transmits an enable signal, energizing 2. Clock counter 118 then begins counting the clock signal generated by oscillator 116. Tag selector 119 then receives the count from clock counter 118. Then, the tag selector 119 compares the count received from the clock counter 118 with the preset time interval received from the frequency selector 115, and when the count of the clock counter 118 meets the preset time interval, the transfer switch enable signal is sent to the corresponding tag. 120. Upon receiving the switch enable signal from the tag selector 119, the corresponding tag, such as the sensor amplifier SA1, turns the adjustment transistor M1 on/off.

In Figure 11, there are 4 sensor amplifiers, and therefore, 8 preset time intervals (ie, the time interval between T1ra and P1, T1ra and P2, T1ra and P3, T1ra and P4, T1ra and P5, T1ra and P6, T1ra and P7, and T1ra and P8, as shown in the figure 12A is assigned by the frequency selector 115 to the corresponding sensor amplifier. Since each preset time interval corresponds to a fixed phase point of the input voltage waveform, each preset time interval also means a phase difference between T1ra and a phase at a corresponding point, such as P1. As such, the terms "preset time interval" and "predetermined phase difference" are used interchangeably.

Note that detector 113 can transmit an enable signal when Vrect rises or falls to Vva1. For example, detector 113 can transmit an enable signal at T1fa and T1fb (or T1ra and T1rb) such that clock counter 114 can count the clock signal at an AC cycle time. Similarly, detector 117 can transmit an enable signal when Vrect rises or falls to Vva1. It is also noted that detectors 113 and 117 can transmit an enable signal at different preset voltage levels.

A digital latching loop or phase latching loop can be used instead of the clock counter 114 (or clock counter 118). Because DLLs, PLLs, and clock counters are well known in the art, no detailed description is given herein.

Figures 12B and 12C show different waveforms of the rectified voltage input to the driver 110 of Figure 11, where the AC input voltage is processed by the dimmer switch. As mentioned, the dimmer switch maintains the AC input voltage to ground until the AC input voltage rises to Vdim (Figure 12B) or to Vdim (Figure 12C). Phase control logic 112 can measure AC 1⁄2 by counting clock signals between T2ra and T2rb or between T2fa and T2fb. circulation time. More specifically, detectors 113 and 117 can transmit an enable signal at a point in time T2ra, T2rb, T2fa, and T2fb. The same analog application is applied to the Vrect of FIG. 12C, that is, the detectors 113 and 117 can transmit the energization signals at a point in time T3ra, T3rb, T3fa, and T3fb.

As described above, phase control logic 112 controls currents i1-i4 based on the frequency and phase of the AC input voltage waveform. This method is useful when the noise level of the AC power source is high and/or preferably the current waveform follows the AC input voltage waveform smoothly. If the current i1 is only controlled by the feedback loop control mechanism, since the feedback control mechanism relies on the Vrect level, the current i1 will fluctuate significantly when the noise level of the Vrect is high. Fluctuations in currents i1-i4 can cause brightness flicker that can be detected by the human eye.

13A-13B show two waveforms of the rectified voltage that can be input to the driver 110 of FIG. (Note that the waveforms in Figures 12A-12C and 13A-13B can also be input to the driver circuit of Figures 1-10), unlike the dimmers used to generate the waveforms of Figures 12B and 12C, used to generate the map. The dimmers of the waveforms in 13A and 13B cut off the rear of each cycle, that is, after Vrect rises/falls to Vdim, Vrect remains at the ground level. Because phase control logic 112 measures frequency and phase in the same manner as described in connection with Figures 12B and 12C, a detailed description of the operational procedures of phase control logic 112 is not repeated.

Figure 14A shows the output signal of phase control logic 112 of Figure 11, with four tag switches (or in short, tags) corresponding to four sensor amplifiers SA1-SA4. More specifically, each tag switch signal, for example For example, the tag 1 switching signal is transmitted to a corresponding sensor amplifier, for example, SA1, to cause the sensor amplifier to turn on/off the corresponding adjustment transistor, for example, M1. As shown in FIG. 14A, the hat portion of each tag switch signal waveform represents the time interval when the corresponding sensor amplifier is turned on, that is, the tag switch signal is in the active state. As such, the signals transmitted to the sensor amplifiers are sorted in time so that only one of the adjustment transistors M1-M4 is turned on at each point in time. More specifically, the on and off signals are transmitted by phase control logic 112 to SA1 at P1 and P2, respectively. (Here, P1-P8 of Fig. 14A correspond to P1-P8 of Fig. 12A, respectively). Similarly, SA2, SA3, and SA4 are turned on/off by signals at P2/P3, P3/P4, and P4/P5, respectively. When Vrect decreases from its peak value, SA3, SA2, and SA1 are turned on/off by signals transmitted at P5/P6, P6/P7, and P7/P8, respectively. As such, only one sensor amplifier is turned on at each point in time (ie, in an active state). Note that each sensor amplifier, such as SA1, continuously compares the source voltage of the corresponding adjustment transistor, such as M1, such as Vs, with Vref1 and regulates the current to keep Vs the same as when the sensor amplifier system Vref1 in the active state.

Figure 14B shows the output signal of phase control logic 112 of Figure 11 in accordance with another embodiment. Unlike the signal waveforms in Figure 14A, the tag switch signals transmitted to the sensor amplifiers are sorted in time to allow one or more of the regulated cell systems to be turned on simultaneously. For example, the adjustment transistor M1 is turned on/off by the signal at P1/P8, and the adjustment transistor M2 is turned on/off by the signal of P2/P7. Therefore, the regulating transistor M2 connected to the tag 2 switch is turned on, and is connected to the regulating transistor of the tag 1 switch. M1 is already connected. Note that the sensor amplifier SA1 can further control the adjustment transistor M1 by using a feedback loop, as described in connection with FIG. Therefore, it is possible that only one of the adjustment transistors M1-M4 is turned on, even if the tag switch signals transmitted by all of the phase control logics 112 are in an active state.

In one example, phase control logic 112 transmits a signal to SA1 to turn on M1 at P1. At P1, current can only flow through the first set of LEDs, that is, only current i1 flows. At P2, the signal is transmitted to SA2 to turn on M2. When Vrect is further increased enough to turn on the first and second LED groups, LED1 and LED2 (or Group 1 and Group 2), current i2 begins to flow through the second current regulation circuit. At the same time, Vs further increases at a point in time and exceeds Vref1. At this point, the feedback loop control mechanism cuts off the current i1, that is, the sensor amplifier SA1 compares the voltage level Vs with the reference voltage Vref1 and transmits a control signal to the adjustment transistor M1. More specifically, when the voltage Vs is higher than Vref1, the sensor amplifier SA1 transmits a low-energy state output signal to the adjustment transistor M1 to thereby turn off the adjustment transistor M1.

Figures 14C and 14D show the output signals of phase control logic 112 of Figure 11 in accordance with another embodiment of the present invention. As shown, the waveform of the Vrect is similar to the Vrect of Figure 13A, that is, the dimmer is used to generate the waveforms of Figures 14C and 14D. The timing sequences in Figures 14C and 14D are similar to the timings in Figures 14A and 14B, respectively, that is, only one sensor amplifier is turned on at each point in time (Figure 14C), or multiple sensor amplifiers can be in time Each point is turned on (Fig. 14D). Note that, in the figure In 14C, the tag 2 switch (such as SA2) can be in the active state of Pd. However, when Vrect drops to ground level at Pd, the current flowing through the second current regulating circuit will also drop to zero at Pd. Moreover, there will be no current flowing through the LED group between P7 and P8, even if SA1 is in the active state. As such, the total light emitted by the LED group will be reduced as expected by the dimmer designer. Similarly, as shown in FIG. 14D, both the tag 1 switch and the tag 2 switch are in the active state at Pd. However, when Vrect drops to ground level at Pd, the current flowing through the LED group will also drop to zero, thereby reducing the total light emitted by the LED group.

Figures 14E and 14F show the output signals of phase control logic 112 of Figure 11 in accordance with another embodiment of the present invention. As shown, the waveform of the Vrect is similar to the Vrect of Figure 12B, that is, the dimmer is used to generate the waveforms of Figures 14E and 14F. The timing sequences in Figures 14E and 14F are similar to the timings in Figures 14A and 14B, respectively, that is, only one sensor amplifier is turned on at each point in time (Figure 14E), or multiple sensor amplifiers can be in time Each point is turned on (Fig. 14F). Note that in Figure 14E, the tag 2 switch (such as SA2) is turned on at P2, however, when Vrect rises from the ground level at Pd, the current will begin to flow through the second current regulation circuit at Pd, ie The current will not flow between P2 and Pd. Also, there will be no current flowing through the LED group between P1 and P2, even if SA1 is in the active state. As such, the total light emitted by the LED group will be reduced as expected by the dimmer designer. Similarly, as shown in FIG. 14F, both the tag 1 switch and the tag 2 switch are in the active state at Pd. However, when Vrect rises from the ground level of Pd, there is no current. The flow passes through the LED group between P1 and Pd, thereby reducing the total light emitted by the LED group.

As described above, the structure and operating mechanism of the phase control logic 102 are similar to the structure and operating mechanism of the phase control logic 112, with the difference that in one embodiment, the four labels of the phase control logic 102 correspond to the protective transistor UHV1- The gate of UHV4. Based on the method described in connection with Figures 12A-14F, phase control logic 102 controls currents i1-i4 by transmitting signals to guard transistors UHV1-UHV4.

Figure 15A shows a schematic diagram of a circuit 150 for controlling the flow of current through a regulated transistor M, wherein the circuit 150 is included in the drive circuit of Figures 1-8 and 10-11. As described, the sensor amplifier SA compares the reference voltage Vref with the voltage level Vs and transmits a signal to the gate of the adjustment transistor M to control the current i. Note that the sensor amplifiers have different reference voltages, Vref, as shown in Figures 1-8 and 10-11. Therefore, the reference voltage Vref in FIG. 15A may be one of the reference voltages Vref1-Vref4. It is also noted that the drive circuit 90 of FIG. 9 does not have an adjustment transistor, and, as such, when the circuit 150 is used in the drive circuit 90, the output signal from the sensor amplifier SA is transmitted to the transistor. The gate of the UHV is shown as a broken line 151 (i.e., the constant voltage VCC2 is not applied to the UHV).

The type and operating mechanism of the components of circuit 150 are illustrated in conjunction with FIG. For example, the conditioning transistor M can be an LV/MV/HV NMOS and the protective transistor can be a UHV NMOS. For the sake of brevity, the description of the other components will not be repeated.

Figure 15B shows a schematic diagram of a circuit 152 for controlling the current i through a regulated transistor M1 in accordance with another embodiment of the present invention. As shown, another transistor M2, which is identical to the conditioning transistor M1, is coupled to the conditioning transistor M1 to form a current mirror configuration. More specifically, the gates of the two transistors M1, M2 are electrically connected to each other to have the same gate voltage. The current Iref flowing through the second transistor M2 is controlled to regulate the current i through which the flow is regulated by the transistor M1. Current regulation circuit 152 can be used in place of current regulation circuit 150 of Figure 15A, and for example, current regulation circuit 152 can be used with the drive circuit of Figures 1-11. Note that the reference currents Iref1-Iref4 are provided instead of the reference voltages Vref1-Vref4. It is also noted that current regulation circuit 152 does not include any sensor amplifiers as compared to circuit 150. Also, circuit 152 does not include current sense resistor Rs.

Figure 15C shows a schematic diagram of a circuit 154 for controlling the flow of current through the conditioning transistor M in accordance with another embodiment of the present invention. As shown, each sensor amplifier SA is provided with a non-inverting input voltage Vref, where Vref is determined by the equation: Vref = Iref * R where Iref represents the current and R represents the total resistance downstream of each voltage node. For example, Vref3 can be calculated by the following equation: Vref3 = Iref* (R1 + R2 + R3).

Current regulation circuit 154 can be used with the drive circuits of Figures 1-8 and 10-11. When the circuit 154 is used in the drive circuit 90 of FIG. 9, the output from the sensor amplifier SA is input to the gate of the UHV as indicated by the broken lines 155a-155d, that is, the constant voltage VCC2 is not applied to the UHV. Gate.

Figure 16 shows a schematic diagram of an overvoltage detector 162 in accordance with another embodiment of the present invention. As described, the overvoltage detector 162 can include a Zener diode coupled to the downstream end of the last LED group, a detector 164 for detecting the voltage, and a sense resistor R. The voltage level at node Z1 is equal to the voltage difference between Vrect and the voltage drop due to the string of LEDs. When the voltage level of Z1 exceeds a preset level, the level is preferably the breakdown voltage of the Zener diode, and the current flows through the sensing resistor R. Detector 164 then detects the voltage level and transmits a signal to the appropriate components of the driver circuit, thereby controlling the current flowing through the LEDs, i.e., cutting off the current flowing through the LEDs or preventing excessive power consumption in the wafer containing the driver circuit. . For example, the output signal of the overvoltage detector 162 is input to SA4 in Fig. 1 so that the current i4 is cut off. In another example, the output signal is passed to a component that produces reference voltages Vref1-Vref4 (not shown in FIG. 1) such that the component can reduce the reference voltage in FIG. In another example, the output signal is used to reduce the gate voltage VCC2 of the guard transistor UHVs. Note that the overvoltage detector 162 can also be used in the drive circuit of Figures 1-11.

As shown in Figures 1-11, each driver can include a rectifier to The current supplied by the rectified AC power source. In some applications, such as high power LED street lights, LEDs can require high power consumption. In such applications, the driver can be isolated from the AC power source by a transformer for safety purposes. 17A-17B show schematic diagrams of input generators 200 and 210 in accordance with another embodiment of the present invention. As shown in FIG. 17A, transformer 204 can be configured between AC input and rectifier 202. Alternatively, rectifier 212 can be disposed between the AC input source and transformer 214, as shown in Figure 17B. In both examples, current i flows through a plurality of LED groups during operation. Input generators 200 and 210 can be applied to the drivers of Figures 1-11.

It is to be understood that the above-described exemplary embodiments of the present invention, as well as modifications, may be made without departing from the spirit and scope of the invention as set forth in the following claims.

10‧‧‧LED drive circuit, driver

Claims (13)

A method for driving light emitting diodes (LEDs), comprising: providing a string of LEDs divided into groups, the groups being electrically connected to each other in series; providing a power source, electrically connected to the string of LEDs; and corresponding one through a current regulating circuit Each of the groups is connected to ground, each of the groups being connected to a different voltage source for providing a different reference voltage; measuring the phase of the voltage waveform of the power source; and downstream based on the measured phase These groups are turned on sequentially. The method of claim 1, further comprising: providing a dimmer switch; and causing the dimmer switch to process the voltage waveform, thereby adjusting the brightness of the string of LEDs. The method of claim 1, wherein each of the current regulating circuits comprises a stacked structure having first and second transistors, and wherein the step of turning on the groups comprises: directing the phase control logic Connecting to a gate of the first transistor; and causing the phase control logic to transmit an output signal to the gate of the first transistor, thereby regulating current flow through the first transistor. The method of claim 1, wherein each of the current regulating circuits includes a sensor amplifier and a stacked structure having the first and second transistors, further comprising: applying a gate voltage to the first a gate of a transistor; Inputting the different reference voltage to the sensor amplifier; and causing the sensor amplifier to transmit an output signal to a gate of the second transistor, thereby regulating current flow through the second transistor. The method of claim 4, wherein the step of applying a gate voltage to the gate of the first transistor comprises: maintaining the gate voltage of the gate applied to the first transistor substantially Constant level. The method of claim 4, wherein the step of turning on the groups comprises: directly connecting phase control logic to the sensor amplifier; and when the difference between the phase and the reference phase of the voltage waveform is in accordance with When the phase difference is set, the phase control logic is caused to transmit a signal to the sensor amplifier. The method of claim 4, further comprising: causing the reference current to flow through the series of complex resistors; and obtaining a voltage upstream of one of the plurality of resistors as the different reference voltage. A driving circuit for driving light-emitting diodes (LEDs), comprising: a series of LEDs divided into n groups, the n groups of LEDs are electrically connected in series, and the downstream end of the group m-1 is electrically connected to the group m The upstream end, where m is a positive number equal to or less than n, the upstream end of group 1 is configured to be connected to a power supply that provides an input voltage; a complex current regulating circuit, each of which is connected Connected to the downstream end of the corresponding group at one end and to the ground at the other end, and including a sensor amplifier and having a first and second transistor overlap, each of the current regulating circuits being connected to Different voltage sources; and phase control logic for transmitting signals to each of the current regulating circuits, thereby controlling current through each of the current regulating circuits. The driving circuit of claim 8, wherein the phase control logic comprises: a frequency selector for determining a frequency of the input voltage and specifying a preset time interval to each of the current regulating circuits; and a selector a special current regulating circuit for selecting the current regulating circuits, and transmitting a signal to the special current regulating circuit when the phase of the input voltage conforms to the preset time interval. The driving circuit of claim 8 wherein the phase control logic is directly connected to the gate of the first transistor. A drive circuit as in claim 8 wherein the phase control logic is directly coupled to the sensor amplifier. The driving circuit of claim 8, wherein the different reference voltage source comprises a reference current source and a series of complex resistors. The driving circuit of claim 8 further comprising: an overvoltage detector connected to the downstream end of the string of LEDs.