TWI517747B - Light emitting diode driver using turn-on voltage of light emitting diode - Google Patents

Description

Light-emitting diode driver using the turn-on voltage of the light-emitting diode [Interactive References in Related Applications]

This application claims priority to US Provisional Application No. 61/422,128, entitled "Light emitting diode driver using turn-on voltage of light emitting diode", which is filed on December 11, 2010, and is related to co-pending US application No. 13/244,892, filed on September 26, 2011, entitled "Light emitting diode driver having cascade structure", filed on September 26, 2011 U.S. Serial No. 13/244,900, filed on Sep. 26, 2011, entitled <RTI ID=0.0>>

This invention relates to light emitting diode (LED) drivers and, more particularly, to circuits for driving a string of light emitting diodes (LEDs).

Due to the concept of low energy consumption, LED lights are very popular and are seen as a practice of lighting in an era of energy shortages. Typically, LED lights contain a string of LEDs to provide the desired light output. The string of LEDs can be configured in parallel or in series or in a combination of the two. Regardless of the type of configuration, providing the correct voltage and/or current is important for efficient operation of the LED.

In applications where the power supply is periodic, the LED driver should be able to convert Change the voltage to the correct voltage and / or current level. Typically, voltage conversion is performed by a circuit commonly referred to as an AC/DC converter. These converters, which use inductors or transformers, capacitors, and/or other components, are large in size and short in life, which results in a form factor, high manufacturing cost, and reduced system reliability that are unpleasant in lamp design. . Accordingly, there is a need for an LED driver that is reliable and has a small form factor, thereby reducing manufacturing costs.

In an embodiment of the present disclosure, a driver circuit for driving a light emitting diode (LED) includes a group of LEDs divided into n groups, the n groups of LEDs are electrically connected in series to each other, and the downstream end of the group m-1 is electrically connected to The upstream end of the group m, where m is a positive number equal to or less than n. The driver circuit also includes a complex current regulation circuit, wherein each of the current regulation circuits is coupled to a downstream end of a respective group and includes at least one transistor and a detector for measuring current flowing through the respective group.

In another embodiment of the present disclosure, a method of driving a light emitting diode (LED) includes: providing a group of LEDs, the groups being electrically connected in series with each other; coupling each of the groups through respective current regulating circuits a group to ground; causing the detectors of the respective current regulating circuits to measure current flowing through a respective one of the groups; and controlling the current based on the measured current.

These and other features, aspects, and advantages of the present invention will be better understood from the appended claims.

Referring to Figure 1, a schematic diagram of an LED driver circuit (or simply a driver) 10 in accordance with an embodiment of the present invention is shown. As shown, the power driver 10 is powered by a power source such as an alternating current (AC) power source. The electrical current from the AC source is rectified by the rectifier circuit. The rectifier circuit can be any suitable rectifier circuit, such as a bridge diode rectifier, capable of rectifying alternating power from an AC source. The rectified voltage Vrect is then supplied to a string of light emitting diodes (LEDs). If desired, a DC (DC) power supply can be used instead of the AC power supply and rectifier. Optionally, a dimmer switch can be installed to adjust the intensity of the light produced by the LED. Thereafter, the term "AC power supply and dimmer switcher" means AC power or AC power connected to the dimmer switch.

The rectified voltage Vrect from the voltage rectifier is converted to a DC voltage by a voltage regulator. The voltage regulator then provides a DC voltage to each of the voltage level controllers. Thereafter, each of the voltage level controllers (such as voltage level controller 1) outputs a DC voltage (V1), wherein V1 can be processed by control logic 1 before being input to the gate of transistor UHV1. A detailed description of the control logic is presented in conjunction with Figure 6.

The LEDs used herein are general terms for many different types of light-emitting diodes, such as conventional LEDs, super bright LEDs, high brightness LEDs, organic LEDs, and the like. The driver of the present invention is suitable for all kinds of LEDs.

As shown in Figure 1, a string of LEDs is electrically connected to the power supply and divided into n groups, where n is an integer. It will be apparent to those of ordinary skill in the art that the string of LEDs can be divided into any suitable number of groups. The LEDs in each group can be a combination of the same or different species (eg, different colors). Connectable They may be connected in parallel or in a mixture of the two. Also, one or more resistors may be included in each group.

Separate current regulating circuits (or simply adjusting circuits) are connected to the downstream end of each LED group, wherein the current regulating circuit refers collectively to a group of components for regulating current flow (eg, i1) and includes one or more transistors ( Such as UHV1), detector (such as detector 1), control logic (such as control logic 1), and voltage level controller (such as voltage level controller 1). Hereinafter, the term "transistor" means an N-channel MOSFET, a P-channel MOSFET, an NPN bipolar transistor, a PNP bipolar transistor, an insulated gate bipolar transistor (IGBT), an analog switcher, or a repeater.

As discussed above, each current regulating circuit is electrically coupled at one end to the downstream end of the respective LED group. Driver 10 can use a corresponding current regulation circuit to continuously turn each group of LEDs on/off. For example, when the Vrect is increased from the ground level, the current flows only through the first LED group LED1, that is, only the current i1 flows. The detector 1 detects the current i1 (or voltage drop) across the resistor of the detector 1 and sends an output signal to the voltage level controller 1. When Vrect is further increased, the output signal from the detector 1 changes, and therefore, the output signal V1 of the voltage level controller 1 changes. When V1 changes, the gate voltage of UHV1 also changes, so the level of current flow i1 is adjusted.

When Vrect is further increased enough to turn on both the first and second LED groups LED1 and LED2 (or Group 1 and Group 2), current i2 begins to flow through the second current regulating circuit. And, the detector 2 sends a signal to both the control logic 1 and the voltage level controller 2. When the current i2 reaches a certain level, come The signal from detector 2 reaches a level where the voltage level from the output signal of control logic 1 is reduced to the ground level. When this ground voltage is applied to the gate of UHV1, the current i1 is completely turned off.

The same analogy applies to other current regulating circuits corresponding to groups 2 through n. For example, current i2 is controlled by voltage level controller 2, control logic 2, and detector 3. When Vrect is high enough to cause current i3 to flow through UHV3, detector 3 sends a signal to control logic 2, causing the gate voltage of UHV2 to be at ground level, thereby completely turning off current i2. When no current i2 passes through detector 2, control logic 1 may mistakenly believe that Vrect is not high enough to turn on current i2 and current i1 should flow. To avoid this misunderstanding, control logic 2 can receive the signal from control logic 3, as shown in Figure 1, and send an output signal to control logic 1 so that control logic 1 does not turn off current when current i3 flows through UHV3. I1. When the source voltage (or rectified voltage Vrect) reaches its peak and Vrect begins to fall, the above procedure is reversed so that the first current regulating circuit is finally turned on.

Optionally, the driver 10 can include a frequency detector and phase control logic 12 (or simply a phase controller or phase control logic). A detailed description of the frequency detector and phase control logic 12 is presented in conjunction with Figures 8A through 10C.

Figure 2 shows a schematic diagram of an LED driver circuit 20 in accordance with another embodiment of the present invention. As shown, the driver 20 is similar to the driver 10 of Figure 1, with the difference that each current regulating circuit includes two transistors UHV and LV/MV/HV arranged in series to form a stacked structure. For simplicity, the frequency detector and phase control logic are not shown in Figures 2 through 5. Even though it can be implemented in the drivers of Figures 2 to 5 in the same manner as in Figure 1. The spliced structure, which is implemented as a current sink, has various advantages over a single transistor current sink. First, it has improved current drive capability. This is desirable for current sinks when operating in its saturation region, and the current drive capability (Idrv) of the LV/MV/HV NMOS is much better than the UHV NMOS. For example, the Idrv of a typical LV NMOS is 500 μA/μm, while the typical UHV NMOS is 10 to 20 μA/μm. Therefore, to adjust the same amount of current flow, the required projected area of the UHV NMOS on the wafer is at least 20 times larger than that of the LV NMOS. Also, a typical UHV NMOS has a minimum channel length of 20 μm, while a typical LV NMOS has a minimum channel length of 0.5 μm. However, a typical LV NMOS would require a shielding mechanism that provides protection from high voltages. In the spliced structure, a first transistor, preferably a UHV NMOS, operates as a shielded transistor, and a second transistor, preferably a LV/MV/HV NMOS, operates as a current regulator to provide improved current drive capability . The shielded transistor does not operate in a saturated region as in the case of using a single UHV NMOS as a current sink, and operates in a linear region. Therefore, the current drive capability Idrv is not a decisive design factor; specifically, the resistance of the shielded transistor Rdson is an important factor in designing the UHV NMOS of the overlap.

Second, due to the tandem configuration of the spliced structure, the required voltage (ie, voltage compliance or headroom) of the spliced structure can be higher than a single UHV NMOS configuration. However, for the LED driver case, the power loss due to the required voltage is much lower than the power loss due to the LED drive voltage. For example, in an AC-driven LED driver In this case, the LED drive voltage (voltage on the LED anode) ranges from 100 Vmrs to 250 Vrms. Assume that the required voltage of a single UHV NMOS is 2V and that of a stacked structure is 5V. In this case, the efficiencies are 98 to 99% and 95 to 98%, respectively. Of course, Rdson can be reduced so that the required voltage of the stacked structure can be about the same as a single UHV NMOS. The focus is on the disadvantage that the extra power consumed by the spliced structure is small. If efficiency is an important design factor, the spliced structure can be designed in a current mirror configuration, and the current mirror configuration using two UHV NMOSs is not practical because of its large area on the wafer.

Third, turning on/off the current sink is easier in the spliced structure because the UHV NMOS and LV/MV/HV NMOS are separately controlled. In a single UHV NMOS current sink, both current regulation and on/off operation are performed by controlling the gate of the UHV NMOS, which has the characteristics of a large capacitor. Conversely, in the spliced structure, current regulation can be performed by controlling the LV/MV/HV NMOS, and the ON/OFF operation can be performed by controlling the UHV NMOS (which only requires logic operation on the gate).

Fourth, the on/off speed is controlled more smoothly in the spliced structure than in a single UHV NMOS configuration. In a single UHV NMOS configuration, linear control of the current cannot be easily achieved by controlling the gate voltage because the current is a function of the square of the gate voltage. Conversely, in the spliced structure, when the gate of the LV/MV/HV NMOS is controlled, current control (slewing) becomes smoother because it operates as a resistor that is an inverse function of the gate voltage.

Fifth, the spliced structure provides better noise immunity. From the power supply The noise of the device can propagate through the LED and can therefore be coupled to the current regulating circuit. In detail, the noise is introduced into the feedback loop of the current regulation circuit. In a single UHV NMOS configuration, this noise is directly coupled to this loop, and in a stacked configuration, this noise is attenuated by the ratio of the Rdohm of the UHV NMOS to the effective resistance of the LV/MV/HV NMOS.

Sixth, the noise generated by the stacked structure is lower than that of a single UHV NMOS configuration. In the spliced structure, the current control is performed mainly by the regulating transistor, and in the single UHV NMOS configuration, the current control is performed by the UHV NMOS. Since the gate capacitance of the LV/MV/HV NMOS is lower than the UHVNMOS, the noise generated by the stacked structure is lower than that of the single UHV NMOS configuration.

It is noted that the shielded transistors UHV1 to UHVn may be identical to or different from each other. Also, the adjustment transistors LV/MV/HV may be the same or different from each other. You can choose to shield and adjust the specifications of the transistor to achieve the designer's goals.

Figure 3 shows a schematic diagram of an LED driver circuit 30 in accordance with another embodiment of the present invention. As shown, the driver 30 is similar to the driver 20 of FIG. 2, with the difference that the gate voltage of each of the shielded transistors (such as UHV1) is supplied by a circuit logic (such as logic 1). Logic 1 to Logic n may be identical to each other or different from each other such that the shielded transistors UHV1 to UHVn may be operated at different gate voltages. For example, the gate voltage from logic 1 can be lowest while the gate voltage from logic n can be the highest.

Figure 4 shows a schematic diagram of an LED driver circuit 40 in accordance with another embodiment of the present invention. As shown, the driver 40 is similar to the driver 20 of FIG. 2, with the difference being the gate voltage of the stacked adjustment transistor (or Equivalently, the source voltage of the shielded transistor is input to the control logic of the current regulation circuit, which corresponds to the LED upstream of the regulation transistor. For example, the source voltage VD2 of the shield transistor UHV2 is input to the control logic 1 corresponding to the LED 1. During operation, as Vrect increases, current i2 increases and source voltage VD2 of shielded transistor UHV2 also increases. When the source voltage VD2 reaches a preset level, the output voltage of the control logic 1 is set to ground to switch the current i1, causing the same current to flow through both the LED 1 and the LED 2. When current i1 is redirected to LED 2, LED 2 produces more light, thereby increasing the overall efficiency of the LED.

Figure 5 shows a schematic diagram of an LED driver circuit 50 in accordance with another embodiment of the present invention. As shown, the driver 50 is similar to the driver 40 of FIG. 4, with the difference that the gate voltage Vcc2 of each of the shielded transistors (e.g., UHV1) is supplied by a circuit logic (e.g., logic 1). Since the operation of the driver 50 is similar to that of the driver 40, the detailed description of the operation is not repeated.

Figure 6 shows a schematic diagram of control logic 60 that may be used in drivers 10, 20, 30, 40, and 50 in accordance with another embodiment of the present invention. As shown, control logic 60 includes: a transistor 68, preferably an NMOS, an inverter 62; a pass gate 66, preferably a combination of NMOS and PMOS; and a voltage level detector 64.

The output Vvlc from the voltage level controller of Figures 1 through 5 is input to the pass gate 66, and the output from the pass gate 66 is connected to the gate of a transistor (such as UHV2 of Fig. 1), or the regulation is regulated. The gate of a crystal (such as LV/MV/HV of Figures 2 to 5) to control flow through, for example, LED2 Current. For convenience of explanation, it is assumed that the control logic 60 of FIG. 6 corresponds to the control logic 2 of FIG. The voltage level detector 64 receives the input signal "OFFnext" from the control logic 3. When current i3 flows through UHV3 and cuts off current i2, control logic 2 sends a signal "OFFprev" to control logic 1, causing control logic 1 to continue to cut off current i1. Voltage level detector 64 also receives a signal from detector 3 ("Vdet") and shuts off current i2 when Vrect is high enough to cause current i3 to reach a predetermined level.

It is noted that voltage level detector 64 can optionally receive signal Vpc from frequency detector and phase control logic 12. (The frequency detector and phase control logic 12 are discussed in conjunction with Figures 8A through 10C). Using input signals Vdet, OFFnext, and optionally Vpc, voltage level detector 64 sends a signal to pass gate 66 and transistor 68, thereby controlling the level of output voltage Vgate from control logic 60 in FIG. (As mentioned above, the output signal Vgate is the input to the gate of UHV or LV/MV/HV.) In detail, when Vdet is low, the output voltage Vcon of the voltage level detector 64 is low and Vvlc is directly transferred. Go to Vgate. As Vdet increases, Vcon gradually decreases. When Vdet reaches a predetermined level, that is, when Vcon is increased to a certain level, pass gate 66, inverter 62, and transistor 68 operate to tie the output of pass gate 66 to the ground level. As a result, Vgate is also at the ground level, causing current i2 to be cut. And, when the current i3 flows, the OFFnext signal is active, so that the control logic 2, in detail, the voltage level detector 64 of the control logic 2, sends the signal OFFprev to the control logic 1, so that the control logic 1 continues to cut off the current i1. .

Figure 7A shows an available drive for use in accordance with another embodiment of the present invention. Schematic diagram of detector 70 in units 10, 20, 30, 40, and 50. As shown, the detector 70 includes an amplifier 71 and a resistor 73. An amplifier 71, which is preferably an operational amplifier, compares the reference voltage Vref with the voltage at node n and transmits an output signal Vdet based on the comparison.

Figure 7B shows a schematic diagram of detectors 76 that may be used in drivers 10, 20, 30, 40, and 50 in accordance with another embodiment of the present invention. Detector 76 is similar to detector 70 except that the reference voltage of amplifier 77 corresponds to the voltage at node Nref.

As shown in FIG. 1, phase control logic 12 sends a signal to control logic 1 to control logic n. In particular, each control logic voltage level detector 64 receives a signal from phase control logic 12. The operation of phase control logic 12 includes measuring the AC 1⁄2 cycle time, where AC 1⁄2 cycle time refers to half of the cycle period of the AC signal. Figure 8A shows the waveform of the rectified voltage input to the driver 10 as a function of time, where the AC 1⁄2 cycle time is the time interval between times T1ra and T1rb or between T1fa and T1fb. Figure 8D shows a schematic diagram of phase control logic 12 of Figure 1. As shown in Figure 8D, detector 83 monitors the voltage level of Vrect and sends a signal enable 1 when Vrect rises to a predetermined level (e.g., Vval). For example, detector 83 transmits a first enable signal at T1ra. Clock pulse counter 84 then begins counting the clock signals received from oscillator 86. When Vrect rises to Vval at T1rb, detector 83 sends a second enable signal to clock counter 84 and clock counter 84 stops counting the clock signal. Next, the measured count value is transferred (or loaded) to the frequency selector 85 to determine the frequency of the AC input (or Vrect). In turn After shifting the measured count value, the clock counter 84 resets the counter value and starts counting again to maintain monitoring of the rectified AC voltage frequency.

Based on the determined frequency, the frequency selector 85 selects a preset time interval of the switcher tab (or simply the tab). The driver 10 (shown in FIG. 1) includes n ears 81 corresponding to the input 控制 of the control logic 1 to the control logic n, and the frequency selector 85 assigns a preset time interval to each of the ears, wherein the preset The time interval refers to the time interval between a reference point (such as T1ra) and the time at which a signal will be sent to the corresponding ear (such as P1 in Figure 8A).

Detector 87 monitors the level of falling (or rising) Vrect and transmits enable signal enable 2 when Vrect falls (or rises) to a predetermined voltage level (such as Vval). Clock pulse counter 88 then begins counting the clock signals generated by oscillator 86. Thereafter, the ear selector 89 receives the count from the clock counter 88. Next, the patch selector 89 compares the count received from the clock counter 88 with the preset time interval received from the frequency selector 85, and transmits the switch enable signal when the count of the pulse counter 88 matches the preset time interval. To one of the ears 81. Upon receiving the switch enable signal from the ear selector 89, a corresponding ear, such as control logic 1, turns on/off the transistor UHV1.

The clock counter 84 (or clock counter 88) can be replaced with a digital lock loop or a phase locked loop. Since DLLs, PLLs, and Time Pulse Counters are well known in the art, they will not be described in detail in this document.

Driver 10 can continuously turn each group of LEDs on/off based on signals received from phase control logic 12. For example, phase control logic 12 A signal is sent to control logic 1 to turn on transistor UHV1 while turning off other transistors UHV2 through UHVn. As will be discussed in conjunction with Figures 10A through 10C, phase control logic 12 can send an output signal to control logic 1 to control logic n to control transistors UHV1 through UHVn in various time series.

For simplicity and ease of illustration, it is assumed that the tab 81 includes four tabs, that is, there are only four LED clusters in the following discussion. Since there are four control logics, eight preset time intervals are assigned by the frequency selector 85 (i.e., as shown in Fig. 8A, T1ra and P1, T1ra and P2, T1ra and P3, T1ra and P4, T1ra and P5). , T1ra and P6, T1ra and P7, the time interval between T1ra and P8) to the corresponding control logic. Since each of the preset time intervals corresponds to a fixed phase point of the input voltage waveform, each of the preset time intervals also refers to a phase difference between the reference phase of T1ra and the phase of the corresponding point (such as P1). . Therefore, the term "preset time interval" and "preset phase difference" can be used interchangeably.

As described above, the detector 83 can transmit an enable signal when the Vrect rises or falls to Vval. For example, detector 83 can send an enable signal at T1fa and T1fb (or T1ra and T1rb), so clock counter 84 can count the clock signal during an AC 1⁄2 cycle time. Likewise, detector 87 can send an enable signal when Vrect rises or falls to Vval. It is also noted that detectors 83 and 87 can transmit enable signals at different preset voltage levels.

Figures 8B and 8C show various waveforms of the rectified voltage to the driver 10 of Figure 1, wherein the AC input voltage is processed by the dimmer switch. As shown, the dimmer switch maintains the AC input voltage to ground level until the AC input voltage rises to Vdim (Fig. 8B) or to Vdim (Fig. 8C). The phase control logic 12 can measure the AC 1⁄2 cycle time by counting the clock signals between T2ra and T2rb or between T2fa and T2fb. In detail, the detectors 83 and 87 can transmit an enable signal at one of the time points T2ra, T2rb, T2fa, and T2fb. The same analogy applies to Vrect in Figure 8C, that is, detectors 83 and 87 can transmit an enable signal at one of time points T3ra, T3rb, T3fa, and T3fb.

Phase control logic 12 controls currents i1 through i4 based on the frequency and phase of the AC input voltage waveform. This mode is useful when the noise level of the AC power source is high and/or it is desirable to have the current waveform smoothly follow the AC input voltage waveform. As shown in Fig. 1, the current i1 is controlled by a feedback control system formed by the detector 1, the control logic 1, the voltage level controller 1, and the UHV1. If the current i1 is controlled only by the feedback control mechanism, when the noise level of the Vrect is high, the current i1 will fluctuate significantly because the feedback control mechanism depends on the level of the Vrect. Fluctuations in current flow i1 to i4 may cause brightness flicker that is perceived by the human eye.

Figures 9A and 9B show two waveforms of the rectified voltage that can be input to the driver 10 of Figure 1. Unlike the dimmer used to generate the waveforms in Figures 8B and 8C, the dimmer used to generate the waveforms in Figures 9A and 9B cuts off the portion after each cycle, that is, after Vrect rises/falls to Vdim. Maintain the Vrect at the ground level. Since the phase control logic 12 measures the frequency and phase in the same manner as described in Figures 8B and 8C, a detailed description of the operational procedures of the phase control logic 12 is omitted for simplicity. can More information on the operation of phase control logic 12 is found in the previously cited U.S. Patent Application Serial No. 13/244,900.

Figure 10A shows the output signal of phase control logic 12 of Figure 1, wherein four tab switches (or simply tabs) correspond to four control logics 1 through 4. In detail, each of the ear switching signals, such as the ear 1 switching signal, is sent to the corresponding control logic, such as control logic 1, to cause the control logic to turn on/off the corresponding regulating transistor, such as UHV1. As shown in FIG. 10A, the hat portion of each of the ear switching signal waveforms represents the time interval when the corresponding control logic is turned on (ie, the output signal of the control logic is higher than the ground level, or in other words, The ear switching signal is in the current state). Therefore, the signal sent to the control logic is serialized in time such that only one of the transistors UHV1 to UHV4 is turned on at each point in time. In particular, the phase control logic 12 sends an enable and disable signal to control logic 1 at P1 and P2, respectively. (Here, P1 to P8 in Fig. 10A correspond to P1 to P8 in Fig. 8A, respectively). Similarly, control logic 2, control logic 3, and control logic 4 are turned on/off by signals at P2/P3, P3/P4, and P4/P5, respectively. When Vrect is reduced from its peak, control logic 3, control logic 2, and control logic 1 are turned on/off by signals at P5/P6, P6/P7, and P7/P8, respectively. Therefore, only one control logic is turned on at each point in time (ie, in the current state).

Figure 10B shows the output signal of phase control logic 12 of Figure 1 in accordance with another embodiment. As shown, the waveform of the Vrect is similar to that of Vrect in Figure 9A, that is, the dimmer is used to generate the waveform of Figure 10B. The timing in Figure 10B is similar to those in Figure 10A, that is, in Only one control logic is turned on at each time point. Note that in Figure 10B, the ear 2 switch (such as control logic 2) can be in the current state at Pd. However, when Vrect drops to ground level at Pd, the current flowing through the second current regulating circuit will also drop to zero at Pd. And, even if the control logic 1 is in the current state, no current flows between the P7 and P8 through the LED group. Thus, the total light emitted by the LED population will dim as desired by the dimmer designer.

Figure 10C shows the output signal of phase control logic 12 of Figure 1 in accordance with another embodiment. As shown, the waveform of the Vrect is similar to the Vrect in Figure 8B, that is, the dimmer is used to generate the waveform in Figure 10C. The timings in Fig. 10C are similar to those in Fig. 10A, that is, only one control logic is turned on at each time point. Note that in Figure 10C, the ear 2 switch (such as control logic 2) is turned on at P2. However, when the Vrect rises from the ground level of Pd, the current will begin to flow through the second current regulating circuit at Pd, that is, the current will not flow between P2 and Pd. And, even if the control logic 1 is in the current state, no current flows between the LED groups between P1 and P2. Thus, the total light emitted by the LED population will dim as desired by the dimmer designer.

As discussed above, phase control logic 12 can be implemented in the drivers of Figures 2 through 5. Also, the dimmer switch can be implemented in the drivers in Figures 2 through 5. Therefore, the waveforms and sorting patterns shown in FIGS. 9A to 10C can be applied to all of the driver circuits described in conjunction with FIGS. 2 to 5.

In Figure 1, phase control logic 12 is depicted as a separate component from the voltage level controller and control logic. However, there is a pass in this skill. It should be apparent to those skilled in the art that phase control logic 12 can be combined with a voltage level controller and control logic to form an integrated circuit.

Of course, it is to be understood that the above-described exemplary embodiments of the present invention may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

10‧‧‧LED driver circuit (driver)

12‧‧‧ Frequency detector and phase control logic (phase control logic)

20‧‧‧LED driver circuit (driver)

30‧‧‧LED driver circuit (driver)

40‧‧‧LED driver circuit (driver)

50‧‧‧LED driver circuit (driver)

60‧‧‧Control logic

62‧‧‧ reverser

64‧‧‧Voltage level detector

66‧‧‧Open gate

68‧‧‧Optoelectronics

70‧‧‧Detector

71‧‧‧Amplifier

73‧‧‧Resistors

76‧‧‧Detector

77‧‧‧Amplifier

81‧‧‧ ear

83‧‧‧Detector

84‧‧‧clock counter

85‧‧‧ frequency selector

86‧‧‧Oscillator

87‧‧‧Detector

88‧‧‧clock counter

89‧‧‧ Ear Selector

1 is a schematic view showing an LED driver circuit according to an embodiment of the present invention; FIG. 2 is a schematic view showing an LED driver circuit according to another embodiment of the present invention; and FIG. 3 is a view showing another embodiment of the present invention. A schematic diagram of an LED driver circuit; FIG. 4 is a schematic diagram showing an LED driver circuit according to another embodiment of the present invention; FIG. 5 is a schematic diagram showing an LED driver circuit according to another embodiment of the present invention; Another embodiment of the invention is a schematic diagram of control logic of the type that can be used in the drivers of Figures 1 through 5; Figure 7A shows a driver that can be used in Figures 1 through 5 in accordance with another embodiment of the present invention. Schematic diagram of a detector of the type; FIG. 7B shows a schematic diagram of a detector of the type usable in the driver of FIGS. 1 to 5 according to another embodiment of the present invention; FIGS. 8A to 8C show the input to the 1 to 5 of the LED's Various waveforms of the rectified voltage; FIG. 8D shows a schematic diagram of a frequency detector and phase control logic of the type that can be included in the driver of FIG. 1 according to another embodiment of the present invention; FIGS. 9A and 9B show input Various waveforms of the rectified voltages of the LEDs of Figs. 1 to 5; Figs. 10A to 10C show the output signals of the frequency detector and phase control logic of Fig. 8D.

10‧‧‧LED driver circuit (driver)

Claims (22)

A driver circuit for driving a light emitting diode (LED), comprising: a group of LEDs divided into n groups, the n groups of LEDs are electrically connected to each other in series, and the downstream end of the group m-1 is electrically connected to the upstream end of the group m, wherein n and m are positive integers and satisfy the condition of l<m<n; and a complex current regulating circuit, each of the current regulating circuits being coupled to a downstream end of a corresponding group and including a stack having first and second transistors A detector for measuring the current flowing through the respective group is connected. The driver circuit of claim 1, wherein each of the groups comprises one or more LEDs and resistors of the same or different kinds, colors, and values connected in parallel or in series or in a combination thereof . The driver circuit of claim 1, wherein the first transistor is an ultra high voltage (UHV) transistor and is an N-channel MOSFET, a P-channel MOSFET, an NPN bipolar transistor, a PNP bipolar transistor, Or an insulated gate bipolar transistor (IGBT), and wherein the second transistor is a low voltage, medium voltage, or high voltage transistor and is an N-channel MOSFET, a P-channel MOSFET, an NPN bipolar transistor, and a PNP bipolar Crystal, or insulated gate bipolar transistor (IGBT). The driver circuit of claim 3, further comprising: a plurality of circuit logics, each of the plurality of circuit logics adapted to provide a predetermined voltage, wherein a gate of the second transistor is coupled to the plurality of circuits Logic A corresponding one. The driver circuit of claim 3, further comprising: circuit logic for providing a predetermined voltage, wherein a gate of the first transistor of each of the current regulating circuits is coupled to the circuit logic. The driver circuit of claim 1, wherein each of the current regulating circuits comprises: a voltage level controller adapted to receive a signal from the detector and transmit an output signal based on the signal from the detector And control logic adapted to receive the output signal from the voltage level controller and directly transmit an output signal to the gate of the second transistor. The driver circuit of claim 6, wherein the detector corresponding to a downstream group is adapted to detect current flowing through the downstream group and to transmit the signal to the control logic corresponding to the next upstream group. The driver circuit of claim 6, wherein the control logic corresponding to a downstream group is adapted to receive signals from the control logic corresponding to the next upstream group. The driver circuit of claim 6, wherein the second transistor has a drain directly connected to a source of the first transistor, and wherein the first transistor corresponding to a downstream group The source is directly connected to the control logic corresponding to the next upstream group. The driver circuit of claim 6, wherein the detector comprises an amplifier connected to the reference voltage for supplying thereto Reference voltage source. The driver circuit of claim 10, wherein the reference voltage source comprises a reference current and a resistor. The driver circuit of claim 6, further comprising: phase control logic comprising: a level for monitoring an input voltage applied to the driver and transmitting an enable signal when the level reaches a preset level a detector; a frequency selector for determining a frequency of the input voltage applied to the driver based on the enable signal and assigning a predetermined time interval to each of the current adjustment circuits; and for using the enable signal The elapsed time matches a particular one of the current regulating circuits when the preset time interval is selected and sends a control signal to the selector of the particular current regulating circuit. The driver circuit of claim 12, wherein the phase control logic is directly coupled to the control logic of each of the current regulation circuits. A method of driving a light emitting diode (LED), comprising: providing a group of LEDs, the groups being electrically connected in series with each other; coupling each of the groups to a ground through respective current regulating circuits, the current regulating circuit comprising Having a stack of first and second transistors; causing detectors of the respective current regulating circuits to measure current flowing through a respective one of the groups; and controlling the current based on the measured current. The method of claim 14, further comprising: causing the detector to send a signal commensurate with the measured current to a voltage level controller of the respective current regulating circuit; causing the voltage level controller to transmit Signaling to control logic of the respective current regulating circuits; and causing the control logic to directly transmit signals to the gates of the second transistors of the respective current regulating circuits. The method of claim 15, further comprising: causing a detector of a downstream group to send a signal to the next group of control logic upstream of the downstream group. The method of claim 15, further comprising: the control logic connecting the drain of the second transistor of a downstream group to the next group upstream of the downstream group. The method of claim 15, further comprising: providing a plurality of circuit logics, each of the plurality of circuit logics adapted to provide a predetermined voltage; and connecting the gates of the second transistor to the plurality of circuits One of the logics corresponds. The method of claim 15, further comprising: Providing circuit logic for supplying a preset voltage; and connecting a gate of the first transistor to the circuit logic. The method of claim 15, further comprising: providing a dimmer switch; and causing the dimmer switch to process voltage waveforms applied to the LEDs of the string to thereby adjust the LEDs of the string Brightness. The method of claim 15, further comprising: directly connecting the phase control logic to the control logic of each of the groups; and between the phase of the voltage waveform applied to the groups and the reference phase When the difference matches the preset phase difference, the phase control logic sends a signal to the control logic. A driver circuit for driving a light emitting diode (LED), comprising: a group of LEDs divided into n groups, the n groups of LEDs are electrically connected to each other in series, and the downstream end of the group m-1 is electrically connected to the upstream end of the group m, wherein n and m are positive integers and satisfy the condition of l<m<n; a complex current regulating circuit, each of the current regulating circuits being coupled to a downstream end of a corresponding group and including a transistor; and phase control logic comprising: a detector for monitoring the level of an input voltage applied to the driver and transmitting an enable signal when the level reaches a preset level; a frequency selector for determining a frequency of the input voltage based on the enable signal and allocating a preset time interval to each of the current adjustment circuits; and for matching the preset time from an elapsed time of the enable signal A selector of one of the current regulating circuits is selected at intervals and a control signal is sent to the gate of the particular current regulating circuit.