TW201705319A - Packaging substrate and manufacturing method thereof - Google Patents

Abstract

A packaging substrate includes a first dielectric layer, a first wiring layer, a first conductive pillar layer, a second dielectric layer, a second wiring layer, an electrical pad layer, and a third dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface, plural openings, and a wall surface that faces at least one of the openings. The first wiring layer is located on the first surface and the wall surface. The first wiring layer on an edge of the wall surface adjacent to the second surface extends in a direction away from the wall surface. The first conductive pillar layer is located on the first wiring layer. The second dielectric layer is located on the first surface, the first wiring layer, and in the openings. And, the first conductive pillar layer is exposed from the second dielectric layer. The second wiring layer is located on the exposed first conductive pillar layer and the second dielectric layer. The electrical pad layer is located on the second wiring layer. The third dielectric layer is located on the second dielectric layer and the second wiring layer.

Description

Package substrate and manufacturing method thereof

The invention relates to a package substrate and a method for fabricating a package substrate.

The package substrate is used to carry an integrated circuit (IC) die and is used as a carrier. In addition, the package substrate has internal lines and contacts, so that the contacts on opposite sides of the package substrate can be used to electrically connect the semiconductor die and the printed circuit board (PCB), respectively. In this way, the semiconductor die and the circuit board can transmit signals through the internal lines of the package substrate. With the evolution of semiconductor process technology, the demand for wiring density, transmission rate, and signal interference of semiconductor dies has been greatly increased, making package substrates widely used in electronic products. For example, the package substrate can be used for products such as smart phones, tablets, network communications, and notebook computers.

When fabricating a conventional package substrate, a patterned conductive layer is first formed on the carrier such that the conductive layer has an opening of the bare carrier. Next, a copper pillar layer is formed on the conductive layer, and the conductive layer and the opening are covered with a dielectric layer. In this way, after removing the carrier, all the conductive layers are exposed, and only a part of these conductive layers are used to electrically connect the semiconductor die. When the conductive layer is directly and semi-conductive When the joints of the body grains are combined, the bonding force is easily broken and the reliability is lowered. In order to improve the bonding force between the package substrate and the semiconductor die, the nickel layer and the gold layer are generally plated on the conductive layer, but limited by the process capability, the nickel layer and the gold layer are formed on all the exposed conductive layers, and It cannot be formed only on the conductive layer corresponding to the semiconductor die contact, so the cost of the package substrate is greatly increased.

One aspect of the present invention is a package substrate.

According to an embodiment of the invention, a package substrate includes a first dielectric layer, a first wiring layer, a first conductive pillar layer, a second dielectric layer, a second wiring layer, an electrical underlayer, and a third dielectric layer. The first dielectric layer has opposing first and second surfaces, a plurality of openings extending through the first surface and the second surface, and a wall facing at least one of the openings. The first wire layer is located on the first surface and the wall surface, and the first wire layer extends in a direction away from the wall surface at an edge of the wall surface adjacent to the second surface. The first conductive pillar layer is on the first wire layer on the first surface. The second dielectric layer is on the first surface, on the first wire layer and in the opening, and the first conductive pillar layer is exposed from the second dielectric layer. The second wire layer is on the exposed first conductive pillar layer and the second dielectric layer. The electrical pad is on the second wire layer. The third dielectric layer is on the second dielectric layer and the second conductive layer, and the electrical underlayer is exposed from the third dielectric layer.

Another technical aspect of the present invention is a method of fabricating a package substrate.

According to an embodiment of the invention, a method of fabricating a package substrate comprises the following steps. Forming a patterned first dielectric layer on the carrier to enable A dielectric layer has a plurality of openings. Forming a first wire layer on the first surface of the first dielectric layer facing away from the carrier and on the wall facing at least one of the openings, and on the carrier in at least one of the openings. Forming a first conductive pillar layer on the first wire layer on the first surface. Forming a second dielectric layer on the first surface, on the first wiring layer and the opening, wherein the first conductive pillar layer is exposed from the second dielectric layer. Forming a second wire layer on the exposed first conductive pillar layer and the second dielectric layer. An electrical underlayer is formed on the second wire layer. Forming a third dielectric layer on the second dielectric layer and the second wiring layer, wherein the electrical pad layer is exposed from the third dielectric layer.

In the above embodiment of the present invention, the first dielectric layer having the plurality of openings is first formed on the carrier, and then the first wiring layer is formed on the first surface of the first dielectric layer and at least one of the openings On the wall, and on the carrier in at least one of the openings. As a result, when the carrier is removed, only a portion of the first wire layer is exposed from the second surface of the first dielectric layer. Wherein, the position of the exposed first wire layer corresponds to the contact position of the semiconductor die. In the subsequent process, since only the first wire layer corresponding to the position of the semiconductor die contact is exposed from the second surface of the first dielectric layer, the nickel layer and the gold layer are only plated on a portion of the first wire layer, so that The package substrate of the invention can effectively save the cost of the nickel layer and the gold layer.

One aspect of the present invention is a package substrate.

According to an embodiment of the invention, a package substrate includes a first dielectric layer, a first wiring layer, a first conductive pillar layer, a second dielectric layer, a second wiring layer, a second conductive pillar layer and a third dielectric layer . The first dielectric layer has opposing first and second surfaces, a plurality of openings extending through the first surface and the second surface, and a wall facing at least one of the openings. The first wire layer is on the first surface On the wall surface, the first wire layer extends in a direction away from the wall surface at an edge of the wall surface adjacent to the second surface. The first conductive pillar layer is on the first wire layer on the first surface. The second dielectric layer is on the first surface, on the first wire layer and in the opening, and the first conductive pillar layer is exposed from the second dielectric layer. The second wire layer is on the exposed first conductive pillar layer and the second dielectric layer. The second conductive pillar layer is on the second wire layer. The third dielectric layer is on the second dielectric layer and the second conductive layer, and the second conductive pillar layer is exposed from the third dielectric layer.

Another technical aspect of the present invention is a method of fabricating a package substrate.

According to an embodiment of the invention, a method of fabricating a package substrate comprises the following steps. Forming a patterned first dielectric layer on the carrier such that the first dielectric layer has a plurality of openings. Forming a first wire layer on the first surface of the first dielectric layer facing away from the carrier and on the wall facing at least one of the openings, and on the carrier in at least one of the openings. Forming a first conductive pillar layer on the first wire layer on the first surface. Forming a second dielectric layer on the first surface, on the first wiring layer and the opening, wherein the first conductive pillar layer is exposed from the second dielectric layer. Forming a second wire layer on the exposed first conductive pillar layer and the second dielectric layer. Forming a second conductive pillar layer on the second wire layer. Forming a third dielectric layer on the second dielectric layer and the second wiring layer, wherein the second conductive pillar layer is exposed from the third dielectric layer.

100‧‧‧Package substrate

110‧‧‧First dielectric layer

112‧‧‧ first surface

114‧‧‧ second surface

116‧‧‧ openings

118‧‧‧ wall

120‧‧‧First wire layer

122‧‧‧ first subsection

124‧‧‧Second subsection

126‧‧‧ Third subsection

130‧‧‧First conductive column

140‧‧‧Second dielectric layer

150‧‧‧Second wire layer

160‧‧‧Electrical mat (second conductive column)

162‧‧‧Electrical structure

170‧‧‧ Third dielectric layer

180‧‧‧Carrier

182‧‧‧ hollow area

200‧‧‧Electronic devices

210‧‧‧Semiconductor grains

212‧‧‧Contacts

214‧‧‧ Nickel layer

216‧‧‧ gold layer

230‧‧‧ boards

D‧‧‧ Direction

L-L‧‧‧ line segment

S1~S7‧‧‧ steps

1 is a cross-sectional view showing a package substrate according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the package substrate of FIG. 1 applied to an electronic device.

FIG. 3 is a flow chart showing a method of fabricating a package substrate according to an embodiment of the present invention.

4 is a cross-sectional view of a carrier and a first dielectric layer in accordance with an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the first wiring layer formed on the first dielectric layer of FIG. 4.

FIG. 6 is a cross-sectional view showing the first conductive pillar layer formed on the first wire layer of FIG. 5.

FIG. 7 is a cross-sectional view showing the first dielectric layer of FIG. 6 and the second dielectric layer formed on the first wiring layer.

Figure 8 is a cross-sectional view showing the second conductive layer formed on the first conductive pillar layer of Figure 7.

Figure 9 is a cross-sectional view showing the formation of an electrical underlayer on the second wiring layer of Figure 8.

Figure 10 is a cross-sectional view showing the formation of a third dielectric layer on the second dielectric layer of Figure 9.

Figure 11 is a cross-sectional view showing the carrier of Figure 10 after etching.

The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. and also That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

FIG. 1 is a cross-sectional view showing a package substrate 100 according to an embodiment of the present invention. As shown, the package substrate 100 is a coreless substrate including a first dielectric layer 110, a first conductive layer 120, a first conductive pillar layer 130, a second dielectric layer 140, and a second conductive layer. 150. The electrical pad layer 160 and the third dielectric layer 170. Herein, the electrical pad layer 160 may have a shape and a material such as the first conductive pillar layer 130. Therefore, the electrical pad layer 160 may also be a second conductive pillar layer. That is to say, the "electrical pad 160" described herein can be replaced by the "second conductive column layer 160", which is described first. The first dielectric layer 110 has a first surface 112, a second surface 114, a plurality of openings 116 and a wall surface 118. The first surface 112 is opposite the second surface 114. The opening 116 extends through the first surface 112 and the second surface 114. The wall 118 faces the opening 116. The first wire layer 120 is on the first surface 112 of the first dielectric layer 110 and the wall surface 118 of at least one of the openings 116. In addition, the first wire layer 120 extends in a direction D away from the wall surface 118 from the edge of the wall surface 118 adjacent to the second surface 114, so that the first wire layer 120 is stepped.

The first conductive pillar layer 130 is located on the first wire layer 120 of the first surface 112. The second dielectric layer 140 is located on the first surface 112 of the first dielectric layer 110, on the first wiring layer 120 and in the opening 116 of the first dielectric layer 110. The top of the first conductive pillar layer 130 is exposed from the second dielectric layer 140, and the second wiring layer 150 is located on the exposed first conductive pillar layer 130 and the second dielectric layer 140. The electrical pad 160 is located on the second wire layer 150. The third dielectric layer 170 is located in the second dielectric The layer 140 is on the second wire layer 150, and the top of the electrical pad layer 160 is exposed from the third dielectric layer 170.

With the above design, only a portion of the first wiring layer 120 of the package substrate 100 of the present invention is exposed from the second surface 114 of the first dielectric layer 110, and the first dielectric layer 110 exposed at the second surface 114 is available. The semiconductor die is electrically connected. That is to say, the package substrate 100 can only expose the first wire layer 120 to be connected to the semiconductor die, thereby saving the cost of plating the nickel layer and the gold layer on the first wire layer 120. In addition, the stepped first wire layer 120 is a 3D three-dimensionally connected trace, which is helpful for circuit layout.

In this embodiment, the material of the first dielectric layer 110, the second dielectric layer 140, and the third dielectric layer 170 may be epoxy resin, ruthenium oxide or nitrogen oxide, and the first dielectric layer 110 The materials of the second dielectric layer 140 and the third dielectric layer 170 may be the same, but are not intended to limit the present invention. The material of the first conductive layer 120, the first conductive pillar layer 130, the second conductive layer 150 and the electrical underlayer 160 may be copper or other electrically conductive metal, such that the first conductive layer 120, the first conductive pillar layer 130, The second wire layer 150 and the electrical pad layer 160 may be electrically connected to each other by contact.

In addition, the orthographic projection of the first conductive pillar layer 130 at the first dielectric layer 110 is spaced apart from the opening 116. That is, the position of the first conductive pillar layer 130 is not aligned with the position of the opening 116, so that the position of the first conductive pillar layer 130 is not limited by the position of the opening 116, and the flexibility in line layout can be provided.

In the present embodiment, the first wire layer 120 includes a first sub-portion 122, a second sub-portion 124, and a third sub-portion 126. The first sub-portion 122 is located on the first surface 112 of the first dielectric layer 110. The second sub-portion 124 is connected to the first sub-portion 122 One end is located on the wall surface 118. The third sub-portion 126 connects one end of the second sub-portion 124 with respect to the first sub-portion 122, and the third sub-portion 126 extends in a direction D away from the wall surface 118. The first sub-portion 122 is opposite to the extending direction D of the third sub-portion 126 in the extending direction of the first surface 112, so that the first sub-portion 122, the second sub-portion 124, and the third sub-portion 126 are substantially zigzag-shaped. In addition, the first sub-portion 122 can be electrically connected to the first conductive pillar layer 130, and the third sub-portion 126 can be used to electrically connect the semiconductor die.

FIG. 2 is a cross-sectional view showing the package substrate 100 of FIG. 1 applied to the electronic device 200. The electronic device 200 includes a package substrate 100, a semiconductor die 210, and a circuit board 230. The semiconductor die 210 is disposed on the package substrate 100 , and the package substrate 100 is disposed on the circuit board 230 . The semiconductor die 210 has contacts 212. The position of the first wire layer 120 exposed from the first dielectric layer 110 corresponds to the position of the contact 212 of the semiconductor die 210, so that the first wire layer 120 is electrically connected to the contact 212 of the semiconductor die 210. In the present embodiment, the nickel layer 214 and the gold layer 216 may be plated on the first wire layer 120 to increase the bonding force between the first wire layer 120 and the contact 212. In addition, a conductive structure 162 may be formed on the exposed electrical pad layer 160 of the third dielectric layer 170 to electrically connect the circuit board 230. The conductive structure 162 can be, for example, a Ball Grid Array (BGA), but is not limited thereto. As such, the package substrate 100 can serve as a medium for signal transmission between the semiconductor die 210 and the circuit board 230.

Only a portion of the first wire layer 120 of the package substrate 100 may be exposed from the second surface 114 of the first dielectric layer 110. Since only the first wire layer 120 corresponding to the position of the contact 212 of the semiconductor die 210 is exposed from the first dielectric layer 110, the nickel layer 214 and the gold layer 216 are formed only in a portion of the first wire layer 120. In the above, the package substrate 100 of the present invention can effectively save the cost of the nickel layer 214 and the gold layer 216.

In this embodiment, the second surface 114 of the first dielectric layer 110 is coplanar with the first wire layer 120 extending away from the wall surface 118, so that the semiconductor die 210 can be stably located on the first dielectric layer 110. Two surfaces 114.

It should be understood that the relationship between the component materials and the components that have been described will not be repeated, and will be described first. In the following description, a method of manufacturing the package substrate 100 will be described.

FIG. 3 is a flow chart showing a method of fabricating a package substrate according to an embodiment of the present invention. The manufacturing method of the package substrate comprises the following steps: First, in step S1, a patterned first dielectric layer is formed on the carrier, so that the first dielectric layer has a plurality of openings. Next, in step S2, a first wire layer is formed on the first surface of the first dielectric layer facing away from the carrier and on the wall facing at least one of the openings, and on the carrier in at least one of the openings. Then in step S3, a first conductive pillar layer is formed on the first wire layer on the first surface. Next, in step S4, a second dielectric layer is formed on the first surface, on the first wiring layer and in the opening, wherein the first conductive pillar layer is exposed from the second dielectric layer. Then in step S5, a second wire layer is formed on the exposed first conductive pillar layer and the second dielectric layer. Next, in step S6, an electrical underlayer is formed on the second wiring layer. Finally, in step S7, a third dielectric layer is formed on the second dielectric layer and the second wiring layer, wherein the electrical pad layer is exposed from the third dielectric layer.

In the following description, each step of the method of manufacturing the package substrate will be described in detail.

4 is a cross-sectional view of the carrier 180 and the first dielectric layer 110 in accordance with an embodiment of the present invention. The first dielectric layer 110 may be formed on the surface of the carrier 180 and subjected to a patterning process such that the first dielectric layer 110 is patterned to have a plurality of openings 116. The patterning process may include photolithography such as exposure, development, and etching.

FIG. 5 is a cross-sectional view showing the first wiring layer 120 formed on the first dielectric layer 110 of FIG. 4. Referring also to FIGS. 4 and 5, the first dielectric layer 110 has a first surface 112 opposite the carrier 180. After the first dielectric layer 110 to be patterned is formed on the carrier 180, the first wire layer 120 may be formed on the first surface 112 of the first dielectric layer 110 and the wall surface 118 facing at least one of the openings 116. And the carrier 180 in at least one of the openings 116. In the present embodiment, the first wire layer 120 may be sequentially formed by electroless plating, press dry film photoresist, patterning and electroplating, but is not intended to limit the present invention. For example, the sputtering or evaporation process can also form the first wire layer 120.

FIG. 6 is a cross-sectional view showing the first conductive pillar layer 130 formed on the first wire layer 120 of FIG. 5. Referring to FIGS. 5 and 6 , after the first conductive layer 120 is formed, the first conductive pillar layer 130 may be formed on the first conductive layer 120 of the first surface 112 of the first dielectric layer 110 . In the present embodiment, the first conductive pillar layer 130 can be sequentially produced by pressing dry film photoresist, patterning and electroplating processes, but is not intended to limit the present invention.

FIG. 7 is a cross-sectional view showing the first dielectric layer 110 of FIG. 6 and the second dielectric layer 140 formed on the first wiring layer 120. After the first conductive pillar layer 130 is formed on the first wiring layer 120, the first surface of the first dielectric layer 110 may be A second dielectric layer 140 is formed on the first wiring layer 120 and the opening 116 of the first dielectric layer 110, and the first conductive pillar layer 130 is exposed from the second dielectric layer 140. In the process of forming the second dielectric layer 140, the first surface 112 of the first dielectric layer 110, the first wiring layer 120, and the opening 116 of the first dielectric layer 110 may be covered by the second dielectric layer 140. The first conductive pillar layer 130, followed by grinding the surface of the second dielectric layer 140, exposes the first conductive pillar layer 130. In the present embodiment, the second dielectric layer 140 can be molded by using a mold, but is not limited thereto.

FIG. 8 is a cross-sectional view showing the second conductive layer 150 formed on the first conductive pillar layer 130 of FIG. 7. FIG. 9 is a cross-sectional view showing the formation of the electrical pad layer 160 on the second wire layer 150 of FIG. Referring to FIG. 8 and FIG. 9 , after the first conductive pillar layer 130 is exposed from the second dielectric layer 140 , the second conductive layer 150 may be formed on the exposed first conductive pillar layer 130 and the second dielectric layer. 140 on. Next, an electrical pad layer 160 may be formed on the second wire layer 150. In the present embodiment, the second wire layer 150 and the electrical pad layer 160 may be formed in the same manner as the first conductive pillar layer 130, but are not intended to limit the present invention.

FIG. 10 is a cross-sectional view showing the third dielectric layer 170 formed on the second dielectric layer 140 of FIG. 9. 11 is a cross-sectional view showing the carrier 180 of FIG. 10 after etching. Referring to FIG. 10 and FIG. 11 , after the electrical pad layer 160 is formed on the second wire layer 150 , the third dielectric layer 170 may be formed on the second dielectric layer 140 and the second wire layer 150 , and The electrical pad 160 is exposed from the surface of the third dielectric layer 170. The first dielectric layer 110 has a second surface 114 that faces away from the first surface 112. After the third dielectric layer 170 is formed, the carrier 180 may be etched such that the second surface 114 of the carrier 180 and the wall 118 are adjacent to one end of the second surface 114 A wire layer 120 is exposed. The etched carrier 180 has a cutout 182 for bonding the semiconductor die to the first wire layer 120.

After the carrier 180 is etched to form the hollow region 182, the remaining carrier 180 and the edges of the first dielectric layer 110, the second dielectric layer 140, and the third dielectric layer 170 may be cut along the line segment LL. The package substrate 100 is shown in FIG.

The package substrate of the present invention is formed by first forming a first dielectric layer 110 having a plurality of openings 116 on the carrier 180, and then forming a first wiring layer 120 on the first surface 112 of the first dielectric layer 110. On the wall surface 118 of at least one of the opening and the opening 116, and the carrier 180 in at least one of the openings 116. As such, only a portion of the first wire layer 120 will be exposed from the second surface 114 of the first dielectric layer 110 when the carrier 180 is removed. In the subsequent process, since only the first wire layer 120 corresponding to the position of the semiconductor die contact is exposed from the second surface 114 of the first dielectric layer 110, the nickel layer and the gold layer are only plated on a portion of the first wire layer. On the 120, the cost of the nickel layer and the gold layer can be effectively saved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100‧‧‧Package substrate

110‧‧‧First dielectric layer

112‧‧‧ first surface

114‧‧‧ second surface

116‧‧‧ openings

118‧‧‧ wall

120‧‧‧First wire layer

122‧‧‧ first subsection

124‧‧‧Second subsection

126‧‧‧ Third subsection

130‧‧‧First conductive column

140‧‧‧Second dielectric layer

150‧‧‧Second wire layer

160‧‧‧Electrical mat (second conductive column)

170‧‧‧ Third dielectric layer

D‧‧‧ Direction

Claims (10)

A package substrate comprising: a first dielectric layer having a first surface and a second surface, a plurality of openings extending through the first surface and the second surface, and at least one of the openings a first wire layer on the first surface and the wall surface, and the first wire layer extends in a direction away from the wall surface at an edge of the wall surface adjacent to the second surface; a first conductive pillar a layer on the first wire layer on the first surface; a second dielectric layer on the first surface, the first wire layer and the openings, and the first conductive pillar layer The second dielectric layer is exposed; a second wire layer is disposed on the exposed first conductive pillar layer and the second dielectric layer; an electrical pad layer is located on the second wire layer; a third dielectric layer is disposed on the second dielectric layer and the second wiring layer, and the electrical pad layer is exposed from the third dielectric layer. The package substrate of claim 1, wherein the second surface of the first dielectric layer is coplanar with the first wire layer extending away from the wall surface. The package substrate of claim 1, wherein the first wire layer comprises: a first sub-portion on the first surface; a second sub-portion connecting one end of the first sub-portion and located on the wall surface; and a third sub-portion connecting the second sub-portion with respect to one end of the first sub-portion and away from the wall surface extend. The package substrate of claim 3, wherein the extending direction of the first sub-portion in the first surface is opposite to the extending direction of the third sub-portion. The package substrate of claim 1, wherein the first wire layer is stepped. A method for fabricating a package substrate, comprising: (a) forming a patterned first dielectric layer on a carrier such that the first dielectric layer has a plurality of openings; and (b) forming a first wiring layer The first dielectric layer is formed on a first surface of the carrier and a wall surface facing at least one of the openings, and the carrier in at least one of the openings; (c) a first conductive pillar layer on the first wire layer on the first surface; (d) forming a second dielectric layer on the first surface, the first wire layer and the openings, wherein The first conductive pillar layer is exposed from the second dielectric layer; (e) forming a second wiring layer on the exposed first conductive pillar layer and the second dielectric layer; (f) forming an electrical a bedding layer on the second wire layer; (g) forming a third dielectric layer on the second dielectric layer and the second wiring layer, wherein the electrical pad layer is exposed from the third dielectric layer. The method of fabricating a package substrate according to claim 6, wherein the first dielectric layer has a second surface facing away from the first surface, and the method for fabricating the package substrate further comprises: etching the carrier to make the first The two surfaces and the first wire layer at one end of the wall adjacent to the second surface are exposed. The method of fabricating a package substrate according to claim 6, wherein the step (d) comprises: covering the second dielectric layer on the first surface, the first wire layer, the openings, and the first conductive pillar layer And grinding the second dielectric layer to expose the first conductive pillar layer. A package substrate comprising: a first dielectric layer having a first surface and a second surface, a plurality of openings extending through the first surface and the second surface, and at least one of the openings a first wire layer on the first surface and the wall surface, and the first wire layer extends in a direction away from the wall surface at an edge of the wall surface adjacent to the second surface; a first conductive pillar a layer on the first wire layer on the first surface; a second dielectric layer on the first surface, the first wire layer and the openings, and the first conductive pillar layer The second dielectric layer is bare; a second wire layer on the exposed first conductive pillar layer and the second dielectric layer; a second conductive pillar layer on the second wire layer; and a third dielectric layer located at the The second dielectric layer and the second conductive layer are exposed, and the second conductive pillar layer is exposed from the third dielectric layer. A method for fabricating a package substrate, comprising: (a) forming a patterned first dielectric layer on a carrier such that the first dielectric layer has a plurality of openings; and (b) forming a first wiring layer The first dielectric layer is formed on a first surface of the carrier and a wall surface facing at least one of the openings, and the carrier in at least one of the openings; (c) a first conductive pillar layer on the first wire layer on the first surface; (d) forming a second dielectric layer on the first surface, the first wire layer and the openings, wherein The first conductive pillar layer is exposed from the second dielectric layer; (e) forming a second wiring layer on the exposed first conductive pillar layer and the second dielectric layer; (f) forming a second a conductive pillar layer on the second wiring layer; and (g) forming a third dielectric layer on the second dielectric layer and the second wiring layer, wherein the second conductive pillar layer is from the third dielectric layer The layer is bare.