TW201701578A - An electrical circuit and a power module for providing electrical power to electronic devices, and a method of assembling a voltage reduction apparatus - Google Patents

Abstract

An electrical circuit for providing electrical power for use in powering electronic devices is described herein. The electrical circuit includes a primary power circuit and a secondary power circuit. The primary power circuit receives an alternating current (AC) input power signal from an electrical power source and generates an intermediate direct current (DC) power signal. The intermediate DC power signal is generated at a first voltage level that is less than a voltage level of the AC input power signal. The secondary power circuit receives the intermediate DC power signal from the primary power circuit and delivers an output DC power signal to an electronic device. The output DC power signal is delivered at an output voltage level that is less than the first voltage level of the intermediate DC power signal.

Description

Circuit and power module for providing power to an electronic device, and method for assembling a step-down device

The present invention generally relates to power circuits and, more particularly, to a power circuit for providing power for charging and/or powering consumer electronic devices.

The energy crisis needs to respond to the demand side of reducing the current load. The energy crisis has exploded on a global scale. For example, the US Department of Energy predicts that by 2015, on average, there will be insufficient electricity to supply the average US demand.

One of the controllable culprits is "Vampire Load". Also known as "Wall Wart Power" or "Standby Power", the US Department of Energy (DOE) estimates that this waste is more than 100 billion kW per year and wastes more than $10 billion. Vampire load producers include cell phone chargers, laptop chargers, tablet chargers, calculator chargers, small devices, and other battery-powered consumer devices.

The US Department of Energy said in 2008:

"Many devices continue to draw a small amount of power when they are turned off. These "phantom" loads occur in most devices that use electricity, such as VCRs, televisions, stereos, computers, and kitchen equipment. This can be avoided by unplugging the device or using the terminal block and using the switches on the terminal block to cut off all power to the device. "

According to the US Department of Energy, the following types of devices consume standby power:

1. Transformer for voltage conversion. (Includes mobile phones, laptops and tablets, calculators, and other battery-powered devices that use wall chargers).

2. A wall power supply that supplies power to the off device. (Includes cell phones, laptops and tablets, calculators, battery-powered drills, and tools, all with wall chargers that are fully charged or actually disconnected from the device).

3. Many devices with a "quick start" function that respond to user actions without a warm-up delay.

4. Electronic and electrical devices in standby mode that can be woken up by remote control, such as some air conditioners, audiovisual devices, such as television receivers.

5. Electronic and electrical devices that perform some functions, for example, using a power supply timer, even when turned off. Most modern computers consume standby power, allowing them to wait remotely (by Wake on the LAN, etc.) or wake up at a specified time. These functions are always enabled even when they are not needed; they can be saved by disconnecting from mains (sometimes with switches on the back), but only if no function is required.

6. Uninterruptible power supply (UPS)

All of this means that even when the phone, laptop or similar device is fully charged, the current is still flowing, but does not accomplish any tasks and wastes electricity. The newly manufactured devices and equipment continue to draw current and spend money throughout the day and increase the global energy crisis.

The International Standards and Technology Agency (NIST) (US Department of Commerce), through its Building Technology R&D Committee, stated in 2010 its goal of reducing the "plug load", claiming that: "The impact of plug load on total consumption is extremely large. For business buildings, the plug is negative. It is estimated to be 35% of total energy use, 25% for residential and 10% for schools.

Opportunities to reduce plug load include: 1) more efficient plug devices and equipment, 2) automated switching devices that turn off unused equipment and reduce the "vampire" load from transformers and other small but always-on devices, or 3) Correct the behavior of the occupants. "

In fact, one of the problems experienced by modern electronic devices is that power supplies (whether external or embedded "power modules") are not energy efficient. This is true for a number of reasons, one of which dates back to 1831 when Michael Faraday invented the transformer. The intrinsic ground of the transformer is energy inefficient because, as an analog device, it can only produce one power output for each particular winding. Therefore, if two power outputs are required, then two secondary windings are necessary. In addition, there are typically more than 50 components and workpieces that are necessary to cooperate with the transformer to form a common modern external power source, which is only slightly reduced with internal or embedded power modules. The number of components in the power supply is inherently inefficient because the current must travel in various components, travel around and through various components, each having a different power dissipation factor; and even circuit traces can cause resistive losses. It causes energy waste.

In addition, the way the transformer works is to create a magnetic field and collapse it. Since it is impossible to "recapture" all electrons by magnetic field formation/crash, the escaping electrons usually escape as heat, which is why mobile phones, laptops, and tablet chargers feel warm or hot. This is also the cause of heat generation in all consumer electronic devices, which not only wastes energy/electricity, but also causes final wear by heating other related electronic components.

Another low energy efficiency system found in current electronic devices requires multiple internal power supplies To run different parts. For example, in contemporary power modules, MOSFETs have become an increasingly important part of the "reality" interface in circuits.

Metal oxide semiconductor field effect transistor (MOSEFT) enable switch, motor/solenoid drive, transformer interface and a host of other functions. Another aspect of the problem is the microprocessor. The microprocessor is characterized by a stable reduced operating voltage and current, which can be 5 volts, 3.3 volts, 2.7 volts or even 1.5 volts. In most systems, MOSFETs and microprocessors are used together or in combination to operate the circuit. However, typically microprocessor and MOSFET drivers operate at different voltages, resulting in the need for multiple power supplies within the circuit.

A standard high-voltage NMOS MOSFET requires a driver that can transmit a gate voltage of 5 volts to 20 volts for successful turn-on and turn-off. In the case of turning on, there is actually a need for the gate drive voltage to exceed the rail type power that will be effective. Specialized drives using charge pump technology have been designed for this purpose. Another major feature of high voltage MOSFET gate drivers is the reduced input drive requirements that make them compatible with the output drive capabilities of modern CMOS processors.

This MOSFET/driver configuration, which is common in most external power supplies, such as chargers, actually requires three separate power supplies. The first power source required is a mains rail, which typically consists of a rectified line voltage that is supplied to the MOSFET in the range of 127 VDC to 375 VDC. The required second power supply is 15 volts (or higher) required by the MOSFET. Finally, the microprocessor requires another independent power supply for many different and varying voltages.

A good example of current low energy efficiency and energy waste is found in typical televisions, which require up to four to six different power modules to run the screen, backlight, main power circuit board, and sound and auxiliary boards. This current system requires multiple voltages and dozens of components for each of the required power supplies. change The voltage regulator and components (including MOSFETs) double the heat through their repeated low energy efficiency, which is one reason why the back of the TV is always hot to the touch. In addition, the more voltages required for various power outputs, the more components are required and the more energy is wasted.

In addition to thermal issues, power supplies based on multiple transformers typically need to operate from forty to six components, requiring dozens of components for a typical transformer-based TV power module, which increases cost and total component size. While reducing reliability. The increased system resistance with numerous components results in wasted energy in the form of heat.

The present invention is directed to one or more of the above problems to provide greater energy efficiency and to provide greater control over the surge current from a rail-mounted power source.

In one aspect of the invention, circuitry is provided for providing power for charging an application and/or powering a constant supply circuit of an electronic device. The circuit includes a primary power circuit adapted to be electrically coupled to the power source, and a secondary circuit electrically coupled to the primary power circuit. The primary power circuit is configured to receive an alternating current (AC) input power signal from a power source and generate an intermediate direct current (DC) power signal power signal. In the case of an AC input, the intermediate DC power signal is generated at a first voltage level that is less than the voltage level of the AC input power signal. The secondary circuit is configured to receive an intermediate DC power signal from the primary power circuit and transmit the output DC power signal to the electronic device. The output DC power signal is transmitted at an output voltage level that is less than the voltage level of the intermediate DC power signal.

In another aspect of the invention, a power module for providing power for powering electronic devices such as monitors, televisions, large appliances, data centers, and telecommunications circuit boards is provided. The power module includes a rectifier circuit, a switched capacitor voltage collapse circuit, a controller integrated circuit, and a forward converter circuit. The rectifier circuit receives the AC power input signal from the power source and generates a rectified DC power signal. The switched capacitor voltage collapse circuit and the controller integrated circuit receive the rectified DC power signal and generate an intermediate DC power signal based on the integrated controller, the integrated controller sensing the voltage level of the AC power input signal and according to the sensed voltage level The gain of the switching capacitor voltage collapse circuit is adjusted. The forward converter circuit includes a transformer that receives an intermediate DC power signal and produces an output DC power signal that is transmitted to the electronic device.

In yet another aspect of the invention, a high efficiency switched capacitor voltage collapse circuit for AC to DC and DC to DC conversion is provided. The high efficiency switched capacitor voltage collapse circuit includes a plurality of switch assemblies that are coupled in parallel with each other and a plurality of switch assemblies electrically coupled to each of the pair of flyback capacitors. In one embodiment, the gates between the capacitors are common. The switch assembly is operative to selectively transmit an input DC power signal to each of the pair of flyback capacitors during a charging phase and to output during a discharge phase having a voltage level lower than the input DC power signal The DC power signal is transmitted to the electronic device. The at least one switch assembly can include an N-channel MOSFET switch and a level shifter for transmitting control signals to the N-channel MOSFET switch. Additionally, a Dixon charge pump can be coupled to the level shifter to receive the input DC power signal and generate an output power signal having a voltage level that is higher than the input DC signal. The output power signal is transmitted to a level shifter for operating the N-channel MOSFET switch (or for other types of MOSFETs for shutdown). Additionally, the switched capacitor voltage collapse circuit can include a control circuit including: a voltage sensing circuit for sensing a voltage level of the input DC power signal; and a gain controller configured to sense the sensed voltage The level selects the gain setting of the switched capacitor voltage collapse circuit and operates each of the plurality of switch assemblies in accordance with the selected gain setting.

The circuit can also include a vampire load cancellation system configured to determine when the consumer device has completed charging and/or disconnecting from the power circuit and operating the power The circuit is disconnected to the power supply of the power circuit and/or the electronic device and can also form a "standby" mode of weak current supply.

In another aspect of the invention, a power circuit is formed on a semiconductor wafer that includes analogous and digital components on the same wafer. Semiconductor processes (such as the 350V Insulator-on-Board (SoI) BCD process) can be used in semiconductors that will allow microprocessors, timer/quartz timing clocks, PID controllers and PWM controllers, MOSFETs, and corresponding drivers to be integrated into one die on. Moreover, CMOS technology typical of the particular capacitance range from 0.1fF / μ m2 (polypoly capacitor) to 5fF / μ m2 (MIM capacitors) may be considered or ceramic capacitor. Further, a process such as DMOS may be used or a bi/substrate may be considered, such as a layer of cesium carbonate in combination with gallium nitrate or a cerium dioxide bi/substrate may also be used. Or alternatively, the use of gallium nitrate or gallium arsenide and deep trench capacitors can be used instead of germanium for the construction of wafers. All of these choices are necessary because of the low R _on MOSFET or the capacitance required for the transistor.

The BCDMOS process can be used to fabricate power circuits. BCDMOS includes a process for integrating bipolar (analog), CMOS (logic) and DMOS (power) functions on a single wafer for high voltage (UHV) applications. BCDMOS offers a wide range of UHV applications such as LED lighting, AC to DC conversion and switch mode power supplies. Optimized 450V/700V DR-LDMOS transistors can be deployed with integrated circuit (IC) implemented in a non-Epi process with "off-line" operation directly from the 110/220 VAC supply, which specifies low on-resistance and More than 750V breakdown voltage. Designers can expect lower conduction and switching losses when used in power switching applications.

10‧‧‧Electronic charging device

12‧‧‧Power Module

14‧‧‧Shell

16‧‧‧Power pin

18‧‧‧ device connection assembly

20‧‧‧Electronic devices

22‧‧‧Power Circuit

24‧‧‧Power supply

26‧‧‧Primary power circuit

28‧‧‧Secondary power circuit

30‧‧‧Rectifier circuit

32‧‧‧Intermediate voltage converter

34‧‧‧Buck regulator

36‧‧‧ Holding capacitors

40‧‧‧Filter capacitor

42‧‧‧Regulator switch assembly

44‧‧‧Buck circuit

46‧‧‧High voltage step-down diode

48‧‧‧Buck energy storage inductor

50‧‧‧ capacitor

52‧‧‧P channel MOSFET

54‧‧‧ drive

56‧‧‧ position shifter

58‧‧‧PWM controller

60‧‧‧Regulator PWM controller

62‧‧‧ voltage sensing circuit

66‧‧‧Charging phase mode

68‧‧‧Discharge phase mode

70‧‧‧Reciprocating Capacitors

72‧‧‧Switch assembly

74‧‧‧Charging circuit

78‧‧‧Switch cover VBC controller

80‧‧‧ voltage sensing circuit

82‧‧‧CP Gain Controller

84‧‧‧Resistor voltage divider

86‧‧‧ comparator

88‧‧‧Logical decoder

90‧‧‧N-channel MOSFET switch

92‧‧‧ position shifter

94‧‧ Dixon Charge Pump

96‧‧‧ Forward Converter

98‧‧‧Primary buck circuit

100‧‧‧Secondary step-down circuit

102‧‧‧Transformers

103‧‧‧ Forward Converter Controller

104‧‧‧Switch assembly

105‧‧‧Primary side voltage sensing circuit

106‧‧‧ Controller

107‧‧‧Primary side current sensing circuit

108‧‧‧Printed circuit board

109‧‧‧current sensing resistor

110‧‧‧ PID regulator control block

111‧‧‧ comparator

112‧‧‧Switch Mode Buck Regulator Controller

114‧‧‧Buck Driver

116‧‧‧current and temperature sensing block

118‧‧‧ Analog to Digital Converter

120‧‧‧Digital to analog converter

122‧‧‧Digital Control Block

124‧‧‧Power Management Unit

126‧‧‧POR

128‧‧‧LDO Buck Regulator

130‧‧‧PID servo loop

132‧‧‧Digital Control Block

134‧‧‧Digital Control Block

136‧‧‧Internal integrated circuit

150‧‧‧RCD circuit

152‧‧‧Three-stage winding

Other advantages of the present invention will be readily appreciated by the following detailed description of the invention. FIG. 2 is a block diagram of a power circuit for providing power to an electronic device in conjunction with the charging device shown in FIG. 1 according to an embodiment of the present invention; FIG. 3 is a diagram of a power circuit according to the present invention; The combined power circuit of the embodiment uses a schematic diagram of a buck regulator circuit that forms a "hybrid" voltage collapse circuit as shown in FIG. 2; FIGS. 4-7 are combined with FIG. 2 in accordance with an embodiment of the present invention. A schematic diagram of a switched capacitor voltage collapse circuit for use with a power circuit, including a common gate between capacitors to further reduce RDS _ON losses; FIG. 8 is a switched capacitor as shown in FIG. 4 in accordance with an embodiment of the present invention. FIG. 9 is a schematic diagram of a gain setting used in conjunction with the switched capacitor voltage collapse circuit shown in FIG. 8 in accordance with an embodiment of the present invention; FIG. FIG. 10 to FIG. 12 are diagrams showing the breakdown of the switched capacitor voltage shown in FIG. 8 in the charging phase mode and the discharging phase mode associated with each of the gain settings shown in FIG. 9 according to an embodiment of the present invention. FIG. 13 is a schematic diagram of a forward converter circuit that can be used in conjunction with the power circuit shown in FIG. 2 in accordance with an embodiment of the present invention; FIG. 14 is an embodiment of the present invention that can be combined with FIG. FIG. 15 is a schematic diagram of a power circuit shown in FIG. 2 including a power controller integrated circuit according to an embodiment of the present invention; FIG. 16, FIG. 17A and FIG. 17B is a block diagram of a power controller integrated circuit shown in FIG. 10 according to an embodiment of the present invention; FIG. 18 is a combination of the power shown in FIG. 16, FIG. 17A, and FIG. 17B according to an embodiment of the present invention. FIG. 19 is a block diagram of a power-on reset threshold voltage that can be used in conjunction with the power controller integrated circuit shown in FIG. 16, FIG. 17A, and FIG. 17B; 20 series according to the invention A schematic diagram of a proportional-integral-derivative regulator control circuit that can be used in conjunction with the power controller integrated circuit shown in FIGS. 16, 17A, and 17B; FIG. 21 and FIG. 22 are embodiments in accordance with the present invention. A block diagram of a digital control block that can be used in conjunction with the power controller integrated circuit shown in FIGS. 16 , 17A, and 17B; FIG. 23 illustrates an operation for providing power to an electronic device in accordance with an embodiment of the present invention. 2 is a flowchart of a method of power circuit shown in FIG. 2; FIG. 24 is a diagram of a state transition that can be used in conjunction with the method shown in FIG. 23 in accordance with an embodiment of the present invention; FIG. 25 is an embodiment in accordance with the present invention. A schematic diagram of a communication interface for use with the power controller integrated circuit shown in FIG. 16, FIG. 17A, and FIG. 17B; FIG. 26 is a combination of FIG. 16, FIG. 17A, and FIG. 17B according to an embodiment of the present invention. A schematic diagram of a microprocessor communication protocol used by the power controller integrated circuit; FIG. 27 is a combination of the power controller integrated circuit shown in FIG. 16, FIG. 17A and FIG. 17B according to an embodiment of the present invention. Schematic diagram of an internal integrated circuit; 28 and 29 are schematic diagrams of the power circuit shown in FIG. 2 according to an embodiment of the present invention; and FIG. 30 is a power control unit as shown in FIG. 16, FIG. 17A and FIG. 17B according to an embodiment of the present invention. FIG. 31 and FIG. 32 are additional schematic diagrams of the integrated circuit of the power controller shown in FIG. 16, FIG. 17A and FIG. 17B according to an embodiment of the present invention; FIG. 33 is in accordance with the present invention. A flowchart of an algorithm for low current detection and error detection that can be used in conjunction with the power controller integrated circuit shown in FIG. 16, FIG. 17A, and FIG. 17B; FIG. 34 and FIG. 35 are diagrams according to the present invention. 2 is a schematic diagram of a power circuit shown in FIG. 2; FIG. 36 is a schematic diagram of a level shifter that can be used in conjunction with the power circuit shown in FIG. 2 according to an embodiment of the present invention; A schematic diagram of an RCD circuit that can be used in conjunction with the forward converter circuit shown in FIG. 13; FIG. 38 and FIG. 39 are additional schematic diagrams of the power circuit shown in FIG. 2 in accordance with an embodiment of the present invention; Figure 40 is a diagram of the power shown in Figure 2 in accordance with an embodiment of the present invention. A schematic view of a portion of the road; and FIG. 41 schematic view showing another power circuit according to the embodiment shown in the embodiment of FIG. 2 in the present invention.

In the drawings, corresponding component symbols indicate corresponding parts.

With reference to the drawings and in operation, the present invention overcomes at least some of the disadvantages of known power transmission systems by providing a power module that includes a power circuit that is powered from AC mains (typically 120 VAC (US) ) to 240 VAC [EU / Asia]) provides DC voltage output power to consumer electronics. The power circuit is configured to provide power to charge the electronic storage device and/or the power consumer electronic product, including but not limited to a cell phone, smart phone, tablet, laptop, and/or any suitable electronic device, The present invention benefits from the extremely high efficiency and extremely low standby power requirements. In general, a power circuit includes a primary power circuit and a secondary power circuit for receiving high voltage AC power from a power source and transmitting the low voltage DC power signal to one or more electronic devices. The primary power circuit receives an AC power signal from the AC power source and generates an intermediate direct current (DC) power signal at a reduced voltage level. The secondary power circuit receives the intermediate DC power signal from the primary power circuit and generates and transmits an output DC power signal having a voltage level suitable for powering and/or charging the consumer electronic device.

The primary power circuit includes: a rectifier circuit for receiving an AC power signal and generating a rectified DC power signal; and a switched capacitor voltage collapse circuit for dividing the rectified DC voltage into a reduced voltage for use by the secondary power circuit . The switched capacitor voltage collapse circuit includes: a flyback capacitor that maximizes power efficiency; and a holding capacitor that minimizes voltage ripple. In one embodiment, the switched capacitor voltage collapse circuit is configured to transmit up to 50 mA and maintains from 50 mA to less than 1 mA under light load conditions. 95% efficiency. The primary power circuit can also include a switch mode buck regulator that is coupled in parallel with the switched capacitor voltage collapse circuit for handling large current loads, for example, up to 430 mA. The buck regulator can include a P-channel MOSFET switch, a high voltage step-down diode, and a buck energy storage inductor. In addition, the buck regulator also includes a pulse width modulator (PWM) controller for generating a pulse width modulated signal to control the on/off time of the buck regulator PMOSFET. It can also be expressed as an NMOSFET with a suitable gate driver.

The secondary power circuit includes a forward converter power circuit including a transformer for receiving an intermediate DC power signal from the primary power circuit and generating an output DC power signal. The forward converter also includes a MOSFET coupled to the primary side of the transformer and a control circuit that operates the MOSFET to regulate the voltage on the output of the forward converter when the load current is drawn from the secondary side of the transformer. For example, the forward converter control loop can be configured to regulate the output voltage under severe fluctuations in load current (4.5 nA to 4.5 A) without triggering any instability.

In the modern world, MOSFETs have become an increasingly important component of the "reality" interface. It enables motor/solenoid drive, transformer interface and a range of other functions. Another aspect of the problem is the microprocessor. It is characterized by a stable reduction in operating voltage and current. In many systems, these components are used together. The standard high voltage MOSEFT requires a driver that can transfer voltages on the order of 5v to 20v to the FET gate to successfully turn the FET on or off. In the case where the NMOSFET is turned on, it is actually required that the gate drive voltage exceeds the rail voltage. Dedicated drivers using charge pump technology have been designed for this purpose, but they are typically discrete components and increase the number of rails required on the circuit. The other major function of the FET driver has a reduced input voltage requirement that is compatible with the output capability of modern CMOS microprocessors. This configuration is expensive in terms of power and typically requires three power supplies. First of all, the mains electricity rail. It consists of a voltage supplied to the MOSFET in the range of 100 to 600 volts. The second power supply driver requires 5 volts to 20 volts and is ultimately the power required by the microprocessor. The present invention combines all of these tracks in a wafer such that power and components typically associated with the circuit are minimized and therefore more efficient.

In many cases, the power supply constitutes a large percentage of the number of components and cost in a small system. The joint component can substantially change this balance. This new part will consist of a combination of a high power MOSFET as the base and a suitable driver with the included charge pump. In addition, the power supply from the drive inside the mains rail power supply is added. The last added output pin is used to supply power to the microprocessor from this internal supply. In many common systems, a complete list of parts will consist of the new device, microprocessor and mains rail components. This will allow the next generation of low cost/low assembly count microprocessor subsystems.

The power module includes an advanced on-wafer power system (Tronium PSSoC), which is the subject of the present invention, and includes a controller-specific integrated circuit (ASIC) to provide a low cost, efficient means to place the AC present on a typical home or corporate electrical outlet. The line voltage conversion is replaced by a reduced regulated DC voltage for consumer electronics applications. Typical applications include, but are not limited to, charging systems for mobile phones, tablets or other handheld devices, USB power conversion, power to consumers, medical and industrial devices, and many other possible uses.

The Tronium PSSoC is configured for use in two major power module applications, including autonomous power modules and universal power modules. The autonomous power module operates in an autonomous mode of operation based on an analog feedback approach to reduce cost. The universal power module operates in a general mode of operation that utilizes a microprocessor (μP) controller to provide feedback for adjusting the final output voltage, which can be one of the rails that can be controlled/monitored or more operated. Some key features of the Tronium PSSoC include, but are not limited to, 90 VAC to 264 VAC line voltage operation (other AC or DC input voltages can be used), programmable output voltage, mixed switched capacitor voltage collapse circuit and switch for DC-DC conversion Mode buck regulator (for efficiency synchronous rectification), high accuracy PID regulation control loop, digital state machine for current and temperature monitoring, ultra low power dissipation for idle (vampire) mode of operation, Optically isolated microprocessor interface for configuration and control, I2C slave for manufacturing test, auto-detect input voltage range: 127 VDC to 373 VDC (global voltage 110 VAC to 260 VAC), featured output power: 22.5 W (any wattage feasible), mixed voltage converter for efficient operation, stacked switched capacitor crash module, PID regulation loop with PWM gate driver, high load level and high efficiency power ratio adjustment in weak standby mode Functionality, thermal sensing and shutdown, short circuit and overcurrent protection, adjustable no load/light load shutdown with restart and control logic, selectable analog or digital control, minimum or no external circuit component count and discrete device size and The best digital interface for two-way communication.

In addition, the switched mode buck regulator circuit can include circuitry commonly referred to as buck/boost circuitry; or can be replaced with SEPIC, Cúk, or push-pull or other topologies. These will have synchronous rectification for efficiency and a flyback or forward converter topology can be used.

The Tronium PSSoC is an advanced power controller integrated circuit that is configured to provide output voltage regulation with high efficiency and accuracy. The advanced features of the Tronium PSSoC provide users with a versatile device that can be used in a variety of applications in either "charger" mode or "constant power" mode. With the Tronium PSSoC, programmable output voltages (1.7V to 48V or higher) are possible, with small or inefficient losses across multiple current load conditions. This feature is called "toggle voltage (Dial). -a-Voltage)" feature. In addition, multiple output currents may be formed by a combination of hybrid or switched capacitor circuits themselves to form multiple voltage/current combinations typically ranging from 1.7V to 48V, which is sufficient to power most electronic devices. This "Dial-a-Voltage" feature can be factory programmed or can be programmed by the customer with appropriate code so that the same wafer can be used for 1.7V or 48V output, with only any external components (such as transformer windings and FETs that drive transformers). Nominal change.

The Tronium On-Chip Power System (PSSoC) ASIC is an advanced power control device that is highly efficient across a wide range of output power. While a typical 'efficient' power controller has ~50% efficiency down to 10% of full load, the Tronium device is designed to deliver >90% efficiency down to and below 1% of full load.

The Tronium PSSoC provides a revolutionary topology for high-voltage power conversion by implementing an intermediate voltage rail, allowing the system's power capability to be scaled with load requirements. It also shrinks the components to the ASIC, minimizing the required external components; and enabling a wider range of transformer options for improved power optimization with lower coil losses. The Tronium PSSoC also provides a PID switch controller (using the PID switch controller to drive the primary side of the transformer if isolation is required), or other conversion and regulation topologies. It also has secondary or primary side control/feedback.

In an embodiment, the Tronium PSSoC uses a dedicated high voltage intermediate voltage capacitor voltage collapse conversion scheme that can be used alone or in conjunction with a switch mode buck regulator to maintain high efficiency regardless of load voltage or current. When the load is not drawing current, the device will enter a low current mode of operation of approximately 1⁄2 milliwatts to minimize and virtually eliminate the traditional 'vampire' current required to maintain wake-up.

The Tronium PSSoC can include the following main circuit blocks: the intermediate capacitor voltage collapse converter module (CVBD module) (which can be used for one or more stages of the desired current output); a high voltage single or two stage switched capacitor voltage collapse circuit; Proximity-integral-derivative (PID) regulator control block for PWM control of the forward converter; switch mode buck regulator PID controller (optional hybrid topology for voltage output); buck regulator switch driver Current and temperature sensing block; 12-bit ADC for voltage and current monitoring; 10-bit DAC for feedback control; digital control block for current monitoring state machine; string for optical isolator communication interface Column input; for testing, I2C serial interface for evaluation, repair, and communication; an oscillator for generating internal clock signals; a power manager for voltage and current generation on the wafer; suitable for incorporating or not embedding an embedded chip or externally Controller use; primary side sensing or secondary side sensing capability; and synchronous forward converter.

The power module can also include the Tronium PSSoC, which includes analog and digital controls to optimize performance and efficiency. In order to not only enable analog control, but also enable digital control, appropriate inputs and outputs must be available on the Tronium PSSoC. Given such availability and in conjunction with power loop control from internal clock control, the clock control can be driven and controlled with an external signal. The novel approach is that the signals can be driven from the secondary side while the Tronium PSSoC is located on the primary side of the transformer.

Digital control is usually done on the same side of the isolation barrier. However, assuming the Tronium PSSoC is inherently isolated and requires end-to-end efficiency optimization, control from the primary side or secondary side back to the primary side can be utilized. This can be done in a number of different ways given a Tronium implementation. This can be accomplished in conjunction with an optocoupler that transmits a digital control signal from a microcontroller and an analog signal from a current sensing circuit. Furthermore, this can be done by using a third winding on the isolation transformer.

Some or all of the circuits and/or electrical devices included in the power circuit may use a process, gallium nitride (GaN) or gallium arsenide (GaA) or other available processes by using deep trench capacitors or providing efficient components ( The premise is that it requires high efficiency) to be integrated onto the wafer. Thus, one or all of these components (even transformers) can be embedded into the ASIC using known germanium (or GaN-GaA) transformer technology rather than as external discrete components. In addition, the use of MIM and MOM capacitors for the purpose of reducing chopping (which in turn reduces the size of the required capacitor), together with low RDS _ON MOSFETs, integrated decoupling capacitors and/or flying capacitors (C _FLY ), can be used This article is used in the case of capacitors or FETs. In addition, the introduction of integrated inductors on the wafer helps achieve maximum efficiency. Alternatively, the most efficient components, such as GaA, GaN or Schottky diode components, will be used.

In addition, the capacitor can be a nanocapacitor and can be based on ferroelectric and core-shell materials as well as on nanowires, nanopillars, nanotubes, and nanoporous materials.

The substrate of the Tronium PSSoC can be made from conventional films currently used in capacitors (such as external) or semiconductor substrates, such as high or low ohmic germanium substrates, polysilicon, gallium nitride, gallium arsenide, germanium or germanium or phosphorous. Indium material.

The key to the process is to integrate as many discrete components as possible on the ASIC board and to identify low RDSon values, high efficiency components, and sufficient voltage collapse components if efficiency is critical. Another key is to operate the switching buck module at a higher frequency, making the components smaller and smaller enough to become on-wafer devices.

Embodiments of the invention selected will now be explained with reference to the drawings. It will be apparent to those skilled in the art that the following description of the embodiments of the present invention is intended to be illustrative only and not to limit the scope of the invention as defined by the appended claims.

1 is a schematic diagram of an electronic charging device 10 for providing power to an electronic device. 2 is a block diagram of a power module 12 that can be used in conjunction with the electronic charging device 10. In the illustrated embodiment, the electronic charging device 10 includes: a housing 14; a pair of power pins 16 that extend outwardly from the housing 14; and a device connection assembly 18 that is adapted to connect to the electronic device 20 The power is transmitted from the charging device 10 to the electronic device. The electronic charging device 10 also includes a power module 12 that includes a power circuit 22 that is configured to receive power from a power source 24 and to transmit power to the electronic device 20, such as, for example, a portable consumer electronic Device, including It is not limited to mobile phones, smart phones, tablets, laptops, and/or any suitable electronic device. In addition, power circuit 22 can transmit power for charging an electronic storage device, such as, for example, a mobile phone/laptop/tablet power storage battery. In an embodiment, power circuit 22 can be configured to provide low voltage DC output (typically 5 VDC) from AC mains supply (typically 120 VAC (US) to 264 VAC [EU/Asia]).

In the illustrated embodiment, power circuit 22 includes primary power circuit 26 and secondary power circuit 28. Primary power circuit 26 is adapted to be electrically coupled to power source 24 and configured to receive an AC (or DC) input power signal from power source 24 and to generate an intermediate direct current (DC) power signal. The intermediate DC power signal is generated at a first voltage level that is less than a voltage level of the AC input power signal. Secondary power circuit 28 is electrically coupled to primary power circuit 26 and is configured to receive an intermediate DC power signal from primary power circuit 26 and to transmit the output DC power signal to electronic device 20. The output DC power signal is transmitted at an output voltage level that is less than a first voltage level of the intermediate DC power signal. For example, in one embodiment, primary power circuit 26 is configured to receive a voltage level having a range between 127 volts to 375 volts AC and to transmit an intermediate DC power signal at a voltage level of approximately 110 volts DC. . Secondary power circuit 28 is configured to receive an intermediate DC power signal and transmit an output DC power signal at approximately 5 volts DC.

In the illustrated AC to DC embodiment, the primary power circuit includes a rectifier circuit 30, an intermediate voltage converter 32, a buck regulator 34, and a holding capacitor 36 that is electrically coupled to the intermediate voltage converter 32 and down. Pressure regulator 34. Intermediate voltage converter 32 and buck regulator 34 are coupled in parallel between rectifier circuit 30 and secondary power circuit 28. The rectifier circuit 30 is configured to receive an AC power input signal from the power source 24 and generate a rectified DC power signal that is transmitted to the intermediate voltage converter 32 and the buck regulator 34. In an embodiment, A rectified, rectified DC power signal having a voltage level that is approximately equal to a voltage level of the AC input power signal. As shown in FIG. 13 and FIG. 15, in the illustrated embodiment, the rectifier circuit 30 includes a plurality of diodes 38, which are arranged in a full-wave bridge rectifier, the full-wave bridge rectifier having a first An input terminal and a second input terminal, coupled to the high voltage side and the low voltage side of the power source 24, are used to generate a DC power signal from the AC input power signal. In an embodiment, rectifier circuit 30 may also include a filter capacitor 40 coupled to a full wave bridge rectifier. In yet another embodiment, the rectifier circuit 30 does not include the filter capacitor 40. In another embodiment, rectifier circuit 30 can include a half bridge rectifier (not shown).

3 is a schematic diagram of a buck regulator circuit 34 that can be used in conjunction with power circuit 22. In the illustrated embodiment, buck regulator circuit 34 includes a regulator switch assembly 42 coupled to buck circuit 44. The buck circuit 44 includes a high voltage buck diode 46, a buck energy storage inductor 48, and a capacitor 50. The regulator switch assembly 42 is operative to selectively transmit the rectified DC power signal to the buck circuit 44. In the illustrated embodiment, the regulator switch assembly 42 includes: a P-channel MOSFET 52; a driver circuit 54 coupled to the P-channel MOSFET 52; and a level shifter 56 coupled to the driver circuit 54. In an embodiment, the regulator switch assembly 42 can include an N-channel MOSFET and/or a P-channel MOSFET. In the illustrated embodiment, buck regulator 34 also includes a regulator control circuit 58 that includes a regulator PWM controller 60 (also shown in Figures 16, 17A and 17B) that controls the PWM The processor 60 is operative to generate a pulse width modulated signal to control the P-channel MOSFET 52. In an embodiment, control circuit 58 may also include a voltage sensing circuit 62 coupled to the primary side of the forward converter transformer for sensing the voltage level of the intermediate DC power signal transmitted to secondary power circuit 28. . The regulator PWM controller 60 can generate a pulse width modulation control signal according to the sensed first voltage level to adjust the transmission to The duty cycle of the PWM control signal of the P-channel MOSFET 52 maintains the voltage level of the intermediate DC power signal. The buck regulator servo loop 58 is voltage controlled and Vprimary is sensed and used to modulate the duty cycle of the driver 54.

In one embodiment, the sensing circuit 62 includes one or more Hall effect sensors that are coupled to the primary side of the forward converter transformer for sensing the magnetic field generated within the transformer. The Hall effect sensor facilitates determining the zero crossing of the transformer by directly sensing the magnetic field generated by the transformer during operation. In an embodiment, the sensing circuit 62 includes a primary side Hall effect sensor coupled to the primary side of the transformer. The primary side Hall effect sensor is coupled to PWM controller 60 for transmitting a signal to PWM controller 60 for determining when the transformer is near "zero crossing." In another embodiment, the sensing circuit 62 includes a secondary side Hall effect sensor coupled to the secondary side of the transformer and to the forward converter controller (Fig. Shown in 13) is used to transmit a signal indicative of the transformer's magnetic field for determining when the transformer has reached the "zero crossing point".

4 through 8 are schematic views of the intermediate voltage converter 32. FIG. 9 is a table showing the gain settings that can be used in conjunction with the intermediate voltage converter 32. 10 through 12 are schematic diagrams of intermediate voltage converters 32 in charge phase mode 66 and discharge phase mode 68 for each of the gain settings shown in FIG. In the illustrated embodiment, intermediate voltage converter 32 includes a single stage switched capacitor voltage collapse circuit coupled to holding capacitor 36 and secondary power circuit 28. The switched capacitor voltage collapse circuit includes a plurality of switch assemblies 70 that are coupled in parallel to each of the flyback capacitor 70 and each of the flyback capacitors 70. Switch assembly 72 selectively operates between charging phase mode 66 and discharging phase mode 68. During the charging phase mode 66, the switch assembly 72 is operated to form the charging circuit 74 to be reciprocated Capacitor 70 is coupled to rectifier circuit 30 to transmit the rectified DC power signal to each of flyback capacitors 70. During the discharge phase mode 68, the switch assembly 72 is operated to form a discharge circuit 76 to connect the flyback capacitor 70 to the secondary power circuit 28 to transmit the intermediate DC power signal to the hold capacitor 36.

In one embodiment, as shown in FIG. 8, the single-stage switched capacitor voltage collapse circuit 32 can include a first flyback capacitor Cfb1 and a second flyback capacitor Cfb2 and nine switch assemblies S1, S2. S3, S4, S5, S6, S7, S8 and S9. In addition, the two switch assemblies S3 and S9 are grounded. During operation, the gain setting of the switched capacitor voltage collapse circuit can be adjusted by selectively operating the switch assembly in accordance with the gain setting table shown in FIG. For example, during charging phase mode 66 (stage 1), switches S1, S4, S7, and S8 are turned on and moved to the closed position and switch assemblies S2, S3, S5, S6, and S9 are closed and moved to the open position to form The charging circuit 74 connects the flyback capacitors Cfb1 and Cfb2 to the rectifier circuit 30. As shown in FIGS. 10 to 12, in the charging circuit 74, the top plates of the flyback capacitors Cfb1 and Cfb2 are connected to the rectifier circuit 30 line voltage Vline. For a gain setting equal to G=1x, during discharge phase mode 68 (stage 2), switch assemblies S2, S3, and S7 are turned on and switch assemblies S1, S4, S5, S6, S8, and S9 are turned off to form a map. The discharge circuit 76 shown in FIG. 10 includes a top plate of a capacitor Cfb1 connected to the holding capacitor 36 and a top plate of a capacitor Cfb2 connected to the bottom plate of the capacitor Cfb1. Referring to Figures 9 and 11, for a gain setting equal to G = 1/2x, during discharge phase mode 68 (stage 2), switch assemblies S2, S5, and S9 are turned on and switch assemblies S1, S3, S4, S6 S7 and S8 are turned off to form a discharge circuit 76 including a top plate of the capacitor Cfb1 connected to the holding capacitor 36, a bottom plate of the grounded capacitor Cfb1, and a top plate of the capacitor Cfb2 connected to the holding capacitor 36 and a capacitor Cfb2 connected to the ground. The bottom plate. reference 9 and 12, for example, in the case where the gain setting is equal to G=2/3x, during the discharge phase mode 68 (phase 2), the switch assemblies S2, S6, and S9 are turned on and the switch assemblies S1, S3, S4, S5, S7 and S8 are turned off to form a discharge circuit 76 comprising a top plate of the capacitor Cfb1 connected to the holding capacitor 36, a top plate of the capacitor Cfb2 connected to the bottom plate of the capacitor Cfb1, and a bottom plate of the grounded capacitor Cfb2.

In one embodiment, as described herein, multiple "stages" of switched capacitor circuits are linked together that can be used to provide additional current output gain with or without the need to add hybrid power conversion/regulation circuitry.

Referring to FIG. 7, in the illustrated embodiment, switched capacitor voltage collapse circuit 32 also includes control circuitry 78 coupled to each of switch assemblies 72 to operate switched capacitor voltage collapse circuit 32. The control circuit 78 includes a voltage sensing circuit 80 for sensing the voltage level of the rectified DC power signal received from the rectifier circuit 30, and a gain controller 82 configured to sense The voltage level selects the gain setting of the switched capacitor voltage collapse circuit 32 and operates each of the plurality of switch assemblies in accordance with the selected gain setting. By providing a control circuit 78 that selects the gain setting of the switched capacitor voltage collapse circuit 32 based on the sensed input voltage level, the switched capacitor voltage collapse circuit 32 can adjust the operation of the switched capacitor voltage collapse circuit 32 to account for different countries and/or grids. The AC voltage level changes and the intermediate DC output signal is transmitted at a predefined voltage level and maintains optimum power efficiency. In the illustrated embodiment, control circuit 78 includes a resistor divider 84, a pair of comparators 86, a logic decoder 88, and a gain controller 82. The negative input of comparator 86 is coupled to the bandgap generator and the positive input is coupled to rectifier circuit 30 line voltage Vline.

Referring to Figures 4-6, in the illustrated embodiment, one or more switch assemblies An N-channel MOSFET switch 90 and a level shifter 92 are included that are coupled to the N-channel MOSFET switch 90 for transmitting control signals to the N-channel MOSFET switch 90 to facilitate operation of the N-channel MOSFET 90. In addition, one or more of the switch assemblies 72 includes a Dixon charge pump 94 that is coupled to a level shifter 92 to provide a high voltage signal required to close the N-channel gate during operation. The Dixon charge pump 94 is configured to generate an output power signal having a voltage level greater than the source voltage of the switch assembly to enable the level shifter 92 to operate the N-channel MOSFET switch 90. In one embodiment, each of the switch assemblies 72 includes an N-channel MOSFET 90, a level shifter 92 coupled to the N-channel MOSFET 90, and a Dixon charge pump 94 coupled to the level shifter 92. In another embodiment, two or more level shifters 92 can be coupled to a single Dickson charge pump 94. Whenever the term NMOS is used in this specification, it can be replaced with a PMOS and vice versa.

In the illustrated embodiment, at least one switch assembly 72 includes a level shifter 92 coupled to an N-channel MOSFET switch 90. In addition, a Dixon charge pump 94 is coupled to the level shifter 92 to provide a power signal sufficient to close the gate of the N-channel MOSFET switch 90. In the illustrated embodiment, a Dixon charge pump 94 is coupled to the source voltage Vsource of the N-channel MOSFET and configured to transmit an output signal to a level shifter 92 that is using an NMOS In this case, there is a voltage level greater than the voltage level of the source voltage. In one embodiment, the Dixon charge pump 94 is configured to transmit an output power signal V _DCP having a voltage level that is approximately 15 to 20 volts greater than the source voltage Vsource to ensure proper gate operation. Gain controller 82 is coupled to level shifter 92 for providing a low voltage control signal to level shifter 92. The level shifter 92 is coupled to the source voltage Vsource and the Dickson charge pump 94 and is configured to transmit a control signal to the N-channel MOSFET 90 having a voltage level sufficient to operate the switch assembly 72 in accordance with the received control signal. quasi.

FIG. 13 is a schematic diagram of a secondary power circuit 28 including a forward converter circuit 96. In the illustrated embodiment, forward converter circuit 96 includes a primary buck circuit 98 and a secondary buck circuit 100. The primary buck circuit 98 is configured to receive an intermediate DC power signal from the primary power circuit 26 and to transmit a secondary DC power signal to the secondary buck circuit 100. The secondary DC power signal has a voltage level that is less than the voltage level of the intermediate DC power signal. Secondary buck circuit 100 is configured to receive a secondary DC power signal and generate an output DC power signal that is transmitted to electronic device 20.

In the illustrated embodiment, primary buck circuit 98 includes a transformer 102. The primary side of transformer 102 is connected to primary power circuit 26 and the secondary side of transformer 102 is connected to secondary buck circuit 100. In an embodiment, the primary buck circuit 98 can include a switch assembly 104 that includes an FET coupled to a primary side of the transformer, and a control circuit 103 coupled to the switch assembly 104 for selective operation Switch assembly 104 to adjust the voltage level of the secondary DC power signal. The transformer control circuit 103 can include a primary side voltage sensing circuit 105 for sensing the voltage and current levels of the DC output signal and operating the transformer switch assembly 104 to maintain the voltage level of the DC output signal at a predefined output voltage level. And the required current level. In this manner, at least five components are removed from the balance, which is typically required to use a secondary side sensing controller, including optocouplers, operational amplifiers, inductors, diodes, and capacitors. The secondary step-down circuit 100 includes a pair of diodes, an inductor, and a capacitor. The forward converter 96 can also include a resistor, capacitor, diode (RCD) circuit 150 (shown in Figure 37). The RCD circuit 150 is configured to perform a transformer reset when the primary side switch 104 is off to avoid saturating the transformer 102. The forward converter 96 is based on a pulse step down converter. The duty cycle modulated pulse is applied to the primary side Off 104 to convert the input DC voltage to an AC voltage. The transformer winding ratio provides a step down. In this case, the step is from 11:1. The secondary side has an ac voltage on its terminal. This AC voltage is rectified by the secondary buck circuit 100 diode and filtered through the LC filter to produce a step-down DC voltage on the output. The duty cycle is modulated by analog or digital servo loops. This servo loop checks the dc voltage on the output side and compares it to the response to generate an error signal. This error signal is used to drive a comparator that converts this error in a pulse width modulated DC pulse. This DC pulse corrects errors on the output when applied to the primary side switch gate 104 and maintains regulation for various load levels.

In an embodiment, the transformer control circuit 103 can include a primary side current sensing circuit 107 coupled to the primary side of the transformer 102 to sense load current and load voltage to facilitate regulation of the DC output signal. Within 5% of the predefined load voltage. Control circuit 103 uses current sense resistor 109 and measures across the primary winding. In the illustrated embodiment, transformer control circuit 103 includes a comparator 111 that drives FET 104. In an embodiment, resistor 109 is a 0.10 ohm resistor. Control circuit 103 is configured to sense the load current pulse by pulse and sense the peak current. For example, in one embodiment, control circuit 103 senses the voltage across resistor 109 and senses the current in a voltage format when switch 104 is turned on. When switch 104 is off, control circuit 103 senses the differential voltage across the primary side of transformer 102, which may be approximately equal to Vprimary minus the drain of shutdown transistor 104. When the transistor 104 is turned off, there is a drain voltage across it, and therefore a sawtooth signal. Both voltage and current are sampled using a switched capacitor sample and hold circuit that scales down to a low voltage and includes a resistor divider to set the differential voltage portion of the primary winding and bring the voltage to sample and hold Circuit. The differential voltage is equal to ΔV across the winding and contains the bottom of Vprimary and Vprimary. The sample and hold circuit and the resistor divider reduce the primary voltage to less than 5 volts and then obtain the difference between ΔV. The sample and hold circuit drives the comparator 111. The other input of comparator 111 senses and maintains the peak current voltage across the 0.1 ohm resistor 109. The input to comparator 111 is scaled and the gain is amplified and offset such that the input is in a steady state and comparator 111 drives the set-reset flow clock. FET 104 includes an "AND" gate that is driven by comparator 111. The clock off comparator 111 adjusts the duty cycle of the AND gate. The AND gate also has a high duty cycle driven by a high pulse width clock as a sawtooth signal. The other input of the AND gate is the output of comparator 111 such that subsequent comparator 111 modulates the duty cycle to a small duty cycle or a large duty cycle. In one embodiment, the clock system is for a 100 KHz clock of the forward converter servo loop.

There is no need for a three-stage winding from the transformer to supply power to the sensor. Power is available from the primary side because the sensing circuit is on the primary side and does not require power from the secondary side. The voltage across the primary side inductor and the current into the primary side FET 104 are used to determine the output voltage of the system. In one embodiment, FET 104 includes a 200 volt Philips component device with a 2 volt threshold that can drive FET 104 with a 5v signal to turn FET 104 on without a level shift. In another embodiment, a 10 volt LDO or a 20 volt LDO can be used in conjunction with a level shifter to change FET 104 from 5 volts to 10 volts or from 5 volts to 20 volts.

In the illustrated embodiment, the control circuit 103 uses a sense resistor 109 that is implemented in a gated manner in the drain path of the MOSFET 104, wherein the sample and hold circuit is just at the switch 104 in the PWM The peak voltage is obtained when the waves in the loop are turned on. The gate control configuration samples when the switch is turned on because no information is available at this time when the switch is turned off.

In the illustrated embodiment, power circuit 22 is configured to accommodate different transformers having different turns ratios to produce DC output signals having various current and/or voltage requirements.

In an embodiment, power circuit 22 may not include full-wave bridge 38, rectifier circuit 30, and input capacitor 40 such that V _LINE is DC and thus the circuit can receive direct current (DC) if needed, and then The voltage collapse is performed using the regulated buck circuit 34 and the switch cover VB 32 is still used as described further herein. However, in some use cases, especially in the event of a low DC to DC voltage collapse, the buck regulator 34 would not be needed and only the switch cover VB 32 could be used, whether or not only one stage could be used (as in Figures 2-12). Shown). In this case, the control signal 105 from the output can be eliminated and only the current sense resistor 109 is relied upon and the voltage that is strictly regulated is still maintained.

In another embodiment, for DC input variations of the circuit, the use may not require a transformer (if a transformer is not needed for voltage/current conversion or if isolation is not required), as in the case of internal components, as seen in smart phones. In this example, the transformer is unnecessary and can be removed from the circuit along with the FET that drives the transformer. In this case, the entire forward converter controller circuit 96, 28 can be removed and the C _hold capacitor 36 will be replaced with the sense resistor circuit segment 109. In addition, if the AC circuit does not need to be rectified or isolated, this circuit can operate in conjunction with AC and DC.

15 is a schematic diagram of a power module 12 that includes a power controller integrated circuit (Tronium PSSoC) 106 that can be used in conjunction with power circuit 22. 16, Figure 17A and Figure 17B are block diagrams of a Tronium PSSoC 106. In the illustrated embodiment, power module 12 includes a printed circuit board 108 and a Tronium PSSoC 106 formed within the package wafer and coupled to printed circuit board 108. At least a portion of circuit 22 is included within Tronium PSSoC 106. In addition, digital control can be performed by a microprocessor or state machine external to the wafer or embedded on the wafer. In one embodiment, some or all of the circuitry and electrical components included in circuitry 22 are included within the Tronium PSSoC 106. The Tronium PSSoC 106 can be configured for use in two major power module applications, including autonomous power modules (shown in Figures 16 and 28) and universal power modules (Figure 17A, 17B and 29). For example, as shown in FIG. 16, the autonomous power module includes a Tronium PSSoC 106 that is configured to operate in an autonomous mode of operation based on analog feedback in order to reduce cost. The universal power module (shown in Figures 17A and 17B) includes a Tronium PSSoC 106 that operates in a general mode of operation and utilizes a microprocessor (μP) controller to provide feedback for adjusting the final output voltage.

In the illustrated embodiment, the Tronium PSSoC 106 is configured to meet predefined requirements for traceability, marking, solderability, and/or solvent resistance. The Tronium PSSoC 106 is marked to indicate the date code, factory identifier, and traceability/authentication code. The authentication code provides a means of identifying and verifying genuine parts for "piracy." All production package components on a roll contain the same unique date code, factory identifier, and traceability/authentication code. Batch isolation may exist to prevent confusion of date codes within components of the same batch. Package parts should be marked to indicate part number, date code, and traceability code. The terminal is configured to meet the solderability requirements of IPC-J-STD-001 and IPC-J-STD-002 for packaged Tronium PSSoC. The packaged Tronium PSSoC and its tags are configured to meet the requirements of MIL-STD-202 Test Method 215.

The Tronium PSSoC106 is an advanced power controller integrated circuit designed to provide output voltage regulation with high efficiency and accuracy. The Tronium PSSoC 106 provides users with a versatile device that can be used in a variety of applications and due to the "Dial-a-Voltage" feature, the same wafer can be configured to actually operate in any electronic device. Similarly, the programmable output voltage is feasible with the Tronium PSSoC, with little or no loss of efficiency across multiple current load conditions.

In the illustrated embodiment, the Tronium PSSoC 106 uses a switched capacitor circuit 32 and a switched mode buck regulator 34 to maintain high efficiency regardless of load voltage or current. example For example, when the load electronics 20 is not drawing current, the Tronium PSSoC 106 enters a low current mode of operation to minimize the traditional 'vampire' current required to maintain wake up. In the illustrated embodiment, the Tronium PSSoC 106 includes a single stage switched capacitor circuit 32, a PID regulator control block 110 (shown in Figure 20) for PWM control of the forward converter secondary transformer 102, and a switch mode. Buck regulator controller 112, buck regulator switch driver 114, current and temperature sensing block 116, 12-bit analog to digital converter (ADC) 118 for voltage and current monitoring, 10 for feedback control Bit digit to analog converter (DAC) 120 (shown in Figures 17A and 17B), digital control block 122 for current monitoring state machine, serial input for optoisolator communication interface, I2C serial interface And a power management unit 124 for voltage and current generation on the wafer. Other types of sensors, such as sound, light detection, radiation, and impact sensors, may also be added depending on usage.

18 is a block diagram of a power management unit 124. In the illustrated embodiment, power management unit (PMU) circuit block 124 generates and monitors the bias voltage and current required for proper operation of the Tronium PSSoC. Two linear voltage regulators provide regulated 5.0V supply for the low voltage circuitry of the IC as well as external support devices such as opto-isolators and optional external microprocessors. In addition to providing proper initialization of the IC when connected to the line voltage, the PMU 124 monitors the voltage supply for the fault condition and provides a primary power-on reset (POR) 126. In the illustrated embodiment, PMU 124 includes a bandgap voltage reference, a current reference generator, a line side low power linear voltage regulator, a transformer primary side linear voltage regulator, and a power on reset. To reduce power dissipation, the line side circuit supplies power from the LINE_0P1 pin, which supplies approximately one tenth of the LINE_IN voltage (Vline). This voltage is internally generated using an external resistor divider connected to the LINE_IN and LINE_RDIV pins of the IC. Initialization of the PMU 124 begins by applying a rectified voltage on the LINE_IN pin.

PMU 124 contains low power bandgap reference for Tronium PSSoC 106 The voltage and current generator, the Tronium PSSoC 106 is powered by the line voltage. The high precision temperature compensated output voltage is provided along with multiple bandgap to absolute temperature (PTAT) current outputs for use as a reference for subsequent circuit blocks. The bandgap output voltage can be fine-tuned on the wafer probe to optimize the temperature coefficient with the bg_trim[7:0] register bit and stored in a one-time programmable (OTP) memory that is stored In the microprocessor. The bandgap unit is self-starting and only requires a preset trim value for initialization. The bandgap unit is deactivated during sleep mode, but is always on and is designed for ultra low power operation.

The PMU 124 also includes a low power linear voltage regulator (LPREG) that is provided to convert the high voltage present on the LINE_IN input of the PSSoC to a regulated voltage in the low power voltage domain. The LPREG uses a bandgap reference voltage to produce a regulated output of 5.0V to drive a low power on-wafer circuit block that is always on, including a low frequency oscillator for the switched capacitor circuit 32, on-wafer logic, and the like. An external (off-chip) bypass capacitor can be used for noise filtering and is connected to the LPREG pin. The regulator is not deactivated during sleep mode and is always on.

The PMU 124 can also include a primary side low voltage regulator that is provided to supply higher current requirements for off-chip optical isolators, PWM gate drivers, and other support circuits. An external 10μF bypass capacitor is required for noise filtering, which is connected to the VREG5 pin. The voltage regulator can be deactivated for testing purposes in conjunction with the en_Vv signal. When the en_Xv input to the cell is 'low', all internal analog currents in the cell are deactivated and the output is high impedance.

The POR 126 block monitors the internal supply voltage of the Tronium PSSoC as produced by the LPREG circuit block. For example, FIG. 19 illustrates the POR threshold voltage that can be used in conjunction with POR 126. In one embodiment, for a voltage on the LPREG pin that is less than the V _POR threshold voltage, the POR output will be asserted as 'high', indicating a reset condition. In addition, for voltages on the LPREG pin that are greater than the V _POR threshold voltage, the POR output will be deasserted as 'low' for normal operation. Hysteresis is provided such that once the V _POR threshold is exceeded, a decrease in threshold voltage occurs. The threshold derived from hysteresis is then equal to V _POR -V _HYS . An inverted version of the POR signal is also available on POR_B.

In the illustrated embodiment, the switched capacitor voltage collapse circuit (SCVBC) 32 included in the Tronium PSSoC 106 is configured as a voltage divider via Capacitor Voltage Crash Technology (CVBD). Through the capacitor, it divides the rectified DC voltage present on the LINE_IN pin into a reduced voltage on the CP2_OUT pin for use by the external transformer 102 and the secondary voltage control loop. The external transformer 102 then further reduces this voltage to the desired voltage depending on the primary to secondary winding ratio. In an embodiment, SCVBC 32 is configured as a cascade of two identical levels, as shown in Figure 17A. In another embodiment, SCVB 32 includes a plurality of switched capacitor stages, as shown in Figures 38-39. The SCVBC 32 is configured to transmit up to 50 mA of each capacitor collapse block, which consists of a switched capacitor block that provides half or other subdivided voltage collapse. This is provided and maintained across the range of load currents from 50 mA to less than 1 mA under light load conditions on the primary side of transformer 102. 95% efficiency. For example, suppose for external transformers and rectifiers 97% efficiency and The overall module efficiency of 92 to 97% has been simulated and achievable. In an embodiment, SCVBC 32 may include on-wafer flyback capacitors to maximize power efficiency, an external 2.2 μF barrel capacitor and two external 7.5 μF holding capacitors to minimize voltage ripple. These capacitors are connected to the CP1_OUT and CP2_OUT pins, respectively, for the output of the first and second stages of the switched capacitor circuit. The two phases are clocked from a two phase non-overlapping clock generator at a rate of 1 KHz, which is derived from the on-wafer RC oscillator.

Referring to Figures 17A and 17B, in one embodiment, for a Tronium PSSoC 106, the SCVBC 32 output voltage on CP2_OUT can be combined with an 8-bit binary weighted digit to analog converter in the range of 0.117 volts in the range of 120 to 90 volts. The SCVBC output is limited to this range to ensure that the forward converter transformer 102 provides the most output current during the step down. SCVBC is limited to an output current of 50mA. If the application requires additional current, the switch mode buck regulator 34 can be enabled to provide current up to 430 mA. Each stage of SCVBC 32 can be programmed to produce a voltage conversion ratio. This stylization is done automatically in the process gain control, where the rectified LINE_IN voltage is compared to the 8-bit DAC setting. The digital control of this DAC allows multiple voltages to be programmed to achieve the desired final output voltage required for the target application. An example of a load voltage can be programmed in conjunction with a DAC based on the transformer turns ratio.

Referring to Figure 16, in an embodiment, SCVBC 32 may comprise a single stage switched capacitor circuit having a respective voltage division ratio of 1, 0.66 or 0.5. The output voltage present is then reduced by an external (off-chip) forward converter 96 to achieve a final applied output voltage of 5.0V. All analog and digital signals of SCVBC (and buck controller) are generated in the 5V domain. The SCVBC error voltage is scaled using a resistor divider to be in the XV domain. The LINE_IN voltage is also scaled so that processing can be done in the XV voltage domain.

In one embodiment shown in FIG. 16, SCVBC 32 includes a gain control block that uses a scaled LINE_IN voltage to determine the appropriate voltage division ratio of SCVBC 32. The scaled LINE_IN voltage is compared to the bandgap reference voltage to select one of three or more possible voltage division ratios depending on the AC mains voltage. The final adjustment of the output voltage can be performed in a switched capacitor regulator where the clock is turned on and off to control the amount of charge transferred to the holding capacitor.

Referring to Figures 17A and 17B, in one embodiment, the SCVBC gain control block The LINE_IN voltage and output voltage DAC settings can be scaled to determine the appropriate process divider ratio from the combined partial pressure steps in CP1 and CP2. In this way, a setting of 120 and 90 volt outputs depending on the global AC input voltage can be achieved. The final adjustment of the CP2 output voltage is performed in a switched capacitor regulator where the clock is turned on and off to control the amount of charge delivered to the CP1 and CP2 holding capacitors. The minimum voltage division ratio required for CP1 and CP2 can be programmed for CP1 to minimize the voltage drop across the high voltage NMOS switch.

The CP2 output is fed to the primary winding of the forward regulator. The final output voltage of the system is set by the following equation: (V _SET /XFMR _RATIO )*dc=V _OUT

When the dc is a forward regulator, the duty cycle should be maintained at 0.5 or less to ensure that the system transformer is not saturated.

The SCVBC 32 includes a Dixon Charge Pump (DCP) 94 (shown in Figures 5 and 6) that can be used to provide boost voltage to the gate of the NMOS high voltage switch. The DCP can be clocked at a clock rate of 1.6 MHz and produces a gate voltage equal to the voltage on the LINE_IN pin plus a voltage of approximately 18V. Additionally, each NMOS high voltage switch 90 can include a corresponding level shifter to translate the drive signal from the low voltage domain to the boost voltage provided by the DCP. In an embodiment, this requires a dual level shifter, and other requirements may require only one level shifter. The input to the level shifter is 5V and translates to the 20V domain for use by the SCVBC 32. This same type of level shifter scaled for output current drive can be used within the Tronium PSSoC 106.

In one embodiment, as shown in Figures 17A and 17B, the Tronium PSSoC 106 can include a digital to analog converter (DAC) that provides switching power to the analog converter (DAC). The programmability of the output voltage of the container circuit. The R2R current mode DAC topology digitally scales the bandgap reference voltage to the control voltage required by the switched capacitor circuit to maintain the user programmed output voltage. The output voltage range of the DAC is from 120V to 90V programmed by the CP_DAC[7:0] register bit in steps of 118mV.

The SCVBC 32 can also include a switched capacitor regulator that includes a comparator and an AND gate for controlling the charging of the SCVBC. In an embodiment, the comparator input can include an output voltage DAC and a scaled version of the CP2 output voltage. For example, if the scaled voltage from the CP2 output is greater than the DAC voltage, the comparator output is low and the pulse gating is off at 1 kHz CP. If the DAC voltage is greater than the proportionally adjusted CP2 output voltage, the comparator output is asserted high and the AND gate enables the clock to charge the output. In addition, the comparator can be designed with hysteresis to minimize CP2 output voltage ripple. In addition, the regulator can operate two CP stages in a discontinuous mode; that is, the clock pulse is only present when a 7.5 μF holding capacitor needs to be charged.

In the illustrated embodiment, if a stack of CVBD modules is not used, it is easy to handle high current loads (up to 430 mA or greater) in conjunction with the use of a hybrid topology that includes a switch mode buck regulator (SWR) ) 34 and CVBD modules. The Tronium PSSoC 106 contains a SWR 34 controller that utilizes an external (off-chip) PMOS switch (which can be used inside the PMOS or NMOS of the die [in combination with an additional Dickson charge pump for the gate]) to supply the high current of the load. demand. Since the high current path is outside the PSSoC, no PSSoC is needed to dissipate most of the load current. This is accomplished by eliminating sources of additional parasitic losses in the PSSoC due to the on-resistance of the high voltage device. The SWR can be adjusted at the same frequency as the CVBD module or at a higher frequency (500KHz to 1MHz) or very high frequency, while the CVBD module operates at a lower frequency to remain more efficient. (CVBD The module can operate at a higher frequency, but in the case of current devices provided in semiconductor platforms today, this increases gate opening/closing, which increases losses).

In an embodiment, the buck regulator 34 can include the following external (off-chip) components: 1. Series high voltage PMOS switches. PMOS can be selected for low RDS _ON , low input capacitance and V _DS >400V; 2. High voltage step-down diode with high voltage collapse, very low leakage and switching current; and 3. Buck energy storage inductor. The inductor must have a low ESR and be able to handle the appropriate degraded current. However, such components, typically depending on the frequency at which the buck is run (the higher the frequency, the smaller the value of the required component) can be internal devices/components on the wafer, rather than external. In the case of GaN and/or GaA and deep trench capacitor technology, and the technique of placing a transformer on a wafer, all components may be present on one wafer.

The Tronium PSSoC 106 can also include a high frequency oscillator that is divided to produce a 100 KHz (nominal) clock for use by the buck regulator PWM controller. The 100 kHz clock uses pseudo-random algorithm jitter in the digital control block to ensure harmonic suppression in the EMI spectrum. The pulse is then pulse width modulated to control the on/off time of the external buck regulator PMOS/NMOS FET. The 100 kHz clock is converted to a sawtooth ramp within the Tronium PSSoC 106, where it is compared to the error amplifier output. A pulse width modulated signal from the comparator output is then applied to the level shifter input to control the on/off time of the external buck regulator PMOSFET. The error amplifier of buck regulator 34 receives feedback from the regulator by scaling the voltage on CP2_OUT using a resistor divider. The voltage feedback signal is then adjusted using internal resistors and capacitors to control the buck regulator's response under all conditions. The resulting transfer function that regulates the servo loop consists of multiple poles and zeros to ensure that the regulator output is stable for load conditions from a full range of 50 mA to 430 mA. The error regulator and PWM controller of the buck regulator are located in the 5 volt domain, where the final control The signal is level shifted to drive an external high voltage PMOSFET switch.

The Tronium PSSoC 106 can also include an LDO buck regulator 128 that is used to form the high voltage side voltage required to drive the gate of the PMOS/NMOS FET of the buck regulator 34. This voltage is then used to supply the gate voltage required to drive the external PMOS/NMOS FET. The capacitors are connected for filtering.

In the illustrated embodiment, the Tronium PSSoC 106 includes a current sense amplifier of a Tronium PSSoC that senses the voltage across the external current sense resistors across the pins RCSP and RCSN. This voltage is sampled and held by the switched capacitor differential amplifier and digitized by the general purpose ADC on the chip. The digits are then compared to the stylized threshold to enable or disable the buck regulator 34 as needed to optimize efficiency. Also for possible fault or alarm conditions, such as an overcurrent monitoring current sense amplifier output, the digital state machine that allows control current sense feedback disables SCVBC 32 to prevent possible damage.

The Tronium PSSoC 106 can also contain at least two self-excited RC oscillators, which share a common trimming controller, including a 16 kHz RC oscillator and a 9.6 MHz RC oscillator. The oscillator frequency can be fine-tuned using the osc_trim register bit.

The low frequency (16 KHz) RC oscillator is a line side RC oscillator that operates continuously after applying a line voltage on LINE_IN. It is supplied by an LPREG regulator. This oscillator output frequency is subdivided into a number, such as 1 kHz, to provide the clock of SCVBC 32. In this case, the oscillator output is also used as the reference clock for the sleep mode shutdown timer. The high frequency (9.6MHz) RC oscillator provides the primary clock for decoding the single line serial data input. The oscillator 9.6 MHz output is divided by 6 to provide the 1.6 MHz clock required for the Dixon charge pump in the switched capacitor circuit. It is further divided to provide a clock source for the buck regulator and the forward converter PWM control block. These 100KHz clocks Pseudo-random algorithm jitter is used by digital logic to ensure harmonic suppression in the EMI spectrum. The oscillator can be enabled with the osc_en register bit and powered by the LPREG regulator on the line side.

In the illustrated embodiment, the Tronium PSSoC 106 includes an ultra low power ADC 118 to digitize the temperature sensor and current sense amplifier analog voltage. These digitized voltages can then be compared by the digital control block to disable or restart the analog circuit. The ADC uses a successive approximation (SAR) topology for low power and higher INL/DNL performance. The input to the ADC is provided by the multiplexer. The multiplexer can select each of the associated channels to be digitized by the ADC. The converted sample values are then stored in the ADC_SAMP register for use by the control state machine. The ADC is powered by low voltage and will be disabled while the device is in sleep mode.

20 is a schematic diagram of a proportional-integral-derivative (PID) regulator control circuit 110 that can be used in conjunction with a Tronium PSSoC 106. In the illustrated embodiment, the Tronium PSSoC 106 includes a PID servo loop 130 to regulate the voltage on the output of the forward converter 96 when the load current is drawn from the secondary side of the external transformer. The PID block contains an error amplifier, a sawtooth waveform generator, a comparator, and a PWM clock control block. The PID loop is designed to regulate the output voltage without severe fluctuations in load current.

The PID buffer amplifier receives the feedback to close the forward regulation loop via the AUTO_ERR input. This is the output of an opto-isolator that provides a voltage to the PSSoC, which represents the output voltage of the forward converter. This voltage is then scaled on the PSSoC using a resistor divider and buffered for the error amplifier.

The error amplifier of the autonomous PID loop is located on the Tronium PSSoC with on-chip compensation resistors and capacitors. The error amplifier uses the bandgap voltage as a reference for the PID servo loop. Sawtooth or other waveform generators provide pulse width modulation (PWM) based on the PID servo loop The means of the clock. The circuit receives the 100KHz clock from the digital logic and converts it to a sawtooth waveform of the same frequency to compare with the output of the error amplifier. The output of the error amplifier and sawtooth waveform generator is compared by a PID comparator to generate the PWM clock required to drive the forward converter. A duty cycle limiter is provided to ensure that the PWM output provided by the PID comparator does not exceed 65%. This output is applied to the FWDOUT pin to drive the external transformer. In normal operation, the PWM duty cycle is limited to the range of 10% to 65% to avoid saturation of the transformer.

In an embodiment, the PID servo loop is designed to operate at low voltage and deliver the maximum required DC current to the load. The adjustment can be controlled to an absolute accuracy of up to a high percentage by using the LC filter on the secondary side and by appropriately determining the size of the internal R and C of the three-stage compensation network. The LC filter double pole is given by the following equation: FLC = 1/2 π L1C4.

The C1 capacitor has a specific ESR (series resistor) that produces zero. This zero produces a +90 degree phase shift: FESR = 1/2 π C1RESR.

The compensation loop has a specific bandwidth (Fc) which is about 1/10 of the clock rate of the forward converter. The goal of the network is to maintain a phase margin of at least 45 degrees under Fc: phase margin = 180 degrees + loop phase.

The PID loop has 2 zeros and 2 poles. The two zero systems provide a 180 degree phase boost to offset the phase loss due to 180 degrees of the output LC filter. Both zeros are placed at approximately ~50% of the LC filter pole frequency. The two poles are then located at the switching frequency of the converter (100KHz). This allows calculation of C1, C2, C3, R2 and R3. R1 is set to a reasonable value to start the calculation procedure.

In another embodiment, the PID servo loop is designed to operate for a plurality of output voltages that can be programmed by a user for a desired application. Loop can transmit ny Current, but in the case shown here, a 4.5A DC current is delivered to the load, combined with an adjustment of up to 0.1% of absolute accuracy. The feedback of the general-purpose loop is provided by an external microprocessor and a voltage sensing support circuit, and is input to the Tronium pin in the form of a serial data stream. The digital word is then performed side by side to a serial conversion, which is converted to an analog voltage for application to the error amplifier, as shown in FIG. The analog to analog conversion is performed using the on-wafer DAC, which is updated at the frequency of the input data rate. The reference voltage of the PID error amplifier is generated by a second DAC that is programmed by the microprocessor.

A digital to analog converter (DAC) generates an analog reference voltage based on a digitally programmed input from a microprocessor to generate a PID control loop. The digital to analog converter (DAC) as shown is a 10-bit scheme, but can be any number of bits. The DAC can also provide feedback from the PID control loop by converting the digital word received from the pin to an analog voltage for input to the loop. The DAC voltage is input to the error amplifier and compared to an analog reference voltage to generate the error voltage of the control loop. The DAC provides an update to the loop at the rate of the input data.

Referring to Figures 17A and 17B, in one embodiment, the Tronium PSSoC 106 can include a ΔV based temperature sensor on the wafer that enables the IC to sense the temperature of the die or module. In this example, a general purpose 12-bit ADC is used to digitize the differential voltage. The digitized value is then compared to the programmable threshold to shut down or re-enable the Tronium PSSoC depending on temperature considerations.

In the illustrated embodiment, the Tronium PSSoC 106 provides two modes of operation and four wake-up states (W0 to W3) applied at power-on.

Boot mode. During the power-on mode, the Tronium PSSoC controls the power-on behavior of the module when power is first applied or when the phone is plugged in (in the case of a charger). When electricity is connected for the first time When connected to AC mains, the rectified and filtered line voltage present on the LINE_IN pin of the IC increases until it reaches its final DC value. The basic support circuitry of the Tronium PSSoC is therefore turned on to enable power management. A timing diagram of an exemplary startup sequence of events is shown in Figure 24, starting with applying a LINE_IN voltage at t=0.

There are three circuit blocks on the line side, which are always on: 1. Low power bandgap reference; 2. Low power 5V regulator (LPREG); and 3. Low power RC oscillator. Other circuits can be powered, but in this example it has been reduced to three in this case to draw very low standby power. These circuits draw power directly from the LINE_IN input, with no transformer action to increase the available current. Therefore, they are designed for ultra low power consumption. Alternatively, the transformer can be deactivated, but this will reduce efficiency.

Normal mode. After the power application and wake-up status is complete, the Tronium PSSoC 106 will enter normal operating mode. The normal mode of operation is maintained until the voltage/current becomes no or lower than the low current threshold, where the microchip within the battery system typically begins to block current to suppress overload. In normal operating mode, the Tronium PSSoC exits sleep mode due to load current detection. The regulation of the load occurs when the buck regulator and SCVBC supply the necessary current. In this mode of operation, all Tronium circuits are turned on and respond to external stimuli.

In one embodiment, the elements of the normal mode, the power-on mode, and the sleep mode are combined, and the battery can be "plugged" for charging. In this exemplary other mode (referred to as the plug-and-charge mode), the logic determination in the wafer is performed when full charge has been performed, meaning that the current is drawn from a higher current to a lower current in a given time period. . This plug-and-charge charging mode of operation may be present in the state machine or enabled/disabled via the I2C interface and will "disconnect" the indicating circuit several times and begin to recharge to a maximum threshold of approximately 150 milliamps at intervals therebetween. In this way, the battery will be prompted to receive additional flow-down charging to ensure it is actually full, rather than displaying "charge" on the device battery indicator full". This will solve the problem that the mobile phone is only charged to about 80 to 90% of its battery capacity, so over time, while the indicator still records 100% of the battery, it is actually 100% of the 80% of the battery capacity. 100% of 100% of non-battery capacity. In plug-and-charge mode, the Tronium PSSoC digit provides an extra current threshold that is above the sleep threshold so that the sleep mode function described below is intact.

Sleep mode. The Tronium PSSoC must use minimal power when connected to AC mains power and does not require charging or power functions. This required circuit 22 has at least two different power domains: 1) a line side field and 2) a primary side field. The line input side must be able to be powered all the time. There is also a 1.6MHz RC oscillator for the Dickson charge pump. This oscillator remains off in sleep mode. The 16KHz oscillator is used as a countdown timer to wake up the Tronium PSSoC when the programmed countdown time has elapsed.

In the illustrated embodiment, the Tronium PSSoC 106 includes a digital control block 122 that provides the user with the ability to manage many aspects of the Tronium application in a set, programmable, normal, test or evaluation mode of operation. . A microprocessor or state machine is provided to monitor the output voltage and current of the switched capacitor circuit and includes a configurable register that provides feature selection and low current or 'sleep' for normal operating modes The mode of operation can be programmed. A communication interface is also provided for the external device according to the needs of the application.

21 is a block diagram of a Tronium universal digital control block 132 that can be used in conjunction with the Tronium PSSoC 106. 22 is a block diagram of a Tronium autonomous digital control block 134 that can be used in conjunction with the Tronium PSSoC 106. 23 is a flow chart showing a method of operating power circuit 22. Figure 24 is a graphical representation of the state transitions that can be implemented by the Tronium PSSoC 106.

Referring to Figure 21, in one embodiment, the Tronium PSSoC 106 includes a universal number Bit control block 132. The Tronium Universal Digital Control Block 132 provides the following functions for controlling general purpose modules: control state machine, clock generator, ADC controller, clock jitter LSFR, I2C interface (single or dual communication mode), programmable communication mode, Microprocessor interface, test/evaluation multiplexer and/or scratchpad file.

The control state machine or microprocessor/microcontroller determines the appropriate mode of operation of the Tronium module by monitoring the output current of the switched capacitor circuit. Provide at least two modes of operation, including sleep mode and normal adjustment mode. The control state machine or microprocessor also provides four states to wake up the PSSoC when power is first applied or when exiting sleep mode, plus the plug and charge mode. In addition, the state machine or microprocessor continuously monitors the overcurrent or undercurrent alarm conditions of the output voltage current.

Monitoring of the switching capacitor output current is achieved in an analog subsystem or in a microprocessor using a current sense amplifier and an analog to digital converter (ADC). The digital control block provides control of the ADC and performs periodic gain and offset correction for the ADC. The ADC samples are then compared to the programmed digital threshold of the switched capacitor current required to control the state machine.

The clock generator provides the clock required by the analog and digital subsystems and also enables clock gating to minimize power consumption in the sleep mode of operation.

The digital control block provides a single-line serial interface that supports the configurability of the PSSoC via an external microprocessor or a multi-line interface that will support two-way communication between the Tronium PSSoC and the microprocessor or state machine. The Clock Jitter Linear Feedback Displacement Register (LSFR) is included to generate pseudorandom numbers for the jitter of the forward and buck regulator PWM clocks. Pseudo-random numbers are used by the analog subsystem to dither the high-frequency oscillator output. I2C埠 is included for manufacturing setup, testing, evaluation, update, health check and commissioning. The scratchpad file containing the configuration register of the device operation can be accessed using the I2C interface. Digital multiplexer is provided to selectively multiply various internal digital signals to DIGTST The output pins are used for testing purposes.

Referring to FIG. 22, in an embodiment, the Tronium PSSoC includes an autonomous digital control block 134 that provides the following functions for controlling an autonomous module: a control state machine or a microcontroller; a clock generator; Clock; jitter jitter LSFR; I2C interface; test multiplexer; and scratchpad file. The control state machine determines the appropriate mode of operation of the Tronium PSSoC 106 by monitoring the output current of the switched capacitor circuit on the CP_OUT pin. Two modes of operation are provided, including sleep mode and normal adjustment mode. The control state machine or microcontroller also provides four states to wake up the IC when power is first applied or when exiting from sleep mode. In addition, the state machine monitors the overcurrent-undercurrent alarm state of the output current and the plug-and-charge mode.

The use of a current sense amplifier achieves monitoring of the switched capacitor output current in an analog subsystem and uses a 12-bit analog to digital converter (ADC) in this example. The digital control block provides control of the ADC and performs periodic gain and offset correction for the ADC. The ADC samples are then compared to the programmed digital threshold of the switched capacitor current required to control the state machine and/or the microcontroller.

The clock generator provides the clock required by the analog and digital subsystems and also enables clock gating to minimize power consumption in the sleep mode of operation or the plug and charge mode.

The Clock Jitter Linear Feedback Displacement Register (LSFR) is included to generate pseudorandom numbers for the jitter of the forward and buck regulator PWM clocks. Pseudo-random numbers are used by the analog subsystem to dither the high-frequency oscillator output.

I2C埠 is included for manufacturing setup, evaluation, update, reset, wafer health check, testing, and commissioning. The scratchpad file containing the configuration register of the device operation can be accessed using the I2C interface.

A digital multiplexer is provided to selectively multiplex various internal digital signals to the DIGTST output pins for testing purposes.

In the illustrated embodiment, the Tronium autonomous digital control block 134 includes a state machine to determine an appropriate mode of operation of the autonomous module based on the load current.

As shown in Figures 23 and 24, the control state machine provides four awake states (W0, W1, W2, and W3) and two modes of operation; normal mode and sleep mode.

Wake-up 0 (W0)--When power is applied, the line-side circuit wakes up: the bandgap (BG) and low power regulator (LPREG) are turned on. After LPREG is stabilized, por_b is released and the system transitions to wake-up 1 (W1).

Wake 1 (W1) - Low Frequency Oscillator (LF_OSC) and Gain Control (GAIN_CTRL) are enabled. At the same time, the high frequency oscillator (HF_OSC) and the charge pump (CP) are enabled. The CP is set to not adjust. When LF_OSC is stable, lf_clk to the digital block is released at the point when (a) the 10mS counter is started and (b) the switched capacitor becomes 1kHz. When the 10ms counter expires, the system transitions to wakeup 2 (W2).

Wake 2 (W2) - The switching regulator (SWR) is enabled, the CP is set to adjust and the 1mS counter is activated. When the 1ms counter expires, the system transitions to wake-up 3 (W3).

Wake 3 (W3) - Forward PID is enabled and two counters are started: 20ms counter and 250ms counter. The following scenarios provide a transition from this state: a.20mS counter expires and the forward PID change option is on: the system transitions to normal mode (NM); b.20ms counter expires, the forward PID change option is off and the forward PID is at 250mS Stable before the counter expires: the system transitions to normal mode (NM); c. sleep mode is not deactivated, the forward PID change option is off and when the 250mS counter expires, the forward PID has not stabilized: the system transitions to sleep mode.

Normal mode (NM) - current sense block (CUR_SNS) and ADC are enabled. If self-calibration is not disabled, the ADC uses the first two samples for gain and offset calibration and signals the ADC data OK when the third sample is ready. If self-calibration is disabled, the ADC performs gain and offset correction using the values programmed in the specified scratchpad and signals the ADC data OK when the third sample is ready. When the ADC data is OK, the system monitors the current load. The following mutually exclusive conditions (which can be programmed) can occur: 1. Overcurrent condition: The system sets the overcurrent status bit. If the sleep mode is not disabled, the system transitions to sleep mode (SM); and 2. Underload condition: if the LCSD_EN pin is high and the sleep mode is not disabled, the system transitions to sleep mode (SM); 3. Low load condition: The system turns off the SWR when it detects a low load condition and re-turns the SWR when the low load condition is weak.

Sleep Mode (SM) - The system disables HF_OSC, CP, SWR, Forward PID, and CUR_SNS and ADC. It also initiates a sleep counter, the duration of which is programmable. The preset sleep time is approximately 5 seconds, which may depend on the application adjustment. If the forward PID has not stabilized before entering sleep mode, it remains in sleep mode. In this case, the pin can be restarted in W1 by triggering the EXT_RST pin or restarted in W0 by removing power. If the forward PID is OK when entering sleep mode, the system transitions to the W1 state when the sleep counter expires.

In the illustrated embodiment, the transition between the normal mode of operation and the sleep mode of operation is achieved by monitoring the output current of the switched capacitor circuit via the current sense amplifier and the ADC. In addition, the control state machine disables the SWR buck regulator when the load current is reduced to the programmed digital threshold. The monitoring of the current and corresponding mode transitions is shown in the graph of Figure 24.

Referring to Figures 21 and 22, the digital control block 122 can include a clock generator, Generate all the clocks required by the digital subsystem. Provides three clock domains that are synchronized with each other, the low frequency clock domain, the high frequency clock domain, and the I2C clock domain.

The low frequency oscillator in the analog subsystem provides the clock in the depicted example for the 16 kHz clock (lf_clk) of the digital subsystem. In addition to the clock used by the scratchpad file, the clock generator derives the following clock from lf_clk: 1.sys_clk--the 8 kHz clock with 50% duty cycle, which is the timing of the control state machine. 2.adc_gclk--The sys_clk of the gated version that is clocked by the ADC controller. At this point, the gate is turned off in sleep mode. 3. lfdiv_clk has a divided clock with a programmable frequency of 1, 2 or 4 kHz, which has a 50% duty cycle to be used in the analog block. At this point, the gate is turned off in sleep mode.

The oscillator can be bypassed in the analog subsystem via the TSTMD0 input to enable the application of a 16 kHz clock from the EXT_CLK pin.

The high frequency oscillator in the analog subsystem provides a 1.6 MHz, 50% duty cycle clock that is further divided by the clock generator to form hfdiv_clk. The hfdiv_clk can be stylized via the scratchpad file to provide frequencies of 100, 200 and 400 kHz. Hfdiv_clk is also used in digital form for clock jitter LFSR and analogously for buck regulators and forward PID loops. The clock is turned off in sleep mode when the HF oscillator is deactivated in analogy.

The I2C interface uses the clock input on the SCLK pin to control the operation of the I2C埠. Support data rates up to 100Kbps.

In the illustrated embodiment, the digital control block 122 also includes an ADC controller that generates control signals for use in a generic 12-bit ADC in the analog subsystem. It is also selected for conversion via the ADC multiplexer and the ADC_MUX_SEL register in the CONTROL0 register to the input of the ADC. The ADC output format is the magnitude. Once the ADC is first deactivated, The digital control block performs the self-calibration procedure. The digital control block configurably uses the gain and offset correction values calculated during self-calibration or uses the gain and offset correction values written to the ADC_GAIN and ADC_OFF registers.

During the self-calibration procedure, the decision gain and offset correction values are described as follows.

The offset is first determined as follows: Set the ADC input multiplexer to select the Reflo reference voltage. Perform an ADC conversion. The ideal value will be zero. Load the ADC conversion data into the local ADC offset correction register.

Next, the gain is determined as follows: Set the ADC input multiplexer to select the Refhi reference voltage. Perform an ADC conversion. The ideal value would be 4095. Load the local ADC gain correction register with the result of (ADC conversion data - offset correction) / 4095.

After the self-calibration phase, the ADC conversion value is corrected as follows: ADC corrected data = (ADC conversion data - offset correction) / 4095.

The clock jitter LFSR provides pseudo-random values to implement jitter on the 1.6 MHz clock to mitigate EMI. The LFSR is a 12-bit polynomial x12+x6+x4+x+1, a maximum sequence, and a Galois-type LESR. The jitter values are generated as shown in the table below. The clock jitter LFSR can be selectively enabled or disabled using the dith_en register in the control register.

In an embodiment, the Tronium PSSoC digital control block 122 can include a configurable down counter having a range of 0.512 seconds to 16.384 seconds to implement the sleep timer function. The step size is 512mS. The timer receives its clock from the clock generator block, where it is divided down from the LF oscillator clock. The counter is loaded with the programmed sleep time value in the SLEEP_CTRL register. The counter will count down from this value until it reaches zero, at which point it tells the control state machine that the sleep timer has expired.

Figure 25 is a schematic illustration of a communication interface that can be used in conjunction with the Tronium PSSoC 106. Figure 26 is a schematic illustration of a microprocessor communication protocol that can be used in conjunction with the Tronium PSSoC 106. In the illustrated embodiment, the communication can be unidirectional or bidirectional. The Tronium PSSoC 106 contains one or more communication interfaces, described herein as three interfaces: 1) a microprocessor interface, 2) a single or dual communication/update interface for stylizing values or returning information to a state machine/micro Processor and 3) Test/Evaluation interface. The microprocessor interface will be used to communicate with an external microprocessor of a particular product, and the communication/update interface can update the microprocessor or any value within the wafer. This allows product configurability and implementation of the control loop for the Tronium charger. For the Tronium PSSoC, this can be a read/write or write-only interface, ie the microprocessor will or will not be able to read from the PSSoC depending on the type of communication being determined (one-way or multi-directional).

The test/assessment interface will be used in the manufacturing test environment and for bench evaluation of the Tronium PSSoC. It will allow write and read access to the scratchpad on the wafer. The update, evaluation, health check and reset interface will be used to reprogram the wafer, change its voltage/current output or change other reprogrammable parts of the control logic (including thresholds) and run scans to help determine if the wafer has a problem. (health examination).

Typically, only one interface can be selected at a time, but this can vary based on state machine or microprocessor settings. The IF_SEL input pin selects I2C at '1' and the microprocessor interface at '0'.

Microprocessor communication interface. The Tronium PSSoC also offers a single-line serial interface to support the configurability of PSSoC. The interface consists of one-way or multi-directional data input/output. The agreement is shown in Figure 26. All packets will be identical in structure and length unless otherwise required. Each packet will be a specific number of bits. The packet bar is described below. By adding another line, you can have a double pass The interface makes the information multi-directional.

To support reliable communication, the data can be encoded by Manchester in accordance with the IEEE 802.3 communication standard. The receiver will then use the oversampled clock to maintain the bit synchronization within the packet. The bit rate will be 600 Kbps. The input data will be oversampled to 16 times the bit rate. The oversampled clock is therefore 9.6 MHz and is derived from the on-wafer RC oscillator.

Start: A single bit whose value is the non-idle state of the signal line. For this application, this will be '1'. R/W: A single bit to indicate a read or write request. At '0', the data is written to the selected Tronium register. Note that Tronium only supports write access. Addr[4:0]: 5 bits are used to address the Tronium configuration register. Data [9:0]: 10 bits will be written to the selected Tronium register. For the case where the target scratchpad is less than 10 bits, the data will be right aligned. For example, when writing to an 8-bit scratchpad, data [7:0] is written to the addressed scratchpad location. Idle: A single bit whose value is the idle state of the signal line. For this application, this will be '0'.

Transfer data by MSB first. For example, Addr[4] is first transmitted by the host in time. The Tronium implementation depends on whether the stylization will support or will not support the read operation of the ASIC register. R/W bits are included for future expansion.

27 is a schematic diagram of an internal integrated circuit 136 that may be included in the Tronium PSSoC 106. In the illustrated embodiment, the Tronium PSSoC 106 contains an I2C slave to support testing of the device. The I2C address can be configured using the I2C_ADDR pin. The I2C_ADDR input is compared to the I2C slave address bit. The Tronium I2C busbar protocol is shown in Figure 27. The I2C interface supports bit transfer rates up to 100Kbs. The I2C interface runs completely outside of the I2C SCLK clock input.

I2C write operation: Tronium PSSoC supports writing to the Tronium memory map register via I2C slave. Receiving an I2C slave address matching the Tronium I2C address Thereafter, it is shown in Figure 27 that the one-bit tuple below byte 1 will contain the 5-bit address field of the Tronium register file address. The Tronium PSSoC only supports one register access per command.

I2C read operation: The Tronium PSSoC supports reading from the Tronium memory map register via I2C slave. The read operation requires two I2C operations. First, the I2C write to the RDREQ register, where the data in byte 2 is the Tronium memory map address of the scratchpad that will be read. The I2C read command will then read the requested scratchpad. Tronium only supports access to one scratchpad per command.

Note that there is a delay between the I2C operation and the RDREQ register update. This means that after the write operation I2C, I2C master 400 μ sec have to wait before issuing a read operation I2C. This wait time applies only to the first I2C read after I2C write to update the RDREQ register.

In one embodiment of the Tronium PSSoC, digital memory is savvy, where if the Tronium PSSoC powers the TV, if the TV is not used for a fixed number of days from a certain time period to another time period (such as midnight to 7 am) Tronium will continue to put itself in sleep mode during these times to save energy and not re-participate in the current sensing program of the wake-up sequence.

In another embodiment of the present invention, the Tronium PSSoC is connected to a wireless (eg, BlueTooth®) or wire type communication protocol and device (external, on-wafer or on a module) through its I2C interface for reception to a state machine or microprocessor Instructions. In this way, there may be "instant" instructions given to Tronium about when to enter sleep mode, when to wake up and reset, update or change other prerequisites, such as overvoltage or PWM regulation. In this way, the Tronium PSSoC can have “instant” sensing and switching of its control mechanism to achieve different levels of frequency, speed or suitability. In low power situations, as in some countries, where the grid typically operates under undervoltage conditions most of the time. In this case, the Tronium PSSoC can get instant information about resetting, operating, or shutting down/restarting, including instant commands from its owner or even from a cellular system to a home communication technology via a cellular system. In this case, a person may want to turn off power to a particular electronic device or electronic device powered by the Tronium PSSoC when not at home, and this may be via wireless or wired communication technology via a communication interface (their through I2C in the Tronium PSSoC) The interface gives a specific instruction indicating that it shuts down the device and even presets the time it should wake up).

In another embodiment of the present invention, and when used as a charger or constant power supply, the Tronium PSSoC is small enough to fit into a wall socket attached to the cord, thus eliminating the need for a charger "box" or laptop The need for a computer "brick".

In one embodiment, the Tronium PSSoC 106 has several test structures to support manufacturing, programming, evaluation, update, health check, communication, testing, and bench evaluation. The Tronium PSSoC provides two test registers for key internal functions and controllability and observability of control signals. The TEST_CTRL0 register provides the user with the ability to selectively enable, disable, or control individual analog circuit functions in the Tronium PSSoC to provide an alternate control method, provided the control state machine is bypassed. The TEST_CTRL1 register provides the ability to translate multiplexed internal analog and digital signals to the ANATST and DIGTST output pins for testing purposes.

Many modifications and variations of the present invention are possible in light of the above teachings. The invention may be practiced otherwise than as specifically described in the scope of the appended claims.

Figure 30 is a connection diagram that can be used in conjunction with the Tronium PSSoC 106. 31 and 32 are additional schematic diagrams of the Tronium PSSoC 106. Figure 33 is a flow diagram of an algorithm for low current detection and error detection that can be used in conjunction with the Tronium PSSoC 106. Figure 34 and Figure 35 contain Schematic diagram of the power circuit 22 of the Tronium PSSoC 106. In the illustrated embodiment, the Tronium PSSoC 106 is an advanced power controller integrated circuit (IC). The Tronium PSSoC 106 and corresponding integrated modules provide a low cost, efficient means to convert AC line voltages present on typical home or corporate electrical outlets into reduced regulated DC voltage for consumer electronics applications. Typical applications include, but are not limited to, charging systems for mobile phones, tablets or other handheld devices, USB power conversion, power to consumers, medical and industrial devices, and many other possible uses.

The Tronium PSSoC provides high efficiency, low noise and low EMI with configurations and features as explained above. In addition, AC to DC, DC to DC converters have high power density, low cost, and electrical isolation. These advantages are achieved by integrating additional discrete components onto the wafer using a switched capacitor voltage collapse scheme and primary side sensing/control. Therefore, the key features of the Tronium PSSoC are as follows: support for a range of available AC input voltages and frequencies; programmable output voltages combined with automatic setting to automatically detect input voltages for configuration to input voltage for proper operation; for AC to DC, High-efficiency switched capacitor circuit for DC to DC conversion; high-accuracy PID (or similar) regulation control loop; digital state machine for current and temperature monitoring; ultra-low power dissipation for idle (vampire) mode of operation; Configuration and control of the optically isolated microprocessor interface; and communication protocols for manufacturing tests.

The analog and digital interfaces, inputs and outputs of the Tronium PSSoC can withstand voltages and currents outside the typical operating range. The unit can also operate over a wide temperature range and provide sufficient ESD immunity.

The Tronium PSSoC provides input and output to external and external circuit interfaces. These include but are not limited to: power input, power output, low current shutdown enable input, mode select input, intermediate connection requiring external circuitry, test connection, communication connection, power output, tuning Timer output, PID-based PWM connection, FET drive output, and feedback input.

The Tronium PSSoC is an advanced power controller integrated circuit designed to provide output voltage regulation with high efficiency and accuracy. The advanced features of the Tronium PSSoC provide users with a versatile device for a wide range of applications. In the case of Tronium PSSoC, the programmable output voltage is feasible and there is less efficiency loss or inefficiency loss across multiple current load conditions.

The Tronium PSSoC uses dedicated switched capacitor circuitry to maintain high efficiency regardless of load voltage or current. When the load is not drawing current, the device will enter a low current mode of operation to minimize the traditional 'vampire' current required to keep awake and the number of active subsystems scaled to the load to provide high efficiency across a wide load range

The top-level block diagram of the Tronium PSSoC is shown below and consists of the following main circuit blocks: high voltage multi-stage/multi-drop switched capacitor voltage collapse circuit; PID (or other switch mode control scheme), regulation of PWM control for the secondary transformer Control block; current and temperature sensing block; ADC or comparator for voltage and current monitoring; DAC, PWM or other signal for feedback control; digital control block for voltage and current monitoring state machine; communication interface And power management for voltage and current generation on the wafer and other power requirements.

Power management. The power management block provides the necessary power rails and references to the remaining ICs. It consists of a voltage regulator, a current reference, and a voltage reference. It also contains all the necessary buffering and amplification required for IC use. The power management system also includes a reset controller that manages the shutdown and power-on of the system on the power cycle.

Switching capacitor voltage breakdown circuit. The Tronium PSSoC's switched capacitor voltage collapse circuit operates as a near-lossless voltage divider. It will rectify the DC present on the LINE_IN pin The voltage is divided into reduced voltages on the CP2_OUT pin for use by external transformers and secondary voltage control loops. The external transformer can then further reduce this voltage to the voltage to be applied depending on the primary to secondary winding ratio and provide isolation if needed.

The switched capacitor circuit is configured as a cascade of multiple identical stages having multiple parallel branches as shown below. The parallel branch switches into and out of the circuit based on the load current sensed by the current sense amplifier. This allows the switched capacitor circuit to maintain high efficiency across a wide range of load currents. In the figure below, the number of parallel subsystems is 4, including two levels. The number of parallel systems and conversion stages can be varied to optimize the system for a particular input/output voltage ratio or power demand.

Switched capacitor circuits use on-wafer or off-chip flyback capacitors to maximize power efficiency and use external holding capacitors to minimize voltage ripple. These capacitors are connected to the CP1_OUT and CP2_OUT pins, respectively, for switching the output of the first and second stages of the capacitor circuit. All stages can have their own dedicated oscillators by oscillator timing or stages. Each branch of the switched capacitor circuit can be independently enabled.

The output voltage can be combined with a digital-to-analog converter (DAC) for high-resolution programming over a range of voltages for a given range of applications. The digital control of this DAC allows multiple voltages to be programmed on the CP2_OUT pin to achieve the desired final output voltage for the target application.

The switched capacitor circuit output settings of other switched capacitor circuit stages can be determined by the user or derived from the measured AC line Vin such that an optimum ratio between Vin and Vout is achievable.

The adjustment of the circuit stages of each switched capacitor is achieved in conjunction with the use of an operational superconducting amplifier (OTA). The OTA adjusts the current applied to the flyback capacitors in each stage based on the difference between the output voltage and the input reference voltage. The input reference voltage can be programmed, derived or fixed depending on the application set.

The voltage measurement of the input line can be performed to optimize the switching capacitor circuit settings. This setting calculation can be performed on-wafer, off-chip or in operation through appropriate on-wafer circuitry such that the output of each switched capacitor circuit stage is at an optimum ratio.

Current sense amplifier. The current sense amplifier in the Tronium PSSoC allows the device to measure current as part of the feedback loop and error reporting. The current is measured by the ADC or by a series of comparators with varying thresholds.

PID control loop. The Tronium PSSoC provides a proportional-integral-derivative PID loop or an alternate PWM control circuit to drive the primary side of the isolation transformer, buck, boost or buck-boost circuit. This circuit will provide post adjustment and isolation when needed.

The feedback to the PID loop can come from a digital source such as, but not limited to, a serialized ADC stream or an analog signal, both depending on the output of the circuit. This feedback provides information about the regulated output current or voltage.

Temperature sensor. An on-board temperature sensor can be implemented to allow adequate protection against over-temperature conditions. Measures taken to protect against thermal damage may include derating of the output power and complete shutdown of the output.

Control circuit. The Tronium PSSoC provides control through digital means or through analog circuits. Through this control circuit, the IC can set and change existing control thresholds and control points and enable/disable specific functions. This can be done in the case of a digital interface through a register or fuse or through an applied voltage to an analog pin (provided an analogy is required).

If the feature is enabled, the Tronium PSSoC allows the system's output to be deactivated or derated. This can be done by turning off the PWM, switching capacitor circuits, or by dropping either or both subsystems. It happened. The output may be disabled due to error detection or due to low output current or output power conditions such as when the battery-connected device completes charging the battery and the Tronium PSSoC only provides power to the non-battery charging function. Once the Tronium PSSoC has entered a low current shutdown state, it will intermittently reapply output power to the end device to check if it now requires more power than a certain threshold, indicating that the battery now requires further charging. The time spent in the off state can be adjusted for different applications. Figure 33 illustrates an example of an algorithm for low current detection and error detection.

The Tronium PSSoC provides multiple interfaces to external circuitry, allowing the device to control and configure the IC. Such interfaces may include, but are not limited to, SPI, I2C, UART, or other synchronous/unsynchronized streams. Alternate encoding in the NRZ format can also be implemented to optimize the size and number of components of the external circuitry. Likewise, such communication interfaces can be connected to the isolation device to enable communication from the isolated area, provided that this is required.

Clock generator. The Tronium PSSoC can have the ability to generate its own internal clock, which can also include frequency control circuitry including, but not limited to, internal RC oscillator, PLL, FLL, clock divider, VCO, and trimming circuitry. In addition, the timing tree can implement intentional clock jitter or other means to change the clock edge arrangement to minimize the effects of timing on radiation and conducted EMI.

Module description. The Tronium PSSoC is intended to be used as a power supply unit to be incorporated into a module that receives an AC power input, converts this power to a DC voltage, and supplies this power to an external device. The module can take many forms, which can include analog or digital feedback to the output of the ASIC or the ASIC can operate in open loop mode without feedback. In addition, the modular circuitry can be constructed such that individual outputs (provided that there are multiple connected outputs) can be discretely monitored and controlled. The sensing capabilities within the module are intended to supplement or replace the measurements made by the ASIC depending on the application and regulatory requirements.

Figure 34 is a diagram of a digital feedback module with isolated and discrete output sensing Schematic diagram of force circuit 22. 35 is a schematic diagram of a power circuit 22 including an analog feedback module with linearization of feedback isolation. These represent analogy feedback versions and digital feedback versions. Both of these figures also indicate that the isolation transformer is part of the design. This component may or may not be included in the module depending on the requirements of the application. Two examples describe a synchronous rectification scheme, but an asynchronous system can also be implemented.

Digital feedback description. The digital feedback module includes a microcontroller, independent ADC or secondary ASIC to monitor the output voltage and allow very accurate measurements on the output connections. This allows the module to compensate for component losses, temperatures, and other variables that may cause variations in the output voltage. This material is then formatted and sent back to the ASIC to provide a digital feedback stream. Current sensing and output enable transistors are also shown such that if multiple outputs are connected to the module, there is individual sensing on each. In this way, the low power shutdown function described in the ASIC description can be applied to individual loads even when power is shared.

Analog feedback description. If an analog feedback system is required for cost or other reasons, the Tronium PSSoC allows this to be achieved via analog feedback inputs. In the illustrated embodiment, the self-current through the optically isolated LED is proportional to the output voltage. The circuit is designed such that the voltage on the analog feedback pin on the IC is at a nominal voltage when the output voltage is at the target output. Current monitoring is performed by the IC on the primary side of the transformer and the measurement is scaled by the turns ratio of the transformer.

36 is a schematic diagram of a level shifter circuit that can be used in conjunction with power circuit 22. In one embodiment, switched capacitor voltage collapse circuit 32 and buck regulator 34 rely on a level shifter that can take a static CMOS level digital signal and shift the signal voltage to various levels. This is done to properly drive the gates of the high voltage switches on and off the Tronium PSSoC chip. The level shifter consists of a differential voltage pair with a static dc current bias voltage. difference The voltage pair amplifies the CMOS level signal and then shifts to a higher voltage rail. There is a cascade used in the signal path to avoid any transistor collapse. The level shifter can be deactivated via the p-channel switch to avoid any quiescent current drain. Once the signal is shifted to another rail, it is further amplified to a single end and then converted back to the static CMOS stage to drive the high voltage switch.

38 and 39 are additional schematic diagrams of power circuit 22. In an embodiment, the forward converter transformer 102 can include a tertiary winding 152 (shown in Figures 39 and 40) that can be used as a replica for the secondary side of current sensing. For example, some Tronium PSSoC applications can operate at low voltages and self-driven synchronous rectifiers may not be a reliable solution. A larger gate voltage will ensure a robust system. For example, there will be an application for a 1.8 volt DC output. Assume a 12:1 transformer and a 43 volt CP_DAC2 setting, and a peak voltage on the 3.6 VDC secondary winding. The 12:2 auxiliary winding can be used to generate a 7.2 volt gate drive for a synchronous rectifier FET. The transformer design can include an auxiliary winding 152 on the secondary side to support this requirement.

41 is a schematic diagram of a power circuit 22 including a DC to DC conversion circuit. In the illustrated embodiment, power circuit 22 includes a switched capacitor voltage collapse circuit 32 for receiving a DC input power signal and generating a DC output power signal having a lower voltage level. In an embodiment, power circuit 22 may also include a switch mode buck regulator 34 coupled in parallel with SCVBC 32. The high efficiency switched capacitor voltage collapse circuit 32 includes a plurality of switch assemblies that are electrically coupled in parallel to each of the flyback capacitors and to each of the pair of flyback capacitors. In one embodiment, the gates between the capacitors are common. The switch assembly is operable to selectively transmit an input DC power signal to each of the pair of flyback capacitors during a charging phase and selectively during a discharge phase having a voltage level lower than the input DC power signal Ground output DC power signal to electronic equipment Set. The at least one switch assembly can include an N-channel MOSFET switch and a level shifter for transmitting control signals to the N-channel MOSFET switch. Additionally, a Dixon charge pump can be coupled to the level shifter to receive the input DC power signal and generate an output power signal having a voltage level that is higher than the input DC signal. The output power signal is transmitted to a level shifter for operating the N-channel MOSFET switch (or for other types of MOSFETs for shutdown). Additionally, the switched capacitor voltage collapse circuit can include a control circuit including: a voltage sensing circuit for sensing a voltage level of the input DC power signal; and a gain controller configured to sense the sensed voltage The level selects the gain setting of the switched capacitor voltage collapse circuit and operates each of the plurality of switch assemblies in accordance with the selected gain setting.

The written description uses examples to disclose the invention, including the best mode, and the invention may be practiced by those skilled in the art, including making and using any device or system and performing any incorporated methods. The patentable scope of the invention is defined by the scope of the claims, and may include other examples that are apparent to those skilled in the art. Other aspects and features of the present invention can be obtained from the drawings, the disclosure, and the scope of the accompanying claims. The invention may be practiced otherwise than as specifically described in the scope of the appended claims. It should also be noted that the steps and/or functions listed in the appended claims are not limited to any particular order of operation, even if the order of the steps and/or functions are listed herein.

Although specific features of various embodiments of the invention may be shown in some drawings and not in other figures, this is only for convenience. In accordance with the principles of the invention, any feature of the drawings may be referenced and/or claimed in conjunction with any feature of any other figure.

10‧‧‧Electronic charging device

12‧‧‧Power Module

20‧‧‧Electronic devices

22‧‧‧Power Circuit

24‧‧‧Power supply

26‧‧‧Primary power circuit

28‧‧‧Secondary power circuit

30‧‧‧Rectifier circuit

32‧‧‧Intermediate voltage converter

34‧‧‧Buck regulator

96‧‧‧ Forward Converter

106‧‧‧ Controller

Claims (20)

A circuit for providing power for powering an electronic device, comprising: a switched capacitor buck device configured to receive an input power signal having an input voltage level from a power source and generating a An intermediate power signal having an intermediate voltage level less than one of the input voltage levels, the switched capacitor buck device comprising a plurality of switching devices coupled to a pair of capacitors; a forward converter coupled to the switched capacitor a step-down device for receiving the intermediate power signal and transmitting an output power signal to an electrical device, the output output power signal having an output voltage level less than the intermediate voltage level, the forward converter including a forward direction a regulator circuit coupled to a transformer; and a controller coupled to the switched capacitor buck device and the forward converter, the controller configured to: when receiving the input power signal from the power source A boot mode is activated, the boot mode includes powering the switched capacitor buck device and the forward converter, and starting a boot meter And including a predefined time period; when the power-on counter expires, starting a normal operation mode, the normal operation mode comprising operating the switched capacitor buck device and the forward converter to transmit the output power signal to the power The device senses a current level of the output power signal transmitted to the electrical device and transmits a control signal to the switched capacitor buck device and the forward converter to adjust the sense based on the sensed current level measurement Outputting a power signal; and initiating a sleep mode of operation if the current level of the output power signal transmitted to the electrical device is less than a predefined current level criterion, the sleep mode of operation comprising powering down the switched capacitor A step-down device and the forward converter. The circuit of claim 1, wherein the controller is further configured to maintain the sleep mode of operation when the current level of the output power signal is less than the predefined current value. The circuit of claim 1, further comprising a control circuit comprising a bandgap generator, a high frequency oscillator, and an analog to digital converter configured to initiate the sleep operation The control circuit is deactivated in mode. The circuit of claim 3, the controller is further configured to initiate the power-on mode, comprising: initiating a first wake-up mode, comprising: energizing the control circuit and the switched capacitor step-down device, and Generating a first wake-up counter; and initiating a second wake-up mode when the first wake-up counter expires, the second wake-up mode comprising powering the forward converter and transmitting a control signal to the forward adjuster circuit. The circuit of claim 4, the controller is further configured to: initiate the second wake-up mode, comprising: initiating a second wake-up counter; if the forward converter is in the second wake-up counter The normal mode of operation is initiated when the previous time has stabilized; and the sleep mode is initiated if the forward converter has not stabilized before the second wake-up counter expires. The circuit of claim 4, the controller is further configured to: initiate the sleep mode of operation comprising initiating a sleep counter; and initiating the power-on mode when the sleep counter expires. The controller is further configured to make a dummy as in the circuit of claim 4 The forward mode is initiated when the forward converter has stabilized before the second wake-up counter expires. The circuit of claim 1, further comprising a buck regulator device electrically coupled in parallel with the switched capacitor buck device, the controller being further configured to: initiate the power-on mode, which includes energizing The buck regulator device, and initiating the normal mode of operation, includes operating the switched capacitor buck device, the buck regulator device, and the forward converter to transmit the output power signal to the electrical device. The circuit of claim 8 wherein the controller is further configured to de-energize the buck regulator circuit if the sensed current level is within a predefined low current range. The circuit of claim 9, wherein the controller is further configured to adjust the switched capacitor voltage collapse circuit at a different frequency than the buck regulator circuit. The circuit of claim 1, wherein the controller is further configured to: detect the output power signal from a high current level to a current level of a low current level; and when detecting the current When the plug-in charging mode is activated, the plug-in charging mode includes repeatedly starting the sleep operation mode, the power-on mode, and the normal operation mode for a predefined time period. A method of operating a circuit for transmitting power to an electronic device, the circuit comprising a switched capacitor buck device and a forward converter, the buck capacitor buck device comprising a plurality of switching devices coupled to a pair of capacitors, The forward converter includes a forward regulator circuit coupled to a transformer, the switched capacitor buck device configured to receive an input power signal having an input voltage level from a power source and generating a Intermediate power signal Having an intermediate voltage level that is less than one of the input voltage levels, the forward converter is configured to receive the intermediate power signal and transmit an output power signal to an electrical device, the output output power signal having less than the intermediate voltage level One of the output voltage levels; the method includes the steps of: initiating a power-on mode when receiving the input power signal from the power source, the power-on mode including powering the switched capacitor buck device and the forward converter, and starting a boot counter comprising a predefined time period; when the boot counter expires, initiating a normal operating mode, the normal operating mode comprising operating the switched capacitor buck device and the forward converter to transmit the output power signal to The electrical device senses a current level of the output power signal transmitted to the electrical device and transmits a control signal to the switched capacitor buck device and the forward converter to detect based on the sensed current level Adjusting the output power signal; and assuming that the current level of the output power signal transmitted to the electrical device is less than Criteria predefined current level starts a sleep mode operation, the operation mode includes a sleep off the switched capacitor step-down device and the forward converter. The method of claim 12, wherein the sleep mode of operation is maintained when the current level of the output power signal is less than the predefined current value. The method of claim 12, wherein the circuit comprises a control circuit comprising a bandgap generator, a high frequency oscillator, and an analog to digital converter, the method further comprising when the sleep mode of operation is initiated The step of deactivating the control circuit. The method of claim 14, comprising the step of initiating the power-on mode, comprising: initiating a first wake-up mode, comprising: energizing the control circuit and the switched capacitor step-down device And activating a first wake-up counter; and starting a second wake-up mode when the first wake-up counter expires, the second wake-up mode comprising powering the forward converter and transmitting a control signal to the forward adjuster circuit . The method of claim 15, comprising the steps of: initiating the second wake-up mode, comprising starting a second wake-up counter; if the forward converter is stable before the second wake-up counter expires The normal mode of operation is initiated; and the sleep mode is initiated if the forward converter has not stabilized before the second wake-up counter expires. The method of claim 12, comprising the steps of: initiating the sleep mode of operation, comprising initiating a sleep counter; and initiating the power-on mode when the sleep counter expires. The method of claim 12, wherein the circuit comprises a buck regulator device electrically coupled in parallel with the switched capacitor buck device, the method comprising the steps of: initiating the power-on mode, including energizing the The buck regulator device is activated and the normal mode of operation is initiated, comprising operating the switched capacitor buck device, the buck regulator device, and the forward converter to transmit the output power signal to the electrical device. The method of claim 18, comprising the step of powering down the buck regulator circuit if the sensed current level is within a predefined low current range. The circuit of claim 19, comprising the step of adjusting the switching capacitor voltage collapse circuit at a different frequency than the buck regulator circuit.