TWI750264B - Over-voltage protection loop and method for providing over-voltage protection - Google Patents

Abstract

Systems and methods are disclosed for providing over-voltage protection for power converters. An over-voltage protection loop includes an error amplifier that maintains an external reference voltage within a highly precise range that can be used to provide a highly precise output voltage from the over-voltage protection loop. The over-voltage protection loop may also include feedback impedance that delays the output of the over-voltage protection loop. The delay may prevent the over-voltage protection loop from being engaged due to voltage transients output from a main servo loop circuit that provides a nominal output voltage under normal operation, thus allowing the threshold voltage and output voltage of the over-voltage protection loop to be set close to the nominal output voltage of the main servo loop circuit.

Description

Overvoltage protection loop and method for providing overvoltage protection

The present invention generally relates to providing overvoltage protection in an active mode of operation.

Power converters change electrical energy from one form to another. For example, some power converters convert AC power signals to DC power signals and vice versa, while some power converters alter the frequency and/or voltage of an input power signal. A DC/DC converter converts an input DC voltage to a different output DC voltage. These converters typically include a transformer electrically coupled through a switching circuit between a voltage source and a load. These converters are also typically controlled by a closed loop feedback system designed so that the converter maintains the output voltage within a predefined and highly accurate range. However, if the feedback loop fails, the output voltage may increase uncontrollably until the converter or the load or both are damaged.

Designers incorporate overvoltage protection into power converter systems to prevent a feedback loop failure from further damaging the transformer circuit or load. Overvoltage protection can be incorporated into other systems where under normal operation a feedback loop is used to prevent the output voltage from exceeding a certain level. Conventional systems and methods for providing overvoltage protection include implementations using a latching scheme or a non-latching scheme. In a latching scheme, the power converter can be shut down when an overvoltage condition occurs and shut down until restarted, eg, by cycling the input power. in a non-latching In the scheme, when an overvoltage condition occurs, the power converter can be power cycled to restart. However, if the power cycle does not correct the overvoltage condition, the power converter may continue to operate in an erroneous power cycle or a "hiccup" mode that stresses the power converter and its load, thus sacrificing circuit integrity and potentially reduce its useful life. Furthermore, conventional systems set a threshold value of 130% or more of the nominal operating voltage before the overvoltage protection loop is engaged to provide the output voltage. A high voltage threshold is necessary to prevent false triggering of the overvoltage protection loop, but it also causes stress on the converter and load circuit by applying an excessively high voltage and can damage the converter and the load circuit. Accordingly, these conventional methods for providing overvoltage protection result in an output voltage that is not used by the load or that, if used, could result in damage to the converter or the load.

An overvoltage protection loop for a transformer, the transformer including a main clock and feedback control circuit, a main servo loop and an overvoltage protection loop, can be summarized as including: an overvoltage winding magnetically coupled to a magnetic core, the overvoltage winding activated in response to a current on a primary winding in the primary clock and feedback control circuit to provide a secondary side voltage supply; an error amplifier electrically coupled to a first node and a second node, wherein the error amplifier maintains a second voltage on the second node using the secondary side voltage supply according to an internal reference voltage; a feedback impedance electrically coupled to the first node and the first node Two nodes, the feedback impedance introduces a time delay to provide feedback from the first node to the second node; and an output voltage sensing circuit electrically coupled to at least the second node and an output node, the output voltage The sensing circuit controls an output voltage at the output node based on the second voltage, wherein the overvoltage protection loop provides an output voltage to the transformer under an error condition. The feedback impedance may cause the overvoltage protection loop to delay providing the output voltage to the transformer for a period of time. this period of time Can output a voltage transient longer than the main servo loop. The output voltage provided by the overvoltage protection loop may be within 5% of a nominal voltage of the servo loop output. The voltage control assembly may include a shunt regulator. The output voltage sensing circuit may include a first resistor and a second resistor, the first resistor having a first resistance and coupled to the second node and the output node, and the second resistor having a second A resistance is coupled to the second node and ground, wherein the first resistance and the second resistance can be based at least in part on the error amplifier maintaining the voltage of the second node at a value thereon. The error amplifier may include an operational amplifier. The feedback impedance may include a capacitor. The magnetic core can be magnetically coupled to the main servo loop. The magnetic core can be magnetically coupled to a first magnetic core of the overvoltage protection loop and the main clock and feedback control circuit, and wherein the main servo loop can be magnetically coupled to a second magnetic core.

100: Power Converter

102: Main clock and feedback controls

102a: First main clock and feedback control

102b: Second main clock and feedback control

104: Magnetic core

104a: first magnetic core

104b: second magnetic core

106: Main Servo Loop

108: Overvoltage protection loop

110: The first main winding

112: The first secondary winding

114: Second secondary winding

200: Power Converter

210: Second main winding

301: Secondary Magnetic Communicator

302: Overvoltage Protection Error Amplifier

303: Feedback Impedance

305: Voltage Reference

307: Reference Line

308: Output voltage sensing circuit

320: Primary Magnetic Communicator

322: Main clock and feedback controls

340: Primary Secondary Magnetic Communicator

342: Primary Error Amplifier

344: Primary Feedback

346: Primary Voltage Reference

348: Main output circuit

501: Voltage Reference

503: Line

505: Feedback Connection

601: Operational Amplifier

607: Voltage Reference

701: Signal V _out

703: Signal V _in

705: First time period

707: Point

709: Remaining time period

801: Signal V _out

803: First time period

805: point

807: Second time period

809: point

811: Remaining time period

901: Signal V _out

903: The first time period

905: The first point

907: Second time period

909: point

911: Remaining time period

1001: Signal V _In

1003: Signal V _out

1005: First time period

1007: point

1009: Delay Phase

1011: Remaining time period

1101: Signal I _out

1103: Signal V _out

1105: Line/3.45 Volt Threshold

1107: point

1109: Voltage Transient

1201: Signal I _out

1203: Signal V _out

A: Node

B: Node

C:node

C1: Capacitor

C2: Capacitor

C3: Capacitor

C4: Capacitor

C5: Capacitor

D: node

D1: Diode

D2: Diode

D3: Diode

D4: Diode

D5: Diode

D6: Diode

D7: Diode

D8: Diode

D11: Diode

E: node

F: Node

FBP: sampling switch control node

G: node

H: node

J: Node

L1: Primary side winding

L2: Primary side winding

L3: Secondary side winding

L4: Overvoltage winding

M1: switch

R1: Resistor

R2: Resistor

R3: Resistor

R4: Resistor

R5: Resistor

R6: Resistor

R7: Resistor

R8: Resistor

V _CCP : Primary side voltage

V _CCS1 : Main servo supply voltage

V _CCS2 : Secondary side voltage supply

V _EA : output voltage/error signal

V _EA1 : output signal/output voltage

V _EA2 : Voltage

V _FB : flyback voltage/primary side feedback signal

V _out : Overvoltage output signal/output voltage

V _REF1 : reference voltage

U1: Integrated Circuit

U2: Operational Amplifier

In the drawings, the same reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not drawn to scale, and portions of these elements may be arbitrarily enlarged and positioned to improve drawing legibility. Furthermore, the particular shapes of elements as drawn are not necessarily intended to convey any information about the actual shape of those particular elements, and may be selected separately for ease of identification in the drawings.

1 is a block diagram illustrating components for voltage control of a power converter, according to at least one illustrated implementation.

2 is a block diagram illustrating components for voltage control of a power converter using two magnetic cores, according to at least one illustrated implementation.

3 is a block diagram illustrating components for voltage control of a magnetic feedback isolator, a magnetic core, a main servo loop, and an overvoltage protection loop, according to one illustrated implementation.

4 is a block diagram illustrating components for voltage control of an overvoltage protection loop, according to one illustrated embodiment.

5 is a low-level circuit diagram of a magnetic coupling to a bidirectional magnetic feedback isolator using an overvoltage protection loop of a shunt regulator, according to one illustrated embodiment.

6 is a low-level circuit diagram of a protected overvoltage servo loop using an operational amplifier to provide an output voltage, according to one illustrated implementation.

7 is a representation of an output voltage node of a power converter with an operational overvoltage protection loop at an output voltage node where the output voltage of the main servo loop is trimmed to exceed the operational overvoltage protection, according to one illustrated implementation A graph of a voltage signal during a time period of the threshold voltage at which the loop is spliced.

8 is a diagram showing an output voltage node of a power converter with an operating overvoltage protection loop during a period of time in which feedback control of the main servo loop is abruptly turned off, according to one illustrated implementation A graph of a voltage signal.

9 is a representation of an output voltage node of a power converter with an operating overvoltage protection loop at an output voltage node where the output voltage of the main servo loop has been interrupted causing a temporary dip and then, according to one illustrated implementation A plot of a voltage signal during a time period that causes a large increase in the output voltage of the main servo loop.

10 is a representation of an output voltage node of a power converter with an operating overvoltage protection loop at an output voltage node where the main servo loop is disabled before the converter starts up, allowing overvoltage, according to one illustrated implementation A graph of a voltage signal during a period of time that the protection loop controls the output voltage after startup.

11 is a graph showing the voltage signal at an output voltage node of a power converter with an operating overvoltage protection loop, according to one illustrated implementation, where when The power converter does not engage the overvoltage protection loop when the output voltage exceeds a threshold voltage due to voltage transients induced by load current steps.

12 is a representation of an output voltage node of a power converter with an operating overvoltage protection loop in which the output voltage of the main servo loop is trimmed to exceed a threshold voltage or to run out of control, according to one illustrated implementation A graph during a time period resulting in an output voltage runaway where the operating overvoltage protection loop has a threshold voltage set to within 5% of the nominal output voltage of the main servo loop.

In the following description, certain specific details are set forth in order to provide a thorough understanding of one of the various disclosed embodiments or implementations. Those skilled in the relevant art will recognize, however, that an embodiment or implementation may be practiced without one or more of these specific details or with other methods, components, materials, etc. . In other instances, well-known structures associated with the various embodiments or implementations have not been shown or described in detail to avoid unnecessarily obstructing the description of the embodiments or implementations.

Unless otherwise required herein, throughout the following specification and claims, the words "comprising" and "comprising" are synonymous and inclusive or open ended (ie, not excluding otherwise undescribed elements or method acts).

Reference in this specification to "one embodiment," "an embodiment," "one implementation," or "an implementation" means that a particular feature, structure, or characteristic described in connection with the example or implementation is included in at least one implementation examples or embodiments. Thus, appearances of the terms "in one embodiment," "in an embodiment," "one embodiment," or "an embodiment" in various places in this specification are not necessarily all referring to the same embodiment or embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments or implementations.

As used in this specification and the appended claims, the singular forms "a" (a, an) and "the" include plural referents unless the context clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its broadest sense, ie, meaning "and/or", unless the context clearly dictates otherwise.

The titles and abstracts of the invention provided herein are for convenience only and do not interpret the scope or meaning of the examples or implementations.

One or more embodiments of the present invention provide overvoltage protection for a servo loop operating with feedback control as part of a power converter. Overvoltage protection is provided by engaging an overvoltage protection loop when an output voltage of one of the servo loops exceeds a threshold voltage, such as may occur, for example, when feedback control fails. In some implementations, the threshold voltage and output voltage of the overvoltage protection loop may be the same. The threshold voltage and output voltage of the overvoltage protection loop can be controlled by a voltage controller that maintains a highly accurate voltage difference between two nodes in the overvoltage protection loop. Such a voltage controller may include, for example, a shunt regulator (eg, resistors, capacitors, inductors, as described below) implemented using an integrated circuit or optionally implemented using an operational amplifier and associated circuit components discuss). In some implementations, the output voltage of the overvoltage protection loop is based on a highly accurate voltage maintained by a voltage control structure at a particular node; in addition, by using a suitable configuration of resistors or other resistive elements Change the output voltage and/or threshold voltage of the overvoltage protection loop.

In some implementations, the start-up of the overvoltage protection loop can be delayed by introducing an impedance into the feedback component of the voltage controller structure of the overvoltage protection loop. The feedback impedance can be provided, for example, by various combinations of resistors and/or capacitors. The value and configuration of the components that provide the feedback impedance can be based, at least in part, on the amount of delay required by the servo loop. The amount of delay can, for example, be based on a value that can be expected to provide output power to the power converter under normal operation. A characteristic of the voltage transient at the output of the main servo loop. In this case, the delay can be set for a sufficient period of time so that even when the voltage output of the main servo loop experiences a voltage transient that temporarily exceeds the voltage threshold for engaging the overvoltage protection loop, the power conversion The controller can continue to use this voltage output. In some embodiments, this delay period can be up to 400 μs.

The voltage control structure and feedback impedance allow the threshold value of the overvoltage protection loop to be set to within 105% of the nominal output voltage of the main servo loop. Unlike conventional overvoltage protection loops, the overvoltage protection loop described herein includes a voltage control structure that outputs a highly stable and accurate voltage and allows current overvoltage protection loops to advantageously provide an operating output voltage to load without sacrificing the integrity or durability of the load. Additionally, the overvoltage protection loop described herein includes a feedback impedance that delays engagement of the overvoltage protection loop by the power converter for a period of time after the output voltage of the servo loop exceeds a threshold voltage. The feedback impedance prevents the overvoltage protection loop from being engaged due to voltage transients with peaks that temporarily exceed the threshold voltage. Accordingly, this feedback impedance prevents the overvoltage protection loop from tripping erroneously due to voltage transients, thus allowing the overvoltage protection loop threshold to be set close to the nominal output voltage (eg, within 5%) one value. Ultimately, as will be discussed herein, the operation of the overvoltage protection loop can be implemented using the same magnetic core that is also coupled to the servo loop, thus minimizing the footprint and cost for implementing the overvoltage protection loop.

1 is a block diagram illustrating components of a power converter 100 according to at least one illustrated implementation. In some implementations, the power converter 100 includes a main clock and feedback control 102 , a magnetic core 104 , a main servo loop 106 , and an overvoltage protection loop 108 . Magnetic core 104 provides magnetic coupling between primary clock and feedback control 102 and primary servo loop 106 using first primary winding 110 and first secondary winding 112 . The magnetic core 104 also provides the primary clock and the use of the first primary winding between the feedback control 102 and the overvoltage protection loop 108 . Magnetic coupling of group 110 and second secondary winding 114 . Using magnetic core 104 to magnetically couple main servo loop 106 and overvoltage protection loop 108 allows overvoltage protection loop 108 to occupy a smaller footprint within power converter 100 by not having to provide an additional magnetic core.

The main clock and feedback control 102 includes a main side voltage that can be applied to the magnetic core 104 using one or more main windings 110 and causes a magnetizing energy to build up in the magnetic core 104, as discussed below. The magnetizing energy in the magnetic core 104 results in the use of one or more secondary windings 112 and 114 in the primary servo loop 106 and the overvoltage protection loop 108, respectively, to deliver the primary side voltage. The delivered voltage provides the secondary side voltage supply for the primary servo loop 106 and the overvoltage protection loop 108 . Under normal operating conditions, the primary servo loop 106 provides feedback to the power converter. The output power has a nominal voltage that can be used to drive a load. However, during an error condition, such as, for example, when the feedback control of the primary servo loop 106 has failed, the output voltage provided by the primary servo loop 106 may increase uncontrollably. In this case, the power converter 100 may engage the overvoltage protection loop 108 to provide the output voltage to the load. As described herein, the voltage provided by the overvoltage protection loop 108 may be within 5% of the nominal voltage supplied by the main servo loop 106 during normal operation.

FIG. 2 is a block diagram illustrating components of a power converter using two magnetic cores, according to at least one illustrated implementation. In this implementation, a power converter 200 has a first primary clock and feedback control 102a and a second primary clock and feedback control 102b. The first primary clock and feedback control 102a is magnetically coupled to the primary servo loop 106 via a first magnetic core 104a using the first primary winding 110 and the first secondary winding 112. The second primary clock and feedback control 102b is magnetically coupled to the overvoltage protection loop 108 via a second magnetic core 104b using the second primary winding 210 and the second secondary winding 114 . In this implementation, the outputs of the first primary clock and feedback control 102a and the second primary clock and feedback control 102b may be the same of. Alternatively, the outputs of the first primary clock and feedback control 102a and the second primary clock and feedback control 102b may be different. Additionally, the main servo loop 106 and the overvoltage protection loop 108 in the power converter 200 may operate in the same manner as the main servo loop 106 and the overvoltage protection loop 108 in the power converter 100, respectively.

3 is a block diagram illustrating components of a primary clock and feedback control 102, a magnetic core 104, a primary servo loop 106, and an overvoltage protection loop 108, according to one illustrated implementation. The main clock and feedback control 102 includes a main magnetic communicator 320 and a main clock and feedback control 322 . A primary side voltage V _{CCP is} supplied to primary magnetic communicator 320 to power magnetic core 104 . This voltage is communicated to the primary servo loop 106 and the overvoltage protection loop 108 using one or more secondary magnetic communicators 301 and 340, as discussed below. The main side voltage V _CCP is not continuously supplied to the main magnetic communicator 320 . Instead, one of the main clock and feedback controls 322 controls the _{supply of the main side voltage V CCP} to the main magnetic communicator 320 , such as through a switching element. The period of time when the primary side voltage V _{CCP is not being} supplied to the primary magnetic communicator 320 may be referred to as the time period in which the voltage that has been delivered to the primary servo loop 106 or the overvoltage protection loop 108 is returned to the primary clock via the secondary winding and The feedback control 102 acts as one of the "flyback phases" of a flyback voltage. Primary clock and feedback control 322 can use this flyback voltage (eg, V _FB ) to monitor and provide feedback on the output voltage provided by primary servo loop 106 and/or overvoltage protection loop 108 .

The primary servo loop 106 includes a primary secondary magnetic communicator 340 , a primary error amplifier 342 , a primary feedback 344 and a primary voltage reference 346 . The primary secondary magnetic communicator 340 is magnetically coupled to the magnetic core 104 through one or more secondary windings (eg, the first secondary winding 112). Accordingly, when the primary side voltage _{VCCP is} supplied to the primary magnetic communicator 320 in the primary clock and feedback control 102, the primary side voltage _{VCCP is} delivered to one of the windings in the primary secondary magnetic communicator 340 (eg, , the first secondary winding 112) serves as a main servo supply voltage V _CCS1 . Additionally, the primary secondary magnetic communicator 340 may _{provide a voltage during the flyback phase in which the primary supply side voltage V CCP is not} supplied to the primary magnetic communicator 320 . During this flyback phase, primary secondary magnetic communicator 340 receives an output voltage (eg, V _EA ) from primary error amplifier 342 and provides this voltage to primary magnetic communicator 320 as primary magnetic communicator 320 supplies the primary clock and the main clock in the feedback control 102 and the flyback voltage (V _FB ) of the feedback control 322 .

Primary secondary magnetic communicator 340 provides primary servo supply voltage V _CCS1 to primary voltage reference 346 . The main voltage reference 346 is also electrically connected to the main error amplifier 342 and supplies a reference voltage (V _Ref ) to the main error amplifier 342 . The output of main error amplifier 342 is connected to main feedback 344 and returned to main error amplifier 342 as a feedback signal. The feedback signal is also provided to the main output circuit 348 which _{provides the output voltage V out} to the main servo loop 106 . The main error amplifier 342 provides its output voltage V _EA based on the difference between the feedback signal and the reference voltage V _Ref received from the main voltage reference 346 .

The overvoltage protection loop 108 includes an overvoltage secondary magnetic communicator 301 , an overvoltage protection error amplifier 302 , a feedback impedance 303 , a voltage reference 305 and an output voltage sensing circuit 308 . Magnetic communicator 301 is magnetically coupled to magnetic core 104 . The magnetic core 104 is then magnetically coupled to the main clock and feedback control 102 . Accordingly, when the primary side voltage V _{CCP is} supplied to the primary magnetic communicator 320 in the primary clock and feedback control 102, the primary side voltage V _{CCP is} delivered to one of the windings in the overvoltage secondary magnetic communicator 301 ( For example, the second secondary winding 114) supplies V _CCS2 as the primary side voltage. Additionally, the overvoltage secondary magnetic communicator 301 may provide a voltage to the overvoltage protection loop 108 during a flyback phase _{in which the primary supply side voltage V CCP is not supplied to the primary magnetic communicator 320 .} During the flyback phase, the overvoltage secondary magnetic communicator 301 may provide a voltage V _{EA2 with respect to a primary side feedback signal V FB} supplied to the feedback control 322 in the primary clock and feedback control 102 .

Overvoltage secondary magnetic communicator 301 provides reference voltage V _CCS2 to voltage reference 305 which is also electrically connected to overvoltage protection amplifier 302 . In some implementations, the overvoltage protection amplifier 302 may be a _{shunt regulator that controls the voltage and resulting current at its output to maintain a regulated voltage Vref} on a reference line 307, as discussed in further detail below. Feedback impedance 303 provides a connection that allows a feedback signal to pass from the output of overvoltage protected error amplifier 302 to the input of the same error amplifier 302 . However, feedback impedance 303 includes components such as capacitors and/or resistors that introduce a transfer delay of the feedback signal. This propagation delay prevents the overvoltage protection loop 108 from tripping erroneously during a dynamic response time or phase of the main servo loop 106 outputting a voltage transient. The feedback signal is also provided to the output voltage sensing circuit 308 to provide the overvoltage output signal V _out .

4 is a low-level circuit diagram of a main clock and feedback control 102 magnetically coupled to a main servo loop 106 via a magnetic core 104, according to one illustrated implementation. Magnetic core 104 has primary side windings L1 and L2 associated with primary clock and feedback control 102 and a secondary side winding L3 associated with primary servo loop 106 . Winding L1 is located between nodes A and B, winding L2 is located between nodes C and D and winding L3 is located between nodes E and F. The turns ratio of windings L1 , L2 and L3 can be any turns ratio suitable for a particular application, such as 1:1:1, 1:1:2, etc. A fixed frequency pulse signal may be provided at a sampling switch control node FBP coupled to a gate node of a switch M1. Switch M1 can be any type of suitable switch (eg, MOSFET, insulated gate bipolar transistor (IGBT)).

When switch M1 is turned on, winding L1 is coupled to a primary side voltage supply V _CCP . This causes a magnetization energy to build up in the magnetic core 104 . At this time, the voltage across nodes C and D of winding L2 is negative at the anode of a diode D11, making diode D11 non-conductive. When switch M1 is turned on, voltage V _CCP passes from A to B to E to F, which is then peak charged by diodes D5 and D7 into capacitor C3 to supply secondary side supply voltage V _CCS1 . During normal operation, the secondary side supply voltage V _CCS1 may have a nominal value.

An operational amplifier U2 can be powered using the secondary side supply voltage V _{CCS1 .} The operational amplifier U2 has a positive input and a negative input, and provides an output signal V _EA1 . The output signal V _EA1 is fed back through resistor R8 and capacitor C5 to the negative input of operational amplifier U2 and received as a feedback voltage. The operational amplifier U2 receives a reference voltage _Vref1 on its positive input. Therefore, the output signal V _EA1 is the difference between the feedback voltage and the reference voltage. _{In this configuration, the operational amplifier U2 seeks to provide an output voltage V EA1} that maintains the value of the feedback voltage as close as possible to the value of the _{reference voltage V ref1} . _{The output voltage V out} is provided from this feedback voltage. Certain words, output voltage V _out based on the following equation based on the relationship of the resistors R5 and _{R7: V out = [(R5 +} R7) / R5] * V ref1

When the switch M1 is turned off, the magnetizing energy stored in the magnetic core 104 is returned in the form of a flyback voltage. The voltage is clamped by an error signal V _EA via diodes D6 and D8. _{During this flyback time, the error signal V EA is} fed back into the primary side of the core 104 by the voltage reflected across nodes C and D and then peaked into capacitor C4 by diode D11 to form the primary side feedback signal _VFB . A resistor R6 may be provided to control the discharge rate of capacitor C4.

5 is a low-level circuit diagram of the main clock and feedback controls 102 magnetically coupled to an overvoltage protection loop 108 via the magnetic core 104, according to one illustrated implementation. Magnetic core 104 has primary side windings L1 and L2 associated with primary clock and feedback control 102 and an overvoltage winding L4 associated with overvoltage protection loop 108 . Winding L1 is located between nodes A and B, winding L2 is located between nodes C and D, and overvoltage winding L4 is located between nodes G and H. The turns ratio of windings L1 , L2 and L4 can be any turns ratio suitable for a particular application, such as 1:1:1, 1:1:2, and so on. A fixed frequency pulse signal may be provided at a sampling switch control node FBP coupled to a gate node of a switch M1. Switch M1 can be any type of suitable switch (eg, MOSFET, IGBT).

When switch M1 is turned on, winding L1 of magnetic core 104 is coupled to a primary side voltage supply V _CCP . This causes a magnetization energy to build up in the magnetic core 104 . At this time, the voltage across nodes C and D of winding L2 is negative at the anode of a diode D11, making diode D11 non-conductive. When switch M1 is turned on, voltage V _CCP passes from A to B to G to H, which is then peak charged by diodes D2 and D3 into capacitor C2 to provide secondary side supply voltage V _CCS2 . In which the number of windings L4, L3 is equal to the number of windings in the embodiment, may be approximately equal to the voltage V _CCS2 voltage V _CCS1.

In the overvoltage protection loop 108, a shunt regulator is formed by an integrated circuit U1, resistors R2 and R3, and a capacitor C1. A cathode of the shunt regulator is connected to node I. Integrated circuit U1 is shown in FIG. 5 as having a voltage reference 501 _{supplied by line 503 with an external reference voltage V ref .} The integrated circuit U1 also includes an internal voltage supply that maintains an internal reference voltage. The integrated circuit U1 controls the current flow from node I into its cathode so that the external reference voltage _Vref on the reference line 503 matches the internal reference voltage provided by the internal voltage supply. In some implementations, the internal reference voltage that can be used to form a shunt regulator, such as provided by integrated circuits in the TL431 family of devices, is 2.5 volts. A feedback connection 505 provides an electrical connection between node I at the cathode of IC UI and node J at reference line 503 for IC U1. Feedback connection 505 allows the condition at node I to be fed back to integrated circuit U1 via reference line 503 . However, when capacitor C1 charges, capacitor C1 delays the transfer of feedback from node I to node J. The amount of delay experienced by the feedback connection 505 depends on the characteristics of capacitor C1 (eg, capacitance, size and configuration of the conductive plates, etc.).

A pull-up voltage for node I and bias current for integrated circuit U1 is provided via resistor R4 placed between secondary side voltage supply V _{CCS2 and the cathode of U1.} The current and voltage provided at node I should be sufficient to start the integrated circuit U1 as a shunt regulator. In some implementations, the voltage at node I required to activate the integrated circuit U1 as a shunt regulator may be based at least in part on the node _{maintained at an external reference voltage Vref that matches the internal reference voltage within the integrated circuit U1} J. Accordingly, the resistance of resistor R4 can be based on the expected secondary-side supply voltage V _{CCS2 ,} and the voltage and current demands on IC U1 .

Resistor R2 and resistor R3 enable the output voltage V _{o to be adjusted based on the value of V ref} . The output voltage V _{o is related to the reference voltage V ref} on the reference line 503 by the following equation: V _out =[(R1+R2)/R1]*V _ref2 Equation 2

In some implementations, _{the value of Vref} is set to 2.5 volts. Accordingly, the values of R1 and R2 can be modified according to Equation 1 to provide the desired output voltage V _o for the overvoltage protection loop 108 . Furthermore, since the shunt regulator can precisely control _Vref to maintain it within a narrow range of voltage values (eg, within 0.5% to 2% of the set voltage value), the shunt regulator can be equally accurate Ground controls the output voltage V _o to maintain it within a narrow range of voltages.

When the switch M1 is turned off, the magnetizing energy stored in the magnetic core 104 is returned to the secondary side of the magnetic core 104 by the voltage reflected across nodes G and H. Diode D1 and diode D4 direct this voltage to node I to obtain a _{voltage V EA2 with respect to} the voltage of _{the primary clock and primary side feedback signal V FB} in feedback control 102 . In some implementations, the voltage V _EA2 at node I is sufficient to engage the integrated circuit U1 and associated components as a shunt regulator during the flyback time. Accordingly, as discussed above, the voltage V _EA2 should be sufficient to maintain node J at _{an external reference voltage V ref that} matches the internal reference voltages within the integrated circuit U1 . In this case, as discussed above, Equation 1 can be modified according to R1 and R2 to provide 108 during the flyback phase of an overvoltage protection desired loop output voltage V _o.

6 is a low-level circuit diagram of an overvoltage protection loop using an operational amplifier 601 to provide an output voltage, according to one illustrated implementation. An operational amplifier 601 and a voltage reference 607 replace the integrated circuit U1 shown in FIG. 5 . Operational amplifier 601 receives the _Vref signal from reference line 503 and compares _Vref to a reference voltage provided by voltage reference 607 . In the negative feedback configuration shown in FIG. 6, the operational amplifier 601 will maintain its output at node I so that the feedback signal on line 503 is as close to the reference voltage _Vref as possible. In some implementations, for example, the voltage reference 607 can output a reference voltage of about 2.5 volts. In such an implementation, op amp 601 will attempt to maintain the voltage at node I such that the voltage provided by the feedback signal on line 503 is as close as possible to the 2.5 volts provided by voltage reference 607. _{In this case, the value of V out} can be determined based on the values of R1 and R2 according to Equation 2 above. Accordingly, in this embodiment, operational amplifier 601 may be used, and precisely the resistor values V _out of R1 and R2 is maintained within a narrow range of one of the voltage (e.g., V _out at a nominal value of 2.0 to 0.5% %Inside).

The remaining components in FIG. 6 function in the same manner as the similar components in FIG. 5 . Accordingly, resistor R4 provides a pull-up voltage from node H to V _CCS2 to provide the necessary voltage for operational amplifier 601 . Additionally, resistor R3 and capacitor C1 provide a feedback delay to provide the voltage _Vref signal on reference line 503, as previously discussed.

7 shows an output node of a power converter with an overvoltage protection loop 108 at an output node where the output voltage of the main servo loop 106 is trimmed to exceed that for engaging overvoltage protection, according to one illustrated implementation A graph of a voltage signal during a time period of the threshold voltage of the loop 108 . A signal V _out 701 represents a time-varying voltage at an output node of the power converter, and a signal V _in 703 represents a step signal input into the power converter. The output voltage of the main servo loop is set to 4.0 volts and the threshold or set point for engaging the overvoltage protection loop 108 is set to 3.8 volts. As seen in FIG. 7, during a first time period 705, the power of the _{signal V out 701 is provided by the output of the main servo loop 106.} During this phase, the output voltage of the main servo loop 106 is less than the 3.8 voltage threshold for engaging the overvoltage protection loop 108 . However, at point 707 the output voltage of the main servo loop 106 exceeds the 3.8 voltage threshold, at which point the power converter supplies the power of _{V out 701 from the overvoltage protection loop 108 . Power for V out} 701 continues to come from overvoltage protection loop 108 for the remainder of time period 709 shown in the graph of FIG. 7 .

8 shows an output node of a power converter with an operating overvoltage protection loop 108 engaged during a time in which the feedback control of the main servo loop 106 is disconnected, according to one illustrated implementation One of the voltage signals is one of the graphs. A signal V _out 801 represents a time-varying voltage at an output voltage node of a power converter. The output voltage of the main servo loop 106 is initially set to 3.3 volts, and the threshold or set point of the overvoltage protection loop 108 is set to 3.8 volts. During a first time period 803, the power of the _{signal V out 801 is provided by the main servo loop 106 .} At point 805 , however, the feedback control of the main servo loop 106 is disconnected, causing the voltage output of the main servo loop 106 to rapidly increase over 3.8 volts during a second time period 807 . During this time period, the feedback impedance in the overvoltage protection loop 108 delays the engagement of the overvoltage protection loop 108 . However, at point 809, the power converter 108 from over-voltage protection loop power supply V _out 801, the over-voltage protection from the continued power supply V _out 801 loops 108 of the remaining 811 in the period.

9 is a diagram showing a voltage signal at an output voltage node of a power converter with an operating overvoltage protection loop 108 when the output voltage of the main servo loop 106 has been disabled, according to one illustrated implementation One of the pictures. A signal V _out 901 represents a time-varying voltage at an output voltage node of a power converter. The output voltage of the main servo loop 106 is initially set to 3.3 volts, and the threshold or set point of the overvoltage protection loop 108 is set to 3.8 volts. During a first time period 903, the main servo loop 106 functions normally and provides an output voltage of 3.3 volts. At a first point 905, the main servo loop 106 breaks, first causing one of the voltages to momentarily drop to less than 1.0 volts. During a second time period 907 , the output voltage of the main servo loop 106 increases until it finally reaches and then exceeds the 3.8 voltage threshold for engaging the overvoltage protection loop 108 . During this phase, the output voltage of the main servo loop 106 continues to increase beyond 4.5 volts. At point 909 , the power converter engages the overvoltage protection loop 108 to provide _{the power of the signal V out} 901 , at which point the signal V _out 901 drops rapidly to the 3.8 volt output provided by the overvoltage protection loop 108 . During the remaining time period 911, _{the power of the signal V out} 901 continues to be provided by the overvoltage protection loop 108 .

FIG. 10 shows an output node of a power converter with an operating overvoltage protection loop 108 at an output node where the main servo loop 106 is disabled prior to power converter startup so that the The voltage protection loop 108 is engaged to provide a map of a voltage signal during a time period of the output voltage immediately after startup. Signal V _In 1001 represents an input step signal of the power converter, and signal V _out 1003 represents the output signal of the power converter. Signal V _In 1001 is turned off during first time period 1005 and turned on at point 1007 . Since the main servo loop 106 is disabled, the output voltage increases uncontrollably until it reaches the set point of the overvoltage protection loop. At this point, the power of the _{signal V out} 1003 is provided by the overvoltage protection loop 108 after a delay period 1009 . However, the overvoltage protection loop 108 may have a faster startup time than that of the main servo loop 106 to minimize the delay stage 1009 . This fast start-up time enables the overvoltage protection loop 108 to be protected from overvoltage failures that can occur even before and during operation. The overvoltage protection loop 108 continues to provide the power of the _{signal V out 1003 for the remaining time period 1011 .}

FIG. 11 shows an output node of a power converter with an operating overvoltage protection loop 108 having a threshold voltage in which the overvoltage protection loop 108 is even in main servo, according to one illustrated implementation. A graph of a voltage signal during a period of time during which the output voltage of the loop 106 does not interfere with the output voltage of the main servo loop 106 due to voltage transients that exceed a threshold voltage during a dynamic response time or phase. Signal I _out 1101 represents the output load current of the power converter during a load transient from 0Amp to 15Amp and back to 0Amp. Signal V _out 1103 represents the voltage signal output from the power converter. _{The output signal V out} 1103 of the power converter is provided by the voltage output of the main servo loop 106 during the entire time period shown in FIG. 11 . The nominal voltage of the main servo loop 106 and therefore the nominal voltage of V _out 1103 is set to 3.3 volts. Line 1105 represents the set point or threshold of 3.45 volts for overvoltage protection loop 108 . At point 1107, the output load current _Iout 1101 transitions from 0Amp to 15Amp. This transition causes a voltage transient 1109 to occur in the output signal of the main servo loop 106, where the output voltage of the main servo loop 106 temporarily exceeds the 3.45 volt threshold of the overvoltage protection loop 108 during a dynamic response time or phase The value is 1105. As seen in Figure 11, the voltage transient 1109 exceeds the 3.45 volt threshold 1105 for approximately 400 [mu]s. Due to the delay provided by the feedback impedance in the overvoltage protection loop 108, the power converter does not engage the overvoltage protection loop 108 to provide the output voltage signal _V1203 .

12 shows one of the power converters having an operating overvoltage protection loop 108 having a threshold voltage set to within 5% of the nominal output voltage of the main servo loop, according to one illustrated implementation The output node is a graph of a voltage signal at a time where the output voltage of the main servo loop 106 is trimmed to exceed the threshold voltage. Signal I _out 1201 represents a square wave output load current of _{the power converter, and signal V out} 1203 represents the voltage signal output from the power converter. The nominal voltage of the signal output by the main servo loop 106 has been trimmed to 4.0 volts, and the set point or threshold for engaging the overvoltage protection loop 108 has been set to 3.45 volts. _{Accordingly, the output signal V out} 1203 of the power converter is provided by the voltage output of the overvoltage protection loop 108 during the entire time period shown in FIG. 12 .

The foregoing detailed description has set forth various implementations of devices and/or processes using block diagrams, schematic diagrams, and examples. So long as these block diagrams, schematic diagrams and examples include one or more functions and/or operations, those skilled in the art will understand that each function and/or operation within such block diagrams, flow diagrams or examples can be implemented by a wide variety of hardware, software, The firmware, or indeed any combination thereof, is implemented individually and/or together.

Skilled artisans will appreciate that many of the methods or algorithms set forth herein may employ additional actions, may omit some actions, and/or may perform the actions in one of the orders specified.

The various implementations described above can be combined to provide further implementations. The various embodiments described above can be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications (if any) referenced in this specification and/or listed in the Application Fact Sheet include But not limited to: U.S. Patent No. 8,710,820, entitled "SWITCHED CAPACITOR HOLD-UP SCHEME FOR CONSTANT BOOST OUTPUT VOLTAGE," issued on April 29, 2014; "AC/DC" issued on August 16, 2016 POWER CONVERSION SYSTEM AND METHOD OF MANUFACTURE OF SAME," U.S. Patent No. 9,419,538; filed on July 18, 2011, entitled "POWER CONVERTER APPARATUS AND METHOD WITH U.S. Patent Application Serial No. 13/185,142 for COMPENSATION FOR LIGHT LOAD CONDITIONS; U.S. Patent No. 8,885,308, issued November 11, 2014, entitled "INPUT CONTROL APPARATUS AND METHOD WITH INRUSH CURRENT, UNDER AND OVER VOLTAGE HANDLING,"; issued September 9, 2014, entitled "POWER CONVERTER APPARATUS AND METHOD WITH OUTPUT CURRENT SENSING AND COMPENSATION FOR CURRENT LIMIT/CURRENT SHARE OPERATION," US Patent No. 8,829,868; No. 8,890,630; U.S. Provisional Patent Application No. 61 entitled "OUTPUT FILTER FOR USE WITH POWER CONVERTERS, FOR EXAMPLE DC/DC POWER CONVERTERS, FOR INSTANCE INTERPOINT MFP POL DC/DC POWER CONVERTERS," filed October 14, 2011 /547,327; US Patent No. 8,866,551, filed October 21, 2014, entitled "IMPEDANCE COMPENSATION FOR OPERATIONAL AMPLIFIERS USED IN VARIABLE ENVIRONMENTS,"; issued May 26, 2015, entitled "DYNAMIC MANEUVERING CONFIGURATION FOR MULTIPLE CONTROL" MODES IN A UNIFIED SERVO SYSTEM," U.S. Patent No. 9,041,378 ;The name of the application filed on October 28, 2015 is "DYNAMIC" MANEUVERING CONFIGURATION FOR MULTIPLE CONTROL MODES IN A UNIFIED SERVO SYSTEM," U.S. Patent Application No. 14/787,565; U.S. Patent entitled "TRANSFORMER-BASED POWER CONVERTERS WITH 3D PRINTED MICROCHANNEL HEAT SINK," issued January 5, 2016 No. 9,230,726; U.S. Patent No. 9,160,228, issued October 13, 2015, entitled "INTEGRATED TRI-STATE ELECTROMAGNETIC INTERFERENCE FILTER AND LINE CONDITIONING MODULE,"; issued March 22, 2016, entitled "AUTOMATIC ENHANCED SELF- DRIVEN SYNCHRONOUS RECTIFICATION FOR POWER CONVERTERS," U.S. Patent No. 9,293,999; U.S. Patent Application "DYNAMIC SHARING AVERAGE CURRENT MODE CONTROL FOR ACTIVE-RESET AND SELF-DRIVEN SYNCHRONOUS RECTIFICATION FOR POWER CONVERTERS," filed June 10, 2016 Application No. 15/178,968, the full text of which is hereby incorporated by reference. If possible, aspects of the embodiments may be modified to employ concepts from various patents, applications, and publications to provide further embodiments. These and other changes can be made to the implementations in light of the above detailed description.

In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments and such etc. the full scope of equivalents granted by the scope of the patent application. Accordingly, the present disclosure does not limit the scope of these claims.

100: Power Converter

102: Main clock and feedback controls

104: Magnetic core

106: Main Servo Loop

108: Overvoltage protection loop

110: The first main winding

112: The first secondary winding

114: Second secondary winding

Claims (11)

An overvoltage protection loop for a transformer, the transformer comprising a main clock and feedback control circuit, a main servo loop, and the overvoltage protection loop, the overvoltage protection loop comprising: an overvoltage winding , which is magnetically coupled to a magnetic core, and the overvoltage winding is activated in response to a voltage on a primary winding in the primary clock and feedback control circuit to provide a primary-side voltage supply; an error amplifier, which electrically coupled to a first node and a second node, wherein the error amplifier uses the secondary side voltage supply to maintain a second voltage on the second node according to an internal reference voltage; a feedback impedance at The first node and the second node are electrically coupled, the feedback impedance introduces a time delay to provide feedback from the first node to the second node; and an output voltage sensing circuit is electrically coupled to at least the second node and an output node, the output voltage sensing circuit controls an output voltage at the output node based on the second voltage at the second node, wherein the overvoltage protection loop is in an error condition down, supply the output voltage to the transformer. The overvoltage protection loop of claim 1, wherein the feedback impedance prevents the overvoltage protection loop from interfering with an output of the main servo loop for a period of time that is longer than when the main servo loop output an output One of the voltage transients has a longer dynamic response time. The overvoltage protection loop of claim 1, wherein an activation time of the overvoltage protection loop is faster than an activation time of the main servo loop. The overvoltage protection loop of claim 2, wherein the output voltage provided by the overvoltage protection loop is within 5% of a nominal voltage at the output of the main servo loop. The overvoltage protection loop of claim 1, wherein the error amplifier includes a shunt regulator. The overvoltage protection loop of claim 5, wherein the output voltage sensing circuit includes a first resistor and a second resistor, the first resistor having a first resistance and coupled to the second node and the an output node, and the second resistor has a second resistance and is coupled to the second node and ground, wherein the first resistance and the second resistance are based at least in part on the second resistance of the second node by the error amplifier The voltage is maintained at one value there. The overvoltage protection loop of claim 1, wherein the error amplifier comprises an operational amplifier. The overvoltage protection loop of claim 1, wherein the feedback impedance includes a capacitor. The overvoltage protection loop of claim 1, wherein the magnetic core is magnetically coupled to the main servo loop. The overvoltage protection loop of claim 1, wherein the magnetic core is magnetically coupled to the overvoltage protection loop and a first magnetic core of the primary clock and feedback control circuit, and wherein the primary servo loop is Magnetically coupled to a second magnetic core. A method of providing overvoltage protection for a transformer using an overvoltage protection loop, the transformer comprising a main clock and feedback control circuit, a main servo loop and the overvoltage protection loop, the method comprising: by starting an overvoltage winding to provide a primary-side voltage responsive to a voltage on a primary winding in the primary clock and feedback control circuit to activate the overvoltage winding; using the secondary-side voltage to maintain one of an error amplifier a voltage on a first node to which the error amplifier is electrically coupled to a first node and a second node, wherein the voltage on the first node is maintained according to an internal reference voltage of the error amplifier; delaying a time Introduce to a feedback signal transmitted from the second node to the first node through a feedback impedance, the feedback impedance is electrically coupled between the first node and the second node; and using the electrically coupled to at least the first node An output voltage sensing circuit at a node and an output node controls an output voltage at the output node based on the voltage at the first node, wherein the overvoltage protection loop is the transformer under an error condition supply this output voltage.

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