TW201640568A - Integrated circuit structure and method for forming the same - Google Patents

Abstract

An integrated circuits structure includes a semiconductor substrate, at least an non-planar field effect transistor (FET) device formed on the semiconductor substrate, and an interconnection structure formed on the semiconductor substrate. The non-planar FET device includes a plurality of fins and a gate electrode. The interconnection structure includes a plurality of first group metals and a plurality of second group metals. The first group metals are formed on the non-planar FET and the second group metals are formed on the first group metals. The first group metals include a first metal pitch and the second group metals include a second metal pitch. The second metal pitch is 1.2-1.5 times to the first metal pitch.

Description

Integrated circuit structure and manufacturing method thereof

The invention relates to an integrated circuit structure and a manufacturing method thereof, in particular to an integrated circuit structure for reducing the number of times of using multiple patterning methods and a manufacturing method thereof.

In the process of the semiconductor integrated circuit, the fabrication of the microstructure of the integrated circuit needs to be utilized in a suitable substrate or material layer such as a semiconductor substrate/film layer, a dielectric material layer, or a metal material layer. Processes such as shadowing and etching form tiny patterns with precise dimensions. To achieve this goal, in conventional semiconductor technology, a mask layer is formed over the target material layer to form/define these minute patterns in the mask layer, and then transfer the patterns. To the target film layer. In general, the mask layer can comprise a patterned photoresist layer formed by a lithography process, and/or a patterned mask layer formed using the patterned photoresist layer. With the complication of integrated circuits, the size of these tiny patterns is continually decreasing, so the equipment used to generate the pattern must meet the stringent requirements of process resolution and overlay accuracy. At this point, the resolution is considered a measure of the ability to pattern the smallest size image under predetermined manufacturing conditions.

However, as semiconductor technology continues to advance to 85 nanometers (nm), single patterning methods have been unable to meet the resolution requirements or process requirements for fabricating tiny linewidth patterns. Therefore, semiconductor companies are now adopting multiple patterning methods, such as double patterning processes, as a way to overcome the resolution limits of lithographic exposure devices. In general, in a multiple patterning process, a dense pattern (whose individual pattern size and/or inter-pattern spacing is below the resolution limit of the lithography apparatus) is first disassembled into different masks. The patterns on the masks are then transferred to the photoresist layer/mask layer so that the patterns on the different masks can be combined into the original target pattern.

It can be seen that the multi-patterning method is a process method with high precision and extremely high process control requirements, so the adoption of the multi-patterning method inevitably increases the process complexity and the process cost.

Accordingly, the present invention provides a method of fabricating the number of uses of a multiple patterning process in a semiconductor process.

According to the scope of the invention provided by the present invention, an integrated circuit structure is provided, the integrated circuit structure comprising a semiconductor substrate, at least one non-planar field effect transistor disposed on the semiconductor substrate ( A field effect transistor (hereinafter referred to as FET) element and an interconnect structure disposed on the semiconductor substrate. The non-planar FET device includes a plurality of fin structures and a gate electrode, and the interconnect structure includes a plurality of first sets of metals and a plurality of second sets of metals, and the first set of metal lines are disposed on the non-planar The planar FET elements are disposed on the first set of metals. The first set of metals includes a first metal pitch, the second set of metals includes a second metal pitch, and the second metal pitch is 1.2 to 1.5 times the first metal pitch.

According to the patent application scope provided by the present invention, a method for fabricating an integrated circuit structure is provided, which comprises the following steps. First, a semiconductor substrate is provided, and at least one non-planar FET element is formed on the semiconductor substrate. Next, a plurality of first groups of metals are formed on the non-planar FET device, the sizes and positions of the first groups of metals are defined by a multiple patterning method, and the first group of metals includes a first metal spacing. After forming the first set of metals, forming a plurality of second sets of metals on the first set of metals, the size and position of the second set of metals being defined by a single patterning method, and the second The group metal includes a second metal pitch. The second metal pitch is 1.2 to 1.5 times the first metal pitch.

An integrated circuit structure and a method of fabricating the same according to the present invention, wherein a first group of metals is formed on a non-planar FET element, and then a second group of metals is formed on the first group of metals, and more importantly, the second group The second metal spacing included in the metal is 1.2 to 1.5 times the first metal pitch comprised by the first set of metals. Since the second group of metals is defined by a single patterning method, that is, in the process of fabricating the integrated circuit structure provided by the present invention, the second group of metals is replaced by a single patterning process instead of the multiple patterning process, so The use of at least one reticle omits at least one alignment action. That is to say, the integrated circuit structure and the manufacturing method thereof provided by the invention enjoy the advantages of reducing process complexity, simplifying the process flow, and reducing the manufacturing cost.

After the component has been developed to the 65 nm technology generation, it is difficult to continue to shrink using a conventional planar metal-oxide-semiconductor (MOS) transistor process. Therefore, conventional techniques are proposed to be stereo or non-planar (non -planar) A multi-gate transistor component such as a FinFET (hereinafter referred to as FinFET) component replaces the planar transistor component. Therefore, the method for fabricating the integrated circuit provided by the preferred embodiment is mainly for fabricating a non-planar multi-gate FET device, especially for fabricating a fin field effect transistor (hereinafter referred to as a FinFET) component, but not Limited to this. Please refer to FIG. 1 to FIG. 4 . FIG. 1 to FIG. 4 are schematic diagrams showing a first preferred embodiment of a method for fabricating an integrated circuit structure according to the present invention. As shown in FIG. 1, the preferred embodiment first provides a semiconductor substrate 100, such as a germanium substrate. In the preferred embodiment, the semiconductor substrate 100 can also be a semiconductor on insulator (hereinafter referred to as SOI) substrate. As known to those skilled in the art, the SOI substrate may include a substrate, a bottom oxide (BOX) layer, and a semiconductor layer formed on the bottom oxide layer, such as a single crystal, from bottom to top. The layer of structure. In addition, the substrate provided by the preferred embodiment may also be a bulk silicon substrate. Alternatively, substrate 100 can comprise other elementary semiconductors such as germanium. The semiconductor substrate 100 may also comprise a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide (indium). Arsenic), and/or indium antimonide. The semiconductor substrate 100 may also comprise an alloy semiconductor such as a germanium alloy semiconductor (SiGe), a gallium arsenide alloy semiconductor (GaAsP), an aluminum indium arsenide alloy semiconductor (AlInAs), an aluminum gallium arsenide alloy semiconductor (AlGaAs), gallium. An alloy semiconductor of indium arsenic alloy semiconductor (GaInAs), gallium indium phosphorus alloy semiconductor (GaInP), and/or gallium indium arsenide alloy semiconductor (GaInAsP). Of course, the semiconductor substrate 100 may also comprise a combination of the above materials.

Next, a patterned hard mask (not shown) is formed on the semiconductor substrate 100 for defining the position and size of the fin structures of the plurality of non-planar FET transistors on the semiconductor substrate 100. In the preferred embodiment, since the fin structures are less than 75 nm apart, a single patterning method cannot meet the resolution requirements of the pitch. Therefore, the preferred embodiment utilizes a multiple patterning process, such as a double patterning process, to form a patterned hard mask on the semiconductor substrate 100 to define the location and size of the fin structure. In the preferred embodiment, the double patterning process may include a litho-etching-litho-etching (LELE) method, a lithography-freeze-lithography-etching process (hereinafter referred to as LELE). Litho-freeze-litho-etch, hereinafter referred to as LFLE) method, and self-aligned double patterning (SADP) method (also known as "spacer image transfer" (hereinafter referred to as "spacer image transfer" For the SIT) method). After forming the patterned hard mask, the patterned semiconductor mask 100 is etched using the patterned hard mask as an etch mask, and a plurality of fin structures 102 are formed on the semiconductor substrate 100. After forming the fin structure 102, the patterned hard mask can be retained or removed as desired by the product. Since the fin structure 102 is produced by etching the semiconductor substrate 100, the fin structure 102 may comprise germanium, germanium, or a III-V semiconductor material, or a semiconductor material as described above. As shown in FIG. 1, the fin structure 102 has a fin pitch P1 which is the sum of the width of the fin structure 102 itself and the distance between the fin structures 102 adjacent thereto. Still alternatively, the fin pitch P1 can be considered as the distance of the center point of two adjacent fin structures 102. Further, as shown in FIG. 1, the fin structures 102 are parallel to each other and extend in a first direction D1. In addition, in the preferred embodiment, at least one landing pad 102p is selectively formed in the source/drain regions of the front and rear ends of the fin structure 102. The connection pad 102p is electrically connected to each of the fin structures 102 as shown in FIG. 1, and is used as a contact place of the source/drain contact plug after the fabrication of the multi-gate transistor element is completed.

After the fin structure 102 is formed, a gate electrode 104 is formed on the semiconductor substrate 100. The gate electrode 104 is interleaved with the fin structure 102 as shown in FIG. 1, and the gate electrode 104 covers a portion of each fin structure 102. The gate electrode 104 can include a gate dielectric layer (not shown) and a gate conductive layer (not shown). The gate dielectric layer may comprise a dielectric material such as cerium oxide (SiO), tantalum nitride (SiN), or cerium oxynitride (SiON). In the preferred embodiment, the gate dielectric layer may further comprise a high-k material, such as hafnium oxide (HfO), hafnium niobate (HfSiO) or aluminum, zirconium, hafnium or the like. Metal oxides or metal silicates, etc., but are not limited thereto. In addition, when the gate dielectric layer of the preferred embodiment uses a high-K material, the present invention can be integrated with a metal gate process to provide a control electrode sufficient to match the high-K gate dielectric layer. . Accordingly, the gate conductive layer can be made of a different material depending on the gate-first process or the gate-last process of the metal gate. For example, when the preferred embodiment is integrated with the front gate process, the gate conductive layer may comprise a metal such as tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo), or the like. Alloys, metal nitrides such as tantalum nitride (TaN), titanium nitride (TiN), molybdenum nitride (MoN), etc., metal carbides such as tantalum carbide (TaC). And the selection of the metals is based on the principle of the conductive form of the multi-gate transistor element to be obtained, that is, the metal satisfying the required work function of the N-type or P-type transistor is selected as the selection principle, and the gate conductive layer It can be a single work function metal layer or a composite work function metal layer. When the preferred embodiment is integrated with the post gate process, the gate conductive layer acts as a dummy gate, which may comprise a semiconductor material such as a polysilicon or the like.

After the fabrication of the gate electrode is completed, the preferred embodiment can be fabricated into other components, such as lightly doped drain, gate sidewall, source/drain, etc., to form at least one FinFET. The crystal element 110 is a non-planar field effect transistor element. In addition, the selective epitaxial growth (SEG) process and the metal telluride process, which are well known to those skilled in the art, can be integrated into the FinFET device process as needed, and will not be repeated here. In addition, in the post-gate process, after the fabrication of other constituent elements is completed, the dummy gate is removed and a desired metal gate including a gate dielectric layer and a work function metal layer is formed.

Please refer to Figure 2. Next, an inter-layer dielectric (hereinafter referred to as ILD) layer (not shown) is formed on the semiconductor substrate 100, and then a plurality of contact plugs 120 are formed in the ILD layer, and the contact plugs are formed. The 120 series includes a contact plug pitch P2. In other embodiments of the present invention, the contact plug pitch P2 may be the contact plug pitch between the gate contact plug and the gate contact plug (not shown), or the source of the fin structure/ Contact plug spacing between the drain contact plug and the source/drain contact plug, or it may be between the gate contact plug (not shown) and the source/drain contact plug of the fin structure Contact plug spacing. Briefly, the contact plug pitch P2 can be the spacing between the various contact plugs formed within the ILD layer. Further, reference is made to Fig. 3, which is a schematic view of a variation of the present invention. In the present variation, the fabrication of the contact pads 102p can be omitted, and the strip contact plugs 102s are formed in the ILD layer, and the strip contact plugs 102s also include the contact plug pitch P2. It should also be noted that in order to emphasize the relationship between the contact plug 120/102s and the fin structure 102, the ILD layer is not depicted in Figures 2 and 3, but those skilled in the art should be able to easily think about ILD. The relevant location of the layer.

Please refer back to Figure 2. In detail, a patterned hard mask (not shown) can be formed on the surface of the ILD layer by a lithography process to define the size and position of the contact plug 120. A patterned hard mask is then used as an etch mask to etch the ILD layer, and a plurality of contact plug openings (not shown) are formed in the ILD layer. Next, a metal layer (not shown) is formed on the ILD layer, and the metal layer fills the contact plug opening. A planarization process is then performed to remove excess metal, and contact plugs 120 are formed in the ILD layer, i.e., FinFET element 110. Each of the contact plugs 120 includes a contact plug pitch P2 which is the sum of the width of the contact plug itself and the distance between the adjacent contact plugs. As described above, in other embodiments of the present invention, the contact plug pitch P2 may be a contact plug pitch between gate contact plugs (not shown) or a source/drain of the fin structure. The contact plug spacing between the contact plugs may alternatively be the contact plug spacing between the gate contact plug and the source/drain contact plug of the fin structure. It is worth noting that in the general process, the contact plug pitch P2 will be the same as the fin pitch P1, so in the prior art process, the contact plug 120 must be formed using the same lithography process as the fin structure 102. That is, in a typical prior art process, the contact plug pitch P2 would have to use a multiple patterning process due to less than the limit of a single patterning process (ie, 75 nm). However, in the preferred embodiment, regardless of the size of the fin structure 102, the contact plug pitch P2 of the contact plug 120 provided by the preferred embodiment is greater than the fin pitch P1 of the fin structure 102, preferably. The contact plug pitch P2 of the embodiment is greater than 75 nm. Therefore, the contact plug 120 provided by the preferred embodiment of the present invention can be fabricated by a single patterning process such as immersion DUV lithography or electron beam lithography (E- Beam lithography), but not limited to this.

Please refer to Figure 4. Next, fabrication of components such as interconnect structures can be continued on the semiconductor substrate 100 to form a metal interconnect structure on the FinFET component 110. For example, a dielectric layer 130d (shown in FIG. 7) may be formed on the contact plug 120 and the ILD layer, and then a patterned hard mask is formed on the surface of the dielectric layer 130d by a lithography process (not shown). ), used to define the size and location of a plurality of metal wire structures. Subsequently, the patterned hard mask is used as an etch mask to etch the dielectric layer 130d, and openings (not shown) of the plurality of metal wiring structures are formed in the dielectric layer 130d. Next, a metal layer (not shown) is formed on the dielectric layer 130d, and the metal layer fills the metal wire structure opening. A planarization process is then performed to remove excess metal, and a plurality of metal wire structures 130w parallel to each other are formed in the dielectric layer 130d, and the metal wire structures 130w extend in the second direction D2. It should be noted that the metal wire structure 130w is the bottom layer of the interconnect structure (ie, the layer closest to the semiconductor substrate 100 and the FinFET device 110), so in the preferred embodiment, the bottommost metal wire structure 130w is again regarded as the first metal layer M1 of the interconnect structure. In addition, the contact plug 120 is used to electrically connect the FinFET element 110 and the first metal layer M1 of the interconnect structure (ie, the metal wire structure 130w). Therefore, in the preferred embodiment, the contact plug 120 is regarded as being It is the 0th plug structure V0. It is to be noted that the metal wire structure 130w has a metal pitch P3 which is the sum of the width of a metal wire structure 130w itself and the distance between the metal wire structure 130w adjacent thereto. Alternatively, the metal pitch P3 may be the distance from the center point of the adjacent metal wire structure 130w. It should be noted that in the preferred embodiment, the metal pitch P3 refers particularly to the minimum metal pitch of the metal wire structure 130w in the dielectric layer 130d. In addition, since the metal wire structure 130w extends in the second direction D2, the metal pitch P3 is parallel to the first direction D1 as shown in FIG. In general, the metal pitch P3 of the first metal layer M1 has a ratio to the fin pitch P1 of the fin structure 102, for example, 1:1. However, as the process progresses, the ratio of the metal pitch P3 to the fin pitch P1 is gradually adjusted to 3:4. For example, after entering the 22 nm node process, the metal pitch P3 is less than 75 nm, and the pitch is smaller than the limit of the existing single patterning process, so the first metal layer M1 (ie, the metal wire structure 130w) must use multiple patterning. A method, such as a dual patterning method, completes the lithography process. The double patterning method may include the foregoing method, and thus will not be described again. In addition, it should be noted that since the first metal layer M1 defines the metal wire structure by the double patterning method, the first metal layer M1 may simultaneously extend along the first direction and the second direction D2 as needed.

Please continue to see Figure 4. After the first metal layer M1 is completed, a dielectric layer 132d is formed on the first metal layer M1 and the dielectric layer 130d (shown in FIG. 7), and then a lithography process is formed on the surface of the dielectric layer 132d. A patterned hard mask (not shown) is used to define the size and location of the metal wire structure and/or the contact plug. Subsequently, the patterned hard mask is used as an etch mask to etch the dielectric layer 132d, and a plurality of metal wire structures and contact plug openings (not shown) are formed in the dielectric layer 132d. Next, a metal layer (not shown) is formed on the dielectric layer 132d, and the metal layer fills the metal wire structure and the opening of the contact plug. Then, a planarization process is performed to remove excess metal, and a plurality of metal wire structures 132w and a plurality of plug structures 132v are formed in the dielectric layer 132d, and the metal wire structures 132w extend along the first direction D1. Parallel to each other. In addition, the metal wire structure 132w can be regarded as the second metal layer M2 of the interconnect structure, and the plug structure 132v serves as the first via plug V1 connecting the first metal layer M1 and the second metal layer M2. It should be noted that the second metal layer M2 (ie, the metal wire structure 132w) and the first interlayer plug V1 (ie, the plug structure 132v) are formed on the same dielectric layer 132d, and thus can be regarded as the same metal structure. In other words, this layer of metal structure comprises a pair of structures consisting of a second metal layer M2 and a first via plug V1. However, the second metal layer M2 (ie, the metal wire structure 132w and the first via plug V1 may also be formed in different dielectric materials respectively. Second, the metal wire structure 132w and the plug structure 132v may adopt a dual damascene method. It is produced, but since the method is known to those skilled in the art, it will not be described here. More importantly, the metal wire structure 132w also has a metal pitch P3. It should be noted that as before The metal pitch P3 also refers to the metal pitch of the metal wire structure 132w in the layer of the dielectric layer 132d. In addition, since the metal wire structure 132w extends along the first direction D1, the metal in the dielectric layer 132d The pitch P3 is parallel to the second direction D2 as shown in Fig. 4. In the preferred embodiment, these metal structures having the same metal pitch are classified as the first group of metals (MG1). In a preferred embodiment, the number of layers of the first group of metal MG1 may be only one layer, but not more than two layers. At least one metal structure of the first group of metal MG1 has the same extending direction as the fin structure 102. Said in the preferred embodiment The second metal layer M2 in the first group of metal MG1 extends in the same direction as the fin structure 102 and extends in the first direction D1.

It should also be noted that since the metal pitch P3 of the first group of metal MG1 is smaller than the limit of the single patterning method, the size and position of the metal wire structure 132w must be defined by a double patterning method, and then defined by a double patterning method. The size and position of the plug structure 132v.

Please refer to FIG. 5, which is a simplified schematic diagram of the interconnect structure provided by the present invention. As shown in FIG. 5, the wire extending direction of any of the metal layers Mn in the interconnect structure provided by the present invention is perpendicular to the wire extending direction of the metal layer Mn+1 disposed in the vertically adjacent layer. For example, in the preferred embodiment, the first metal layer M1 wire extends in the second direction D2, and the second metal layer M2 wire extends in the first direction D1. In addition, it should be noted that since the first group of metal MG1 defines the metal wire structure by the double patterning method, the wire structures of the first metal layer M1 and the second metal layer M2 can simultaneously be along the first direction D1 and the second direction. D2 extends.

The integrated circuit structure and the manufacturing method thereof according to the preferred embodiment are performed by using a multiple patterning method to complete the fabrication of the fin structure 102, and completing the front-end process of the FinFET device 110 (front-end-of- After line), regardless of the size of the fin pitch P1 of the fin structure 102 of the FinFET element 110, the contact plug pitch P2 of the contact plug 120 is increased, so that the contact plug pitch P2 is greater than the limit value of the single patterning process. Therefore, the lithography process required to fabricate the contact plug 120 can be performed by a single patterning method. In addition, as described above, the contact plug pitch P2 includes the contact plug pitch between the gate contact plugs (not shown) and the contact plug pitch between the source/drain contact plugs of the fin structure. And the contact plug spacing between the gate contact plug (not shown) and the source/drain contact plug of the fin structure. It can be seen that the contact plug pitch P2 of the contact plug 120 in the preferred embodiment is not only larger than the fin pitch P1 of the fin structure 102, but also larger than the metal pitch P3 of the first group of metal MG1. In other words, the preferred embodiment defines the size and position of the fin structure 102 and the first set of metal MG1 using a multiple patterning method, but defines the size and position of the contact plug 120 using a single patterning method. In contrast to conventional techniques, it is necessary to define the size and position of the contact plug 120 using a multiple patterning method. In the preferred embodiment, at least one reticle can be omitted, and thus at least one alignment action is omitted. That is to say, the integrated circuit structure and the manufacturing method thereof provided by the preferred embodiment enjoy the advantages of reducing process complexity, simplifying the process flow, and reducing the manufacturing cost.

Please refer to FIG. 1 to FIG. 7 . FIG. 1 to FIG. 7 are schematic diagrams showing a second preferred embodiment of a method for fabricating an integrated circuit structure according to a preferred embodiment. It should be noted that in the second preferred embodiment, the same constituent elements as the first preferred embodiment may contain the same materials, and thus the material selections are not described again. Further, the manufacturing steps of the same constituent elements as those of the first preferred embodiment can be the same as those of the first preferred embodiment. As shown in FIG. 1, the preferred embodiment also provides a semiconductor substrate 100, and a patterned hard mask (not shown) is formed on the semiconductor substrate 100 by a multiple patterning method, and through the patterned hard mask. The cover etches the semiconductor substrate 100 to form a plurality of fin structures 102 that are parallel to each other, and the fin structures 102 respectively include a fin pitch P1. As described above, since the fin pitch P1 is smaller than the limit of the single patterning method, the preferred embodiment uses the multiple patterning method to form the fin structure 102, and the multiple patterning method may include LELE, LFLE, SADP/SIT And other methods, but are not limited to this. Subsequently, a gate electrode 104 is formed on the semiconductor substrate 100, and fabrication of the FinFET element 110 is completed.

Next, an ILD layer (not shown) is formed on the semiconductor substrate 100 as described in the foregoing preferred embodiment, and a patterned hard mask is formed on the ILD layer by a single patterning method, followed by The patterned hard mask etches the ILD layer to form a plurality of contact plug openings or strip contact plug openings (not shown). Next, as shown in FIG. 2 or FIG. 3, a contact plug 120 is formed in each of the contact plug openings. Alternatively, a strip-shaped contact plug 102s is formed in the ILD layer, and a contact plug 102 disposed on the strip-shaped contact plug 102s is formed in the other ILD layer. Each of the contact plugs 120/102s includes a contact plug pitch P2, and the contact plug pitch P2 includes a contact plug pitch between the gate contact plugs (not shown), and a source/drain contact plug of the fin structure. The contact plug spacing between the plugs, and the contact plug spacing between the gate contact plugs (not shown) and the source/drain contact plugs of the fin structure. As described above, in the preferred embodiment, regardless of the size of the fin structure 102, the contact plug pitch P2 of the contact plug 120 provided by the preferred embodiment is greater than the fin pitch of the fin structure 102. P1 is preferably greater than 75 nm. Therefore, the size and position of the contact plug 120 provided by the preferred embodiment may be defined by a single patterning process, such as a dip-type deep ultraviolet light development method or electron beam lithography, but is not limited thereto.

Please refer to Figure 4. Next, fabrication of an element such as an interconnect structure can be performed on the semiconductor substrate 100. For example, a dielectric layer 130d (shown in FIG. 7) may be formed on the contact plug 120 and the ILD layer, and then a patterned hard mask is formed on the surface of the dielectric layer 130d by a lithography process (not shown). ), used to define the size and location of a plurality of metal wire structures. Then, a patterned hard mask is used as the etch mask to etch the dielectric layer 130d, and an opening (not shown) of the plurality of metal wiring structures is formed in the dielectric layer 130d. Next, as shown in Fig. 4, a metal wire structure 130w is formed in each of the openings of the metal wire structure. As previously mentioned, the metal wire structure 130w serves as the bottommost layer of the interconnect structure (ie, the layer closest to the semiconductor substrate 100 and the FinFET device 110), so in the preferred embodiment, the bottommost metal wire structure 130w is also regarded as the first metal layer M1. In addition, the contact plug 120 is used to electrically connect the FinFET element 110 and the first metal layer M1 of the interconnect structure. Therefore, in the preferred embodiment, the contact plug 120 is regarded as the 0th plug structure V0. . It is worth noting that the metal wire structure 130w has a metal pitch P3. As previously mentioned, the metal pitch P3 refers in particular to the metal pitch of the metal wire structure 130w which is the smallest in the dielectric layer 130d. In addition, since the metal wire structure 130w extends in the second direction D2, the metal pitch P3 in the dielectric layer 130d is parallel to the first direction D1 as shown in FIG. In the preferred embodiment, the metal pitch P3 is less than 75 nm, so a multiple patterning method, such as a double patterning method, must be used to complete the lithography process. The double patterning method may include the foregoing method, and thus will not be described again. In addition, it should be noted that since the first metal layer M1 defines the metal wire structure by the double patterning method, the wires of the first metal layer M1 may simultaneously extend in the first direction D1 and the second direction D2.

Please continue to see Figure 4. After the first metal layer M1 is completed, a dielectric layer 132d is formed on the first metal layer M1 and the dielectric layer (shown in FIG. 6), and then a pattern is formed on the dielectric layer 132d by using a lithography process. A hard mask (not shown) is used to define the size and location of the plurality of metal wire structures and/or the plurality of contact plugs. Subsequently, the patterned hard mask is used as an etch mask to etch the dielectric layer 132d, and a plurality of metal wire structures and contact plug openings (not shown) are formed in the dielectric layer 132d. Next, metal wire structures 132w and plug structures 132v are formed in the openings of the metal wire structures and the contact plugs, and the metal wire structures 132w extend in the first direction D1 to be parallel to each other. In addition, the metal wire structure 132w can be regarded as the second metal layer M2 of the interconnect structure, and the plug structure 132v serves as the first via plug V1 connecting the first metal layer M1 and the second metal layer M2. It should be noted that the second metal layer M2 (ie, the metal wire structure 132w) and the first interlayer plug V1 (ie, the plug structure 132v) are formed on the same dielectric layer 132d, and thus can be regarded as the same metal structure. Thus, in other words, this layer of metal structure comprises a pair of structures consisting of a second metal layer M2 and a first via plug V1. However, in other embodiments of the present invention, the second metal layer M2 (ie, the metal wire structure 132w) and the first via plug V1 may also be formed in different dielectric material layers, respectively. As previously mentioned, the metal wire structure 132w and the plug structure 132v may employ a dual damascene method, but since the method is known to those skilled in the art, it will not be described herein. More importantly, the metal wire structure 132w has a metal pitch P3 between them, and the plug structure 132v also has a metal pitch P3. As described above, the metal pitch P3 is particularly in the layer of the dielectric layer 132d. The metal wire structure 132w has a minimum metal pitch. As described above, since the metal wire structure 132w extends in the first direction D1, the metal pitch P3 in the dielectric layer 132d is parallel to the second direction D2 as shown in FIG. The metal pitch P3 of the metal wire structure 132w and the plug structure 132v is the same as the metal pitch P3 of the first metal layer M1, and in the preferred embodiment, these metal structures having the same metal pitch are classified into the first group. Metal MG1. In addition, in the preferred embodiment, the number of layers of the first group of metals MG1 is not more than two. As shown in FIG. 4, at least one of the metal structures of the first group of metals MG1 extends in the same direction as the fin structure 102. For example, in the preferred embodiment, the second metal layer M2 of the first group of metal MG1 extends in the same direction as the fin structure 102 and extends in the first direction D1.

As described above, since the metal pitch P3 of the first group of metals MG1 is smaller than the limit (75 nm) of the single patterning method, it is necessary to define the size and position of the metal wire structure 132w by the double patterning method, and then use a double patterning method. The size and position of the plug structure 132v is defined. In addition, it should be noted that since the first group of metal MG1 defines a metal wire structure by a double patterning method, the first metal layer M1 and the second metal layer M2 wire may simultaneously extend along the first direction D1 and the second direction D2. .

Next, please refer to Figure 6. After the formation of the first group of metals MG1, fabrication of components such as interconnect structures is continued on the semiconductor substrate 100. As shown in FIG. 6 and FIG. 7, a dielectric layer 140d is formed on the first group of metal MG1 and the dielectric layer 132d (shown in FIG. 7), and then formed on the surface of the dielectric layer 140d by a lithography process. A patterned hard mask (not shown) is used to define the size and location of the plurality of metal wire structures and/or the plurality of contact plugs. Subsequently, the patterned hard mask is used as an etch mask to etch the dielectric layer 140d, and a plurality of metal wire structures and contact plug openings (not shown) are formed in the dielectric layer 140d. Next, a metal layer (not shown) is formed on the dielectric layer 140d, and the metal layer fills the metal wire structure and the opening of the contact plug. A planarization process is then performed to remove excess metal, and a metal wire structure 140w and a plug structure 140v are formed in the dielectric layer 140d, and the metal wire structures 140w extend in the second direction D2 to be parallel to each other. In addition, the metal wire structure 140w can be regarded as the third metal layer M3 of the interconnect structure, and the plug structure 140v serves as the second via plug V2 connecting the second metal layer M2 and the third metal layer M3. As shown in FIGS. 6 and 7, the third metal layer M3 (ie, the metal wire structure 140w) and the second via plug V2 (ie, the plug structure 140v) are formed in the same dielectric layer 140d, so that it is visible. It is the same layer of metal structure. However, in other embodiments of the present invention, the third metal layer M3 (ie, the metal wire structure 140w) and the second via plug V2 may also be formed in different dielectric material layers, respectively. In other words, this layer of metal structure comprises a pair of structures consisting of a third metal layer M3 and a second via plug V2. The metal wire structure 140w and the plug structure 140v may employ a dual damascene method, but since the method is known to those skilled in the art, it will not be described herein. More importantly, there is a metal pitch P4 between the metal wire structures 140w, and a metal pitch P4 between the plug structures 140v. In the preferred embodiment, the metal pitch P4 refers particularly to the minimum metal pitch of the metal wire structure 140w in the dielectric layer 140d. In addition, since the metal wire structure 140w extends in the second direction D2, the metal pitch P4 in the dielectric layer 140d is parallel to the first direction D1 as shown in FIG. The metal pitch P4 of the metal wire structure 140w and the plug structure 140v is 1.2 times to 1.5 times the metal pitch P3 of the first metal layer M1. In the preferred embodiment, the metal pitch P4 of the metal wire structure 140w and the plug structure 140v is between 75 nm and 85 nm, but is not limited thereto.

Please refer to Figure 7. Next, in the preferred embodiment, the dielectric layer 142d is formed repeatedly, the patterned hard mask is formed on the dielectric layer 142d by the lithography process, and the dielectric layer 142d is etched through the patterned hard mask. A plurality of metal wire structures and/or openings of a plurality of contact plugs are formed in the electrical layer 142d, and a metal wire structure 142w and a contact plug 142v are formed in the openings of the metal wire structure and/or the plurality of contact plugs. The metal wire structure 142w can be regarded as the fourth metal layer M4 of the interconnect structure, and the plug structure 142v serves as the third via plug V3 connecting the third metal layer M3 and the fourth metal layer M4. As shown in FIG. 7, the fourth metal layer M4 and the third via plug V3 are formed in the same dielectric layer 142d, and thus can be regarded as the same metal structure. However, in other embodiments of the present invention, the fourth metal layer M4 (ie, the metal wire structure 142w) and the third via plug V3 may also be formed in different dielectric material layers, respectively. In other words, this layer of metal structure comprises a pair of structures consisting of a fourth metal layer M4 and a third via plug V3. It should be noted that the metal wire structure 142w and the contact plug 142v also have a metal pitch P4, and the metal pitch P4 refers particularly to the metal pitch of the metal wire structure 142w in the layer of the dielectric layer 142d. As described above, since the metal wiring structure 142w extends in the first direction D1, the metal pitch P4 in the dielectric layer 142d is as shown in FIG. 7, parallel to the second direction D2. In the preferred embodiment, these metal structures having the same metal pitch P4 are classified as the second group of metals MG2. More importantly, the metal pitch P4 of the second group of metals MG2 is 1.2 to 1.5 times the metal pitch P3 of the first group of metals MG1. In the preferred embodiment, the metal pitch P4 of the second group of metals MG2 may be between 75 nm and 85 nm, but is not limited thereto. In addition, in the preferred embodiment, the above steps may be repeated as needed, so that the number of layers included in the second group of metal MG2 is not limited to the two layers shown in FIG. 6 and FIG. 7, but the second group of metal MG2. The number of layers is no more than four layers.

It should also be noted that since the metal pitch P4 of the second group of metal MG2 is greater than the limit of the single patterning method, the size and position of the metal wire structure 140w/142w can be defined by a single patterning method, and another single pattern can be utilized. The method defines the size and position of the plug structure 140v/142v. In other words, the metal structure of the same layer must use a secondary single patterning method to define the metal wire structure and the plug structure.

Please refer to Figure 7. After the formation of the second group of metals MG2, fabrication of components such as interconnect structures is continued on the semiconductor substrate 100. As shown in FIG. 7, the following steps are repeated on the second group of metal MG2: a dielectric layer 150d/152d/154d is formed, and the dielectric layers 150d/152d/154d are respectively formed of a plurality of layers of dielectric material. A patterned hard mask (not shown) is then formed on the surface of the dielectric layer by a lithography process to define the size and location of the plurality of metal wire structures and/or the plurality of contact plugs. A patterned hard mask is then used as an etch mask to etch the dielectric layer, and a plurality of metal wire structures and contact plug openings (not shown) are formed in the dielectric layer. Next, a metal layer (not shown) is formed on the dielectric layer, and the metal layer fills the metal wire structure and the opening of the contact plug. A planarization process is then performed to remove excess metal, and metal wire structures 150w/152w/154w and plug structures 150v/152v/154v are formed in dielectric layers 150d/152d/154d. In addition, the metal wire structure 150w can be regarded as the fifth metal layer M5 of the interconnect structure, and the plug structure 150v serves as the fourth via plug V4 connecting the fourth metal layer M4 and the fifth metal layer M5. And so on, the metal wire structure 152w is the sixth metal layer M6, and the plug structure 152v is the fifth interlayer plug V5; the metal wire structure 154w is the seventh metal layer M7, and the plug structure 154v is the sixth layer. Plug V6. As shown in FIG. 7, the fifth metal layer M5 and the fourth via plug V4 are formed in the same dielectric layer 150d, and thus can be regarded as the same metal structure. And so on, the sixth metal layer M6 and the fifth interlayer plug V5 are formed in the same dielectric layer 152d, so that it can be regarded as the same metal structure; and the seventh metal layer M7 and the sixth interlayer plug V6 It is formed in the same dielectric layer 154d, so it can be regarded as the same metal structure. It can be seen that each of the metal structures includes a structural pair composed of the nth metal layer Mn and the n-1th dielectric plug Vn-1. More importantly, the metal wire structure 150w/152w/154w has a metal pitch P5, and the plug structure 150v/152v/154v also has a metal pitch P5, and the metal pitch P5 is particularly referred to as the dielectric layer 150d/152d/154d. In the layer, the metal wire structure 150w/152w/154w has the smallest metal pitch. Through the above steps, the construction of the interconnect structure 200 and the integrated circuit structure 300 can be completed.

In addition, as shown in FIGS. 5 to 7, the extending direction of any metal layer Mn in the interconnect structure 200 provided by the present invention is the extending direction of the metal layer Mn+1 disposed in the vertically adjacent layer. vertical.

The interconnect structure and the method of fabricating the same according to the preferred embodiment are completed after the fabrication of the fin structure 102 by the multiple patterning method and the fabrication of the FinFET device 110, regardless of the front-end process of the FinFET device 110. The size of the fin pitch P1 of the fin structure 102 not only increases the contact plug pitch P2 of the contact plug 120, but also makes the contact plug pitch P2 larger than the limit value of the single patterning process, so that it can be fabricated by a single patterning method. The lithography process required to contact the plug 120. As mentioned before, the contact plug pitch P2 includes the contact plug spacing between the gate contact plugs, the contact plug spacing between the source/drain contact plugs of the fin structure, and the gate contact plugs and fins. The contact plug spacing between the source/drain contact plugs of the sheet structure. More importantly, the preferred embodiment further limits the number of layers of the first group of metal MG1 defined by the multiple patterning method to not more than two layers, and forms a first definition on the first group of metal MG1 by a single patterning method. Two sets of metal MG2. In detail, in the preferred embodiment, the metal pitch P3 of the first group of metal MG1 is less than a predetermined value, and the predetermined value may be 75 nm, and the metal pitch P4 of the second group of metal MG2 is the first group of metal MG1. The metal pitch P3 is 1.2 times to 1.5 times, and may be, for example, between 75 nm and 85 nm. Since the metal pitch P4 of the second group of metal MG2 is greater than the limit value of the single patterning process, the lithography process required to fabricate the second group of metal MG2 can be performed by a single patterning method. In other words, the preferred embodiment sequentially defines the fin structure 102 by using a multiple patterning method, defines the size and position of the contact plug 120 by a single patterning method, and defines the first group of metal MG1 by using a multiple patterning method. Size and position, and the size and position of the second set of metal MG2 is defined using a single patterning method. The prior art must use a multiple patterning method to define the size and position of the contact plug 120 and the second set of metal MG2. In the preferred embodiment, at least two masks can be omitted, and thus at least two times are omitted. Alignment action. In addition, as the number of layers of the second group of metal MG2 increases, the number of masks and the number of alignment steps that can be omitted in the back-end-of-line provided by the preferred embodiment can be further reduced. Therefore, the integrated circuit structure and the manufacturing method thereof provided by the preferred embodiment enjoy the advantages of reduced process complexity, simplified process flow, and reduced manufacturing cost.

Please refer to FIG. 7 again, and FIG. 7 can also be used as a schematic diagram of a third preferred embodiment of the manufacturing method of the integrated circuit structure provided by the present invention. It should be noted that in the third preferred embodiment, the same constituent elements as the first preferred embodiment may comprise the same material, so the selection of materials is not described again, and the same manufacturing steps are also No longer. As shown in FIG. 7, the preferred embodiment provides a semiconductor substrate 100 having at least one non-planar field effect transistor device, such as a FinFET device 110, formed thereon. The FinFET device 100 includes a plurality of fin structures 102 arranged along a first direction D1, and a gate electrode 104 covering a portion of each of the fin structures 102. Next, an ILD layer (not shown) is formed on the semiconductor substrate 100, and then a plurality of contact plugs 120 or a plurality of strip contact plugs 120 are formed in the ILD layer.

After the fabrication of the contact plug 120 or the strip contact plug 120 is completed, the fabrication of components such as interconnect structures can be continued on the semiconductor substrate 100 to form an interconnect structure on the FinFET component 110. For example, a dielectric layer 130d may be formed on the contact plug 120 and the ILD layer, and then a patterned hard mask (not shown) may be formed on the surface of the dielectric layer 130d by using a lithography process to define a plurality of The size and location of the metal wire structure. A patterned hard mask is then used as the etch mask to etch the dielectric layer 130d, and openings (not shown) of the plurality of metal wiring structures are formed in the dielectric layer. Next, as shown in Fig. 7, a metal wire structure 130w is formed in each of the openings of the metal wire structure. As described above, the metal wire structure 130 is regarded as the first metal layer M1 of the interconnect structure, and the first metal layer M1 can be connected to the FinFET element 110 by the 0th dielectric plug V0 (ie, the contact plug 120). Electrical connection. After the first metal layer M1 is completed, the fabrication of the second metal layer M2 and the first via plug V1 can be performed. As described above, since the second metal layer M2 and the first via plug V1 are formed on the same dielectric layer 132d, it can be regarded as the same metal structure. In other words, this layer of metal structure comprises a pair of structures consisting of a second metal layer M2 and a first via plug V1. As described above, the second metal layer M2 and the first via plug V1 may employ a dual damascene method, but since the method is known to those skilled in the art, it will not be described herein. More importantly, the first metal layer M1, the first interlayer plug V1, and the second metal layer M2 each have a metal pitch P3. In the preferred embodiment, the metal structures having the same metal pitch are Classified as the first group of metals MG1. In addition, in the preferred embodiment, the number of layers of the first group of metals MG1 is not more than two. As shown in FIG. 7, at least one of the metal structures of the first group of metals MG1 extends in the same direction as the fin structure 102. For example, in the preferred embodiment, the second metal layer M2 of the first group of metal MG1 extends in the same direction as the fin structure 102 and extends in the first direction D1.

More importantly, in the preferred embodiment, the metal pitch P3 of the first group of metal MG1 is not only smaller than the limit of the single patterning method (75 nm), but is smaller than the limit of the double patterning method (50 nm), so it is necessary to utilize one. A quadruple patterning defines a first set of metals MG1. In addition, since the first metal layer M2 and the first interlayer plug V1 can be included in one layer of the first metal MG1, the preferred embodiment can define the size of the first metal layer M1 by using a quadruple patterning method. Position, and another patterning method is used to define the size and position of the first via plug V1. In other words, the metal structure of the same layer must be defined using a quadratic quadruple patterning method.

Next, please refer to Figure 7. After the formation of the first group of metals MG1, the fabrication of the components of the interconnect structure is continued on the semiconductor substrate 100. As shown in FIG. 7, a dielectric layer 140d is further formed on the first group of metal MG1, and then a patterned hard mask is formed on the surface of the dielectric layer 140d by using a lithography process to define a plurality of metal wire structures and / or the size and position of a plurality of contact plugs. Subsequently, the patterned hard mask is used as an etch mask to etch the dielectric layer 140d, and a plurality of metal wire structures and contact plug openings (not shown) are formed in the dielectric layer. Next, a third metal layer M3 and a second via plug V2 are formed in the metal wire structure and the opening of the contact plug. In addition, the above steps may be repeated, and a dielectric layer 142d and a fourth metal layer M4 and a third via plug V3 formed in the dielectric layer 142d are further formed on the dielectric layer 140d. It should be noted that the third metal layer M3, the second via plug V2, the fourth metal layer M4 and the third via plug V3 have the same metal pitch P4, respectively, and thus have the third metal pitch P4. The metal layer M3, the second via plug V2, the fourth metal layer M4, and the third via plug V3 are classified into a second group of metal MG2. More importantly, the metal pitch P4 of the second group of metal MG2 is 1.2 times to 1.5 times the metal pitch P3 of the first group of metals MG1. In the preferred embodiment, the metal pitch P4 of the second group of metals MG2 is between 50 nm and 75 nm, but is not limited thereto. In addition, in the preferred embodiment, the above steps may be repeated as needed, so that the number of layers of the second group of metal MG2 is not limited to the two layers shown in FIG. 7, but the second layer of metal MG2. No more than four layers.

In addition, it should be noted that since the metal pitch P4 of the second group of metals MG2 is greater than the limit of the four-fold patterning method, but still less than the limit of the single patterning method, each layer of the second group of metal MG2 can be utilized. A double patterning method defines the size and position of the metal wire structure, and another double patterning method is used to define the size and position of the plug structure.

Please continue to see Figure 7. After the formation of the second group of metals MG2, the fabrication of the components of the interconnect structure is continued on the semiconductor substrate 100. As shown in FIG. 6, the following steps are repeated on the second group of metal MG2: a dielectric layer 150d/152d/154d is formed, and then a pattern is formed on the surface of the dielectric layer 150d/152d/154d by a lithography process. A hard mask (not shown) is used to define the size and location of the plurality of metal wire structures and/or the plurality of contact plugs. Subsequently, the patterned hard mask is used as an etch mask to etch the dielectric layer 150d/152d/154d, and a plurality of metal wire structures and contact plug openings are formed in the dielectric layer 150d/152d/154d (not shown). . Next, a metal wire structure and a plug structure are formed at the metal wire structure and the opening of the contact plug. As shown in FIG. 7, a fifth metal layer M5 and a fourth via plug V4 are formed in the dielectric layer 150d, and a sixth metal layer M6 and a fifth via plug V5 are formed in the dielectric layer 152d. A seventh metal layer M7 and a sixth via plug V6 are formed in the dielectric layer 154d. It can be seen that each of the metal structures includes a structural pair composed of the nth metal layer Mn and the n-1th dielectric plug Vn-1. More importantly, the metal layers M5, M6, and M7 and the interlayer plugs V4, V5, and V6 have the same metal pitch P5, so the metal layers M5, M6, M7 and the interlayer plug having the same metal pitch P5. V4, V5, and V6 are classified into a third group of metals MG3. More importantly, the metal pitch P5 of the third group of metal MG3 is also 1.2 times to 1.5 times the metal pitch P4 of the second group of metals MG2. In the preferred embodiment, the metal pitch P4 of the second group of metals MG2 is greater than 75 nm, but is not limited thereto.

In addition, since the metal pitch P5 of the third group of metal MG3 is greater than the limit of the single patterning method, each single layer of the third group of metal MG3 can define the metal wire structure by using a single patterning method. Size and position, another single patterning method is used to define the size and position of the plug structure. In other words, the metal structure of the same layer must be defined using a secondary single patterning method.

According to the interconnect structure and the manufacturing method thereof, the first group of metal MG1 of the interconnect structure 200 includes a metal pitch P3 which is smaller than a first predetermined value and a metal of the second group of metal MG2. The pitch P4 is greater than the first predetermined value but less than a second predetermined value, and the metal pitch P5 of the third group of metals MG3 is greater than the second predetermined value. The first predetermined value and the second predetermined value may be limit values of different levels of developing devices. For example, in the preferred embodiment, the first predetermined value is 50 nm and the second predetermined value is 75 nm, but those skilled in the art will recognize that the first predetermined value and the second predetermined value are different grades of the developing device. The limit value is not limited to this. Therefore, the first group of metals MG1 having a metal pitch P3 of less than 50 nm must be defined by a four-fold patterning method, and the second group of metals MG2 having a metal pitch P4 between 50 nm and 75 nm must be defined by a double patterning method, and the metal pitch P5 A third set of metal MG3 greater than 75 nm can be defined using a single patterning process. Briefly, the preferred embodiment can define a first set of metals MG1 using a higher order developing device in a semiconductor process, a second set of metal MG2 using a second-order developing device, and a second-order developing device definition. The third group of metals MG3.

The integrated circuit structure and the method of fabricating the same according to the present invention can increase the contact plug pitch of the contact plug/strip contact plug such that the contact plug is larger than the metal pitch and/or the fin of the first set of metal The fin spacing of the structure is replaced by a single patterning process to replace the multi-patterning process to make the contact plug/strip contact plug, so that the use of at least one photomask can be omitted, and thus at least one alignment action is omitted. More importantly, the present invention can form a first group of metals on the non-planar FET device, then form a second group of metals on the first group of metals, and the second group of metals included in the second group of metals is A set of metals comprises between 1.2 and 1.5 times the pitch of the first metal. Since the second group of metals is defined by a single patterning method, in the fabrication process of the integrated circuit structure, the position and size of the second group of metals are defined by a single patterning process instead of the multiple patterning process, so that at least the above can be omitted. The use of a mask and the alignment action that is omitted at least once. Briefly, the fabrication method taught by the present invention defines the position and size of the first set of metals by the highest order developing device in the semiconductor process, but uses the next-order developing device to define the position and size of the second set of metals. Therefore, the number of reticle use can be reduced. That is to say, the integrated circuit structure and the manufacturing method thereof provided by the invention enjoy the advantages of reducing process complexity, simplifying the process flow, and reducing the manufacturing cost. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Base
102‧‧‧Fin structure
102p‧‧‧ connection pad
102s‧‧‧ strip contact plug
104‧‧‧gate electrode
110‧‧‧Fin field effect transistor components
120‧‧‧Contact plug/strip contact plug
130d, 132d, 140d, 142d, 150d, 152d, 154d‧‧‧ dielectric layer
130w, 132w, 140w, 142w, 150w, 152w, 154w‧‧‧ metal wire structure
132v, 140v, 142v, 150v, 152v, 154v‧‧‧ plug structure
200‧‧‧Interconnection structure
300‧‧‧Integrated circuit structure
MG1‧‧‧The first group of metals
MG2‧‧‧Second Group of Metals
MG3‧‧‧ third group of metals
M1‧‧‧ first metal layer
M2‧‧‧ second metal layer
M3‧‧‧ third metal layer
M4‧‧‧ fourth metal layer
M5‧‧‧ fifth metal layer
M6‧‧‧ sixth metal layer
M7‧‧‧ seventh metal layer
V0‧‧‧ contact plug
V1‧‧‧ first layer plug
V2‧‧‧Second layer plug
V3‧‧‧ third layer plug
V4‧‧‧fourth layer plug
V5‧‧‧ fifth layer plug
V6‧‧‧ sixth layer plug
P1‧‧‧Fin spacing
P2‧‧‧Contact plug spacing
P3, P4, P5‧‧‧ metal spacing

1 to 4 are schematic views of a first preferred embodiment of a method for fabricating an integrated circuit structure provided by the present invention, and FIG. 3 is a schematic view showing a variation of the present invention. Figure 5 is a simplified schematic diagram of the interconnect structure provided by the present invention. 1 to 7 are schematic views showing a second preferred embodiment of a method for fabricating an integrated circuit structure provided by the present invention. FIG. 7 is also a schematic diagram of a third preferred embodiment of a method for fabricating an integrated circuit structure provided by the present invention.

100‧‧‧Base

102‧‧‧Fin structure

104‧‧‧gate electrode

110‧‧‧Fin field effect transistor components

120‧‧‧Contact plug/strip contact plug

130d, 132d, 140d, 142d, 150d, 152d, 154d‧‧‧ dielectric layer

130w, 132w, 140w, 142w, 150w, 152w, 154w‧‧‧ metal wire structure

132v, 140v, 142v, 150v, 152v, 154v‧‧‧ plug structure

200‧‧‧Interconnection structure

300‧‧‧Integrated circuit structure

MG1‧‧‧The first group of metals

MG2‧‧‧Second Group of Metals

MG3‧‧‧ third group of metals

M1‧‧‧ first metal layer

M2‧‧‧ second metal layer

M3‧‧‧ third metal layer

M4‧‧‧ fourth metal layer

M5‧‧‧ fifth metal layer

M6‧‧‧ sixth metal layer

M7‧‧‧ seventh metal layer

V0‧‧‧ contact plug

V1‧‧‧ first layer plug

V2‧‧‧Second layer plug

V3‧‧‧ third layer plug

V4‧‧‧fourth layer plug

V5‧‧‧ fifth layer plug

V6‧‧‧ sixth layer plug

P1‧‧‧Fin spacing

P2‧‧‧Contact plug spacing

P3, P4, P5‧‧‧ metal spacing

Claims (26)

An integrated circuit structure comprising: a semiconductor substrate; at least one non-planar field effect transistor (FET) component disposed on the semiconductor substrate, and the non-planar field effect electric The crystal element includes a plurality of fin structures and a gate electrode; and an interconnect structure disposed on the semiconductor substrate, and the interconnect structure includes a plurality of first group metals and a plurality of second groups of metals The first set of metal is disposed on the non-planar field effect transistor component, and the second set of metal is disposed on the first set of metals, the first set of metals including a first metal pitch The second set of metals includes a second metal pitch, and the second metal pitch is 1.2 to 1.5 times the first metal pitch. The integrated circuit structure of claim 1, further comprising at least one slot contact, and the strip contact plug electrically connecting the non-planar field effect transistor element and the interconnect structure The first group of metals. The integrated circuit structure of claim 1, further comprising at least one contact plug, wherein the contact plug is electrically connected to the non-planar field effect transistor component and the interconnect structure The first group of metals. The integrated circuit structure of claim 3, wherein the contact plug comprises a contact plug pitch, and the contact plug pitch is greater than the first metal pitch. The integrated circuit structure of claim 1, wherein the first group of metals comprises no more than two layers. The integrated circuit structure of claim 1, wherein the second group of metals comprises no more than four layers. The integrated circuit structure of claim 6, wherein each of the second set of metals comprises a structural pair consisting of at least one metal wire structure and at least one plug structure. The integrated circuit structure of claim 1, wherein the first metal pitch is less than a predetermined value. The integrated circuit structure of claim 8, wherein the predetermined value is 75 nanometers (nm). The integrated circuit structure of claim 9, wherein the second metal pitch is between 75 nm and 85 nm. The integrated circuit structure of claim 1, further comprising a plurality of third groups of metals, and the third group of metals comprises a third metal pitch. The integrated circuit structure of claim 11, wherein the first metal pitch is less than a first predetermined value, and the second metal pitch is greater than the first predetermined value and less than a second predetermined value, and The third metal pitch is greater than the second predetermined value. The integrated circuit structure of claim 12, wherein the first predetermined value is 50 nm and the second predetermined value is 75 nm. The integrated circuit structure of claim 1, wherein the fin structures of the non-planar field effect transistor device comprise germanium, germanium, or a III-V semiconductor material. The integrated circuit structure of claim 1, wherein the gate electrode of the non-planar field effect transistor device comprises a single work function metal layer or a composite work function metal layer. A method for fabricating an integrated circuit structure, comprising: providing a semiconductor substrate, wherein the semiconductor substrate is formed with at least one non-planar field effect transistor element; forming a plurality of first on the non-planar field effect transistor device Group metal, the position and size of the first group of metals are defined by a multiple patterning method, and the first group of metals includes a first metal pitch; forming a plurality of the first group of metals Two sets of metals, the positions and sizes of the second sets of metals are defined by a single patterning method, and the second set of metals includes a second metal pitch, and the second metal pitch is the first metal 1.2 to 1.5 times the pitch. The method of manufacturing of claim 16, wherein the positions and sizes of the first set of metals are defined by a double patterning method. The manufacturing method of claim 17, wherein the double patterning process comprises a litho-etching-litho-etching (LELE) method, a lithography-freeze-micro A litho-freeze-litho-etch (LFLE) method, and a self-aligned double patterning (SADP) method. The manufacturing method of claim 17, further comprising forming a plurality of third groups of metals on the semiconductor substrate, and the positions and sizes of the third groups of metals are quadruple patterning. Method definition. The manufacturing method of claim 19, wherein the third group of metals comprises a third metal pitch, and the first metal pitch is 1.2 to 1.5 times the third metal pitch. The manufacturing method of claim 16, further comprising at least one slot contact, and the strip contact plug electrically connecting the non-planar field effect transistor element and the first group of metals. The manufacturing method of claim 16, further comprising performing a single patterning process for forming at least one contact plug, and the contact plugs are electrically connected to the non-planar field effect transistor element and the Wait for the first group of metals. The manufacturing method of claim 22, wherein the contact plug comprises a contact pitch, and the contact pitch is greater than the first metal pitch. The manufacturing method of claim 16, wherein the first group of metals comprises no more than two layers. The manufacturing method of claim 16, wherein the second group of metals comprises no more than four layers. The manufacturing method of claim 25, wherein each of the second group of metals comprises a structural pair consisting of at least one wire structure and at least one plug structure.