TW201638786A - Computer apparatuses comprising SSDs (Solid-State Drive) and methods for accessing the SSDs - Google Patents

Abstract

An embodiment of a computer apparatus comprising a CPU (Central Processing Unit), a PCH (Platform Controller Hub) chip and a SSD (Solid-State Drive) is introduced. The CPU comprises a north bridge chip and the PCH chip connects the north bridge via a DMI (Direct Media Interface) bus. The PCH chip comprises an AHCI (Advanced Host Controller Interface) and the SSD connects the AHCI. The SSD comprises multiple channels and each channel connects a MRAM (Magnetoresistive Random Access Memory) or a RRAM (Resistive Random Access memory) for random access.

Description

Computer device including solid state hard disk and method for accessing solid state hard disk

The present invention is related to a storage technology, particularly a computer device including a solid state hard disk and a method of accessing a solid state hard disk.

Today's solid state drives (SSDs, Solid-State Drives) are composed of NAND flash memory devices. However, limited by the characteristics of the components (capacitive storage device), the random read time of the NAND flash memory device is more than one thousand times that of a dynamic random access memory (DRAM), such as random read. It takes 50 us to take the 4K byte of the NAND flash memory device and 10 ns to read the dynamic random access memory 4K byte randomly. Therefore, the solid state hard disk has considerable room for improvement in the efficiency of random reading. In view of this, the present invention proposes a solid state hard disk and a method of accessing a solid state hard disk to solve the above problems.

Embodiments of the present invention provide a computer device including a central processing unit, a platform control hub chip, and a solid state hard disk. The central processing unit includes a north bridge wafer, and the platform control hub chip connects the north bridge wafer through a direct media interface bus. The platform control hub chip contains an advanced host controller interface and the solid state drive is connected to the advanced host controller interface. Solid state hard drive included A plurality of channels, and each channel is connected to a magnetoresistive random access memory or a resistive random access memory for random access.

Embodiments of the present invention provide a method of accessing a solid state hard disk, executed by a processing unit in a solid state hard disk, comprising the following steps. The logic write command issued by the platform control hub chip, the logical write address, and the data to be written are received through the advanced host controller interface. Determine whether the data to be written is random access data. When the data to be written is random access data, the data is written into the reluctance random access memory or the resistive random access memory connected to the channel in the solid state hard disk.

10‧‧‧ Computing device

110‧‧‧Central Processing Unit

111‧‧‧ North Bridge Chip

113‧‧‧Dynamic Random Access Memory Controller

150‧‧‧ Dynamic Random Access Memory

160‧‧‧Direct media interface bus

170‧‧‧ Platform Control Hub Wafer

171‧‧‧Advanced Host Controller Interface

173‧‧‧ Solid State Drive

175‧‧‧CD player

20‧‧‧ Solid State Drive

210‧‧‧Processing unit

220‧‧‧Access interface

230‧‧‧ storage unit

220_0, 220_1, ..., 220_j‧‧‧ access subinterface

230_0_0, 230_0_1, ..., 230_j_i‧‧‧ storage subunit

420_0_0,...,420_0_i‧‧‧ wafer enable control signal

410_0‧‧‧Information line

S511~S535‧‧‧ method steps

1 is a system block diagram of a computer device in accordance with an embodiment of the present invention.

2 is a schematic diagram of a system architecture of a solid state hard disk according to an embodiment of the present invention.

Figure 3 is a block diagram of an access interface and a storage unit in accordance with an embodiment of the present invention.

Figure 4 is a schematic diagram showing the connection of an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention.

Figure 5 is a flow chart of a method of writing data in a processing unit in accordance with an embodiment of the present invention.

The following description is a preferred embodiment of the invention, which is intended to describe the basic spirit of the invention, but is not intended to limit the invention. The actual inventive content must be referenced to the scope of the following claims.

It must be understood that the "include" and "packages" used in this specification "", etc., is used to mean that there are specific technical features, numerical values, method steps, work processes, components, and/or components, but does not exclude the addition of additional technical features, numerical values, method steps, and operational processing. A component, component, or any combination of the above.

The words "first", "second", and "third" are used in the claims to modify the elements in the claims, and are not used to indicate a priority order, an advance relationship, or a component. Prior to another component, or the chronological order in which the method steps are performed, it is only used to distinguish components with the same name.

1 is a system block diagram of a computer device in accordance with an embodiment of the present invention. The computer device 10 includes at least a central processing unit 110, a DRAM (Dynamic Random Access Memory) 150, and a Platform Controller Hub Chip (PCH) 170. The central processing unit 110 can be implemented in a variety of ways, such as with dedicated hardware circuitry or general purpose hardware (eg, a single processor, multiprocessor with parallel processing capabilities, a graphics processor, or other computing capable processor), and Provides the required functionality when executing code or software. The central processing unit 110 includes a north bridge wafer 111, which is connected to the platform control hub wafer 170 using a direct media interface (DMI) bus, and the north bridge wafer 111 includes a dynamic random access memory controller 113 for accessing dynamics. The data in the random access memory 150. The platform control hub chip 170 can access connected devices through an Advanced Host Controller Interface (AHCI) 171, such as Solid State Drives (SSDs) 173, CD players 175, and the like. It should be noted here that the north bridge chip 111 is used to connect the high speed output / The device controls the hub chip 170 for connecting to a low-speed output/input device, for example, a solid-state hard disk, a CD player, a WiFi communication module, or the like.

2 is a schematic diagram of a system architecture of a solid state hard disk according to an embodiment of the present invention. The system architecture 20 of the solid state drive includes a processing unit 210 for writing data to a specified address in the storage unit 230 and reading data from a specified address in the storage unit 230. In detail, the processing unit 210 writes the data to the specified address in the storage unit 230 through the access interface 220, and reads the data from the specified address in the storage unit 230. The system architecture 20 uses a plurality of electronic signals to coordinate data and command transfer between the processing unit 210 and the storage unit 230, including a data line, a clock signal, and a control signal. The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transmit chip enable (CE), address latch enable (ALE), command extraction Control signals such as command latch enable (CLE) and write enable (WE). The access interface 220 can communicate with the storage unit 230 using a double data rate (DDR) protocol, such as an open NAND flash interface (ONFI), a double data rate switch (DDR toggle), or Other interface. The processing unit 210 can also communicate with the platform control hub wafer 170 via a designated communication protocol using an advanced host controller interface 171, such as a serial advanced technology attachment (SATA) or other interface. The platform control hub chip 170 can provide a logical block address (LBA) to the processing unit 210 through the advanced host controller interface 171 to indicate writing or reading data of a specific area. Access interface 220 is the most The efficiency of data writing can spread a piece of data with consecutive logical block addresses in different areas in different storage sub-units. Therefore, a Flash Translation Layer table (FTL) is needed to indicate in which storage sub-unit information the data of each logical block address is actually stored.

The storage unit 230 can include a plurality of storage subunits, each of which is implemented on a die, each communicating with the processing unit 210 using an associated access sub-interface. Figure 3 is a block diagram of an access interface and a storage unit in accordance with an embodiment of the present invention. The solid state drive 170 may include j + 1 access sub-interfaces 220_0 to 220_j. The access sub-interfaces may also be referred to as channels, and each access sub-interface is connected to i + 1 storage sub-units. In other words, i + 1 th sub-storage units share one accessor interface. For example, when the solid state hard disk 170 contains 8 channels ( j = 7 ) and each channel is connected to 4 storage units ( i = 3 ), the solid state hard disk 170 has a total of 32 storage units 230_0_0 to 230_j_i. The processing unit 210 can drive one of the access sub-interfaces 220_0 to 220_j to read data from the designated storage sub-unit. Each storage subunit has an independent wafer enable (CE) control signal. In other words, when data reading is to be performed on a specified storage subunit, it is necessary to drive the associated access subinterface to enable the wafer enable control signal of the storage subunit. In each channel, the 0th storage subunit may be a magnetoresistive random access memory (MRAM) or a resistive random access memory (RRAM), the first to The i storage subunits may be NAND flash memories. The access speed of the magnetoresistive random access memory or the resistive random access memory is faster than that of the NAND flash memory, and is more suitable for storing random access data. The 0th storage subunit can be used to store flash translation layer tables or randomly accessed data. NAND-type flash memory is not random access, but serial access. The platform control hub wafer 170 needs to write the value of the byte of the sequence to the NAND type flash memory to define the type of the request command (eg, read, write, erase, etc.), And the address used on this command. The address can point to a page (the smallest data block of a write job in flash memory) or a block (the smallest data block of an erase job in flash memory).

Figure 4 is a schematic diagram showing the connection of an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention. The processing unit 210 can select one of the connected storage sub-units 230_0_0 to 230_0_i through the access sub-interface 220_0 using the independent wafer enable control signals 420_0_0 to 420_0_j, and then select from the shared data line 410_0. Read the data at the specified location of the storage subunit.

Figure 5 is a flow chart of a method of writing data in a processing unit in accordance with an embodiment of the present invention. The processing unit 210 receives the logical write command, the logical write address, and the data to be written by the platform control hub chip 170 via the advanced host controller interface 171 (step S511), and determines whether the data to be written is randomly stored. The data is taken (step S531). If yes, the data is written into the 0th storage subunit of the channel connection (that is, the magnetoresistive random access memory or the resistive random access memory) (step S533); otherwise, the data is written to at least The first to ith storage subunits (i.e., NAND type flash memories) connected by one channel (step S535). In an example in step S531, the processing unit 210 can determine whether the length of the data to be written is greater than a threshold (eg, 1 MBytes). No random access data. When the length of the data to be written does not exceed a threshold, it is judged as random access data; otherwise, no. In another example in step S531, the processing unit 210 can determine whether the 22nd or 23rd auxiliary field bit (Auxiliary Field Bit 22 or 23) in the logical write command is raised. When the 22nd or 23th auxiliary field bit in the logical write command is raised, it is judged as random access data; otherwise, no.

Although the above-described elements are included in FIG. 1, it is not excluded that more other additional elements are used without departing from the spirit of the invention, and a better technical effect has been achieved. In addition, although the flowchart of FIG. 5 is executed in a specified order, without departing from the spirit of the invention, those skilled in the art can modify the order among the steps while achieving the same effect, and therefore, the present invention It is not limited to using only the order as described above. In addition, those skilled in the art may also integrate several steps into one step, or in addition to these steps, performing more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. On the contrary, this invention covers modifications and similar arrangements that are apparent to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest form to include all obvious modifications and similar arrangements.

10‧‧‧ Computing device

110‧‧‧Central Processing Unit

111‧‧‧ North Bridge Chip

113‧‧‧Dynamic Random Access Memory Controller

150‧‧‧ Dynamic Random Access Memory

160‧‧‧Direct media interface bus

170‧‧‧ Platform Control Hub Wafer

171‧‧‧Advanced Host Controller Interface

173‧‧‧ Solid State Drive

175‧‧‧CD player

Claims (10)

A computer device including a solid state hard disk, comprising: a central processing unit including a north bridge chip; a platform control hub chip including an advanced host controller interface, and the north bridge chip connected through a direct media interface bus; a solid state hard disk connected to the advanced host controller interface, wherein the solid state hard disk includes a plurality of channels, and each of the channels is connected to a magnetoresistive random access memory or a resistive random access memory. Perform random access. A computer device comprising a solid state drive according to claim 1, wherein each of the channels is further connected to a NAND type flash memory for serial access. The computer device comprising the solid state hard disk according to claim 1, wherein the magnetoresistive random access memory or the resistive random access memory stores data of a flash translation layer table. A computer device comprising a solid state drive according to claim 3, wherein the flash translation layer table is used to indicate in which storage subunit the data of each logical block address is actually stored. News. The computer device including the solid state hard disk according to claim 2, wherein the magnetoresistive random access memory or the resistive random access memory of each of the channels, and the NAND flash memory The body is enabled using a separate wafer enable control signal. A method of accessing a solid state hard disk, executed by a processing unit of a solid state hard disk, comprising: Receiving, by an advanced host controller interface, a logical write command, a logical write address, and a to-be-written data sent by a platform control hub chip; determining whether the data to be written is random access data; When the data to be written is random access data, the data is written into a magnetoresistive random access memory or a resistive random access memory connected to one of the solid state hard disks. The method for accessing a solid state hard disk according to claim 6, further comprising: when the data to be written is not random access data, writing the data to one of the connected channels of the solid state hard disk NAND type flash memory. The method for accessing a solid state hard disk according to claim 6, wherein in the step of determining whether the data to be written is random access data, the method further comprises: determining whether the length of the data to be written is Exceeding a threshold value, wherein when the length of the data to be written does not exceed the threshold, the data to be written is random access data. The method for accessing a solid state drive according to claim 6, wherein in the step of determining whether the data to be written is random access data, the method further comprises: determining one of the logical write commands. Whether the 22 or 23 auxiliary field bit is raised, wherein when the 22nd or 23rd auxiliary field bit is raised, the data to be written is random access data. The method of accessing a solid state hard disk according to claim 7, wherein the solid state hard disk comprises a plurality of channels, each of the channels connecting the magnetoresistance The random access memory or the resistive random access memory is used for random access, and each of the channels is connected to the NAND type flash memory for serial access.