TWM548816U - Storage device using host memory buffer - Google Patents

Abstract

A storage device using a host memory buffer is provided. The storage device includes: a non-volatile memory; a dynamic random access memory for storing an address mapping table of the non-volatile memory; and a controller for receiving a sequential writing command of writing data from a host, wherein the writing data is stored in a host memory buffer of a system memory of the host. The controller retrieves the address mapping table from the dynamic random access memory and determines a physical block address of the writing data to be written into the non-volatile memory. After the controller determines the physical block address of the writing data to be written into the non-volatile memory, the controller writes the writing data from the host memory buffer directly to the non-volatile memory according to the physical block address.

Description

Storage device using host memory buffer

This creation relates to storage devices, and more particularly to a storage device that utilizes a host memory buffer.

With the development of technology, the storage speed of storage devices in computer systems is also increasing. For example, Solid-state Disk is a non-volatile memory that can perform fast data access. In recent years, non-volatile memory transmission standards have been set by various computer manufacturers, such as Advanced Host Controller Interface (AHCI) and Non-volatile Memory Express (NVMe). )and many more.

The above two standard steps are interface standards including instruction set, flash memory access control, register transfer level, and driver layer on the storage device and the operating system side.

Furthermore, NVME is a new type of storage device controller that improves the traditional AHCI, which can improve the use of system resources, such as using system multi-core instructions, reducing unnecessary scratchpad control, and so on. In the traditional computer system, the main control terminal (ie, the central processing unit and the platform control hub) and the storage device (such as the NVME solid state drive) can perform high-speed data transmission, for example, through the PCIe Gen 3x4 interface.

However, when a conventional computer system wants to sequentially write data to a storage device, it still needs to write the data to a static random access memory (SRAM) in the controller of the storage device, and then the static random access memory. The data in is written to dynamic random access memory (DRAM). At the same time, the controller queries the address mapping table in the dynamic random access memory, and then writes the data in the DRAM into the NAND flash memory.

In the current solid-state hard disk drive, when the 8CH2CE 512GB solid state hard disk drive is expanded to 8CH4CE 1TB solid state drive, the write speed is almost the same, for example, it can only be maintained at 2100MB/ s or so, where CH is the number of channels, and CE is the chip enable.

Therefore, the controller in the conventional solid-state hard disk drive needs to first arrange the data to be written in the static random access memory of the controller, and then write the flash memory, but the write bandwidth is still the distance. The theoretical bandwidth of DMI is still 4GB/s.

Therefore, there is a need for a storage device that utilizes a host memory buffer to solve the above problems of conventional storage devices.

The present invention provides a storage device using a host memory buffer, comprising: a non-volatile memory; a dynamic random access memory for storing an address map of the non-volatile memory; a controller for receiving a continuous write command of a write data from a master terminal, wherein the write data is stored in one of the system memory of the master terminal, the host memory buffer Where the controller obtains the bit from the dynamic random access memory Address mapping table, and determining the physical data block address of the write data in the non-volatile memory; wherein after the controller determines the write data in the physical block address in the non-volatile memory The controller controls the memory of the system, and writes the write data directly to the non-volatile memory by the host memory buffer in the system memory according to the physical block address.

In an embodiment, the storage device and the host end comprise a plurality of transmission channels.

In one embodiment, wherein the storage device supports the Fast Non-Volatile Memory (NVMe) standard.

In one embodiment, the controller includes a static random access memory, and the write data is written to the non-volatile memory without passing through the static random access memory.

In one embodiment, the host includes a central processing unit and a platform control hub, and the platform control hub is coupled to the controller via a transmission port.

In one embodiment, the system memory of the master is a dynamic random access memory.

This creation provides a storage device that utilizes a host memory buffer. When the host wants to write continuous data to a storage device (such as a solid state drive), the controller of the storage device can directly control the host memory buffer in the system memory of the host, and The data to be written to the storage device is directly written into the non-volatile memory (such as flash memory) in the storage device by the host memory buffer to achieve faster writing speed without being limited to storage. The buffer in the device drags the write speed.

100‧‧‧ computer system

110‧‧‧Central Processing Unit

120‧‧‧System Memory

121‧‧‧Master memory buffer

130‧‧‧ Platform Control Hub

131‧‧‧Transportation

140‧‧‧Storage device

141‧‧‧ Controller

142‧‧‧ volatile memory

143‧‧‧ Dynamic Random Access Memory

144-147‧‧‧ Non-volatile memory

150-153‧‧‧ channel

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing a computer system in accordance with an embodiment of the present invention.

In order to make the above objects, features and advantages of the present invention more comprehensible, the following detailed description of the preferred embodiments and the accompanying drawings are set forth below.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing a computer system in accordance with an embodiment of the present invention. In one embodiment, the computer system 100 includes a central processing unit 110, a system memory 120, a platform control hub (PCH) 130, and a storage device 140. The central processing unit 110 and the platform control hub 130 may be referred to as a host. The storage device 140 includes a controller 141 that supports the NVMe standard for controlling access to the non-volatile memory 144-147.

The system memory 120 is, for example, a dynamic random access memory (DRAM).

The non-volatile memory 144 to 147 is, for example, a NAND flash memory, but the present creation is not limited thereto. In some embodiments, the non-volatile memory 144-147 is a different non-volatile memory block segmented in a non-volatile memory, and the creation is not limited to non-volatile memory. The number of non-volatile memory blocks.

In some embodiments, the controller 141 can be, for example, an application oriented Application-Specific Integrated Circuit (ASIC) or a circuit having similar functions, but the creation is not limited thereto.

In addition, the controller 141 includes a volatile memory 142, such as a static random access memory, which can be used to temporarily store data to be written from the host. In some embodiments, the volatile memory 142 may not be used to temporarily store data from the host to be written.

In addition, the platform control hub 130 and the storage device 140 are connected by a PCIe bus, for example, a set of PCIe Gen 3x4 channels, for example, including channels 150-153.

Further, the platform control hub 130 is connected to the controller 141 via the transport port 131 and the channels 150-153 for data transmission. In some embodiments, the transport port 131 may also be referred to as a root port.

It should be noted that the function of the host memory buffer (HMB) is defined in the NVMe specification. This function utilizes the feature that the NVMe storage device of the PCIe interface can directly access the data of the system memory, and uses the capacity of the system memory to replace the function of the static random access memory in the storage device, thereby avoiding writing. A write bottleneck was encountered when entering data into NAND flash memory.

However, when the controller of the conventional storage device writes data, it must load the data directly into the static random access memory, and the work of reading the address mapping table by the dynamic random access memory is performed for sequential writing. In terms of continuous write behavior, it will still be affected to a certain extent, meaning that the write speed will decrease.

In the computer system 100 of the present creation, the system memory 120 is planned A master memory buffer 121 is divided to replace the function of the volatile memory 142 in the controller 141.

For example, the author uses the function of the host memory buffer defined by the NVMe standard to replace the static random access memory for writing data. In addition, the dynamic random access memory in the storage device 140 is a full-time access and arrangement of the FTL table.

Finally, the controller 141 can directly issue a control command to the system memory 120 to write the data from the host memory buffer 121 in the system memory 120 to the non-volatile memory 144-147.

Furthermore, the data writing method proposed by the present creation does not conflict with the function of the host memory buffer defined by the current NVMe standard. For example, the function of the original host memory buffer is to replace the dynamic random access memory in the solid state drive, and to hand over the space of the address mapping table in the original solid state drive. System memory is used for storage, but this traditional method is only to save the cost of the solid state drive, and it does not help the performance of the solid state drive.

For high-end solid state drives, the efficiency of configuring dynamic random access memory to access the flash translation layer (FTL) address mapping table is still better, especially today's solid state hard The capacity of the disc player is getting larger and larger, and the change is that the size of the address mapping table of the flash translation layer is also proportionally increased.

In an embodiment, when the central processing unit 110 wants to write data to the storage device 140, the central processing unit 110 temporarily stores the data to be written in the main memory memory buffer 121 in the system memory 120. .

At this time, the controller 141 of the storage device 140 obtains the address mapping table of the flash translation layer from the dynamic random access memory 143, and determines the physical block to be written in the non-volatile memory 144~147. Physical block address (PBA). After the controller 141 determines the physical block address to be written in the non-volatile memory 144~147, the controller 141 can directly control the system memory 120 and write the data according to the address mapping table. The data is directly written into the non-volatile memory 144~147 by the host memory buffer 121, and does not need to pass through the volatile memory 142 of the controller 141, thereby achieving the division of the write behavior.

Furthermore, when the host terminal wants to continuously write to the storage device 140, it can no longer be limited by the speed limit of the volatile memory 142 (for example, access memory requires communication time).

In summary, the present invention provides a storage device that utilizes a host memory buffer. When the host wants to write continuous data to a storage device (such as a solid state drive), the controller of the storage device can directly control the host memory buffer in the system memory of the host, and The data to be written to the storage device is directly written into the non-volatile memory (such as flash memory) in the storage device by the host memory buffer to achieve faster writing speed without being limited to storage. The buffer in the device drags the write speed.

The present invention is disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any person having ordinary skill in the art can make some changes without departing from the spirit and scope of the present invention. Retouching, therefore, the scope of protection of this creation is subject to the definition of the scope of the patent application attached.

100‧‧‧ computer system

110‧‧‧Central Processing Unit

120‧‧‧System Memory

121‧‧‧Master memory buffer

130‧‧‧ Platform Control Hub

131‧‧‧Transportation

140‧‧‧Storage device

141‧‧‧ Controller

142‧‧‧ volatile memory

143‧‧‧ Dynamic Random Access Memory

144-147‧‧‧ Non-volatile memory

150-153‧‧‧ channel

Claims (6)

A storage device using a memory buffer of a host terminal, comprising: a non-volatile memory; a dynamic random access memory for storing an address mapping table of the non-volatile memory; and a controller, a continuous write command for receiving a write data from a host, wherein the write data is stored in one of the system memory of the host, the host memory buffer, wherein the control Obtaining the address mapping table by the dynamic random access memory, and determining the physical data block address of the write data in the non-volatile memory; wherein the controller determines that the write data is in the non-volatile memory After the physical block address in the volatile memory, the controller controls the system memory, and the written data is written by the host memory in the system memory according to the physical block address. The buffer is written directly to the non-volatile memory. The storage device of claim 1, wherein the storage device and the main control end comprise a plurality of transmission channels. The storage device of claim 2, wherein the storage device supports the Fast Non-Volatile Memory (NVMe) standard. The storage device of claim 3, wherein the controller comprises a static random access memory, and the written data is written to the non-volatile memory without passing through the static random access memory. The storage device of claim 1, wherein the main control terminal comprises a central processing unit and a platform control hub, and the platform controls the collection line. The device is connected to the controller through a transmission port. The storage device of claim 1, wherein the system memory of the main control terminal is a dynamic random access memory.