TW201636823A - Systems, apparatuses, and methods for K nearest neighbor search - Google Patents

Abstract

Systems, apparatuses, and methods for k-nearest neighbor (KNN) searches are described. In particular, embodiments of a KNN accelerator and its uses are described. In some embodiments, the KNN accelerator includes a plurality of vector partial distance computation circuits each to calculate a partial sum, a minimum sort network to sort partial sums from the plurality of vector partial distance computation circuits to find k nearest neighbor matches and a global control circuit to control aspects of operations of the plurality of vector partial distance computation circuits.

Description

System, device and method for K nearest neighbor search

The field of the invention relates generally to computer processor architectures and, more particularly, to nearest neighbor searches.

Background of the invention

In many applications, it is desirable to have a fast and efficient nearest neighbor search for a multidimensional feature (point) of a data set. For example, this type of search facilitates areas such as image reconstruction and machine learning. There are several ways to search for neighbor data sets recently. In the nearest neighbor search, given a set of points and an input instance (query point) in a space, a search is performed to find a point in the set that is closest to the input instance.

In accordance with an embodiment of the present invention, an apparatus is specifically provided that includes: at least one vector portion distance calculation circuit to calculate a partial sum and a cumulative distance of a set of vectors in a search space; a minimum order network to sort a set of bits selected from one of the cumulative distances, indicating a minimum value of the set of selected bits from the vectors in the search space and whether the minimum value is unique; and a global control circuit to receive the Minimizing an output of the network and controlling the at least one vector Partial distance calculates various aspects of the operation of the circuit.

101‧‧‧Query object vector

103_0~103_N‧‧‧ Vector 0~N partial distance calculation

105‧‧‧Global Control

107‧‧‧Minimum sorting network

109‧‧‧0 level comparison node

111‧‧‧"k" level comparison node

203‧‧‧Vector partial distance calculation

205‧‧‧data component calculator circuit

207‧‧‧Local control circuit

209‧‧‧ shifter

211‧‧‧Compressor tree

213‧‧‧Factor

215‧‧‧Adder

219‧‧‧Selector

301‧‧‧Querying objects

303‧‧‧Stored object latch

305‧‧‧|a-b|

307‧‧‧Selection from control

309‧‧‧Selector

311‧‧‧Multiplier

313‧‧‧Adder

401‧‧‧Querying objects

403‧‧‧ Stored object latch

405‧‧‧|a-b|

407‧‧‧Selection from control

409‧‧‧Selector

501‧‧‧ Global Indicators

503‧‧‧Vector Address

505‧‧‧Minimum address

509‧‧‧Minimum accuracy

511‧‧‧AND gate

513‧‧‧AND gate

515‧‧‧Remove

517‧‧‧Local calculation control

901‧‧‧OR gate

903‧‧‧12b global mask

905‧‧‧Priority encoder

907‧‧‧OR tree

911‧‧‧Selector

913‧‧12x12b lookup table

1001‧‧‧OR gate

1003‧‧‧XOR gate

1005‧‧‧OR gate

1007‧‧‧|a-b|>ε

1009‧‧‧AND gate

1501~1527‧‧‧

1600‧‧‧ pipeline

1602‧‧‧ extraction

1604‧‧‧ Length decoding

1606‧‧‧Decoding

16016‧‧‧ Distribution

1610‧‧‧Rename

1612‧‧‧ Schedule

1614‧‧‧Scratchpad read/memory read

1616‧‧‧implementation phase

16116‧‧‧Write back/memory write

1622‧‧‧Exception handling

Submitted 1624‧‧

1630‧‧‧ front unit

1632‧‧‧ branch prediction unit

1634‧‧‧Command cache unit

1636‧‧‧Instructed TLB unit

16316‧‧‧ instruction extraction

1640‧‧‧Decoding unit

1650‧‧‧Execution engine unit

1652‧‧‧Rename/Distributor Unit

1654‧‧‧Retirement unit

1656‧‧‧scheduler unit

16516‧‧‧Physical register unit

1660‧‧‧Executing a cluster

1662‧‧‧Execution unit

1664‧‧‧Memory access unit

1670‧‧‧ memory unit

1672‧‧‧Information TLB unit

1674‧‧‧Data cache unit

1676‧‧‧L2 cache unit

1690‧‧‧ core

1700‧‧‧ instruction code

1702‧‧‧Circular network

1704‧‧‧Local subset of the L2 cache

1706‧‧‧L1 cache

1708‧‧‧ scalar unit

1710‧‧‧ vector unit

1712‧‧‧ scalar register

1714‧‧‧Vector register

1706A‧‧‧L1 data cache

1720‧‧‧ Mixing unit

1720A, 1722B‧‧‧ Digital Conversion

1724‧‧‧Copy

1726‧‧‧Write mask register

1728‧‧16 wide vector ALU

1800‧‧‧ processor

1802A~N‧‧‧ core

1804A~N‧‧‧ cache unit

1806‧‧‧Shared cache unit

1808‧‧‧Special Logic

1810‧‧‧System Agent Unit

1812‧‧‧ ring

1814‧‧‧Integrated memory controller unit

1816‧‧‧ Busbar Controller Unit

1900‧‧‧ system

1910‧‧‧ Processor

1915‧‧‧ Processor

1920‧‧‧Controller Hub

1940‧‧‧ memory

1945‧‧‧coprocessor

1950‧‧‧IOH

1960‧‧‧I/O

1990‧‧‧GMCH

1995‧‧‧Connect

2000‧‧‧ system

2014‧‧‧I/O device

2015‧‧‧ processor

2016‧‧‧First bus

2018‧‧‧ Bus Bars

2020‧‧‧Second bus

2022‧‧‧ keyboard and / or mouse

2024‧‧‧Audio I/O

2027‧‧‧Communication device

2028‧‧‧Data storage

2030‧‧‧Program code and data

2032, 2034‧‧‧ memory

2038‧‧‧Synthesis processor

2039‧‧‧High-performance interface

2050, 2052‧‧ ‧ point-to-point interconnection

2072, 2082‧‧‧IMC

2076, 2078, 2086, 2088, 2094, 2098‧‧‧P-P

2070‧‧‧ processor

2072, 2082‧‧‧CL

2080‧‧‧Processor/coprocessor

2090‧‧‧ Chipset

2092, 2096‧‧‧I/F

2100‧‧‧ system

2114‧‧‧I/O devices

2115‧‧‧Traditional I/O

2200‧‧‧ system single chip

2202‧‧‧Interconnect unit

2210‧‧‧Application Processor

2220‧‧‧coprocessor

2230‧‧‧SRAM unit

2232‧‧‧DMA unit

2240‧‧‧Display unit

2302‧‧‧High-level language

2304‧‧x86 compiler

2306‧‧‧x86 binary code

2308‧‧‧Alternative Instruction Set Compiler

2310‧‧‧Alternative instruction set binary code

2312‧‧‧Command Converter

2314‧‧‧Processor without an x86 instruction set core

2316‧‧‧Processor with at least one x86 instruction set core

The present invention is illustrated by way of example only, and not by way of limitation One embodiment demonstrates a high order kNN accelerator organization.

2 illustrates an exemplary vector portion distance calculation circuit in accordance with an embodiment.

3 illustrates an exemplary vector partial distance summation of a square difference data element calculation circuit, in accordance with an embodiment.

4 illustrates an exemplary vector partial distance summation of an absolute difference data element calculation circuit, in accordance with an embodiment.

FIG. 5 illustrates an exemplary local control circuit in accordance with an embodiment.

FIG. 6 illustrates an exemplary Manhattan binning process in accordance with an embodiment.

Figure 7 illustrates an exemplary data element Euclidean distance sorting process, in accordance with an embodiment.

Figure 8 illustrates an exemplary ranking process using one of the partial distances, in accordance with an embodiment.

Figure 9 illustrates an exemplary global control circuit in accordance with an embodiment.

Figure 10 illustrates an exemplary level 0 comparison node in accordance with an embodiment. Circuit.

Figure 11 illustrates an exemplary k-level comparison node circuit in accordance with an embodiment.

Figure 12 illustrates an exemplary 8-bit/16-bit reconfigurable computing circuit in accordance with an embodiment.

Figure 13 illustrates an exemplary partial distance calculation for the sum of squares of 16-bit elements, in accordance with an embodiment.

Figure 14 illustrates a cosine similarity calculation (1d distance) circuit and an exemplary partial distance calculation for inner product in accordance with an embodiment, in accordance with an embodiment.

15A-B illustrate an exemplary method of a kNN search, in accordance with an embodiment.

Figure 16A is a block diagram illustrating an exemplary sequential pipeline and an exemplary scratchpad renaming, out of order distribution/execution pipeline, in accordance with an embodiment of the present invention.

Figure 16B is a block diagram illustrating an exemplary embodiment of a sequential structure core and an exemplary scratchpad renaming, out of order distribution, to be included in a processor, in accordance with an embodiment of the present invention. Execute both of the structural cores.

17A-B illustrate a more specific exemplary sequential core structure block diagram that will be one of several logical blocks (including other cores of the same type and/or different types) in a wafer.

Figure 18 is a block diagram of a processor 1800, which may have more than one core, possibly having an integrated record, in accordance with an embodiment of the present invention. Recall the body controller, and possibly have an integrated graphic.

19-22 are block diagrams of exemplary computer structures.

23 is a block diagram comparing the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set, in accordance with an embodiment of the present invention.

Detailed description of the preferred embodiment

In the following description, numerous specific details are set forth. However, it is understood that the embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the understanding of the specification.

References to "an embodiment", "an embodiment", "an example embodiment" and the like in this specification indicate that the described embodiments may include a particular feature, structure, or characteristic, but each embodiment does not This particular feature, structure, or characteristic must be included. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is recognized that such features, structures, or characteristics may be combined with other embodiments within the knowledge of those skilled in the art. , whether or not it is clearly described.

One method of recent neighbor search is to calculate the distance from the input instance to each point in a data set, and to track the shortest distance. However, this simple approach may not be feasible for larger data sets. This distance calculation can perform all features one feature at a time using a k-dimensional (k-d) tree An exhaustive check to complete. Therefore this method is slow and has high power consumption.

Another recent neighbor method uses the Voronoi diagram. Each Voronoi diagram divides a plane into equal nearest neighbor regions, which are called cells. This can be illustrated as a number of cells, each with a feature (point). In theory, a Voronoi diagram can be used to find this feature in a particular cell to find a "best match" feature for any input instance. However, as shown, the Voronoi cells have highly irregular shapes and are difficult to calculate (they require a lot of time and processor at the same time) and use. In other words, the Voronoi diagram itself is not a convenient or efficient method for searching for nearest neighbor features.

Embodiments of systems, devices, and methods that will be used in improving nearest neighbor search are set forth in detail herein that overcome the shortcomings of the above methods. In summary, given an input (i.e., an observation), a feature that finds the best match in a feature space (i.e., a dictionary of features) is achieved. This method is particularly suitable for feature vectors that are typically sparsely present in high dimensional vector spaces (note that features are vectors in this specification, and therefore features and feature vectors are used interchangeably).

Described below is an embodiment of a k-nearest neighbor (kNN) accelerator that adjusts the accuracy of the equidistant calculation to minimize the number of levels required to query each nearest neighbor. Many candidate vectors are removed from the search space using only low accuracy calculations, while the remaining candidates closer to the nearest neighbor are removed with higher accuracy at a later iteration to announce a winner. . Since most calculations require lower accuracy and Consuming less energy, the overall kNN energy efficiency is significantly improved. Typically, this kNN accelerator is part of a central processing unit (CPU), graphics processing unit (GPU), and the like. However, the kNN accelerator can be external to the CPU, GPU, and the like.

Figure 1 illustrates a high order kNN accelerator in accordance with an embodiment. In this accelerator, there are some main components including a plurality of vector local distance calculation circuits 103_0 to 103_N, a global control circuit 105, and a minimum order network 107. Each of these components will be discussed in detail below.

A query object vector 101 is input to the plurality of vector portion distance calculating circuits 103_0 to 103_N for calculation of the partial distance. What is not shown is the storage for this rendered object vector. The partial distance calculation circuits 103_0 to 103_N calculate a partial distance and a cumulative distance for each reference vector and provide a valid indication to the minimum ordering network 107. Using multiple iterative partial distance calculations with less significant bit precision between a query 101 and a stored vector and improving as detailed in this iteration in each iteration is more energy efficient than in the past. Partial distance calculation involves calculating different distance metrics (such as Euclidean (square sum) distance and Manhatan (sum of absolute difference)) in each iteration to calculate fewer bits from the MSB's full distance from the MSB . This partial result is added to the cumulative completed distance with the correct validity, thereby increasing the accuracy of the lower significant bit as the calculation continues.

FIG. 2 illustrates an exemplary vector portion distance calculation circuit 203 in accordance with an embodiment. The vector is made up of a number of dimensions, each of which is represented by 8b in this example. The individual distances in each dimension are first Calculated by 205 then they are summed to get the total distance at 211. A local control circuit 207 provides an indication of which bits are to be selected in the different data element calculator circuit 205.

As mentioned above, several different types of distance metrics can be used, thus having different data element calculator circuits 205. When an absolute difference sum (Manhatan distance) metric is used, selecting the appropriate two bits (2b) from the absolute difference of each vector element and summing them up is done in the vector portion distance calculation circuit 203. of. 3 illustrates an exemplary vector partial distance sum of a squared difference (Euclidean distance) data element calculator circuit 205, in accordance with an embodiment. As shown, a portion of a query object (8 bits as shown) and a portion of a stored object (the same number of bits) have an absolute difference (|ab|) calculated by the hardware and the result The particular bit is selected using a multiplexer and a control signal. In some embodiments, the control signal provided by a local control circuit will be detailed below. The results of the multiplex are multiplied (a pair of 2bx2b multiplications) and then added. In this example, the output is a 5-bit value that represents a portion of the distance when calculating the square of the difference. These are added by the compressor tree 211 to calculate a portion of the Euclidean distance of the entire vector.

When using a sum of absolute difference (Manhatan distance) metric, the appropriate two bits (2b) are selected from the absolute difference of each vector element and added up in the vector portion distance calculation circuit 203. Completed. 4 illustrates an exemplary vector partial distance sum of an absolute difference data element calculator circuit 205, in accordance with an embodiment. As shown, a part of the query object (8 bits as shown) and a storage object (the same number of bits) A portion has an absolute difference (|a-b|) calculated by the hardware and the particular bit of the result is selected using a multiplexer and a control signal. In some embodiments, the control signal provided by a local control circuit will be detailed below. In this example, the output is a 2-bit value.

This part of the SAD calculation reduces the size of the compressor tree by a factor of four, and this part of the Euclidean metric calculation replaces the 8-bit by 8-bit multiplier of each vector element with a pair of trivial 2-bit multipliers. Therefore, the area of the compressor tree 211 is reduced by a factor of three. This non-obvious construction of the Euclidean distance ensures that any subsequent lower MSB refinement will not affect any higher bits beyond 1 after processing a higher MSB bit, as shown below for Figure 3. Discussed in 4, 6, and 7. Figure 7 illustrates an embodiment of a complete squared difference operation (for calculating the Euclidean distance) that is broken up into a partial computational iteration calculated by the exemplary circuit of Figure 3. Figure 7 illustrates that by performing the calculations and ordering as shown in the display order, the computational operations on the lower order bits do not disturb the processed higher order bits by more than one. Similarly, Figure 4 illustrates an embodiment of the circuit for each component and Figure 6 illustrates an example of the corresponding computational operation performed by the circuit for the Manhattan distance. Figure 6 illustrates that by performing the calculations and ordering as shown in the display order, the computational operations on the lower order bits do not disturb the processed higher order bits by more than one.

In some embodiments, a single circuit is used to reconfigure between different metrics due to a common hardware data path.

A compressor tree 211 adds the outputs of the data element distance calculator to each of the outputs. In a 256-dimensional vector of Euclidean distance, this output is a 13-bit value. The output of the compressor tree 211 will be Send to a shifter 209. Typically, this shifter is a right shift shifter, however, depending on the bit material order configuration, it can be a left shift shifter. In most embodiments, the shifting element is controlled by local control circuitry 207. The shifter aligns the partial distance with respect to the correct validity of the cumulative distance.

The flip flop 213 stores the accumulated distance from the previous iteration and the output of the adder 215 is the cumulative distance in the current iteration. This value is written to the flip flop 213 at the beginning of the next iteration. The selector 219 selects the 2b from the cumulative distance based on the global indicator. It also selects the carry output from the portion and the previous accumulated distance to the 2b position.

The local control circuit 207 takes psumi as an input and modifies only the higher bit as a psum value (e.g., 3 bits) before passing it to the sorting network 107. A valid bit is also passed to the minimum ordering network 107. FIG. 5 illustrates an exemplary local control circuit in accordance with an embodiment. The local control circuit controls several different aspects of the vector portion distance calculation circuit, as described above. The circuit receives a global metric from a global control unit (described in more detail below) along with a psumi from the selector 219 and a minimum sum, address, and precision indication from the minimum ordered network 107.

As shown, the local control circuit takes the address of the vector being processed and a minimum address from the minimum ordering network 107 and uses a comparison circuit to determine if they are equal. Logically AND from the output of the comparison and the minimum precision from the minimum ordering network 107 to aid in determining No, the object vector does not need to be processed any more. In particular, the output is used in the calculation of a valid bit such as through the AND gate as shown. The local control circuit uses the minimum sum, psumi, and global indices to generate a removal signal, and a local calculation signal (for controlling the different data component calculator circuits 205) as shown. Vector processing can be stopped for one of two reasons - 1) the current vector is declared as a winner or 2) the current vector is removed from the search space when it is guaranteed not to be the nearest neighbor . In the above description, the "complete" signal is determined for the former. This reversal of this signal (illustrated as going through a small turn to enter the AND gate 513) affects the valid signal. If the "complete" is determined, the valid signal will be de-judged. The remaining logic that affects the effect determines if the vector is not complete but is still part of the search space. The removal signal indicates that the vector was removed from the search space in the current iteration and this information is used by the global control. The circuit shown in Figure 5 also generates a clock from the global CLK signal to control the clock of the storage element (including 213). The local control circuit also receives "computation control" from the global control circuit, which is then passed to the partial distance calculation 205 and the shifter circuit 209.

Essentially, the local control circuit provides global state control across all vectors for a local state control of each vector to record distance calculation states and iterations in which they are removed such that when calculating an ordered list of k > 1 The previous distance calculations and comparisons can be used again.

Partial distance calculations and sorting iterations are interleaved as shown in Figures 6 and 7. 6 illustrates an exemplary Manhattan shift calculation and sorting process in accordance with an embodiment, and FIG. 7 illustrates an exemplary data component in accordance with an embodiment. Euclidean distance calculation and sorting processing. In these figures the letters (a, b, c, and d) are the 2b components of the absolute difference between the 8b elements of the queries and reference vectors. As shown, the typical procedure is a computational iteration by vector partial distance calculation circuits 103_0 through 103_N followed by a ranking in the minimum ordering network 107. However, there may be times when there is no computational iteration between consecutive sorting iterations as shown in Figure 7.

The minimum ordering network 107 performs window based ordering. In particular, this sorting network handles a much smaller bit window starting from a portion of the most significant bit (MSB) of the calculated distance, allowing further partial calculations to be used with much smaller comparator circuits and The earlier removal of the vector candidate.

For example, in some embodiments, the sequencing network processes only one window of one bit from the MSB to the LSB cumulative vector distance in each iteration (Figures 6 and 7). This allows for a high degree of parallelism with very low hardware complexity. Since this computational refinement at lower bits can affect the number of bits processed in the MSB up to one, the sequencing network 107 also needs to process the carry output generated from the current iteration of the current 2b window. Thus, the sorting network 107 compares, for example, the number of 3b at each node 109 and 111 (the sum of the carry output and 2b). In comparison, for a 256-dimensional vector distance comparison (8b per component), a conventional sorting network would require a 24b comparator at each node.

The sorting network 107 broadcasts the obtained minimum 3b result globally and local control for the respective vector distance calculations to compare their 3b psum (carry output with the sum of 2b) to see the broadcast result to see if the particular vector is available. It is removed in distance refinement calculations and comparisons from further use of the global domain 105 and local control circuitry.

Since the lower order calculation can affect the currently processed window to one in a future iteration, for the removal of the candidate, all 3b comparisons in the local control and sequencing network 107 require a difference of more than one. For the same reason, the local control also considers whether a particular vector is greater than one in the previous iteration. Using an accurate signal, the sequencing network 107 indicates whether the minimum value of the discovery is unique. The sorting iteration continues until a unique recent vector is found or reaches the LSB. The feedback from the sorting network removes the candidate vectors from further distance calculations and comparisons, resulting in up to a 3x reduction in computation.

Figure 8 illustrates an exemplary ranking process using one of the partial distances, in accordance with an embodiment. Since the vector candidates are removed when the best candidate is found, their local state control stores the iterations in which they were removed (as in the 1ptr signal in Figure 5 and the block in Figure 8). Show).

Meanwhile, when the global control indicator moves forward (toward the LSB), even if a single vector is discarded, a 1 is written into the associated bit position of a global binary mask (which is stored) In the global control circuit 105). After the first vector is found, the global binary mask indicates to the global control logic 105 that the global metric needs to jump back to where the set of vectors may contain the next nearest neighbor. The process continues iteratively and is illustrated for the second and third nearest neighbor searches in FIG. When a global metric has been hopped back to the MSB, only those vectors whose iterative state matches the global metric location will become active. Closer to the The nearest neighbor's vector will be removed at a closer global indicator position. This technique of maintaining state has three major advantages over a traditional sorting method that simply removes the nearest neighbor and performs the entire calculation and sorting process from scratch - (a) it is reused in the previous order Partial distance calculations that have been completed at the level, (b) reduce the number of vectors that need to be compared by using the already calculated comparison, and (c) do not need k to be predefined to minimize the calculation for any ranking level and Comparison. Using the advantages of such control calculations and comparison reuse, quantify the incremental cost of finding the next nearest neighbor from X (eg, 256) vectors (eg, 256 8-b elements per vector) After 3 nearest neighbors have been found. A conventional sorting technique will result in finding the nearest vector from the remaining 253 candidate vectors, and the proposed control will result in a reduction of 19X for this search space and a 20X reduction for this associated calculation.

In this illustration, a 2-bit window from a partial distance of the vectors is processed. The arrows pointing to the right are from the valid bits of the local control circuit. In cycle 0, the seventh comparison is turned off because it is greater than one than the minimum value, so the vector can be removed. This removal is stored in the local control circuit. This process is performed as described in detail above. If all vectors perform all partial sum calculations, the resulting distance will match the complete distance, which is displayed on the far left for reference only.

Figure 9 illustrates an exemplary global control circuit in accordance with an embodiment. As shown in FIG. 1, the global control circuit 105 receives minimum precision, address, and sum values from the minimum ordering network 107. The minimum accurate signal and a signal indicating a global indicator at one of the LSB locations are logically ORed and used As a selection signal for a global indicator output, it is not one of the previous global indicator increments or one that has been encoded (priority) from a global binary mask, as shown. The global binary mask is made up of an OR tree received from the local control circuit 207 to remove the signal. The calculation of the calculation control signal uses a lookup table that is used as an index to the table. Until a unique minimum or LSB is not found, the global indicator continually moves toward the LSB for each iteration (which is incremented by one to achieve this). This situation is tested by the OR gate 901. Otherwise, the indicator rolls back to the nearest 1 in the binary mask to find the next nearest neighbor. Even if a vector is removed, a 1 is written to the indicator position within the binary mask, otherwise a 0 is written. The OR tree 907 detects that even if only one vector is removed (these removal signals are generated by all of the respective local control circuits), the subsequent demultiplexer uses the global metric to set the input to the appropriate location to be 1, And when the next iteration begins (the rising edge of CLK) this will be written to the global binary mask (held in store 903). This position closest to 1 is calculated by the priority encoder 905. This calculation controls the broadcast to all vectors based on the indicator position. By storing them in a lookup table 913, this can be programmable and the appropriate control signals can be read based on the indicator.

Looking at the minimum ordering network 107 in more detail, there are two types of comparison node-0 and "k" level nodes. Figure 10 illustrates an exemplary level 0 comparison node circuit in accordance with an embodiment. As shown, the circuit accepts a valid bit that is used to indicate whether the psum is from a vector that is part of the search space. If the valid bit associated with a psum is 0, Then the psum will be ignored in a comparison of nodes.

The adjacent valid bits are logically ORed to provide a level 0 effective bit. These significant bits are also XOR and ORed with a signal to produce an exact bit that indicates that the absolute difference between the input sums is greater than a threshold ε. A precise bit if "1" means that no other vector is close. Finally, the adjacent sums are also compared to each other, and the result is ANDed with one of the valid bits to form a selection of the address and the sum to be output. The overall output of the level 0 comparison node is a bit address, a valid bit, an exact bit, and a sum. The output is valid to indicate if the result is valid (at least one of the valid inputs must be true to satisfy this condition). The result of the comparison is added to the lowest order bit of the found minimum vector (in this case bit [0] because it is the first comparison level). The output precision signal indicates that the two vectors are not equivalent or close (if ε is 1, the difference is greater than 1; or if ε is 0, the difference is greater than 0). If only one of the inputs is valid, the XOR 1003 determines the exact signal, regardless of the result of the comparison (because the comparison is not important if one of the sums is invalid). The comparison results to the smaller sum along with its input address to the next node.

Figure 11 illustrates an exemplary k-level comparison node circuit in accordance with an embodiment. The circuit accepts the adjacent outputs from the address (e.g., level 0) of the preceding stage (e.g., level 0), and supplies them to the illustrated circuit. This operation is similar to the operation shown in FIG. The result of the comparison of the sum signals is now also selected from the incoming precision signal and the precision of the selection is ANDed with the exact signal calculated at this node to produce This outputs an accurate signal. The output accurate signal indicates whether the output sum is unique, that is, the smallest one of any nearest vectors of all vectors starting at level 0 that exceeds the ε bound.

The different embodiments of the kNN accelerator described above add flexibility and/or application space that the accelerator will benefit. For example, in some embodiments, to enable calculations on vector elements greater than 8b, the distance calculation circuit designed for the 8b elements can be reused for the 16b elements by combining pairs of adjacent 8b element circuits. Figure 12 illustrates an exemplary 8-bit/16-bit reconfigurable computing circuit in accordance with an embodiment. In this circuit, a control signal broadcasts two sets of selection signals for an even/odd numbered 8b operation circuit. For a fixed circuit and storage size, the number of vector dimensions or stored vectors is reduced by half when operating in 16b mode. The number of iterations required to calculate a complete sum of squares in 16b mode is increased from 6 (for 8b components) to 15. Multiple computational iterations may be required between successive ordering iterations to ensure that higher order bits are not affected by more than 1 when processing lower order bits. Even in 16b mode, the accelerator ranking based on partial calculation greatly reduces the computation used to find the nearest neighbor. Figure 13 illustrates an exemplary partial distance calculation for the sum of squares of 16-bit elements, in accordance with an embodiment. In some embodiments, only 16b width or reconfiguration is used. Of course, other bit widths or reconfigurations can be used as well.

In some embodiments, the kNN accelerator can be reconfigured to support larger vector dimensions with additional stages in the compressor tree of the distance calculation unit to join results from other distance calculation unit blocks. Therefore, because the dimension of each vector is increased, the number of stored vectors is reduced. not enough.

In some embodiments, the functionality of the kNN accelerator is extended to operate on a data set that is larger than the accelerator storage capacity. The sorted k-nearest candidates from one of the libraries stored in the accelerator are first calculated, the removed candidates are replaced by any remaining object descriptors from the memory, and the process continues until all Object candidates are iterated to find the overall k-nearest descriptor vector. For an accelerator with 256 object capacity and each object feature has a 256-dimensional (8b per dimension) vector, across an object library size from 512 to 2048 objects, the accelerator consistently reduces the number of 16-for a sort. The square of the nearest candidate list is calculated.

In some embodiments, in addition to finding the vector from the minimum distance, the accelerator can be reconfigured to find the vector in descending order of distance by inverting the 3b comparator circuit within the comparison nodes of the sequencing network. The output. Alternatively, the descending permutation is calculated by subtracting the cumulative partial distance from the maximum possible distance and then processing the resulting numbers using the same window-based minimum ordering network.

In some embodiments, the accommodation of various distance metrics can be achieved by reconfiguring only the 1D distance circuit in the network. In addition to the distance between Euclidean and Manhatan, another popular metric for finding the closest match to a vector is the cosine similarity, which takes the angular distance between the vectors to find the closest match. . The cosine of this angle between the two vectors A and B is calculated as [Σ(a _i .b _i )]/[(Σa _i ² ) ^1/2 .(Σb _i ² ) ^1/2 ], a smaller The angle can produce a large cosine. For cosine-based similarity, if the stored database has been normalized, then normalization is not needed, and then the optimization is converted to find the point product (a _i .b _i ) has the largest The vector of magnitude. This dot product between the query and stored objects can be partially calculated using the existing 2b multipliers of the Euclidean metric.

Figure 14 illustrates a cosine similarity calculation (1d distance) circuit and an exemplary partial distance calculation for dot product in accordance with an embodiment, in accordance with an embodiment. Multiple computational iterations may be required between successive ordering iterations to ensure that higher order bits are not affected by more than 1 when processing lower order bits. For a dot product with symbolic components, each calculation iteration requires 2 steps - the first step sums all positive product products to the accumulated partial distance, and then subtracts the sum of all negative product products from the accumulated partial distance.

In some embodiments, as the iteration proceeds, the candidate vectors may also be removed early based on comparing the accumulated partial distances to a predetermined absolute threshold. In addition, declaring a winning vector need not be precise, and the iteration of picking a winner may be stopped earlier based on a predetermined relative accuracy (using global indicator position) or absolute accumulation of partial distance. Such a scheme can reduce the energy consumption for optimization to approximate the nearest neighbor (ANN) search algorithm.

Figure 15 illustrates an exemplary method of kNN search, using an embodiment of the kNN accelerator detailed above, in accordance with an embodiment. In a high level, the method of kNN search involves calculating partial distances, accumulating these distances, and sorting those accumulated distances in an interleaved manner. The following is a more detailed description of the program.

In some embodiments, one or more variables are reset. Example For example, a cumulative distance for each reference vector, a global indicator, a global binary mask, a k value, a valid bit for each reference vector (set to 1), for each A "done" bit of the reference vector (set to 0), and a local indicator for each reference vector.

At 1501, for each reference vector and each element of the reference vector, an absolute difference between the element and a corresponding element in the query vector is calculated.

At 1503, a comparison threshold is set based on the global indicator.

At 1505 it is determined if a portion of the distance will be calculated. When the partial distance should be calculated, at 1507, for each reference object vector having a valid bit set to 1 (indicating valid), a portion of the distance is calculated (eg, used in Figures 3 and 4 and compressor tree 211). The circuit) is shifted and added to a cumulative distance.

At 1509, when the partial distance should not be calculated or after 1507 has occurred, for each reference object vector having a valid bit set to 1 (indicating valid), a global region of the cumulative distance bit (psum) The indicator dependent subset is sent to the least ordered network.

At 1511, the sorting network finds a global minimum and a second minimum.

At 1513, it is determined whether the global minimum is subtracted from the second minimum is greater than the set threshold. If so, it is set to exactly one. At 1515, when the precision is 1, or the global indicator is the LSB of the cumulative distance, then the minimum value is found to be set to one.

At 1517, typically parallel to 1513, for an effective equal to 1 Each reference object vector compares the psum to the global minimum based on the set threshold and a previous iteration comparison. Based on this comparison, the valid bit is updated to either remain at 1 or be invalidated to zero. If the validity is updated to 0 in the current iteration, the current global metric is written to the local metric store associated with the reference vector and 1 is written to the global binary mask at the global metric location in.

At 1519, it is determined whether the minimum value is found to be equal to one. If so, k is incremented by 1 in 1521. In addition, for the global minimum vector, the completion at 1521 is set to 1 and the validity is set to 0. If not, then at 1527 the global indicator is incremented by one and the comparison threshold is set again.

After k is incremented, at 1523 the global indicator is decremented to a position closest to 1 in the global binary mask. Essentially, the global metric is rolled back to a final position where a reference object vector is removed from the search space.

At 1525, for each reference object vector, if the local index is greater than or equal to the global index and the completion bit is equal to 0, the valid bit is set to 1 and the comparison threshold is set again. When the next most recent vector is to be calculated, this will insert a reference vector again into the search space.

Although the sorting and calculation described above is done parallel to all reference vectors, these operations can save floor space by sequentially calculating and sorting different vectors on the same circuit.

The systems, methods, and devices described above can be used to provide Many advantages. This distance between the vectors is iteratively calculated such that the accuracy of the calculated distance is increased from MSB to LSB in successive iterations. In each iteration, this calculation of a partial distance of a vector provides the purpose of improving the accuracy of the complete (cumulative) distance at a particular effective or bit position. The complete distance calculation is broken down into a number of partial distance calculations for different metrics such as Euclidean, Manhatan or dot product such that after calculating the higher bits, in the lower order position in successive iterations The improvement in accuracy above never changes the higher order bits beyond a certain threshold.

The above completion uses (i) a partial distance calculation circuit having a 1D calculation circuit, which uses the control signal to calculate the distance of the right portion and arranges according to the dimension of the vector, (ii) the use of the partial distances of all 1D calculations. A compressor tree is summed up in stages (iii) an accumulator having storage for the current cumulative distance, which is added to it using a shifter at an appropriate validity.

Sorting these accumulated vector distances does not have to wait until the full distance has been calculated - the sorting can begin with a low precision distance. Sorting does not take into account all the bits of the cumulative distance - it is done iteratively, starting with a small window of bits, from MSB to LSB. The sorting network uses a programmable threshold (in the exemplary case, it is 1 or 0) to announce whether the minimum found for each comparison and the entire sorting network in an iteration is greater than any other The number is smaller than the threshold.

The calculation and ordering are interleaved from the MSB to the LSB such that many reference vectors are removed from the search space using low-precision distance calculations, while only the remaining vectors are next iterations to improve lower bit accuracy. Degree is used to determine the nearest neighbor.

There is local control in the calculation associated with each vector that uses the results of the ranking network to determine whether the calculations and rankings for the vector proceed to or are removed from the next iteration.

In each vector calculation the local control and distance accumulator will remain in state even if it is removed from the search space. When the next nearest neighbor is found, the local control can reinsert the vector into the search space (based on the global metric) and reuse any previous calculations prior to the previous removal point.

The global control coordinates the activities in which the bits are broadcast to all of the vectors in which the global metrics are sent to the sorting network.

Control signals for the partial distance calculations that are dependent on the iteration are also broadcast from all global controls to all vectors. These control signals can be stored in a programmable lookup table that can be referenced by the global indicator or as a fixed function logic.

The global control record is the iteration of the vector being removed from the search space when a nearest neighbor is found. The global control jumps back to the most recent iteration state in which the vector was removed to begin searching for only the next nearest neighbor in the search space.

The kNN accelerator can be made programmable to change the order of the permutations.

Any number of bit sizes, dimensions, or vectors can be supported. Additionally, in some embodiments, the kNN accelerator is programmable The number of such bit sizes, dimensions or reference vectors for each dimension can be programmed.

This operation can be serialized such that the calculation and ordering for different reference vectors can be done using a common partial distance calculation and ordering circuit.

Example core structure, processor, and computer structure

The processor core can be implemented in different ways for different purposes and in different processors. For example, such core implementations may include: 1) a generic sequential core intended for general purpose computing; 2) a high performance general out-of-order core intended for general purpose computing; 3) primarily intended for general purpose A special purpose core for computational graphics and/or scientific (throughput) calculations. Implementations of different processors may include: 1) a CPU that includes one or more generic sequential cores intended for general purpose computing and/or one or more high performance general purpose out-of-order cores intended for general purpose computing And 2) a co-processor that includes one or more special purpose cores primarily intended for graphics and/or scientific (throughput) calculations of general purpose computing. Such different processors result in different computer system architectures, which may include: 1) the coprocessor is on a separate wafer from the CPU; 2) the coprocessor is different in the same package as a CPU 3) The coprocessor is on the same die as a CPU (in this case, such a coprocessor is sometimes referred to as dedicated logic, such as integrated graphics and/or science (throughput) logic, or special purpose core); and 4) a system single chip that can contain the described CPU on the same die (sometimes referred to as the (etc) application) Core or application processing The above-described coprocessor, and other functions. An exemplary core structure will be described next, followed by an illustration of an exemplary processor and computer architecture.

Sample core structure Sequential and out-of-order core block diagram

Figure 16A is a block diagram illustrating an exemplary sequential pipeline and an exemplary scratchpad renaming, out of order distribution/execution pipeline, in accordance with an embodiment of the present invention. Figure 16B is a block diagram illustrating an exemplary embodiment of a sequential structure core and one exemplary temporary register renaming, out of order distribution, to be included in a processor, in accordance with an embodiment of the present invention. Execute both of the structural cores. The sequential pipeline and sequential cores are shown in solid-line block diagrams in Figures 16A-B, and a dashed block diagram is shown optionally showing the register renaming, out-of-order distribution/execution pipelines and cores. Since the sequential aspect is a subset of the out-of-order aspect, the out-of-order aspect will be explained.

In FIG. 16A, a processor pipeline 1600 includes an extraction phase 1602, a length decoding phase 1604, a decoding phase 1606, an allocation phase 1608, a rename phase 1610, and a scheduling (also known as scheduling or distribution) phase. 1612. A scratchpad read/memory read stage 1614, an execution stage 1616, a write back/memory write stage 1618, an exception processing stage 1622, and a commit stage 1624.

16B shows a processor core 1690 that includes a front end unit 1630 coupled to an execution engine unit 1650, and both are coupled to a memory unit 1670. The core 1690 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, and an ultra-long Command Word (VLIW) core, or a hybrid or alternative core type. Alternatively, the core 1690 can be a special purpose core such as, for example, a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, or analog.

The front end unit 1630 includes a branch prediction unit 1632 coupled to the instruction cache unit 1634, the cache unit being coupled to an instruction address translation buffer (TLB) 1636 that is coupled to an instruction fetch unit 1638. The extraction unit is coupled to a decoding unit 1640. The decoding unit 1640 (or decoder) can decode the instructions and generate an output as one or more micro-ops, microcode entry points, microinstructions, other instructions, or other control signals that are decoded, or otherwise Reacting, or derived from such original instructions. The decoding unit 1640 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memory (ROM), and the like. In one embodiment, the core 1690 includes a microcode ROM or other medium that stores microcode for certain macro instructions (eg, in the decoding unit 1640 or otherwise in the front end unit 1630). The decoding unit 1640 is coupled to a rename/allocator unit 1652 in the execution engine unit 1650.

The execution engine unit 1650 includes a rename/distributor unit 1652 coupled to one of the retirement units 1654 and a set of one or more scheduler units 1656. The (etc.) scheduler unit 1656 represents any number of different schedulers, including reservation stations, central command windows, and the like. The (etc.) schedule The unit 1656 is coupled to the (etc.) physical register set unit 1658. Each of the (or) physical register set units 1658 represents one or more physical register sets, wherein different ones store one or more different data types, such as scalar integers, scalar floating point numbers, Package integers, packed floating-point numbers, vector integers, vector floating-points, states (for example, an instruction metric that will execute the next instruction address), and so on. In one embodiment, the (etc.) physical scratchpad set unit 1658 includes a vector register unit, a write mask register unit, and a scalar register unit. These register units can provide structured vector registers, vector mask registers, and general purpose registers. The (etc.) physical scratchpad set unit 1658 is overlaid by the retirement unit 1654 to illustrate various ways in which register renaming and out-of-order execution can be implemented (eg, using one (multiple) reordering buffers and One (multiple) retiring register sets; using one (multiple) future files, one (multiple) history buffers, and one (multiple) retiring register sets; using a temporary map and a temporary Cache pool; etc.). The retirement unit 1654 and the (or other) physical register set unit 1658 are coupled to the (etc.) execution cluster 1660. The (etc.) execution cluster 1660 includes a set of one or more execution units 1662 and a set of one or more memory access units 1664. The execution units 1662 can perform various operations on various types of data (eg, scalar floating point numbers, packed integers, packed floating point numbers, vector integers, vector floating point numbers) (eg, shift, add, subtract, Multiply). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units all to perform all functions. The (etc.) scheduler unit 1656, the physical register set unit 1658, and the execution cluster 1660 are shown as possibly plural Separate pipelines for specific types of data/operations are generated in some embodiments (eg, a scalar integer pipeline, a scalar floating point/packed integer/packed floating point number/vector integer/vector floating point number pipeline, and/or Or a memory access pipeline, each of which has its own scheduler unit, physical register set unit, and/or execution cluster - and in the case of a separate memory access pipeline, some implementations The execution cluster implemented in this example with only this pipe has the (etc.) memory access unit 1664). It should also be understood that where individual pipelines are used, one or more of these pipelines may be distributed/executed out of order while the remainder are sequential.

The set of memory access units 1664 are coupled to the memory unit 1670, which includes a data TLB unit 1672 that is coupled to a data cache unit 1674 that is coupled to a level 2 (L2) cache unit 1676. In an exemplary embodiment, the memory access unit 1664 can include a load unit, a storage address unit, and a stored data unit, each of which is coupled to the data in the memory unit 1670. TLB unit 1672. The instruction cache unit 1634 is further coupled to a level 2 (L2) cache unit 1676 in the memory unit 1670. The L2 cache unit 1676 is coupled to one or more other levels of the cache and is ultimately coupled to a primary memory.

By way of example, the example register is renamed, the out-of-order distribution/execution core structure can implement the pipeline 1600 as follows: 1) the instruction fetch 1638 performs the fetch and length decoding stages 1602 and 1604; 2) the decoding unit 1640 performs the decoding phase 1606; 3) the rename/allocator unit 1652 performs the allocation phase 1608 and the rename phase 1610; 4) the (etc.) Scheduling unit 1656 executes the scheduling phase 1612; 5) the (etc.) physical scratchpad set unit 1658 and the memory unit 1670 execute the scratchpad read/memory read stage 1614; the execution cluster 1660 executes the Execution stage 1616; 6) the memory unit 1670 and the (etc.) physical register set unit 1658 perform the write back/memory write stage 1618; 7) various units may be involved in the exception processing stage 1622; 8) The retirement unit 1654 and the (or other) physical register set unit 1658 perform the commit phase 1624.

The core 1690 can support one or more instruction sets (eg, the x86 instruction set (with some extensions already added to the updated version); MIPS Technologies MIPS Architecture, Sunnyvale, California; ARM Holdings, Sunnyvale, California, USA The ARM instruction set (and optional additional extensions such as NEON) includes the (etc.) instructions described herein. In an embodiment, the core 1690 includes logic to support a packed data instruction set extension (eg, AVX1, AVX2) The operations that are thus allowed to be used by many multimedia applications will be performed using the packaged material.

It should be understood that the core can support multiple threads (performing two or more parallel operations or thread collections) and can be done in a variety of ways, including time slicing multithreading, synchronous multithreading (one of which is single The entity core provides a logical core for each of the threads that the core of the entity is executing synchronously with multiple threads, or a combination thereof (eg, subsequent slice extraction and decoding and synchronization of multiple threads such as ^Intel® Ultra Thread technology).

Although register renaming is described in an out-of-order execution environment, it should be understood that register renaming can be used in In a sequential structure. Although the illustrated embodiment of the processor also includes separate instruction and data cache units 1634/1674 and a shared L2 cache unit 1676, additional embodiments may be used with both a single internal cache and instructions. Information such as, for example, a level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system can include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all caches may be external to the core and/or the processor.

Specific example sequential core structure

17A-B illustrate a more specific exemplary sequential core structure block diagram that will be one of several logical blocks (including other cores of the same type and/or different types) in a wafer. The logic blocks communicate over a high frequency wide interconnect network (e.g., a ring network) having fixed function logic, a memory I/O interface, and other necessary I/O logic, depending on the application.

Figure 17A is a block diagram of a single processor core connected to a die interconnect network 1702, with its local subset of the level 2 (L2) cache 1704, in accordance with an embodiment of the present invention. In one embodiment, an instruction encoder 1700 supports the x86 instruction set with a packed data instruction set extension. An L1 cache 1706 allows low latency access to the cache memory into the scalar and vector elements. Although in an embodiment (to simplify the design), a scalar unit 1708 and a vector unit 1710 use separate sets of registers (both scalar registers 1712 and vector registers 1714, respectively) and in them. The data transferred between is written to the memory and then read back from a level 1 (L1) cache 1706, the present invention Alternate embodiments may use different methods (e.g., using a single set of registers or including a communication path that allows data to be transferred between two sets of registers without being written and read back).

The local subset of the L2 cache 1704 is part of a global L2 cache that is split into separate local subsets, one for each processor core. Each processor core has a direct access path to the L2 cache 1704 its own local subset. The data read by a processor core is stored in its L2 cache subset 1704 and can be accessed quickly, accessing its own local L2 cache subsets parallel to other processor cores. The data written by a processor core is stored in its own L2 cache subset 1704 and cleared from other subsets, if needed. The ring network ensures the consistency of shared data. The ring network is bidirectional to allow actors such as processor cores, L2 caches, and other logic blocks to communicate with each other within the wafer. Each circular data path is 1012-bit wide in each direction.

Figure 17B is an expanded view of a portion of the processor core of Figure 17A, in accordance with an embodiment of the present invention. Figure 17B includes an L1 data cache 1706A portion of the L1 cache 1704, and more particularly with respect to the vector unit 1710 and the vector registers 1714. In particular, the vector unit 1710 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 1728) that executes one or more integer, single precision floating point, and double precision floating point instructions. The VPU supports mixing of the register inputs with the blending unit 1720, numerical conversion by the digital conversion unit 1722A-B, and copying by the copy unit 1724 on the memory input. The write mask register 1726 allows prediction of the resulting vector writes.

Processor with integrated memory controller and graphics

18 is a block diagram of a processor 1800, which may have more than one core, may have an integrated memory controller, and may have an integrated graphics, in accordance with an embodiment of the present invention. The solid line block diagram in FIG. 18 shows a processor 1800 having a single core 1802A, a system agent 1810, a set of one or more bus controller units 1816, and an optional additional dashed box. The diagram illustrates an alternate processor 1800 having a plurality of cores 1802A-N, a set of one or more integrated memory controller units 1814, and dedicated logic 1808 in the system proxy unit 1810.

Thus, different implementations of the processor 1800 can include: 1) a CPU having the dedicated logic 1808 integrated with graphics and/or science (throughput) logic (which can include one or more cores), and such The cores 1802A-N are one or more general cores (eg, a generic sequential core, a general out-of-order core, a combination of the two); 2) a co-processor with such cores 1802A-N is a large number of A dedicated core intended for graphics and/or science (throughput); and 3) a co-processor with such cores 1802A-N being a large number of generic sequential cores. Accordingly, the processor 1800 can be a general purpose processor, a coprocessor or a dedicated processor such as, for example, a network or communications processor, a compression engine, a graphics processor, a GPGPU (general graphics processing unit), A high throughput multi-integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor can be implemented on one or more wafers. Use any of several process techniques, such as, for example, BiCMOS, CMOS, or NMOS, the processor 1800 can be part of and/or can be implemented on one or more substrates.

The memory hierarchy includes one or more levels cached within the cores, a set or one or more shared cache units 1806, and external memory coupled to the set of integrated memory controller units 1814 Body (not shown). The set of shared cache units 1806 may include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache ( LLC), and/or combinations thereof. Although in one embodiment a ring-based interconnect unit 1812 interconnects the integrated graphics logic 1808, the set of shared cache units 1806, and the system proxy unit 1810/integrated memory controller unit 1814, Alternate embodiments may use any number of well known techniques for interconnecting these units. In an embodiment, consistency is maintained between one or more cache units 1806 and cores 1802-A-N.

In some embodiments, one or more of the cores 1802A-N are capable of multiple threads. The system agent 1810 includes those components that coordinate and operate the cores 1802A-N. The system proxy unit 1810 can include, for example, a power control unit (PCU) and a display unit. The PCU can be or include logic and components needed to adjust the power states of the cores 1802A-N and the integrated graphics logic 1808. The display unit is a display for driving one or more external connections.

From the point of view of the structural instruction set, the cores 1802A-N may be homogeneous or heterogeneous; that is, two or more of the cores 1802A-N may be capable of executing the same set of instructions, while others may be able to perform the Instruction Set a subset of or a different instruction set.

Sample computer structure

19-22 are block diagrams of exemplary computer structures. Other system designs and configurations well known in the art are notebook computers, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital Signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

Referring now to Figure 19, shown is a block diagram of a system 1900 in accordance with an embodiment of the present invention. The system 1900 can include one or more processors 1910, 1915 that are coupled to a controller hub 1920. In one embodiment, the controller hub 1920 includes a graphics memory controller hub (GMCH) 1990 and an input/output hub (IOH) 1950 (which may be on different wafers); the GMCH 1990 includes memory And the graphics controller is coupled to a memory 1940 and a coprocessor 1945; the IOH 1950 couples an input/output (I/O) device 1960 to the GMCH 1990. Alternatively, one or both of the memory and graphics controller are integrated within the processor (as described herein), the memory 1940 and the coprocessor 1945 are directly coupled to the processor 1910, and The controller hub 1920 and the IOH 1950 are on the same single wafer.

The optional features of the additional processor 1915 are in Figure 19 It is indicated by a dotted line. Each processor 1910, 1915 can include one or more of the processing cores described herein and can be some version of the processor 1800.

The memory 1940 can be, for example, a dynamic random access memory (DRAM), a phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 1920 and the (or other) processors 1910, 1915 pass through a multi-drop bus, such as a front-end bus (FSB), a point-to-point interface such as QuickPath Interconnect (QPI), or the like. Connect 1995 to communicate.

In one embodiment, the coprocessor 1945 is a dedicated processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded Processor, or the like. In an embodiment, controller hub 1920 can include an integrated graphics accelerator.

In terms of quality factor spectroscopy considerations, including structure, microstructure, heat, power consumption characteristics, etc., there may be multiple differences between these physical resources 1910, 1915.

In an embodiment, the processor 1910 executes instructions that control general type data processing operations. Embedded in these instructions may be coprocessor instructions. The processor 1910 identifies that the coprocessor instructions are of a type that should be executed by the attached coprocessor 1945. Accordingly, the processor 1910 issues the coprocessor instructions (or control signals representative of the coprocessor instructions) to the coprocessor 1945 over a coprocessor bus or other interconnect. The coprocessor 1945 accepts and executes the Wait for the received coprocessor instructions.

Referring now to Figure 20, a block diagram of a first more specific example system 2000 is shown in accordance with an embodiment of the present invention. As shown in FIG. 20, multiprocessor system 2000 is a point-to-point interconnect system and includes a first processor 2070 and a second processor 2080 that are coupled via a point-to-point interconnect 2050. Each of processors 2070 and 2080 can be some version of the processor 1800. In one embodiment of the invention, processors 2070 and 2080 are processors 1910 and 1915, respectively, and coprocessor 2038 is a coprocessor 1945. In another embodiment, processors 2070 and 2080 are processor 1910 and coprocessor 1945, respectively.

Processors 2070 and 2080 are shown to include integrated memory controller (IMC) units 2072 and 2082, respectively. Processor 2070 also includes a portion of its bus controller unit point-to-point (P-P) interfaces 2076 and 2078; similarly, second processor 2080 includes P-P interfaces 2086 and 2088. Processors 2070, 2080 can exchange information via point-to-point (P-P) interface 2050 using P-P interface circuits 2078, 2088. As shown in FIG. 20, IMCs 2072 and 2082 couple the processors to respective memories, a memory 2032 and a memory 2034, which may be primary memories that are locally attached to the respective processors. Part of the body.

Processors 2070, 2080 can each exchange information with a chipset 2090 via respective P-P interfaces 2052, 2054 using point-to-point interface circuits 2076, 2094, 2086, 2098. The chipset 2090 can optionally exchange information with the coprocessor 2038 via a high performance interface 2039. In an embodiment, the coprocessor 2038 is a dedicated processor, such as For example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like.

A shared cache (not shown) may be included in either or both of the two processors, still connected to the processors via the PP interconnect, such that any of the processors Or partial cache information of both may be stored in the shared cache if a processor is placed in a low power mode.

Wafer set 2090 can be coupled to a first bus bar 2016 via an interface 2096. In an embodiment, the first bus bar 2016 may be a peripheral component interconnect (PCI) bus bar, or a bus bar such as a PCI Express bus bar or another third generation I/O interconnect bus bar, although the invention The scope is not limited to this.

As shown in FIG. 20, various I/O devices 2014 can be coupled to the first bus bar 2016, with the same bus bar bridge 2018 coupling the first bus bar 2016 to a second bus bar 2020. In an embodiment, one or more additional processors 2015, such as a coprocessor, a high throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or a digital signal processing (DSP) unit), may be A programmed gate array, or any other processor, is coupled to the first bus 2016. In an embodiment, the second bus 2020 can be a low pin count (LPC) bus. Various devices can be coupled to a second bus 2020, including, for example, a keyboard and/or mouse 2022, a communication device 2027, and a storage unit 2028 such as a magnetic disk or other large-capacity storage device. Including instructions/code and data 2030, In one embodiment. Additionally, an audio I/O 2024 can be coupled to the second bus 2020. Note that other architectures are also possible. For example, instead of using the point-to-point architecture of Figure 20, a system can implement a multi-drop bus or other such architecture.

Referring now to Figure 21, a block diagram of a second more specific example system 2100 is illustrated in accordance with an embodiment of the present invention. The same elements in Figures 20 and 21 have the same reference numerals, and certain aspects of Figure 20 have been removed from Figure 21 to avoid obscuring the other aspects of Figure 21.

21 illustrates that the processors 2070, 2080 can each include integrated memory and I/O control logic ("CL") 2072 and 2082, respectively. Thus, the CL 2072, 2082 includes an integrated memory controller unit and includes I/O control logic. 21 not only illustrates the memories 2032, 2034 coupled to the CLs 2072, 2082, but the I/O devices 2114 are also coupled to the control logic 2072, 2082. A conventional I/O device 2115 is coupled to the wafer set 2090.

Referring now to Figure 22, a block diagram of an SoC 2200 is illustrated in accordance with an embodiment of the present invention. Similar elements in Figure 18 have similar reference numerals. In addition, the dotted squares have optional features on more advanced SoCs. In FIG. 22, an interconnect unit 2202 is coupled to: an application processor 2210 that includes a set of one or more cores 202A-N and a shared cache unit 1806; a system proxy unit 1810; a bus controller Unit 1816; an integrated memory controller unit 1814; a set of one or more coprocessors 2220, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a random access memory (SRAM) unit 2230; a direct memory access (DMA) unit 2232; A display unit 2240 coupled to one or more external displays. In one embodiment, the co-processor 2220 includes a dedicated processor such as, for example, a network or communications processor, a compression engine, a GPGPU, a high throughput MIC processor, embedded processing. , or the like.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of these implementations. Embodiments of the invention may be implemented as a computer program or code embodied on a programmable system including at least one processor, a storage system (including electrical and non-electrical memory and/or storage elements) At least one input device and at least one output device.

A code, such as code 2030 shown in Figure 20, can be applied to input instructions to perform the functions described herein and to generate output information. This output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor. Any system of the device.

The code can be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The code can also be implemented in a combined or machine language, if desired. In fact, the mechanisms described in this article are not limited to the scope of any particular programming language. In any case, the language can be a compiled or literal language.

One or more aspects of at least one embodiment may be stored Implemented on a machine readable medium representative of instructions that represent various logic in the processor that, when read by a machine, causes the machine to fabricate logic to perform the techniques described herein . Such representations, referred to as "IP cores", can be stored on a tangible, machine-readable medium and provided to various customers or production facilities for loading into the manufacturing machines that actually make the logic or processor. in.

Such machine readable storage medium may include, without limitation, non-transitory, tangible arrangements for manufacture or formation of articles by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks. , optical disc, CD-ROM, rewritable disc (CD-RW), and magneto-optical disc, semiconductor devices such as read-only memory (ROM), random access memory (RAM) such as dynamic random Access Memory (DRAM), Static Random Access Memory (SRAM), Erasable Programmable Read Only Memory (EPROM), Flash Memory, Electrically Erasable Programmable Read Only Memory (EEPROM) ), phase change memory (PCM), magnetic or optical card, or any other type of medium suitable for storing electronic instructions.

Accordingly, embodiments of the present invention also include non-transitory, tangible machine readable media containing instructions or including design material, such as a hardware description language (HDL), which defines the structures, circuits, and Device, processor, and/or system features. Such an embodiment may also be referred to as a program product.

Simulation (including binary translation, code translation, etc.)

In some cases, an instruction converter can be used to convert an instruction from a source instruction set to a target instruction set. For example, the finger The converter may be translated (eg, using static binary translation, dynamic binary conversion including dynamic compilation), morphing, emulating, or otherwise converting the instructions into one or more other instructions to be processed by the core. The command converter can be implemented in software, hardware, firmware, or a combination thereof. The instruction conversion may be on the processor, not on the processor, or partially and partially off the processor.

23 is a block diagram comparing the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set, in accordance with an embodiment of the present invention. In the illustrated embodiment, the command converter is a software command converter, although alternatively the command converter can be implemented in software, firmware, hardware, or various combinations thereof. 23 shows that a high-level language 2302 program can be compiled with an x86 compiler 2304 to produce an x86 binary code 2306 that can be natively executed by a processor having at least one x86 instruction set core 2316. The processor having at least one x86 instruction set core 2316 represents any processor that performs substantially the same functions as an Intel processor having at least one x86 instruction set core, by performing or otherwise processing ( 1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) an object code version of the application or other software whose target is to run on an Intel processor having at least one x86 instruction set core, in order to Achieve substantially the same results as an Intel processor with at least one x86 instruction set core. The x86 compiler 2304 represents a compiler that is operable to generate an x86 binary code 2306 (eg, a destination code), which may, with or without additional linking processing, in the processing with at least one x86 instruction set core 2316

Is executed on the device. Similarly, FIG. 23 shows that the higher-order language 2302 program can be compiled using an alternate instruction set compiler 2308 to generate an alternate instruction set binary code 2310 that can be natively composed of a core 2316 that does not have at least one x86 instruction set core 2316. The processor executes (eg, a processor having the core of the MIPS instruction set executing MIPS Technologies of Sunnyvale, California, USA and/or having the core of the ARM instruction set executing ARM Holdings, Sunnyvale, California, USA). The instruction converter 2312 is used to convert the x86 binary code 2306 into a code that can be natively executed by the processor without the x86 instruction set core 2314. The code of this conversion is unlikely to be the same as the alternate instruction set binary code 2310, because the instruction converter capable of doing this is difficult to do; however, the converted code will complete the general operation and be replaced by the replacement instruction. The set of instructions to form. Thus, the command converter 2312 represents software, firmware, hardware, or a combination thereof that allows for a processor or other electronic device that does not have an x86 instruction set processor or core, through emulation, simulation, or any other method. The x86 binary code 2306 is executed.

101‧‧‧Query object vector

103_0~103_N‧‧‧ Vector 0~N partial distance calculation

105‧‧‧Global Control

107‧‧‧Minimum sorting network

109‧‧‧0 level comparison node

111‧‧‧"k" level comparison node

Claims (22)

An apparatus comprising: at least one vector portion distance calculation circuit for calculating a sum of a portion of a set of vectors in a search space and a cumulative distance; a minimum ordering network for sorting from the cumulative distances a selected set of bits indicating a minimum value of the set of selected bits from the vectors in the search space and whether the minimum is unique; and a global control circuit for receiving the minimum order An output of the network and controlling aspects of the operation of the at least one vector portion distance calculation circuit. The device of claim 1, wherein each of the vector portion distance calculation circuits comprises: a plurality of data component calculator circuits; and a compressor tree circuit for performing each of the plurality of data component calculator circuits a total control circuit for outputting a smaller bit window from the cumulative distance and using a result of the minimum ordering network to determine when a calculation and ordering of a vector will proceed to the next iteration Or being removed from the search space; and an accumulator for increasing the result of the partial distances in a current iteration, wherein a correct validity is added prior to adding the accumulated distance to the previous iteration Provided by a shifter to shift the portion distance. The device of claim 1, wherein the minimum ordering network comprises: a plurality of first level comparison nodes for receiving a portion of the adjacent vector local distance calculation circuit and the effective bit, and for outputting a valid bit And an exact bit, an address, and a sum, wherein the first level comparison node is configured to logically OR operate the received adjacent valid bits to provide the output valid bit, and mutually exclusive OR operations the receiving And the adjacent valid bit to logically OR an output of the mutually exclusive OR operation and the output of the adjacent sum may have a difference sum to generate the output precise bit, wherein the precise bit is 1 To indicate whether the difference between the two inputs is greater than a programmable threshold or whether both inputs are invalid; and a plurality of second-level comparison nodes for receiving a portion of the sum from the adjacent comparison node, The effective bit, the address, and the precision bit are used to output a valid bit, an exact bit, an address, and a sum, and a comparison result of the received sums is used to select from the incoming accurate signal, The precision of the selection is logically ANDed with the exact signal calculated at this node to produce the output accurate signal indicating whether the output sum is unique, wherein the comparison results in a highest order of the address Bit. The device of claim 3, wherein the global control circuit comprises: an OR tree for receiving and OR operations from a plurality of local controls a plurality of removed bits of the circuit; a global mask for indicating to the global control logic that the global indicator needs to jump back to the set of vectors that may include the next nearest neighbor; a selector And selecting the global metric from a previous global metric of incrementing one and an output from a priority coder coupled to the global mask. The device of claim 1, wherein the one-bit size, dimension, and reference number of each dimension are reconfigurable. The apparatus of claim 2, wherein each of the plurality of data element calculator circuits is a partial distance calculation sum of one of the absolute difference circuits. The apparatus of claim 2, wherein each of the plurality of data element calculator circuits is a local distance calculating a sum of local distances. The device of claim 2, wherein each of the plurality of data element calculator circuits is reconfigurable to operate as part of a larger data element calculator circuit for one of a plurality of data element bit widths. The device of claim 2, wherein each of the plurality of data component calculator circuits is a portion of a distance calculation circuit. A device as claimed in claim 1, wherein the global control circuit is operative to coordinate activities in which the bits are transmitted to the sorting network in the accumulated distances, using a global indicator broadcasted to all vectors, broadcasting for the iteration The dependent portion of the distance calculates the control signal to all vectors, and records the iterations from which the vector is removed from the search space when a nearest neighbor is found. The device of claim 10, wherein the control signals are stored in a programmable lookup table that is referenced by the global indicator. As with the device of claim 2, the local control circuits and the distance accumulator in each vector portion distance calculation circuit maintain state even if it is removed from the search space, and when the next nearest neighbor is found The local control circuit can reinsert the vector into the search space and reuse any previous calculations prior to the previous removal point, wherein the local control circuit uses the output of the minimum ordering network to determine a This calculation and sorting of the vector will proceed to or be removed from the next iteration. A device as claimed in claim 1, wherein the device is configured to be ordered by increasing distance. The device of claim 1, wherein the device is configured to change an order of the ordering. The device of claim 1, wherein the device operates on a data set having a larger storage capacity than the device, and calculates the sorted k-most recent candidate from the database of the device for use in the remaining memory. The object descriptor replaces the removed candidate and the process is repeated until all object candidates have been iterated to find the overall k-nearest descriptor vector. A method comprising the steps of: performing a continuous iteration using at least one vector partial distance calculation circuit to calculate a partial distance of a plurality of vectors for a query vector, shifting the calculated partial distances, and accumulating the shifted Part of the distance calculated, and A minimum ordering network is used to sort those accumulated distances, starting from a most significant bit to a least significant bit. The method of claim 16, wherein each successive iteration improves the accuracy of the calculated partial distance from a most significant bit to a least significant bit. The method of claim 16, wherein the accumulated distances from a most significant bit to a least significant bit start at a low precision distance, and only the remaining vectors enter the next iteration to target Determine nearest neighbors to improve lower bit accuracy. The method of claim 16, wherein the sorting network performs the ranking using a programmable threshold to declare whether a minimum value found in each of the comparisons and in one of the iterations of the entire sorting network is greater than Any other number is smaller than this threshold. The method of claim 16, wherein the cumulative distance calculation is broken down into a plurality of partial distance calculations for different metrics such that an accuracy improvement in low order bit positions in successive iterations after calculating the higher bits Do not change higher order bits beyond a critical value. The method of claim 16, wherein the step of calculating a partial distance of the plurality of vectors for a query vector comprises: using a circuit having a circuit for 1D calculation, using a control signal to calculate the right portion distance and according to the vector Dimensions are arranged; a compressor tree is used to add up the partial distances of all 1D calculations; The summed partial distances are added to a currently accumulated distance. The method of claim 16, wherein each iteration is performed in conjunction with the at least one vector portion distance calculation and the minimum order network circuit.