DE102015015182A1 - Systems, devices, and methods for k-nearest neighbor search - Google Patents

Abstract

Described are systems, apparatus and methods for k nearest neighbor (KNN) searches. In particular, embodiments of an CNN accelerator and its uses are described. In some embodiments, the CNN accelerator includes a plurality of vector fraction calculation circuits each for calculating a partial sum, a minimum sorting network for sorting partial sums of the plurality of vector partial spacing calculation circuits to find k nearest neighbor matches, and a global control circuit for controlling aspects of Operations of the plurality of vector pitch calculating circuits.

Description

Field of the invention

The field of the invention generally relates to computer processor architecture, and more particularly to nearest neighbor searching.

background

There are numerous applications where fast and efficient neighbor neighbor search for multi-dimensional features (points) of a data set is desirable. For example, this type of search in areas such. Image reconstruction and machine learning. There are several types of Next-neighbor record search. When searching for nearest neighbors, a search is made by specifying a set of points in a space and an input instance (query point) to find in a sentence the closest point to the input instance.

Brief description of the drawings

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, wherein like numerals indicate like elements, and wherein:

1 shows a high quality kNN accelerator organization according to one embodiment.

2 an exemplary vector pitch calculation circuit according to one embodiment.

3 an exemplary vector pitch sum-of-squares difference data element calculation circuit according to one embodiment.

4 FIG. 10 shows an exemplary vector sub-sum-of-absolute-difference data element calculation circuit according to an embodiment. FIG.

5 an exemplary local control circuit according to an embodiment shows.

6 an exemplary Manhattan distance sorting processing according to an embodiment.

7 an exemplary data element Euclidean distance sorting processing according to an embodiment.

8th shows an example sorting process using pitches according to one embodiment.

9 an exemplary global control circuit according to an embodiment shows.

10 an exemplary level 0 compare node circuit according to one embodiment.

11 an exemplary level-k comparison node circuit according to one embodiment.

12 FIG. 10 shows an exemplary 8-bit / 16-bit reconfigurable computing circuit according to one embodiment. FIG.

13 FIG. 16 shows example pitch-distance calculations for 16-bit squares squares according to one embodiment.

14 a cosine similarity calculation circuit (1d distance) according to an embodiment and exemplary scalar product pitch calculations according to an embodiment.

15 shows an exemplary method for kNN search according to an embodiment.

16A FIG. 12 is a block diagram showing both an exemplary in-order pipeline and an exemplary register rename out-of-order problem / execution pipeline in accordance with embodiments of the invention. FIG.

16B 12 is a block diagram showing both an exemplary embodiment of an in-order architecture core and an exemplary register renaming out-of-order problem / execution architecture core for incorporation into a processor in accordance with embodiments of the invention.

the 17A and Figure B shows a block diagram of a more concrete example in-order core architecture, where the core would be one of several logic blocks (including other cores of the same type and / or different types) in a chip.

18 a block diagram of a processor 1800 which may have more than one core, may have an integrated memory controller, and may have integrated graphics in accordance with embodiments of the invention.

the 19 to 22 Block diagrams of exemplary computer architectures are.

23 FIG. 12 is a block diagram contrasting the use of a software instruction converter to convert binary instructions into a source instruction set to binary instructions in a target instruction set in accordance with embodiments of the invention. FIG.

Detailed description

In the following description, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been illustrated in detail so as not to obscure the understanding of this description.

References in the description to "one embodiment", "an embodiment", etc., indicate that the described embodiment may include a particular feature, structure or property, but not every embodiment includes the particular feature that mandatorily includes particular structure or property got to. In addition, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it will be understood that those skilled in the art will be able to contemplate such feature, structure, or property in conjunction with other embodiments as to whether (FIGS. s) is now explicitly described or not.

One approach to the nearest neighbor search is to calculate a distance from the input instance to each point in a record and track the shortest distance. However, this simplistic approach may not be feasible for larger data sets. The distance calculation may be performed using a k-dimensional (k-d) tree to perform an exhaustive examination of all features of a feature at once. Therefore, this approach is slow and also involves high energy consumption.

Another neighbor-neighbor approach uses Voronoi diagrams. Each Voronoi diagram decomposes a plane into regions with equal nearest neighbors called cells. This is illustrated by a plurality of cells each having a feature (a dot). Theoretically, a "best matching" feature for each input instance can be found using a Voronoi plot to locate the feature in a particular cell. However, as shown, Voronoi cells are very irregular in shape and difficult to calculate (they are both time and processor intensive) and to use. In other words, Voronoi diagrams do not lend themselves to simple or efficient neighbor neighbor feature searches.

Embodied herein are embodiments of system, apparatus, and methods for use in improved neighbor neighbor searches that overcome the disadvantages of the above approaches. Briefly, an input (i.e., an observation) is used to search for the best matching feature in a feature space (i.e., a lexicon of features). This approach is particularly well-suited for feature vectors that are typically sparse in a high-dimensional vector space (note that features in this description are vectors and therefore "feature" and "feature vector" are used interchangeably).

Below are embodiments of a k nearest neighbor (kNN) accelerator that adjusts the accuracy of the distance calculations to minimize the amount needed to find each nearest neighbor. Many candidate vectors are displaced out of the search space using only low precision calculations, while remaining candidates closer to the nearest neighbor are displaced in later iterations using higher accuracy to announce a winner. Since the majority of calculations require less accuracy and consume less energy, overall, kNN energy efficiency improves significantly. Typically, this kNN accelerator is part of a main processor (CPU), a graphics processor (GPU), etc. The kNN accelerator may also be located outside the CPU, the GPU, etc.

1 shows a high-quality kNN accelerator according to one embodiment. In this accelerator, there are some main components including a plurality of vector pitch calculating circuits 103_0 to 103_N , a global control circuit 105 and a minimum sorting network 107 include. Each of these components will be discussed in detail below.

A query object vector 101 becomes the pitch calculation in the plurality of vector pitch calculating circuits 103_0 to 103_N entered. Not shown is the storage for this object vector, which is present. The vector pitch calculation circuits 103_0 to 103_N calculate pitches for each reference vector and an accumulated distance and put the minimum sorting network 107 a valid ad ready. Using a Partial distance calculation with multiple iterations between a query 101 and stored vectors with lower bit-value accuracy, which improves in each iteration as set forth herein, is more energy efficient than previous approaches. Partial distance calculation involves calculating fewer full distance bits starting at the MSB in each iteration for a different distance metric (such as the Euclidean (square sum) distance and the Manhattan (sum-of-absolute-difference) distance). The sub-result is added to the accumulated complemented distance with the correct value, resulting in increased accuracy of the lower-order bits as the calculations progress.

2 Fig. 10 shows an exemplary vector pitch calculation circuit 203 according to one embodiment. The vector consists of many dimensions, each in dimension being represented by 8b in this example. Individual distances in each dimension are first through 205 calculated and then in 211 added to find the total distance. A local control circuit 207 provides an indication of those bits that are in the different data element circuits 205 are to be selected.

As mentioned above, there may be some different types of distance metrics, and therefore different data element computing circuits 205 be in use. When applying a sum-of-absolute differences (Manhattan distance) metric, selection of the corresponding two bits (2b) is made from the absolute difference of each vector element and their summation in the vector sub-distance calculation circuit 203 , 3 Fig. 12 shows an exemplary vector pitch sum-of-square difference (Euclidean distance) element calculator circuit 205 according to one embodiment. As shown, a portion of a query object (8 bits as shown) and a portion of a stored object (equal number of bits) have a hardware-generated absolute-difference calculation (| a-b |) and become certain bits of that result selected using multiplexer and a control signal. In some embodiments, a local control circuit provides the control signal, as discussed below. The results of the multiplexing are multiplied (a pair of 2b × 2b multiplications) and then added. In this example, the result is a 5-bit value representing a pitch in calculating the square of the differences. These are through the compressor boom 211 is added to calculate a Euclidean pitch for the entire vector.

When a sum-of-absolute-differences (Manhattan distance) metric is employed, selection of the corresponding two bits (2b) is made from the absolute difference of each vector element and their summation in the vector sub-distance calculation circuit 203 , 4 FIG. 10 shows an exemplary vector pitch sum of the absolute difference data element circuit. FIG 205 according to one embodiment. As shown, a portion of a query object (8 bits as shown) and a portion of a stored object (equal number of bits) have a hardware-generated absolute-difference calculation (| a-b |) and become certain bits of that result selected using multiplexer and a control signal. In some embodiments, a local control circuit provides the control signal, as discussed below. In this example, the result is a 2-bit value.

The sub-SAD calculation reduces the compressor tree size and a factor of four, while the Euclidean Metric sub-calculation replaces 8-bit × 8-bit multipliers per vector element with a pair of trivial 2-bit multipliers and also the area of the compressor tree 211 reduced by a factor of three. This non-obvious construction of the Euclidean distance ensures that, after processing a higher MSB position, any subsequent lower MSB refinement will not affect higher order bits by more than 1, as with reference to FIGS 3 . 4 . 6 and 7 is discussed below. 7 FIG. 12 shows an embodiment of a whole difference square operation (for computing a Euclidean distance) that has been decomposed into subcomputation iterations that are illustrated by the example circuit of FIG 3 be calculated. 7 shows that by performing computation and sorting in the order shown, a lower order bit calculation process disturbs the processed higher order bits by no more than one. 4 also shows an embodiment of the circuit for each element and 6 Fig. 10 shows an example of the corresponding computation operations performed by this circuit for a Manhattan distance. 6 shows that by performing computation and sorting in the order shown, computational operations on lower order bits do not disturb the processed higher order bits by more than one.

In some embodiments, a single hardware data path uses a single circuit to reconfigure between different metrics.

A compressor tree 211 adds the results from each of the data element spacers. In a 256-dimension vector with Euclidean Distance, this result is a 13-bit value. The result of the compressor boom 211 gets to a slider 209 Posted. Typically, this slider is a right-hand slider, but depending on the endian configuration, it can also be a left-hand slider. The amount of shift is in most embodiments by the local control circuit 207 controlled. The slider aligns the pitch with the correct value according to the accumulated distance.

A flip flop 213 stores the accumulated distance from a previous iteration while the result of the adder 215 is the accumulated distance in the current iteration. At the beginning of the next iteration, this value will be in the flip-flop 213 enrolled. The selector 219 selects 2b from the accumulated distance based on the global pointer. In addition, it selects the execution at this 2b position by adding the partial sum to the previous accumulated distance.

The local control circuit 207 takes psumi as input and only modifies the upper bit before sending it to the sorting network 107 as psum value (eg 3 bits). A valid bit is also sent to the minimum sorting network 107 forwarded. 5 shows an exemplary local control circuit according to an embodiment. The local control circuit controls a plurality of different aspects of the vector sub-spacing calculation circuit as set forth above. This circuit receives a global pointer (outlined below) from a global controller along with a psumi from the selector 219 and a minimum sum, an address and an accurate indicator from the minimum sorting network 107 ,

As shown, the local control circuit takes an address of the vector being processed and a minimum address from the minimum sort network 107 and determines whether they are equal by means of comparison circuitry. The result of this comparison is with the minimum accuracy from the minimum sorting network 107 logically ENOUGH to help determine whether the object vector should no longer be processed. In particular, this result is used in the calculation of a valid bit, such. B. by the AND gate shown. The local control circuit uses the minimum sum psumi and the global pointer thereto, a displacement signal and a local calculation signal (which is used to control the various data element circuits 205 For one of two reasons, the vector processing can be stopped: 1) the current vector is declared the winner, or: 2) the current vector is removed from the search space if it is guaranteed not to be the nearest neighbor. The above description serves the former and affirms the "done" signal. The reversal of this signal (that through a bubble in the AND gate 513 entering) interferes with the valid signal. If the "done" is affirmed, the valid signal disappears. The remaining invalidation logic determines whether the vector is not done, but still part of the search space. The displacement signal indicates that the vector in the current iteration is removed from the search space, and this information is used by the global controller. In the 5 The circuit shown also generates clocks from the global CLK signal to control the timing of memory elements (including 213 ) to control. The local control circuit also receives "computational control" from the global control circuit, which then sends it to the fractional distance calculation engine. 205 and the slider circuit 209 forwards.

In essence, the local control circuit provides a local state control per vector with global state control over all vectors to track distance calculation states and iterations in which they are displaced, allowing reuse of previous distance calculations and comparisons when calculating a sorted list for k> 1 ,

Partial distance calculation and sorting iterations are interlaced, as in the 6 and 7 is shown. 6 FIG. 10 shows exemplary Manhattan distance calculation and sorting processing according to an embodiment; and FIG 7 FIG. 10 illustrates exemplary data element Euclidean distance calculation and sorting processing according to one embodiment. FIG. In these figures, the letters (a, b, c and d) are 2b components of the absolute difference between 8b elements of the interrogation and reference vectors. As illustrated, the typical process is to have a calculation iteration by the vector pitch calculation circuits 103_0 to 103_N followed by sorting in the minimum sorting network 107 , However, it may happen that compilation iterations are missing between successive sort iterations, such as: B. the in 7 shown.

The minimum sorting network 107 performs window-based sorting. In particular, this sorting network processes a much smaller window of bits starting at the most significant bit (MSB) of a partially calculated distance to allow much smaller comparator circuits and early displacement of vector candidates for further sub-computation.

For example, in some embodiments, the sorting network processes in each embodiment a window of only 2 bits of the accumulated vector distances from the MSB to the LSB (FIG. 6 and 7 ). This allows a strong parallelization with very little hardware complexity. Since the lower bit calculation refinements may affect already processed bits in the MSB by no more than 1, the sorting network must 107 also process the execution that was generated from the calculation iteration on the current 2b window. As a result, the sorting network compares 107 z. B. 3b numbers (execution and 2b sum) at each node 109 and 111 , In comparison, a conventional sorting network for a 256-dimension vector distance comparison would require (8b per element) 24b comparators at each node.

The sorting network 107 transmits the found minimum 3b result globally, and local control for individual vector distance calculations compare its 3b psum (execution and 2b sum) with this transmission result to determine if that particular vector is from further distance refinement calculations and comparisons using the global one 105 and the local control circuits can be displaced.

Due to the property that low-order computations can affect a currently processed window in a future iteration by one, all 3b comparisons in the local control and sorting network require 107 a difference of more than 1, so that a candidate can be eliminated. For the same reason, local control also takes into account when a particular vector was 1 larger than the minimum in a previous iteration. Using accurate signals shows the sorting network 107 whether the found minimum is unique. Sort iterations continue until a unique next vector is found or the LSB is reached. Feedback from the sorting network displaces candidate vectors from further distance calculation and comparison, resulting in an up to 3-fold calculation reduction.

8th shows the exemplary sorting process using partial distances according to an embodiment. Since vector candidates are displaced while the best candidate is found, their local state control stores the iteration at which they are displaced (in 5 as an lptr signal and in 8th with box).

Simultaneously, as the global control pointer (in the direction of the LSB) advances, if even a single vector is dropped, a 1 is written to the associated bit position of a global binary mask (that in the global control circuit 105 is stored). After finding a first vector, the global binary mask shows the global control logic 105 where the global pointer must return for the group of vectors containing the next following neighbor (s). This process continues in iterations and is in for the second and third neighbor neighbor searches 8th shown. If a global pointer has jumped back in the direction of the MSB, only those vectors are active whose stored iteration state matches the position of the global pointer. Vectors closer to the nearest neighbor are displaced at a closer position of the global pointer. This state maintenance technique has three advantages over a conventional sorting technique, which would simply eliminate the nearest neighbor and start the entire calculation and sorting process from scratch: (a) it will reuse already performed part distance calculations while finding the previous sort rank, (b) it reduces the number of vectors that must be compared using already calculated comparisons, and (c) does not require that k be predefined to minimize calculations and comparisons for any sorted rank. Benefits of reusing calculations and comparing with this control quantify the growing cost of finding the next nearest neighbor from X (eg, 256) vectors (eg, 256 8-b elements per vector) after already having 3 nearest neighbors were found. A conventional sorting technique would have led to finding the next vector from the remaining 253 candidate vectors, while the proposed control would reduce that search space tenfold and the associated calculation twentyfold.

In the illustration, a 2-bit pitch window is processed from the vectors. The arrows pointing to the right are valid bits from local control circuitry. In cycle 0, the seventh comparison deviates by more than 1 from the minimum, so this vector can be displaced. This displacement is stored in the local control circuitry. This process is carried out as stated above. When all subtotal calculations are processed for all vectors, the resulting distance will be the same as the full distances shown on the left-hand side for reference only.

9 FIG. 12 shows an example global control circuit according to an embodiment. FIG. As in 1 shown receives the global control circuit 105 minimum accuracy, address and summation values for the minimum sorting network 107 , The minimum accuracy signal is logically ORed together with a signal indicating a global pointer at the LSB position and used as a global pointer output signal that is either a previous global pointer incremented by one or one greater than a global pointer global binary mask as shown (priority) coded. The global binary mask is constructed from the OR ramification of displaced signals derived from the local control circuitry 207 was received. Computation control signals are found using a lookup table, with the global pointer serving as the index for that table. As long as no unique minimum or LSB is found, the global pointer will continue to move towards the LSB at each iteration (the pointer will increment by 1). This condition is controlled by the OR gate 901 checked. Otherwise, the pointer rolls back to the next 1 in the binary mask to find the next nearest neighbor. Even if a vector is displaced, a 1 is written to the pointer position inside the binary mask, otherwise a 0 is written. The OR tree 907 detects whether even a vector has been displaced (the displacement signals are generated by all the local control circuits), the following demultiplexing operation sets the input of the corresponding position to 1 by means of the global pointer, and this is put into (in memory 903 stored) global binary mask when the next iteration begins (rising edge of CLK). The position of the next 1 is determined by the priority encoder 905 calculated. The calculation control transfer to all vectors is based on the pointer position. This can be made programmable by looking in the lookup table 913 is stored, wherein the corresponding control signals are read based on the pointer.

Upon closer inspection of the minimum sorting network 107 There are two types of comparison nodes: level 0 and level "k" nodes. 10 FIG. 12 shows an example level 0 compare node circuit according to one embodiment. FIG. As shown, the circuit receives valid bits used to indicate whether the psum is from a vector that is part of the search space. If the validity associated with a psum is 0, the psum is ignored in a comparison at a node.

The adjacent valid bits are logically ORed to provide a valid level 0 bit. These valid bits are also X-ORed, then with a signal indicating that the absolute difference between the input sums is greater than a threshold ε, ORed to produce an accurate bit. If an exact bit is "1", it means no other vector is nearby. Finally, the adjacent sum are also compared with each other, where the result is extracted with one of the valid bits to form an address and a selector of the sum to be output. The overall output of the level 0 compare node is an address, a valid bit, an exact bit and a sum. The validity issue indicates whether the result is valid (at least one of the input validities must be correct to meet these conditions). The result of the comparison is added to the highest order bit of the minimum vector found address (bit [0] in this case since it is the first compare level). The output of an accurate signal indicates that the 2 vectors are not equal or close to each other (the difference is greater than 1 if ε = 1, or the difference is greater than 0 if ε = 0). The X-ORung 1003 affirms the exact signal if only one of the inputs is valid, regardless of the comparison result (since the comparison does not matter if one of the sums is not valid). The comparison result forwards the smaller sum together with its input address to the next node.

11 FIG. 12 shows an example level-k compare node circuit according to an embodiment. FIG. This circuit receives adjacent outputs of address, valid bit, exact bit, and a sum from the previous level (eg, level 0) and exposes them to the illustrated circuitry. The process is similar to the one in 10 shown. The result of the comparison of the sum signals now also selects from incoming accurate signals and ANDet the selected exact with the exact signal calculated at that node to produce the exact output signal. The exact output signal indicates whether the output sum is unique, ie, the smallest one with a distance of more than ε from any next vector over all vectors starting with the 0 level.

Other embodiments of the above described for the kNN accelerator increase the flexibility and / or the application space in which the accelerator would be beneficial. For example, in some embodiments, to facilitate calculations on vector elements greater than 8b, the 16b element distance calculation circuits designed for 8b elements may be reused by combining pairs of adjacent 8b element circuits. 12 FIG. 10 shows an example 8-bit / 16-bit reconfigurable computing circuit according to one embodiment. FIG. In this circuit, a control signal transmits two sets of selection signals for even / odd numbered 8b calculation circuits. For a fixed circuit and storage size, the vector dimension or the number of stored vectors is halved when operating in 16b mode. The number of iterations required to compute a full sum of squares in 16b mode increases from 6 (for 8b elements) to 15. Multiple computational iterations may be required between successive sort iterations to ensure that higher order bits do not translate more than 1 impaired when lower-order bits are processed. Even in 16b mode, sorting based on sub-calculations significantly reduces calculations to find the nearest neighbor. 13 FIG. 12 shows exemplary pitch calculations for 16-bit squares sums according to one embodiment. FIG. In some embodiments, only 16b widths or reconfigurations are used. Needless to say, other bit widths or reconfigurations can also be used.

In some embodiments, the kNN accelerator is reproducible to support larger vector dimensions with an additional stage in the compressor space of the distance calculation unit to add results from other distance calculation unit blocks. Consequently, the number of stored vectors reduces as the dimension of each vector increases.

In some embodiments, the functionality of the kNN accelerator is expanded to allow operation on data sets larger than the storage capacity of the accelerator. Sorted k-nearest candidates from a database stored within the accelerator are first computed, replaced displaced candidates with any remaining object descriptors from memory, and the process continues until all object candidates have been performed to find the k-nearest descriptor vectors. For an accelerator having a capacity of 256 objects and a 256-dimensioned vector (8b per dimension) for each object feature description over an object database size of 512 to 2048 objects, the accelerator steadily allows a reduction of the squares sums calculations for a sorted list of 16 nearest candidates.

In some embodiments, in addition to finding vectors based on the minimum distance, the accelerator may be reconfigured for finding vectors in descending order of pitch by reversing the output of the 3b comparator within the collation nodes of the collation network. Alternatively, the descending order of satisfaction is calculated by subtracting the accumulated sub-distances from the greatest possible distance and then using the same window-based minimum sorting network to process the resulting numbers.

In some embodiments, various distance metrics are met by reconfiguring only the 1D distance circuitry in the network. Besides Euclidean and Manhattan distances, another popular metric for finding the closest match to a vector is cosine similarity, which uses the angular distance between vectors to find the closest match. The cosine of the angle between two vectors A and B is calculated as [Σ (a _i * b _i )] / [(Σ a _i ² ) ^1/2 * (Σb _i ² ) ^1/2 ], where a smaller angle to a larger cosine leads. In terms of cosine-based similarity, no normalization is required if the stored database is already normalized and then the optimization is converted to finding the vector that yields the largest-scalar product Σ (a _i * b _i ). The scalar product between query and stored objects can be partially calculated using the existing 2b multipliers used for the Euclidean metric.

14 FIG. 10 illustrates a cosine similarity calculation circuit (1d distance) according to an embodiment and exemplary scalar product pitch calculations according to an embodiment. FIG. Multiple compilation iterations may be required between successive sort iterations to ensure that higher order bits are not compromised by more than 1 when processing lower order bits. For scalar products with signed elements, each calculation iteration requires 2 steps: first summing all the positive products to the accumulated sub-distance and then subtracting the sum of all negative products from the accumulated sub-distance.

In some embodiments, with progressive iterations, candidate vectors may be displaced earlier based on a comparison of the accumulated pitch to a predetermined absolute threshold. In addition, the promulgation of a winning vector does not have to be exact, and iterations for determining a winner can be stopped earlier either based on a predetermined relative accuracy (using the position of the global pointer) or based on the absolute accumulated sub-distance. Such a scheme would reduce power consumption for algorithms optimized for approximate nearest neighbor (ANN) searches.

15 FIG. 12 illustrates an example method of kNN searching according to an embodiment using embodiments of the above-described kNN accelerator. FIG. At a high level, the kNN search method involves calculating pitches, accumulating those pitches, and sorting those accumulated pitches in an entangled manner. Below is a more detailed description of this process.

In some embodiments, one or more variables are reset. For example, an accumulated distance for each reference vector, a global pointer, a global binary mask, a k-value, a valid bit for each reference vector (set to 1), a "done" bit for each reference vector (set to 0), and a local pointer for each reference vector.

at 1501 For each reference vector and element of this reference vector, an absolute difference is made between that element and a corresponding element in the query vector.

at 1503 a comparison threshold is set based on the global pointer.

A determination of whether to calculate a pitch is included 1505 performed. If the pitch is calculated, a pitch is calculated for each reference object vector with a valid bit set to 1 (indicating validity) (eg, using the circuitry in FIGS 3 and 4 and the compressor tree 211 ) and moved and at 1507 added to an accumulated distance.

If the pitch is not calculated or after 1507 is done is at 1509 for each reference object vector with a valid bit set to 1 (indicating validity), a global pointer dependent subset of bits (psum) of the accumulated distance are sent to the minimum sort network.

The sorting network finds 1511 a global minimum and a second minimum.

A determination of whether the global minimum minus the second minimum is greater than the specified threshold is included 1513 performed. If so, the accuracy is set to 1. If the precision is 1 or the global pointer is the LSB of the accumulated distance, the found minimum will be added 1515 set to 1.

at 1517 is typically parallel to 1513 for each reference object vector with a validity equal to 1, a comparison of the psum with the global minimum based on the specified threshold and a comparison of a previous iteration. Based on this comparison and the exact bit, the valid bit is updated so that it either remains at 1 and goes to zero. When the validity in the current iteration is updated to a 0, the current global pointer is written to the local pointer storage associated with this reference vector, and a 1 in the global binary mask is written to a 1 at the location of the global pointer.

at 1519 a determination is made as to whether the found minimum is equal to one. If so, k will join 1521 increased by 1. For the global minium vector is added 1521 Done also set to 1 and Valid set to 0. If not, the global pointer is included 1527 increased by 1 and the comparison threshold is set again.

After k has been increased, the global pointer will be added 1523 reduced to a position closest to 1 in the global binary mask. Essentially, a reset of the global pointer is made to a last position at which a reference object vector has been displaced from the search space.

at 1525 For each reference object vector, if the local pointer is greater than or equal to the global pointer and the done bit is equal to 0, the valid bit is set to 1 and the comparison threshold is reset. As a result, a reference vector is newly inserted into the search space when the nearest vectors are to be calculated.

Although the sorting and computation described above, which is performed in parallel for all reference vectors, these operations can be made more serial by performing the computation and the sorting operation for different vectors on the same circuit to save space.

The above-described systems, methods, and apparatus are operable to provide numerous advantages. The distance between vectors is calculated repeatedly so that in consecutive iterations the accuracy of the calculated distance improves from MSB to LSB. In each iteration, the calculation of a partial distance for a vector serves the purpose of improving the accuracy of the full (accumulated) distance at a particular value or bit position. The calculation of the full distance is divided into a number of part distance calculations for different metrics, such as: Euclid, Manhattan or scalar product, so that after computing the higher bits, accuracy improvement on lower order bit positions over successive iterations never alters the higher order bits beyond a certain threshold.

The above is accomplished by (i) dividing distance calculation circuits with circuits for 1D calculation using control signals to calculate the correct pitch and arranged according to the dimensionality of the vector, (ii) the partial distances of all 1D calculations summed using a compressor tree, and (iii) a Accumulator with storage for the current accumulated distance to which the pitch is added, having reached a corresponding value using a slider.

Sorting at these accumulated vector spacings does not wait for the full distance to be calculated - sorting can begin at low accuracy intervals. Sorting does not take into account all the bits of the accumulated distances - it is done in iterations with only a small window of bits from the MSB to the LSB. The sorting network uses a programmable threshold (in the example, it is 1 or 0) to explain whether the minimum found in each comparison and in the entire sort network in an iteration is smaller than any other number by more than this threshold.

The computation and sorting are interleaved from the MSB to the LSB so that many reference vectors with low accuracy distance computations are displaced out of the search space while only remaining vectors transition to the next iteration to improve the lower bit accuracy for closest neighbor determination.

Computations related to each vector have a local control that uses results from the sorting network to determine whether calculation and sorting for that vector will proceed to the next iteration or be removed from the search space.

Local control and space accumulators in each calculation maintain a state even after displacement from the search space. In finding the next nearest neighbor, the local controller can reinsert the vector (based on the global pointer) into the search space and any previous calculations up to the moment reuse earlier repression.

The global controller coordinates the activity of those bits in the accumulated distances sent to the sorting network using a global pointer that is transmitted to all vectors.

Control signals for the iteration-dependent partial distance calculation are also transmitted to all vectors from the global control. These control signals may be stored in a programmable look-up table referenced by the global pointer or as a fixed-function logic.

The global controller tracks iterations in which vectors are forced out of the search space when a next neighbor is found. Global control jumps back to the next iteration state where vectors have been displaced to begin searching only with those displaced vectors in the search space to find the next nearest neighbor.

The kNN accelerator can be made programmable to change the order of sorting.

Any number of bit sizes, dimensions, or any number of vectors is supportable. Additionally, in some embodiments, the kNN accelerator is programmable to program the bit sizes per dimension, dimensionality, or number of reference vectors.

The process can be made serial such that computation and sorting for different reference vectors are performed using common pitch calculation and sort circuits.

Exemplary core architectures, processors, and computer architectures

Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores include: 1) an in-order general purpose kernel intended for general purpose computing; 2) a high performance out-of-order general purpose kernel intended for general purpose computing; 3) a special purpose kernel intended primarily for graphics and / or scientific (throughput) computation. Implementations of different processors may include: 1) a main processor having one or more in-order general purpose cores intended for general purpose computing and / or one or more out-of-order general purpose cores intended for general purpose computation; and 2) a coprocessor comprising one or more special purpose cores intended primarily for graphics and / or for scientific (throughput) computation. Such different processors entail different computer system architectures that may include: 1) the coprocessor on a different chip than the main processor; 2) the coprocessor on another nude chip in the same housing as a main processor; 3) the coprocessor on the same die as a main processor (in which case a coprocessor is sometimes referred to as special purpose logic, e.g., as integrated graphics and / or scientific (throughput) logic or general purpose cores); and 4) a one-chip system running on the same die described main processor (sometimes referred to as the application core (s) or application processor (s)) may include the coprocessor described above and additional functions. Exemplary core architectures are described below, followed by descriptions of exemplary processors and computer architectures.

Exemplary core architectures

Block diagram of in-order and out-of-order cores

16A FIG. 10 is a block diagram showing both an exemplary in-order pipeline and an exemplary register rename out-of-order problem / execution pipeline in accordance with embodiments of the invention. FIG. 16B FIG. 12 is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming out-of-order problem / execution architecture core for incorporation into a processor in accordance with embodiments of the invention. The boxes framed by solid lines in the 16A and B show the in-order pipeline and the in-order core, while the optional complement, the boxes framed with dashed lines, show the register renaming out-of-order problem / execution pipeline or kernel. Assuming that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect is described.

In 16A includes a processor pipeline 1600 a charge level 1602 a length decoding stage 1604 , a decoding stage 1606 , an assignment level 1608 , a renaming level 1610 , a scheduling level (also known as the check-in or problem level) 1612 , a register read / memory read stage 1614 , an execution stage 1616 , a writeback / memory write stage 1618 , an exception handling level 1622 and a commitment level 1624 ,

16B shows a processor core 1690 , one with an execution engine unit 1650 coupled ballast unit 1630 includes, and both are with a storage unit 1670 coupled. The core 1690 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or a be alternative core type. As again another option may be the core 1690 be a special purpose core, such. A network or communication kernel, a compression engine, a coprocessor core, a general purpose computer graphics processor (GPGPU) core, graphics core, or the like.

The ballast unit 1630 includes one with a command cache unit 1634 coupled branch prediction unit 1632 using a command translation buffer (TLB) 1636 coupled with an instruction loading unit 1638 coupled with a decoding unit 1640 is coupled. The decoding unit 1640 (or the decoder) may decode instructions and generate as output one or more micro-ops, microcode entry points, micro-instructions, other instructions, or other control signals that are decoded from, or otherwise reflect or originate from, the original instructions. The decoding unit 1640 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read only memory (ROM), etc. In one embodiment, the core comprises 1690 a microcode ROM or other medium containing the microcode for certain macroinstructions (e.g., in the decode unit 1640 or otherwise within the ballast unit 1630 ) stores. The decoding unit 1640 is with a rename / assignment unit 1652 in the execution machine unit 1650 coupled.

The execution machine unit 1650 includes the rename / assignment unit 1652 with a rest unit 1654 and a set of one or more scheduler units 1656 , The one or more scheduler units 1656 stand for any number of different schedulers, including reservation stations, central command window, etc. The one or more scheduler units 1656 are with the physical register unit (s) 1658 coupled. Each of the registry units 1658 stands for one or more physical register sets, each of which stores one or more different types of data, such as: Scalar integer, scalar floating point, encoded integer, floating floating point, integer vector number, vector floating point, status (eg, an instruction pointer which is the address of the next instruction to execute), etc. In one embodiment, the one or more comprises several physical register sets 1658 a vector register unit, a write mask register unit and a scalar register unit. These register units provide architectural vector registers, vector mask registers, and general-purpose registers. The one or more physical register data units 1658 overlaps with the rest unit 1654 to illustrate various ways in which register renaming and out-of-order execution may be implemented (eg, using one or more reordering buffers and one or more idle register sets using one or more Future sets, history buffers, and idle register sets; using a tab and a pool of registers; Etc.). The resting unit 1654 and the one or more physical register data units 1658 are with the one or more execution clusters 1660 coupled. The one or more execution clusters 1660 comprise a set of one or more execution units 1662 and a set of one or more memory access units 1664 , The execution units 1662 can carry out various operations (eg shifts, addition, subtraction, multiplication) and on various types of data (eg at the scalar floating point, at the integer integer, at the floating floating point, at the whole vector number, at the vector floating point) , While such embodiments may include a number of execution units associated with particular functions or groups of functions, other embodiments may include only one or more execution units, all of which perform all functions. The one or more scheduler units 1656 containing one or more physical register data units 1658 and the one or more execution clusters 1660 are presented as possibly in the plural, as certain embodiments generate separate pipelines for certain types of data / operations (eg, a scalar integer pipeline, a scalar floating point / integer integer / hopped floating / integer vector / floating point) and / or a memory access pipeline each having its own scheduler unit, one or more physical register unit units and / or execution clusters - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of that pipeline is the one or more memory access units 1664 having). Thus, it will also be understood that if separate pipelines are used, one or more of these pipelines may be out-of-order problem / execution and the remainder in-order.

The set of storage access units 1664 is with the storage unit 1670 coupled to a data TLB unit 1672 includes with a data cache unit 1674 coupled with a level 2 (L2) cache unit 1676 is coupled. In one embodiment, the memory access units 1664 a load unit, a memory address unit, and a memory data unit, each associated with the data TLB unit 1672 in the storage unit 1670 are coupled. The command cache unit 1634 is further provided with a level 2 (L2) cache unit 1676 in the storage unit 1670 coupled. The L2 cache unit 1676 is coupled to one or more other cache levels and ultimately to a main memory.

For example, the exemplary register renaming out-of-order problem / execution core architecture may be the pipeline 1600 implement as follows: 1) the load instruction 1638 performs the load and length decode stages 1602 respectively. 1604 by; 2) the decoding unit 1640 performs the decode stage 1606 by; 3) the rename / assignment unit 1652 performs the assignment stage 1608 and the renaming level 1610 by; 4) the one or more scheduler units 1656 lead the scheduling stage 1612 by; 5) the one or more physical register data units 1658 and the storage unit 1670 carry the register read / memory read stage 1614 by; the execution cluster 1660 leads the execution stage 1616 by; 6) the storage unit 1670 and the one or more physical register data units 1658 perform the writeback / memory write stage 1618 by; 7) Diverse units can be at the exception handling level 1622 be involved; and 8) the rest unit 1654 and the one or more physical register data units 1658 lead the commitment level 1624 by.

The core 1690 may include one or more sets of instructions (e.g., the x86 instruction set (with some extensions added with newer versions); the MIPS instruction set from MIPS Technologies of Sunnyvale, California, the ARM instruction set (with optional additional extensions, such as the. NEON) from ARM Holdings in Sunnyvale, California), including the one or more commands described herein. In an embodiment, the core comprises 1690 Logic to support a cached data instruction set extension (e.g., AVX1, AVX2), which allows the operations used by many multimedia applications to be performed using cached data.

It should be understood that the core can support multi-strandedness (carrying out two or more parallel groups of processes or strands) in a variety of ways, including time-slicing, simultaneous multi-stranding (where a single physical core provides a logical core for each of the strands in which this core multithreading same applies) or a combination thereof (eg. as a loading and decoding in time slices and then simultaneous multithreading, such as. for example, in the Hyper-Threading technology from Intel ^®).

Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming may also be used in an in-order architecture. Although the illustrated embodiment of the processor also includes separate command and Data cache units 1634 / 1674 and a common L2 cache unit 1676 However, alternative embodiments may include a single internal cache for both instructions and data, such as: An internal level 1 (L1) cache or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and / or the processor. Alternatively, the entire cache may be external to the core and / or the processor.

Concrete exemplary in-order core architecture

The 17A and Figure B show a block diagram of a more concrete example in-order core architecture, where the core would be one of several logic blocks (including other cores of the same type and / or different types) in a chip. The logic blocks communicate through a high bandwidth interconnect network (eg, a ring network) with fixed-function logic, memory I / O interfaces, and other necessary I / O logic, depending on the application.

17A Figure 4 is a block diagram of a single processor core along with its connection to the bare-chip interconnect network 1702 and with its local subset at the level 2 (L2) cache 1704 according to embodiments of the invention. In one embodiment, a command decoder supports 1700 the x86 instruction set with a purged data instruction set extension. An L1 cache 1706 allows accesses to caches in the low latency scalar and vector units. While in one embodiment (to simplify the design), a scalar unit is used 1708 and a vector unit 1710 separate register sets (namely the scalar registers 1712 or the vector registers 1714 ) and the data transferred between them are written to the memory and then from a level 1 (L1) cache 1706 but alternative embodiments of the invention may use a different approach (eg, use a single set of registers or include a communication path that allows data to be transferred between the two sets of registers without being written in and read back).

The local subset of the L2 cache 1704 is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a random access path on its own subset of the L2 cache 1704 on. Data read by a processor core becomes in its L2 cache subset 1704 are stored, and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core becomes its own L2 cache subset 1704 stored and if necessary rinsed out of other subsets. The ring network ensures coherence for shared data. The ring network is bidirectional so that agents such as processor cores, L2 caches, and other logic blocks within the chip can communicate with each other. Each ring data path is in each direction 1012 Bits wide.

17B is an enlarged view of a portion of the processor core 17A according to embodiments of the invention. 17B includes an L1 data cache that is part of the L1 cache 1704 is, as well as more details about the vector unit 1710 and to the vector registers 1714 , Concrete is the vector unit 1710 a vector processor (VPU) of width 16 (see the ALU 1728 width 16) that executes one or more of the integer, single precision, and double precision floating point commands. The VPU supports mixing the register inputs with the mixing unit 1720 , numerical conversion with the numerical conversion units 1722a and B and replication with the replication unit 1724 on the storage input. Write mask registers 1726 allow for predicting resulting vector writes.

Processor with integrated memory control and graphics

18 is a block diagram of a processor 1800 which may have more than one core, may have an integrated memory controller and may have integrated graphics, according to embodiments of the invention. The boxes framed by solid lines in 18 show a processor 1800 with a single core 1802A , a system agent 1810 , a group of one or more bus control units 1816 while the extra complement, the boxed framed boxes, an alternative processor 1800 with several cores 1802A to N, a group of one or more integrated memory control units 1814 in the system agent unit 1810 and special purpose logic 1808 shows.

So can different implementations of the processor 1800 The following comprise: 1) a main processor, where the special purpose logic 1808 integrated graphics and / or scientific (throughput) logic (which may include one or more cores) and the cores 1802A until N is one or more general purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, a combination of these two); 2) a coprocessor, in which the cores 1802A to N a large number of Special purpose cores intended primarily for graphics and / or scientific (throughput) logic; and 3) a coprocessor in which the cores 1802A until N are a large number of general-purpose in-order cores. So can the processor 1800 a general purpose processor, a coprocessor or a special purpose processor such as A network or communications processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processor), a high-throughput many-integer-core (- MIC) coprocessor (comprising 30 or more cores), an embedded processor or the like, be. the processor may be implemented on one or more chips. The processor 1800 may be part of and / or implemented on one or more substrates using any of a variety of process technologies, such as: B. BiCMOS, CMOS or NMOS.

The memory hierarchy includes one or more cache levels within the cores, a set, or one or more shared cache units 1806 and external memory (not shown) coupled to the set of integrated memory control units 1814 is coupled. The set of shared cache units 1806 may include one or more center-level caches, such as Level 2 (L2), Level 3 (L3), Level 4 (L4) or other cache levels, a Last Level Cache (LLC), and / or combinations thereof. While in one embodiment, a ring-based interconnect unit 1812 the integrated graphics logic 1808 , the set of shared cache units 1806 and the system agent unit 1810 the one or more integrated memory controllers 1814 alternate embodiments may use any number of well-known methods for connecting such devices. In one embodiment, coherency between one or more cache units becomes 1806 and the cores 1802-A -N maintained.

In some embodiments, one or more of the cores 1802A to N to multi-stranded in the situation. The system agent 1810 includes those components that are the cores 1802A to coordinate and operate N. The system agent unit 1810 can z. A power control unit (PCU) and a display unit. The PCU may be logic and or for regulating the power state of the cores 1802A to N and the integrated graphics logic 1808 be required components or include. The display unit is used to operate one or more externally connected displays.

The cores 1802A to N may be homogeneous or heterogeneous in their architectural instruction set; ie two or more of the cores 1802A to may be capable of executing the same instruction set while others may be capable of executing only a subset of that instruction set or other instruction set.

Exemplary Computer Architectures

The 19 to 22 are block diagrams of exemplary computer architectures. Also other well-known designs and configurations for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network nodes, switches, embedded processors, digital signal processors (DSP), graphics devices, video game devices, set-top boxes, microcontrollers, Cell phones, portable media players, handheld devices, and various other electronic devices are suitable. In general, a gigantic variety of systems or electronic devices capable of incorporating a processor and / or other execution logic as disclosed herein are generally suitable.

Referring now to 19 is a block diagram of a system 1900 according to an embodiment of the present invention. The system 1900 can be one or more processors 1910 . 1915 include with a control hub 1920 are coupled. In an embodiment, the control node comprises 1920 a graphics memory control hub (GMCH) 1990 and an input / output network node (IOH) 1950 (which may each be on separate chips); the GMCH 1990 includes memory and graphics controls that use a memory 1940 and a coprocessor 1945 coupled; the IOH 1950 couples input / output (I / O) devices 1960 with the GMCH 1990 , Alternatively, one or both of memory and graphics controllers are integrated into the processor (as described herein) are the memory 1940 and the coprocessor 1945 directly with the processor 1910 coupled and the control network node 1920 with the IOH 1950 in a single chip.

That extra processors 1915 are optional, will be in 19 indicated by broken lines. Every processor 1910 . 1915 may include one or more of the processor cores described herein and one or the other version of the processor 1800 be.

The memory 1940 can z. Dynamic random access memory (DRAM), phase change memory (PCM), or a combination of both. For at least one embodiment, the control node communicates 1920 with the one or more processors 1910 . 1915 via a multidrop bus, such. B. a front-side bus (FSB), a point-to-point interface, such as For example, QuickPath Interconnect (QPI) or a similar connection 1995 ,

In one embodiment, the co-processor is 1945 a special purpose processor, such as A high-throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like. In one embodiment, the control node may be 1920 include an integrated graphics accelerator.

In terms of a useful metric spectrum, there can be many differences between physical resources 1910 . 1915 such as architectural, microarchitectural, temperature related, power consumption characteristics, and the like.

In one embodiment, the processor performs 1910 Commands that control data processing operations of a general type. Coprocessor instructions may be embedded in the instructions. The processor 1910 recognizes these coprocessor instructions as such of a type that is provided by the attached coprocessor 1945 should be executed. Accordingly, the processor judges 1910 these coprocessor instructions (or coprocessor instructions representing control signals) on a coprocessor bus or other interconnect to the coprocessor 1945 , The one or more coprocessors 1945 accept and execute the received coprocessor instructions.

Referring now to 20 Figure 13 is a block diagram of a first more concrete exemplary system 2000 according to an embodiment of the present invention. As in 20 is the multiprocessor system 2000 a point-to-point interconnect system and includes a first processor 2070 and a second processor 2080 that have a point-to-point link 2050 coupled together. Each of the processors 2070 and 2080 can be one or the other version of the processor 1800 be. In one embodiment of the invention, the processors are 2070 and 280 each of the processors 1910 respectively. 1915 while the coprocessor 2038 the coprocessor 1945 is. In another embodiment, the processors are 2070 and 2080 each processor 1910 or the coprocessor 1945 ,

The processors 2070 and 2080 including integrated memory control (IMC) units 2072 respectively. 2982 shown. The processor 2070 also includes point-to-point (PP) interfaces as part of its bus control units 2076 and 2078 ; Analogously, the second processor comprises 2080 the PP interfaces 2086 and 2088 , The processors 2070 . 2080 can use a point-to-point (PP) interface 2050 using the PP interface circuits 2078 . 2088 Exchange information. As in 20 shown, couple the IMC 2072 and 2082 the processors with respective memories, namely a memory 2032 and a memory 2034 which may be sections of a main memory locally connected to the respective processors.

The processors 2070 . 2080 can via individual PP interfaces 2052 . 2054 using the point-to-point interface circuits 2076 . 2094 . 2086 . 2098 each information with a chipset 2090 change. The chipset 2090 may optionally have a high performance interface 2039 Information with the coprocessor 2038 change. In one embodiment, the co-processor is 2038 a special purpose processor, such as A high-throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like.

A shared cache (not shown) may be included in either or both of the two processors, but connected to the processors via a PP interconnect, such that the local cache information of one or both processors may be stored in the shared cache, if any Processor is placed in a low power mode.

The chipset 2090 can via an interface 2096 with a first bus 2016 be coupled. In an embodiment, the first bus 2016 a Peripheral Component Interconnect (PCI) bus or a bus such as a PCI Express bus or other third generation I / O interconnect bus, although the scope of the present invention is not limited thereto.

As in 20 shown, various I / O devices 2014 with a first bus 2016 together with a bus bridge 2018 be coupled to the first bus 2016 with a second bus 2020 coupled. In one embodiment, one or more additional processors 2015 , such as Coprocessors, high-throughput MIC processors, GPGPU, accelerators (such as graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor with the first bus 2015 coupled. In one embodiment, the second bus 2020 be a low pin count (LPC) bus. Various devices may in one embodiment with a second bus 2020 be coupled, including z. As a keyboard and / or a mouse 2022 , Communication devices 2027 and a storage unit 2028 , such as B. a drive or any other mass storage device containing commands / code and data 2030 may include. Furthermore, an audio I / O 2024 with the second bus 2020 be coupled. It should be noted that other architectures may be possible. For example, instead of using a point-to-point architecture 20 a system implementing a multidrop bus or other such architecture.

Referring now to 21 Figure 13 is a block diagram of a second, more concrete exemplary system 2100 according to an embodiment of the present invention. Same elements in the 20 and 21 carry the same reference numerals, and certain aspects 20 missing in 21 to obscure other aspects of 21 to avoid.

21 shows that the processors 2070 . 2080 integrated memory and I / O control logic ("CL") 2072 respectively. 2082 may include. So include the CL 2072 . 2082 integrated memory control units and include I / O control logic. 21 shows that not only the memory 2032 . 2034 with the CL 2072 . 2082 but also I / O devices 2114 with the control logic 2072 . 2082 are coupled. Older I / O devices 2115 are with chipset 2090 coupled.

Referring now to 22 is a block diagram of a one-chip system 220 according to an embodiment of the present invention. Similar elements in 18 bear the same reference numerals. In addition, boxes framed with dashed lines are optional features on more advanced one-chip systems. In 22 is one or more interconnecting units 2202 coupled with: an application processor 2210 , which is a set of one or more cores 202A to N and one or more shared cache units 1806 includes; a system agent unit 1810 ; one or more bus control units 1816 ; one or more integrated memory control units 1814 ; a set of one or more coprocessors 2220 which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 2230 ; a direct memory access (DMA) unit 2232 ; and a display unit 2240 for pairing with one or more external displays. In an embodiment, the one or more coprocessors 2220 a special purpose processor, such as A network or communications processor, a compression engine, a GPGPU, a high-throughput MIC processor, an embedded processor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems including at least one processor, a storage system (including volatile and nonvolatile memory and / or storage elements), at least one input device, and at least one output device.

Program code, such as. B. the in 20 represented code 2030 may be applied to input instructions for performing the functions described herein and to generate output information. The output information may be applied in known manner to one or more output devices. For the purposes of this application, a processing system includes any system having a processor, such as a processor. A digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC) or a microprocessor.

The program code may be implemented in a high-quality procedural or object-oriented programming language to communicate with a processing system. The program code may also be implemented in assembler or machine language, if desired. In fact, the mechanisms described herein are not limited in their scope to any particular programming language. Anyway, the language can be a compiled or interpreted language.

One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium representing various logic within the processor that, when read by a machine, causes the machine to produce logic. to apply the techniques described herein. Such representations, known as "IP cores," may be stored on a tangible, machine readable medium and forwarded to various customers or manufacturing facilities to load them into the machine makes that make up the actual logic or processor.

Such machine-readable storage media may include, without limitation, non-transitory, specific arrangements of manufactured goods manufactured by a machine or device, including storage media such as hard disks, any other type of data disks such as floppy disks, optical disks, compact disk read only memories ( CD-ROM), rewritable compact disks (CD-RW) and magneto-optical disks, semiconductor devices such as read only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read only memory Memory (EPROM), phase change memory (PCM), magnetic or optical cards or any other type of medium suitable for storing electronic commands.

Accordingly, embodiments of the invention also include non-transitory, tangible, machine-readable media containing instructions or design data, such as hardware description language (HDL), that defines structures, circuits, devices, processors, and / or system features described herein. Such embodiments may also be referred to as program products.

Emulation (including binary translation, code morphing, etc.)

In some cases, a command converter can be used to convert a command from a source command set to a target command set. For example, the command converter may translate, morph, mimic, or otherwise convert a command into one or more other commands (eg, using a static binary translation, a dynamic binary translation, including dynamic compilation) to be processed by the core , The command converter can be executed in software, hardware, firmware or a combination thereof. The command converter may reside on a processor, not on a processor, partially on and partially off a processor.

23 FIG. 10 is a block diagram contrasting the use of a software instruction converter to convert binary instructions into a source instruction set of binary instructions in a target instruction set in accordance with embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although the instruction converter may alternatively be implemented in software, firmware, hardware, or combinations thereof. 23 shows that a program in a higher-level programming language 2302 using an x86 compiler 2304 can be compiled to binary x86 2306 to be generated by a processor with at least one x86 instruction set kernel 2316 can be carried out natively. The processor with at least one x86 instruction set core 2316 represents any processor that performs substantially the same functions as an Intel processor with at least one x86 instruction set kernel by (1) allocating a substantial portion of the instruction set of the Intel x86 instruction set kernel or (2) object code versions of applications or other software, which is designed to execute on an Intel processor having at least one x86 instruction set core, compatibly executes, or otherwise processes to achieve substantially the same result as an Intel processor having at least one x86 instruction set core. The x86 compiler 2304 represents a compiler that is used to generate binary code x86 2306 (eg, object code) operable with or without additional linking processing on the processor with at least one x86 instruction set core 2316 can be executed. 23 also shows that the program in the higher-level programming language using an alternative instruction set compiler 2308 can be compiled to an alternative instruction set binary code 2310 to be generated by a processor without at least one x86 instruction set kernel 2314 (eg, a processor having cores executing the MIPS instruction set from MIPS Technologies of Sunnyvale, California and / or executing the ARM instruction set from ARMS Holdings of Sunnyvale, California) may be natively executed. The command converter 2312 is used to binary code x86 2306 to convert that code from the processor without an x86 command set core 2314 can be carried out natively. This converted code is probably not the same as the alternative instruction set binary code 2310 because a command converter capable of doing so is difficult to manufacture; however, the converted code will accomplish the general operation and will consist of instructions from the alternative instruction set. Thus, the command converter 2312 Software, firmware, hardware, or a combination thereof, which through a processor or other electronic device that does not have an x86 instruction set processor or core, emulate, simulate, or otherwise process the x86 binary code 2306 perform.

Claims (22)

An apparatus, comprising: at least one vector pitch calculation circuit for calculating a partial sum and an accumulated distance for a set of vectors in a search space; a minimum sorting network for sorting a selected set of bits from the accumulated distances and specifying a minimum of the selected sets of bits of vectors in the search space and whether the minimum is unique; and a global control circuit for receiving an output of the minimum sorting network and for controlling aspects of operations of at least one vector pitch calculation circuit. The apparatus of claim 1, wherein each vector pitch calculation circuit comprises: a plurality of data element processing circuits; a compressor tree circuit for adding each result of the plurality of data element computer circuits; a local control circuit for outputting a smaller window of bits from the accumulated distance and using a result of the minimum sorting network to determine when calculation and sorting for a vector is to proceed with a next iteration or is removed from the search space; and an accumulator for adding results of the pitches in a current iteration, wherein correct significance is provided by a shifter to shift the pitch prior to adding to the accumulated distance over previous iterations. The apparatus of claim 1, wherein the minimum sorting network comprises: a plurality of first level compare nodes for receiving a partial sum and a valid bit from adjacent vector pitch calculation circuits and outputting a valid bit, an accurate bit, an address, and a sum, wherein the first level compare nodes serve logically OR the received adjacent valid bits to provide the issued valid bit, the adjacent valid bits exclusive to ORn, logically ORing a result of the exclusive OR with an output of a sum of possible differences in the comparison of adjacent sums to produce the output exact bit, wherein the exact bit is 1, to indicate whether a difference between the two inputs is greater than a programmable one Threshold or whether both inputs are not valid; and a plurality of second-level compare nodes for receiving a partial sum, a valid bit, an address, and an accurate bit from adjacent compare nodes, and outputting a valid bit, an accurate bit, an address, and a sum as a result of comparing the received sums to Selecting from incoming accurate signals and logically ANDing the selected exact bits with the exact signal calculated at that node to produce the output accurate signal indicative of whether the output sum is unique, the result of the comparison being one bit highest Order of the address is. The apparatus of claim 3, wherein the global control circuit comprises: an OR-tree for receiving and ORing a plurality of displacement bits from a plurality of local control circuits; a global mask for indicating to the global control logic where a global pointer must return to the group of vectors containing the next nearest neighbor; a selector for selecting the global pointer from a one-incremented previous global pointer and an output from a global encoder coupled priority encoder. The apparatus of claim 1, wherein a bit size per dimension, a dimensionality and a number of references are reconfigurable. An apparatus according to claim 2, wherein each of said plurality of data element processing circuits is a partial distance calculation sum of said absolute difference circuit. The apparatus of claim 2, wherein each of the plurality of data element computing circuits is a pitch calculation squaring circuit. The apparatus of claim 2, wherein each of the plurality of data element computing circuits is reconfigurable to function as part of a larger data element computing circuit for a plurality of data element bit-widths. The apparatus of claim 2, wherein each of the plurality of data element computing circuits is a pitch calculation scalar product circuit. The apparatus of claim 1, wherein the global control circuit is operative to coordinate the activity of the bits in the accumulated distances sent to the sorting network using a global pointer transmitted to all the vectors, control signals for iteration-dependent fractional distance calculation to all Transfer vectors and track iterations that displace vectors from the search space when they find a nearest neighbor. The apparatus of claim 10, wherein the control signals are to be stored in a programmable look-up table referenced by the global pointer. An apparatus according to claim 2, wherein the local control circuits and distance accumulators in each vector pitch calculation circuit serve to maintain a state even after being displaced from the search space, and the local control circuits are capable of reentering the vector into the search space, reusing the next nearest neighbor, and reusing any previous calculations up to the point of previous repression, wherein the local control circuits use the output of the minimum sorting network to determine when the calculation is done and sorting for a vector should continue with a next iteration or be removed from the search space. The device of claim 1, wherein the sorting device is configurable with increasing distance. The apparatus of claim 1, wherein the means for changing an order of sorting is configurable. The apparatus of claim 1, wherein the device is to operate on data sets larger than the memory capacity of the device, to compute sorted k nearest neighbor candidates with the device from a database, to replace displaced candidates with remaining object descriptors in memory, and to repeat until all object candidates have been worked through to find the k-nearest neighbor descriptor vectors. A method comprising: performing continuous iterations using at least one vector pitch calculation circuit for calculating pitches for a plurality of vectors with respect to a query vector, shifting the calculated pitches and accumulating the shifted calculated pitches, and using a minimum sorting network to sort these accumulated distances, starting from a most significant bit to a least significant bit. The method of claim 16, wherein each consecutive iteration improves accuracy of the calculated fractional distance from a most significant bit to a least significant bit. The method of claim 16, wherein the sorting of these accumulated distances begins from a most significant bit to a least significant bit with low precision intervals, and only remaining vectors continue with a next iteration to improve the lower bit accuracy for determining the nearest neighbor. The method of claim 16, wherein the sorting network performs the sorting using a programmable threshold to announce when a minimum found in each comparison and in an entire sorting network is less than any other number in an iteration by more than that threshold. The method of claim 16, wherein the calculation of the accumulated distances is decomposed into a number of sub-distance calculations for different metrics, such that after computing the upper bits, the accuracy improvement at lower-order bit positions never changes higher-order bits beyond a threshold. The method of claim 16, wherein calculating fractional distances for a plurality of vectors with respect to a query object vector comprises: using circuits with circuits for 1D computation using control signals to calculate the correct pitch and ordered by the dimensionality of the vector; summing the pitches of all 1D calculations using a compressor tree; and adding the summed separations to a current accumulated distance. The method of claim 16, wherein each iteration is performed in concert by the at least one vector pitch calculation and minimum sort network circuits.

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