TW201630168A - Pixel structure and manufacturing method thereof - Google Patents

Abstract

A pixel structure and a manufacturing method thereof are provided. The manufacturing methods includes forming a first electrode layer and a first insulating layer on a first substrate, forming a semiconductor layer on the first insulating layer, forming a gate insulating pattern layer on the semiconductor layer, and forming a first conductive layer, a second insulating layer, and a second conductive layer in sequence. The semiconductor layer includes first and second semiconductor patterns. The first conductive layer includes a scan line, a first gate electrode, a second gate electrode, and a first capacitor electrode. The second insulating layer includes first, second, third, and fourth openings. The second conductive layer includes a second capacitor electrode, a data line, first source and drain electrodes, and second source and drain electrodes. The second capacitor electrode, the first capacitor electrode, and the first electrode layer are overlapped to form a storage capacitor.

Description

Pixel structure and its manufacturing method

The present invention relates to a pixel structure and a method of fabricating the same, and more particularly to a pixel structure capable of maintaining a high aperture ratio and a method of fabricating the same.

The Organic Light Emitting Diode (OLED) panel is a self-illuminating display device, which has the advantages of wide viewing angle, power saving, simple process, low cost, wide operating temperature, high response speed and full color. And is expected to become the mainstream of the next generation of flat panel displays. In general, an organic light emitting diode panel includes a plurality of pixel structures, and each pixel structure includes a plurality of active components (eg, thin film transistors) or passive components (eg, resistors, capacitors), and A cathode or an anode electrically connected to the active element and an organic light-emitting layer between the cathode and the anode.

The active elements of the pixel structure can be fabricated using Indium gallium zinc oxide (IGZO) technology. IGZO is a metal oxide containing indium, gallium and zinc, and its carrier mobility is more than 10 times that of amorphous germanium (a-Si). Therefore, the charge and discharge rate of the active electrode to the pixel electrode can be greatly improved, and the implementation can be faster. The frame rate makes the animation play more smoothly. At present, the top gate type pixel structure generally has an anode disposed on the active device and the uppermost layer of the passive component. However, since this design will make the area occupied by the traces in the pixel structure larger, the aperture ratio cannot be improved. On the other hand, the current pixel structure also has a flat layer. However, due to the presence of a flat layer, miniaturization of the panel has a certain degree of difficulty.

The invention provides a pixel structure and a manufacturing method thereof, which can increase the aperture ratio and reduce the number of masks.

The method for fabricating a pixel structure of the present invention comprises forming a first electrode layer on a substrate and a first insulating layer covering a portion of the first electrode layer, forming a semiconductor layer on the first insulating layer, forming on the semiconductor layer a gate insulating pattern layer and a first conductive layer, a second insulating layer and a second conductive layer are sequentially formed. The semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern. The first conductive layer includes a scan line, a first gate over the first semiconductor pattern and connected to the scan line, a second gate over the second semiconductor pattern, and a first layer above the first electrode layer Capacitor electrode. The second insulating layer covers the first conductive layer, and the second insulating layer has a first opening and a second opening exposing the first semiconductor pattern and a third opening and a fourth opening exposing the second semiconductor pattern, wherein The fourth opening exposes the first electrode layer more. The second conductive layer includes a second capacitor electrode above the first capacitor electrode, a data line, a first source connected to the data line, a first drain, a second source, and a second drain, wherein the first source and the first drain are electrically connected to the first semiconductor pattern through the first opening and the second opening, respectively, the second source And the second drain is electrically connected to the second semiconductor pattern through the third opening and the fourth opening, the first drain is electrically connected to the second gate through the second opening, and the second capacitor electrode is transmitted through the fourth opening The first electrode layer is electrically connected, and the second capacitor electrode, the first capacitor electrode and the first electrode layer are overlapped to form a storage capacitor.

The pixel structure of the present invention comprises a substrate, a first electrode layer, a first insulating layer, a semiconductor layer, a gate insulating pattern layer, a first conductive layer, a second insulating layer and a second conductive layer. The first electrode layer is on the substrate. The first insulating layer is on the substrate and exposes the first electrode layer. The semiconductor layer is located on the first insulating layer and includes a first semiconductor pattern and a second semiconductor pattern. The gate insulating pattern layer is on the semiconductor layer. The first conductive layer includes a scan line, a first gate over the first semiconductor pattern and connected to the scan line, a second gate over the second semiconductor pattern, and a first layer above the first electrode layer Capacitor electrode. The second insulating layer covers the first conductive layer, wherein the second insulating layer has a first opening, a second opening, a third opening, and a fourth opening. The second conductive layer includes a second capacitor electrode above the first capacitor electrode, a data line, a first source connected to the data line, a first drain, a second source, and a second drain. The first source and the first drain are electrically connected to the first semiconductor pattern through the first opening and the second opening, respectively, and the second source and the second drain respectively pass through the third opening and the fourth opening and the second The semiconductor pattern is electrically connected, and the first drain passes through the second opening and the second The gate is electrically connected, and the second capacitor electrode is electrically connected to the first electrode layer through the fourth opening, and the second capacitor electrode, the first capacitor electrode and the first electrode layer are overlapped to form a storage capacitor.

Based on the above, the second capacitor electrode of the pixel structure of the present invention is disposed to overlap the first capacitor electrode and the first electrode layer. By this configuration, the capacitive structure of the pixel structure in the organic light emitting diode panel can be a parallel capacitor structure, which can reduce the required area of the capacitor. Therefore, the aperture ratio of the organic light emitting diode panel can be improved. On the other hand, since the pixel structure of the present invention can reduce two processes compared to the conventional pixel structure, cost can be saved.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Substrate

110‧‧‧First electrode layer

120‧‧‧First insulation material

122‧‧‧First insulation

130‧‧‧Semiconductor layer

132‧‧‧First semiconductor pattern

134‧‧‧second semiconductor pattern

140‧‧‧Second insulation material

142‧‧‧ brake insulating pattern layer

150‧‧‧Electrical materials

152‧‧‧First conductive layer

160‧‧‧metal layer

170‧‧‧ layer of oxidized metal material

170a‧‧ ‧ thin layer of oxidized metal

180‧‧‧Second layer of insulating material

180a‧‧‧Second insulation

190‧‧‧Second conductive layer

200‧‧‧Barrier

300‧‧‧Lighting layer

400‧‧‧Second electrode layer

G1‧‧‧ first gate

G2‧‧‧second gate

SL‧‧‧ scan line

DL‧‧‧ data line

PL‧‧‧Power cord

CE1‧‧‧first capacitor electrode

CE2‧‧‧second capacitor electrode

SR1‧‧‧First source area

DR1‧‧‧First bungee area

CR1‧‧‧ first passage area

S1‧‧‧first source

D1‧‧‧First bungee

SR2‧‧‧Second source region

DR2‧‧‧Second bungee area

CR2‧‧‧Second passage area

S2‧‧‧Second source

D2‧‧‧second bungee

CST‧‧‧ storage capacitor

CN‧‧‧Connecting Department

V1‧‧‧ first opening

V2‧‧‧ second opening

V3‧‧‧ third opening

V4‧‧‧ fourth opening

T1‧‧‧ first active component

T2‧‧‧second active component

OLED‧‧ Organic Light Emitting Diode

1A to 10A are schematic top views showing a manufacturing process of a pixel structure according to an embodiment of the present invention.

1B to 10B are schematic views showing a manufacturing process of a cross section taken along line A-A' and line B-B' of Figs. 1A to 10A.

Figure 11 is a cross-sectional view showing a pixel structure of an organic light emitting diode display panel according to an embodiment of the present invention.

Fig. 12 is an equivalent circuit diagram showing a pixel structure of an organic light emitting diode display panel according to an embodiment of the present invention.

Figure 13 is a cross-sectional view showing a pixel structure of an organic light emitting diode display panel according to another embodiment of the present invention.

1A to 10A are schematic top views showing a manufacturing process of a pixel structure according to an embodiment of the present invention. 1B to 10B are schematic views showing a manufacturing process of a cross section taken along line A-A' and line B-B' of Figs. 1A to 10A. The process flow of the pixel structure of the present invention will be sequentially described below.

Referring to FIG. 1A and FIG. 1B simultaneously, a substrate 100 is provided. The material of the substrate 100 may be glass, quartz, organic polymer, or other applicable materials. Next, a first electrode layer 110 and a first insulating material 120 are formed on the substrate 100. Wherein, in the present example, the first electrode layer 110 is in contact with the substrate 100 , and the first insulating material 120 covers the first electrode layer 110 . The first electrode layer 110 may be made of a conductive material such as a metal or a metal oxide. The first electrode layer 110 may be a transparent or opaque conductive material. In detail, the first electrode layer 110 is formed by forming a layer of an electrode material (not shown) on the substrate 100, and patterning the electrode material layer by a lithography and etching process to define the first electrode layer 110. An electrode layer 110. That is, in this step, the first mask process is used. In the present invention, the first electrode layer 110 may serve as an anode of the organic light emitting diode panel, but the invention is not limited thereto. In another aspect, the material of the first insulating material 120 comprises an inorganic material (eg, yttria, tantalum nitride, niobium oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), an organic material, or other suitable Material, or a combination of the above.

Referring to FIG. 2A and FIG. 2B simultaneously, the semiconductor layer 130 is formed on the first insulating material 120. The semiconductor layer 130 is formed by, for example, chemical vapor deposition (CVD) or other suitable processes, first forming a semiconductor material (not shown), and then lithography and etching to define a pattern. A semiconductor layer 130 is formed. In this step, a second mask process is used. In more detail, as shown in FIG. 2A, the semiconductor layer 130 has a first semiconductor pattern 132 and a second semiconductor pattern 134. The first semiconductor pattern 132 is separated from the second semiconductor pattern 134. The semiconductor layer 130 may be a metal oxide semiconductor material, polycrystalline germanium, amorphous germanium or other suitable semiconductor material, such as Indium-Gallium-Zinc Oxide (IGZO), zinc oxide (Indium-Gallium-Zinc Oxide, IGZO) ZnO) SnO, Indium-Zinc Oxide (IZO), Gallium-Zinc Oxide (GZO), Zinc-Tin Oxide (ZTO) or Indium-Indium- Tin Oxide, ITO).

Referring to FIG. 3A and FIG. 3B simultaneously, a second insulating material 140 and a conductive material 150 are sequentially formed on the semiconductor layer 130. The second insulating material 140 may be the same or different material as the first insulating material 120. For example, the material of the second insulating material 140 comprises an inorganic material (eg, yttria, tantalum nitride, ytterbium oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), an organic material, or other suitable Material, or a combination of the above. The material of the conductive material 150 includes a metal, and is formed by, for example, chemical vapor deposition (CVD) or other suitable process methods.

Next, the patterned conductive material 150, the second insulating material 140, and the first The insulating material 120 is formed to form the first conductive layer 152, the gate insulating pattern layer 142, and the first insulating layer 122, respectively, as shown in FIGS. 4A and 4B. In this embodiment, after the first conductive layer 152 and the gate insulating pattern layer 142 are first defined by the lithography process and the etching process, an etching process is used to remove the first insulation not covered by the semiconductor layer 130 and the first conductive layer 152. The material 120 is formed to form a first insulating layer 122 that exposes the first electrode layer 110. It should be noted that since the first conductive layer 152 and the gate insulating pattern layer 142 are defined by the same lithography process, that is, the first conductive layer 152 and the gate insulating pattern layer 142 use the same mask, A conductive layer 152 and a gate insulating pattern layer 142 have the same pattern. In this step, a third mask process is used.

As described above, the first conductive layer 152 includes the scan line SL, the first gate G1, the second gate G2, the first capacitor electrode CE1, and the connection portion CN. The first gate G1 is located on the gate insulating pattern layer 142 above the first semiconductor pattern 132 and is electrically connected to the scan line SL. The second gate G2 is formed on the gate insulating pattern layer 142 over the second semiconductor pattern 134. The first capacitor electrode CE1 is formed on the gate insulating pattern layer 142 over the first electrode layer 110. The connection portion CN is located on the gate insulating pattern layer 142 above the first semiconductor pattern 132 and is electrically connected to the second gate G2. In other words, the first gate G1 and the connection portion CN are disposed to overlap the first semiconductor pattern 132, the second gate G2 is overlapped with the second semiconductor pattern 134, and the first capacitor electrode CE1 is disposed to overlap the first electrode layer 110.

Referring to FIG. 5A and FIG. 5B simultaneously, after the first conductive layer 152 is formed, the first insulating layer 122, the semiconductor layer 130, and the first conductive layer 152 are further included. A thin metal layer 160 is formed on the first electrode layer 110. The material of the thin metal layer 160 is, for example, aluminum or other metal material, but the invention is not limited thereto. An annealing process is then performed such that the thin metal layer 160 forms a layer 170 of oxidized metal material, as shown in Figures 6A and 6B. It is to be noted that, in order to better clearly show the configuration between the elements, the metal thin layer 160 and the oxidized metal material layer 170 are not shown in the upper views of FIGS. 5A and 6A.

Referring again to FIGS. 6A and 6B, in the above annealing process, at a region where the thin metal layer 160 and the semiconductor layer 130 are in contact, metal atoms in the metal thin layer 160 may react with the semiconductor layer 130 to make the conductive portion there. The degree is increased to form a first source region SR1, a first drain region DR1, a second source region SR2, and a second drain region DR2. The semiconductor layer 130 between the first source region SR1 and the first drain region DR1 forms the first channel region CR1, and the semiconductor layer 130 between the second source region SR2 and the second drain region DR2 is formed. The second channel area CR2. In other words, in the embodiment, the first semiconductor pattern 132 has a first source region SR1, a first drain region DR1 and a first channel region CR1, and the second semiconductor pattern 134 has a second source region SR2, a second The drain region DR2 and the second channel region CR2. Additionally, the oxidized metal material layer 170 can serve as an insulating layer to provide insulation between the first conductive layer 152 and the metal layer formed by subsequent processes.

Referring to FIG. 7A and FIG. 7B simultaneously, a second insulating material layer 180 is formed on the oxidized metal material layer 170. The material of the second insulating material layer 180 may be the same or different material as the gate insulating pattern layer 142 and the first insulating layer 122. For example, the material of the second insulating material layer 180 contains an inorganic material (for example: yttrium oxide, Niobium nitride, niobium oxynitride, other suitable materials, or a stacked layer of at least two of the above materials, organic materials, or other suitable materials, or a combination thereof, but the invention is not limited thereto.

Next, referring to FIG. 8A and FIG. 8B, a second lithography process is performed on the second insulating material layer 180 and the oxidized metal material layer 170 to form a first opening V1, a second opening V2, a third opening V3, and The thin metal oxide layer 170a and the second insulating layer 180a of the fourth opening V4. The first opening V1 exposes the first source region SR1, the second opening V2 exposes the first drain region DR1 and a portion of the first conductive layer 152 (connection portion CN), and the third opening V3 exposes the second source region SR2, and the fourth opening V4 exposes the second drain region DR2 and the first electrode layer 110. It is worth noting that in this step, the fourth mask process is used.

Referring to FIG. 9A and FIG. 9B simultaneously, a second conductive layer 190 is formed on the second insulating layer 180a. The second conductive layer 190 includes a data line DL, a first source S1, a first drain D1, a second capacitor electrode CE2, a second source S2, a second drain D2, and a power line PL. The second conductive layer 190 is formed by, for example, forming a layer of a conductive material (not shown) and then patterning it, which is a fifth mask process. The data line DL is electrically connected to the first source S1, the second drain D2 is electrically connected to the second capacitor electrode CE2, and the second source S2 is electrically connected to the power line PL. The first source S1 is connected to the first source region SR1 of the first semiconductor pattern 132 through the first opening V1. The first drain D1 is connected to the connection portion CN (first conductive layer 152) and the first drain region DR1 of the first semiconductor pattern 132 through the second opening V2. The second source S2 is connected to the second source region SR2 of the second semiconductor pattern 134 through the third opening V3. The second drain D2 is electrically connected to the second drain region DR2 of the second semiconductor pattern 134 and the first electrode layer 110 through the fourth opening V4. As described above, since the first drain D1 is connected to the connection portion CN through the second opening V2, and the connection portion CN is electrically connected to the first capacitor electrode CE1 and the second gate G2, the first drain D1 is substantially The upper portion is electrically connected to the first capacitor electrode CE1 and the second gate G2 through the second opening V2 and the connection portion CN. On the other hand, the second capacitor electrode CE2 is disposed to overlap the first capacitor electrode CE1 and the first electrode layer 110 to constitute a storage capacitor CST. In detail, a coupling capacitance is formed between the second capacitor electrode CE2 and the first capacitor electrode CE1, and a coupling capacitor is also formed between the first capacitor electrode CE1 and the first electrode layer 110, and the storage capacitor CST is The coupling capacitors are added together.

Referring to FIG. 10A and FIG. 10B, a barrier layer 200 is formed on the second conductive layer 190, and the barrier layer 200 exposes the first electrode layer 110 by a process of the sixth mask. The material of the barrier layer 200 includes an inorganic material or an organic material. In the present embodiment, the barrier layer 200 is an organic material, and the barrier layer 200 is formed by coating, and thus has a flat surface. In detail, the organic material used for the barrier layer 200 may be a novolac, a polyimide (PI), or an Acrylic. Next, the light emitting layer 300 is formed on the first electrode layer 110 exposed by the barrier layer 200. The light emitting layer 300 may be a red organic light emitting pattern, a green organic light emitting pattern, a blue organic light emitting pattern, or a different color (eg, white, orange, purple, etc.) light emitting pattern generated by mixing light of each spectrum, but the present invention is not limited thereto. this.

Please refer to FIG. 11 , and then formed on the light-emitting layer 300 and the barrier layer 200. The second electrode layer 400. The material of the second electrode layer 400 may be a conductive material such as a metal or a metal oxide. In the present invention, the second electrode layer 400 can serve as a cathode of the organic light emitting diode panel, but the present invention is not limited thereto. In other words, the first electrode layer 110, the light emitting layer 300, and the second electrode layer 400 constitute an organic light emitting diode OLED.

The pixel structure formed by the above process is shown in FIG. 11, and FIG. 12 is an equivalent circuit diagram of the pixel structure of the organic light emitting diode display panel according to an embodiment of the present invention. Referring to FIG. 11 and FIG. 12 simultaneously, the first electrode layer 110 is located on the substrate 100. The first insulating layer 122 is located on the substrate 100 and exposes the first electrode layer 110. The semiconductor layer 130 is located on the first insulating layer 122 and includes a first semiconductor pattern 132 and a second semiconductor pattern 134. The gate insulating pattern layer 142 is on the semiconductor layer 130. The first conductive layer 152 includes a scan line SL, a first gate G1 connected to the gate insulating pattern layer 142 above the first semiconductor pattern 132, and connected to the scan line SL1, and a gate insulating pattern layer 142 over the second semiconductor pattern 134. The upper second gate G2, the connection portion CN on the gate insulating pattern layer 142 above the first semiconductor pattern 132 and electrically connected to the second gate G2, and the gate insulating pattern layer above the first electrode layer 110 The first capacitor electrode CE1. The second insulating layer 180a covers the first conductive layer 152 and has a first opening V1, a second opening V2, a third opening V3, and a fourth opening V4. The second conductive layer 190 includes a second capacitor electrode CE2 located above the first capacitor electrode CE1, a data line DL, and a first source S1, a first drain D1, a second source S2, and a second port connected to the data line DL. The pole D2 and the power line PL electrically connected to the second source S2. The first source S1, the first drain D1, and the first gate G1 constitute a first active device T1, a second source S2, a second drain D2, and a second gate G2 The second active element T2 is formed. The first source S1 and the first drain D1 are electrically connected to the first semiconductor pattern 132 through the first opening V1 and the second opening V2, respectively, and the second source S2 and the second drain D2 respectively pass through the third opening V3 and The fourth opening V4 is electrically connected to the second semiconductor pattern 134. The first drain electrode D1 is electrically connected to the first capacitor electrode CE1 and the second gate G2 through the second opening V2 and the connection portion CN, and the second capacitor electrode CE2 is electrically connected to the first electrode layer 110 through the fourth opening V4. . The second capacitor electrode CE2, the first capacitor electrode CE1, and the first electrode layer 110 are overlapped to form a storage capacitor CST. The barrier layer 200 is located on the second conductive layer 190 and exposes the first electrode layer 110. The light emitting layer 300 is located on the exposed first electrode layer 110. The second electrode layer 400 is located on the light emitting layer 300 and covers the barrier layer 200 and the light emitting layer 300.

As described above, in the pixel structure of the embodiment, the second capacitor electrode CE2 is disposed to overlap the first capacitor electrode CE1 and the first electrode layer 110, so that a parallel capacitor structure can be formed to reduce the required area of the capacitor. Thereby, the pixel structure of the present embodiment can increase the aperture ratio. In addition, since the first conductive layer 152, the gate insulating pattern layer 142, and the first insulating layer 122 are simultaneously defined by the same mask process, the use of the mask can be reduced. In other words, the present embodiment can reduce the number of processes of the photomask. On the other hand, the barrier layer 200 of the present embodiment is a flat organic material, so that the arrangement of the flat layer in the other conventional pixel structure can be eliminated, thereby achieving the purpose of panel miniaturization.

Figure 13 is a cross-sectional view showing a pixel structure of an organic light emitting diode display panel according to another embodiment of the present invention. Referring to FIG. 13 , the pixel structure of the organic light emitting diode display panel of the present embodiment is similar to that of the pixel structure panel of FIG. 11 , and therefore the same components are denoted by the same reference numerals and the description thereof will not be repeated. The difference between this embodiment and the embodiment of FIG. 11 is that in the present embodiment, the material of the barrier layer 200 is an inorganic material. For example, inorganic material such as a silicon oxide (SiO _x), silicon nitride or other inorganic material, but the present invention is not limited thereto. In the present embodiment, the barrier layer 200 of inorganic material is conformally covered on the surface of the formed structure so that it does not have a flat surface.

Similar to the embodiment of FIG. 11, in the pixel structure of the embodiment, the second capacitor electrode CE2 is overlapped with the first capacitor electrode CE1 and the first electrode layer 110, so that a parallel capacitor structure can be formed to reduce the capacitance required. area. Thereby, the pixel structure of the present embodiment can increase the aperture ratio. In addition, since the gate insulating pattern layer 142, the first conductive layer 152, and the first insulating layer 122 are simultaneously defined by the same mask process, the use of the mask can be reduced. In other words, the present embodiment can reduce the number of processes of the photomask. On the other hand, the barrier layer 200 of the present embodiment is an inorganic material, so that the water blocking force is increased. By improving the water blocking capability of the pixel structure, the stability and reliability of the thin film transistor in the pixel structure can also be improved. In addition, since the arrangement of the flat layer can be eliminated in the present embodiment, the material selection of the barrier layer 200 is not limited by the flat layer, so the barrier of the present embodiment is compared to the conventional pixel structure. The material of layer 200 can be selected to be more flexible.

In summary, the first film layer of the pixel structure of the present invention is a first electrode layer, and the second capacitor electrode is disposed to overlap the first capacitor electrode and the first electrode layer. The capacitor structure of the pixel structure in the organic light emitting diode panel can be configured by this configuration Become a shunt capacitor architecture to reduce the area required for the capacitor. Therefore, the aperture ratio of the organic light emitting diode panel can be improved. On the other hand, since the pixel structure of the present invention has the first electrode layer as the first film layer and the subsequent film layer is electrically connected to the first film layer through the opening, it can at least be compared with the general parallel capacitor structure. Reduce the two processes and save costs. In addition, since the pixel structure of the present invention simultaneously uses the barrier layer as a flat layer, the arrangement of the additional flat layer can be omitted, and the elasticity of the material selection of the barrier layer can be increased.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Substrate

110‧‧‧First electrode layer

122‧‧‧First insulation

130‧‧‧Semiconductor layer

132‧‧‧First semiconductor pattern

134‧‧‧second semiconductor pattern

142‧‧‧ brake insulating pattern layer

152‧‧‧First conductive layer

170a‧‧ ‧ thin layer of oxidized metal

180a‧‧‧Second insulation

190‧‧‧Second conductive layer

200‧‧‧Barrier

300‧‧‧Lighting layer

400‧‧‧Second electrode layer

G1‧‧‧ first gate

G2‧‧‧second gate

DL‧‧‧ data line

PL‧‧‧Power cord

CE1‧‧‧first capacitor electrode

CE2‧‧‧second capacitor electrode

SR1‧‧‧First source area

DR1‧‧‧First bungee area

CR1‧‧‧ first passage area

S1‧‧‧first source

D1‧‧‧First bungee

SR2‧‧‧Second source region

DR2‧‧‧Second bungee area

CR2‧‧‧Second passage area

S2‧‧‧Second source

D2‧‧‧second bungee

CST‧‧‧ storage capacitor

CN‧‧‧Connecting Department

V1‧‧‧ first opening

V2‧‧‧ second opening

V3‧‧‧ third opening

V4‧‧‧ fourth opening

OLED‧‧ Organic Light Emitting Diode

Claims (16)

A method for fabricating a pixel structure includes: forming a first electrode layer on a substrate; forming a first insulating layer on the substrate to cover a portion of the first electrode layer; forming a semiconductor on the first insulating layer a layer, wherein the semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern; forming a gate insulating pattern layer on the semiconductor layer; forming a first conductive layer on the gate insulating pattern layer, wherein the first conductive layer The layer includes a scan line, a first gate above the first semiconductor pattern and connected to the scan line, a second gate above the second semiconductor pattern, and a first layer above the first electrode layer a first capacitor electrode; forming a second insulating layer covering the first conductive layer, and the second insulating layer has a first opening and a second opening exposing the first semiconductor pattern and exposing the second semiconductor pattern a third opening and a fourth opening, wherein the fourth opening exposes the first electrode layer; and forming a second conductive layer, wherein the second conductive layer is located at the first a second capacitor electrode above the capacitor electrode, a data line, a first source connected to the data line, a first drain, a second source, and a second drain, wherein the first source And the first drain and the second opening are electrically connected to the first semiconductor pattern through the first opening and the second opening, respectively, wherein the second source and the second drain respectively pass through the third opening and the fourth opening The second semiconductor pattern is electrically connected, the first drain is electrically connected to the second gate through the second opening, and the second capacitor electrode is transparently The fourth opening is electrically connected to the first electrode layer, and the second capacitor electrode, the first capacitor electrode and the first electrode layer are overlapped to form a storage capacitor. The method for fabricating a pixel structure according to claim 1, further comprising: forming a barrier layer on the second conductive layer to expose the first electrode layer; and exposing the first electrode layer Forming a light emitting layer thereon; forming a second electrode layer on the light emitting layer. The method of fabricating a pixel structure according to claim 2, wherein the barrier layer comprises an inorganic material. The method of fabricating a pixel structure according to claim 2, wherein the barrier layer comprises a flat organic material. The method for manufacturing a pixel structure according to claim 1, wherein the second conductive layer further comprises a power line electrically connected to the second source. The method for manufacturing a pixel structure according to claim 1, wherein after forming the first conductive layer, further comprising: forming a thin metal layer on the first conductive layer; performing an annealing process to enable The first semiconductor pattern in contact with the thin metal layer forms a first source region and a first drain region, and the second semiconductor pattern in contact with the metal thin layer forms a second source region and a first a second drain region, and at the same time, forming a thin layer of metal oxide material; and patterning the metal oxide material layer to form a thin metal oxide layer, wherein the thin metal oxide layer corresponds to the first opening and the first Two openings respectively expose the first The source region and the first drain region respectively expose the second source region and the second drain region corresponding to the third opening and the fourth opening. The method for fabricating a pixel structure according to claim 1, wherein the method of forming the gate insulating pattern layer and the first conductive layer comprises: sequentially forming an insulating material and a conductive material; and simultaneously patterning the a conductive material and the insulating material to define the gate insulating pattern layer and the first conductive layer. The method for fabricating a pixel structure according to claim 1, wherein the method of forming the first insulating layer, the semiconductor layer, the gate insulating pattern layer, and the first conductive layer comprises: forming a a first insulating material covering the first electrode layer; forming the semiconductor layer on the insulating material; sequentially forming a second insulating material and a conductive material on the semiconductor layer; simultaneously patterning the conductive material, and the a second insulating material to define the gate insulating pattern layer and the first conductive layer, and simultaneously removing the first insulating material not covered by the semiconductor layer and the first conductive layer to form the first exposed The first insulating layer of the electrode layer. A pixel structure includes: a first electrode layer on a substrate; a first insulating layer on the substrate and exposing the first electrode layer; a semiconductor layer on the first insulating layer and including a first semiconductor pattern and a second semiconductor pattern; a gate insulating pattern layer on the semiconductor layer; a first conductive layer on the gate insulating pattern layer, wherein the first conductive layer includes a scan line, above the first semiconductor pattern and the scan line a first gate connected, a second gate above the second semiconductor pattern, and a first capacitor electrode above the first electrode layer; a second insulating layer covering the first conductive layer, wherein The second insulating layer has a first opening, a second opening, a third opening, and a fourth opening; and a second conductive layer, the second conductive layer includes a second portion above the first capacitor electrode a capacitor electrode, a data line, a first source connected to the data line, a first drain, a second source, and a second drain, wherein the first source and the first drain respectively The first source and the second opening are electrically connected to the first semiconductor pattern, and the second source and the second drain respectively pass through the third opening and the fourth opening and the second semiconductor pattern are electrically connected Connection, the first one The second capacitor is electrically connected to the second gate through the second opening, and the second capacitor electrode is electrically connected to the first electrode layer through the fourth opening, the second capacitor electrode, the first capacitor electrode, and the first An electrode layer is overlapped to form a storage capacitor. The pixel structure of claim 9, further comprising: a barrier layer on the second conductive layer and exposing the first electrode layer; and a light emitting layer on the exposed first electrode layer And a second electrode layer on the luminescent layer. The pixel structure of claim 10, wherein the barrier layer comprises an inorganic material. The pixel structure of claim 10, wherein the barrier layer comprises a flat organic material. The pixel structure of claim 9, wherein the second conductive layer further comprises a power line electrically connected to the second source. The pixel structure of claim 9, further comprising a thin layer of metal oxide, between the semiconductor layer and the second insulating layer. The pixel structure of claim 14, wherein the first semiconductor pattern has a first source region and a first drain region, the second semiconductor pattern has a second source region and a a second drain region, the first metal source region of the uncovered portion, a portion of the first drain region, a portion of the second source region, and a portion of the second drain region, and The first source and the first drain are electrically connected to the first source region and the first drain region through the first opening and the second opening, respectively, the second source and the second drain The poles are electrically connected to the second source region and the second drain region through the third opening and the fourth opening, respectively. The pixel structure of claim 9, wherein the gate insulating pattern layer and the first conductive layer have the same pattern.