TW201629976A - Non-volatile semiconductor memory device - Google Patents

Abstract

A non-volatile semiconductor memory device, which restrains a breakdown of a low-voltage transistor constructing a bit line selecting circuit, is provided. An NAND string unit and transistors (BLSe, BLso, BIASe, BIASo) that construct bit line selecting circuit are formed in a P-well. The transistors are set in a floating state during erasing operation. The voltages of the transistors are increased when an erasing voltage is applied to the P-well. When the erasing voltage is discharged from the P-well, the gates of the transistors are connected to a reference potential via a discharging circuit (410) such that the gate voltage follows the voltage of the P-well to be discharged.

Description

Non-volatile semiconductor memory device

The present invention relates to a non-volatile semiconductor memory device, and more particularly to a NAND (Not AND) type flash memory.

The NAND type flash memory is constructed by including an array of memory blocks arranged by arranging a plurality of NAND strings in a row direction. The NAND string is composed of a plurality of memory cells connected in series and a selection transistor connected to both ends thereof, wherein one end portion is connected to the bit line via the bit line side selection transistor and the other end is connected to the source line. The side selects the transistor and is connected to the source line. Reading or programming (writing) of data is performed via bit lines connected to the NAND strings.

FIG. 1 is a configuration diagram showing a bit line selection circuit of a conventional NAND flash memory. Here, the pair of bit lines of the even bit line BLe and the odd bit line BLo are shown. The bit line selection circuit 10 has a first selection unit 20 including a bit line selection transistor BLC for connecting an even bit line BLe or an odd bit line BLo to the readout circuit. And the second selection unit 30, package The even-biased transistor BIASe and the odd-biased transistor BIASo, the even-bit line selection transistor BLSe, and the odd-bit line selection transistor BLSo, the even-biased transistor BIASe and the odd-biased transistor BIASo are used for A bias voltage VPRE is applied to the even bit line BLe and the odd bit line BLo for connecting the even bit line BLe to the bit line selection transistor BLS, the odd bit line selecting electricity The crystal BLSo is used to connect the odd bit line BLo to the bit line selection transistor BLC. Such a bit line selection circuit 10 is connected to the readout circuit 40. Here, the second selection unit 30 is formed on a P substrate different from the P well region in which the lattice array is formed, and by applying an erase voltage to the selected block (P well) during the erase operation, all the bit lines are raised. Press to erase voltage. On the other hand, since the P substrate is 0 V (ground (GND)), the even bias transistor BIASe and the odd bias transistor BIASo, the even bit line selection transistor BLSe, and the odd bit constituting the second selection portion 30 are formed. The line selection transistor BLSo includes a high voltage (HV) transistor having a gate oxide film thickness and a long gate length and a high withstand voltage.

In Patent Document 1, Patent Document 2, and Non-Patent Document 1, as shown in FIG. 2, the second selection unit 30A of the bit line selection circuit 10A includes a low voltage (LV) transistor, and the second selection unit 30A and the second selection unit 30A A relay unit 32 including a high voltage (HV) transistor BLS is provided between the first selection units 20. The transistors BIASe, BIASo, BLSe, and BLSo constituting the second selection unit 30A are formed in the block 50 of the memory array in which the NAND string unit NU is formed, that is, in the P well 60, and the transistors BIASe, BIASo, BLSe, and BLSo are in A low voltage (LV) transistor formed in the same process as the memory cell, having a short gate length and a thin gate oxide film. Transistor 32 transistor BLS The transistor BLC of the first selection unit 20 is separated from the transistor of the second selection unit 30A by being disposed outside the P well 60 forming the memory cell array. By configuring the second selection unit 30A as a low-voltage transistor, the layout area occupied by the second selection unit 30A is reduced, and the overall memory size is reduced. On the other hand, at the time of the erasing operation, an erase voltage or an erase pulse of about 20 V is applied to the P well 60, but at this time, the gates of all the transistors constituting the second selection portion 30A are set to float, and the transistor The gate is boosted to near the erase voltage by capacitive coupling with the P-well 60. Therefore, a large potential difference is not applied to the gate oxide film of the transistors BIASe, BIASo, BLSe, BLSo, thereby avoiding breakdown of the gate oxide film.

[Previous Technical Literature]

[Patent Literature]

[Patent Document 1] Japanese Patent No. 5550609

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2011-23661

[Non-Patent Document 1] K. Fukuda. Et al., "151 mm2 64Gb MLC NAND Memory Using 24n CMOS Technology", IEEE International Solid State Circuit Conference, Technical Paper Abstract P198-199, No. 11, 2011 (K. Fukuda. Et al., "A 151 mm2 64 Gb MLC NAND Memory in 24n, CMOS Technology", IEEE International Solid-State Circuit Conference, Digest of Technical Paper P198-199, Session 11, 2011).

As described above, by forming the transistors BIASe, BIASo, BLSe, and BLSo of the second selection unit 30A in the P well 60 which is the block 50 of the memory array, the occupied area of the second selection unit 30A can be reduced. However, the configuration of the second selection unit 30A has the following problems.

In the erase operation, the transistors BIASe, BIASo, BLSe, and BLSo of the second selection unit 30A are set to be in a floating state, and the gate voltage Vgate of the transistors BIASe, BIASo, BLSe, and BLSo is applied to the erase of the P well 60. When the voltage Vers rises, it gradually rises due to capacitive coupling with the P well voltage Vpw. The peak value of the applied erase voltage Vers is, for example, about 20 V, and the erase voltage Vers maintains a peak voltage for a fixed period so that electrons are sufficiently released from the memory cell to the P well 60. When the application of the erase voltage Vers ends, the P well voltage Vpw is discharged, and accordingly, the gate voltage Vgate of the transistor also gradually decreases.

However, wiring extending across the P well 60 is connected to the gates of the transistors BIASe, BIASo, BLSe, and BLSo, so the gate voltage Vgate may be received between the P-type germanium substrate or other wells directly under the wiring. The parasitic capacitance and the influence of the parasitic capacitance between the adjacent wirings do not follow the decrease in the P-well voltage Vpw.

FIG. 3 is a graph schematically showing the P-well voltage Vpw and the gate voltage Vgate of the transistors BIASe, BIASo, BLSe, and BLSo. The P well voltage Vpw is indicated by a solid line, and the gate voltage Vgate is indicated by a broken line. At time t0, 0 V is applied to the word line WL of the selected block, and the transistors BIASe, BIASo, BLSe, BLSo are set to a floating state. At time T1, an erase voltage Vers is applied to the P well 60. example For example, an erase pulse whose voltage is gradually increased is applied to the P well. In response to the application of the erase pulse, the P-well voltage Vpw starts to boost. At the same time, the gate voltage Vgate of the transistors BIASe, BIASo, BLSe, BLSo capacitively coupled to the P-well is boosted. At time T2, the P well voltage Vpw is boosted to about 20 V, and during the period from T2 to T3, the fixed time required for erasing is elapsed, and electrons are extracted from the floating gate to the P well 60.

In the erasing period T2 to T3, the gate voltage Vgate of the transistors BIASe, BIASo, BLSe, and BLSo is set to a fixed potential or lower in accordance with the coupling ratio with the P well 60. As shown in FIG. 3, if the potential difference Va between the P well voltage Vpw and the gate voltage Vgate of the transistor is not set to a fixed value or less, the dielectric breakdown of the transistor due to time dependence may be caused by dielectric breakdown characteristics (Time). Dependent Dielectric Breakdown, TDDB) was damaged. TDDB is a phenomenon as follows: Even if a high voltage is not applied to the gate of the transistor, if a voltage is applied for a long time, the transistor will still break down. Therefore, the coupling ratio between the transistor and the P well is set in such a manner as to satisfy Va<TDDB.

At the time T3, the application of the erase voltage Vers is completed, and the P well voltage Vpw is discharged. When the discharge is started, the discharge path is connected to the P well 60, and the charge is discharged via the discharge path, so that the P well voltage Vpw falls relatively quickly. On the other hand, on the gates of the transistors BIASe, BIASo, BLSe, and BLSo, a discharge path for discharging the electric charge is not connected, and further, a wiring having a parasitic capacitance is connected to the gate, and thus the discharge speed of the gate voltage Vgate is Slower than the P-well voltage Vpw. As a result, at time T4, when the P-well voltage Vpw reaches 0V, the gate voltage Vgate of the transistor is still the voltage Vb, and if Vb>TDDB, it is possible to cause the transistor BIASe, BIASo, BLSe, and BLSo were penetrated.

Accordingly, an object of the present invention is to solve the above conventional problems and to provide a semiconductor memory device which suppresses breakdown of a low voltage transistor constituting a bit line selection circuit.

The semiconductor memory device of the present invention comprises: a memory cell array formed with a plurality of reverse gate strings, wherein the reverse gate strings are electrically rewritten memory cells connected in series; erasing components, erasing the memory a memory cell in the selected block of the cell array; and a bit line selection circuit that selects a bit line respectively connected to the inverse gate string to form at least one bit line of the bit line selection circuit Selecting a transistor formed in the well, the well forming a memory cell, the erase component comprising: a first component that applies an erase voltage to a well of the selected block; and a second component that selects the selected block The at least one bit line selection transistor formed in the well is in a floating state; and the third component selects the at least one bit line when discharging the voltage of the well of the selected block The gate of the crystal is discharged to the reference potential.

Preferably, the third member generates a discharge path between the gate of the at least one bit line selection transistor and the reference potential. Preferably, the third member includes a first discharge transistor for generating a discharge path between a gate of the at least one bit line selection transistor and a reference potential, And the first discharge transistor is turned on when the voltage of the well is discharged. Preferably, the third component includes at least one diode, and the at least one diode is connected in series between the gate of the at least one bit line selection transistor and a reference potential. Place The first discharge transistor is described. Preferably, the at least one diode generates a fixed potential difference between the gate of the at least one bit line selection transistor and the well during the discharge period, and the fixed potential difference is less than The at least one bit line selects a time-dependent dielectric breakdown of the transistor. Preferably, the third member includes a second discharge transistor and a third discharge transistor, and the second discharge transistor is configured to generate a discharge path between the well and a reference potential, the third discharge The transistor is configured to generate a discharge path between the source line and the reference potential connected in common with the gate of the well, and to the gates of the first discharge transistor, the second discharge transistor, and the third discharge transistor. The pole supplies a common discharge enable signal. Preferably, when the voltage of the well and the voltage of the source line are discharged to the reference potential via the second discharge transistor and the third discharge transistor, the at least one diode has a ratio The at least one bit line selects a threshold having a large threshold value of the transistor. Preferably, the at least one bit line selection transistor comprises an even bit line selection transistor for selecting an even bit line, and an odd bit line selection transistor for selecting an odd bit line, The even bit line selection transistor and the odd bit line selection transistor are turned on such that the voltage of the common node of both is discharged to the reference potential. Preferably, the at least one diode comprises a transistor having a higher withstand voltage than the at least one bit line selection transistor. Preferably, the bit line selection circuit includes an even bias transistor that applies a bias voltage to the even bit line, and an odd bias transistor that applies a bias voltage to the odd bit line, the third component The gates of the even bias transistor and the odd bias transistors are discharged.

According to the present invention, a discharge path is generated between the gate of the at least one bit line selection transistor and the reference potential, so that the gate voltage of the bit line selection transistor follows the erase voltage of the P well, even if the bit is The line selection transistor is set to a low voltage structure and its breakdown can also be avoided.

10, 10A‧‧‧ bit line selection circuit

20‧‧‧1st selection

30, 30A‧‧‧Selection 2

32‧‧‧Relay Department

40‧‧‧Readout circuit

50, BLK (0) ~ BLK (m) ‧ ‧ block

60, 230‧‧‧P trap

100‧‧‧flash memory

110‧‧‧Memory array

120‧‧‧Input/Output Buffer

130‧‧‧ address register

140‧‧‧Cache memory

150‧‧‧ Controller

160‧‧‧Word line selection circuit

170‧‧‧Page buffer/readout circuit

180‧‧‧ row selection circuit

190‧‧‧Internal voltage generation circuit

200‧‧‧System clock generation circuit

210‧‧‧矽 substrate

220‧‧‧N trap

222‧‧‧n+ diffusion area

250, 260‧‧‧n type diffusion area

270‧‧‧p+ diffusion area

280‧‧‧Contacts

290, 292‧‧‧Diffusion area

300‧‧‧ drive circuit

400‧‧‧discharge circuit

410‧‧‧1st discharge circuit

420‧‧‧2nd discharge circuit

Ax‧‧‧Listing address information

Ay‧‧‧ Location Information

BIASe‧‧‧ even biased transistor

BIASo‧‧‧odd bias transistor

BL0~BLn‧‧‧ bit line

BLC‧‧‧ bit line selection transistor

BLe‧‧‧ even bit line

BLo‧‧‧ odd bit line

BLS‧‧‧ bit line selection transistor

BLSe‧‧‧ even bit line selection transistor

BLSo‧‧‧odd bit line selection transistor

C1, C2, C3‧‧‧ control signals

CLK‧‧‧ internal system clock

D1, D2‧‧‧ diode

DEN‧‧‧discharge enable signal

FEN‧‧‧Floating enable signal

H, L‧‧‧ level

L1, L2‧‧‧ wiring

MC0~MC31‧‧‧ memory cell

N‧‧‧ node

NU‧‧‧NAND string unit

PW‧‧‧P trap

Q1‧‧‧Drive transistor

Q2, Q3, Q4, Q5‧‧‧ discharge transistors

SGD, SGS‧‧‧ select gate line

SL‧‧‧ source line

T0, T1, T2, T3, T4‧‧‧ moments

TD‧‧‧ bit line side selection transistor

TS‧‧‧Source line side selection transistor

WL0~WL31‧‧‧ word line

Va‧‧‧ potential difference

Vb‧‧‧ voltage

Vers‧‧‧Erasing voltage

Vgate‧‧‧ gate voltage

Vpass‧‧‧ pass voltage

VPRE‧‧‧ imaginary power supply

Vprog‧‧‧ programming voltage

Vpw‧‧‧P-well voltage

Vread‧‧‧ read voltage

Vth‧‧‧ threshold

FIG. 1 is a view showing a configuration of a bit line selection circuit of a conventional NAND flash memory.

2 is a view showing a configuration of a bit line selection circuit of a conventional NAND flash memory.

3 is a graph showing a P-well voltage of a conventional NAND-type flash memory and a gate voltage of a transistor of a bit line selection circuit.

4 is a block diagram showing an example of an overall configuration of a NAND flash memory according to an embodiment of the present invention.

Fig. 5 is an equivalent circuit diagram showing a NAND string.

Fig. 6 is a schematic cross-sectional view showing the structure of a memory cell array.

Fig. 7 is a view showing a configuration of floating and discharging of an even-numbered bit line selection transistor constituting a bit line selection circuit.

FIG. 8 is a timing chart for explaining the relationship between the erasing voltage and the discharge time during the erasing operation.

Figure 9 is a diagram showing gate voltage and P-well of a transistor constituting a bit line selection circuit A diagram of the relationship of voltages.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, it should be noted that in the drawings, the parts are emphasized to be understood in order to facilitate understanding, and the ratio to the actual elements is not the same.

4 is a block diagram showing a configuration example of a NAND type flash memory of the present embodiment. As shown in FIG. 4, the flash memory 100 includes: a memory array 110 formed with a plurality of memory cells arranged in a matrix; an input/output buffer 120 connected to an external input/output terminal I/O; The address register 130 receives the address data from the input/output buffer 120; the cache memory 140 holds the input/output data; the controller 150 generates the control signals C1, C2, C3, etc., the control signal C1 , C2, C3, etc. are based on command data from the input/output buffer 120 and external control signals (wafer enable or address latch enable (not shown), etc.); word line selection circuit 160, The column address information Ax from the address register 130 is decoded, and the selection of the block and the selection of the word line are performed based on the decoding result; the page buffer/readout circuit 170 is read out via the bit line The data, or the programming data is maintained via the bit line; the row selection circuit 180 decodes the row address information Ay from the address register 130, and selects the bit line based on the decoding result; Internal voltage generating circuit 190, generated A voltage required for reading, programming (writing), and erasing data (program voltage Vprog, pass voltage Vpass, read voltage Vread, erase voltage Vers (including erase pulse, etc.)); And the system clock generation circuit 200 generates an internal system clock CLK.

The memory array 110 has a plurality of blocks BLK(0), BLK(1), ..., BLK(m) arranged in the row direction. At one of the ends of the block, a page buffer/readout circuit 170 is disposed. However, the page buffer/readout circuit 170 may also be disposed at the other end of the block or at the ends disposed on both sides.

In one block, as shown in FIG. 5, a plurality of NAND string units NU in which a plurality of memory cells are connected in series are formed, and n+1 string units are arranged in the column direction in one block. NU. The string unit NU includes: a plurality of memory cells MCi (i = 0, 1, ..., 31) connected in series; a bit line side selection transistor TD connected to one of the ends, that is, the memory cell MC31; and a source The line side selection transistor TS is connected to the other end portion, that is, the memory cell MC0, the drain of the bit line side selection transistor TD is connected to the corresponding one bit line BL, and the source line side selects the source of the transistor TS. The poles are connected to the common source line SL. The control gate of the memory cell MCi is connected to the word line WLi, the gate of the selection transistor TD is connected to the gate line SGD, and the gate line SGS is connected to the source line side selection transistor TS. . When the word line selection circuit 160 selects a block based on the column address Ax, the selection transistor TD, TS is selectively driven via the selection gate lines SGS, SGD of the block.

The memory cell typically has a metal oxide semiconductor (MOS) structure including: a source/drain as an N-type diffusion region formed in the P well; and a tunnel oxide film formed between the source/drain On the channel; a floating gate (charge accumulation layer) formed on the tunnel oxide film; and a control gate formed on the floating gate via the dielectric film. When there is no charge accumulated in the floating gate, it is written When the material is "1", the threshold is in a negative state, and the control gate of the memory cell is extremely 0V and is turned on. When electrons are accumulated in the floating gate, that is, when the data "0" is written, the threshold is changed to positive, and the control gate of the memory cell is turned off by 0V. Among them, the memory cell is not limited to memorizing a single bit, but also can memorize multiple bits.

The row selection circuit 180 includes the bit line selection circuit 30A shown in FIG. The bit line selection circuit 30A is formed in a P well forming a memory cell in a manner to be described later. Preferably, the bit line selection circuits 30A are formed in the P wells of the respective blocks, respectively. The operation of the bit line selection circuit 30A is controlled by the controller 150 during reading, programming, and erasing. For example, in the case of performing readout of the selected page, when the even bit line BLe is selected, the odd bit line BLo is non-selected, the even bit line selects the transistor BLSe, and the bit line selects the transistor BLS When turned on, the odd bit line selection transistor BLSo is turned off, the even bias transistor BIASe is turned off, the odd bias transistor BIASo is turned on, and the mask potential is supplied from the imaginary power source VPRE. Moreover, when the odd bit line BLo is selected, the even bit line BLe is non-selected, the odd bit line selection transistor BLSo, the bit line selection transistor BLS is turned on, and the even bit line selection transistor BLSe is turned off, The odd bias transistor BIASo is turned off, the even bias transistor BIASe is turned on, and the mask potential is supplied from the imaginary power supply VPRE. During programming, the odd bias transistor BIASo, the even bias transistor BIASe can supply a program inhibit voltage from the hypothetical power supply VPRE to the write inhibited bit line.

The following table is a table showing an example of a bias voltage applied during each operation of the flash memory:

During the read operation, a positive voltage is applied to the bit line, a certain voltage (for example, 0 V) is applied to the selected word line, and a pass voltage Vpass (for example, 4.5 V) is applied to the unselected word line to select the gate line SGD. A positive voltage (for example, 4.5 V) is applied to the SGS, and the bit line side selection transistor TD and the source line side selection transistor TS are turned on, and 0 V is applied to the common source line. In the programming (write) operation, a high voltage programming voltage Vprog (15V~20V) is applied to the selected word line, and an intermediate potential (for example, 10V) is applied to the unselected word line, so that the bit line side selects the transistor. The TD is turned on, the source line side selection transistor TS is turned off, and the potential corresponding to the material of "0" or "1" is supplied to the bit line BL. In the erasing action, 0V is applied to the selected word line in the block, a high voltage (for example, 20V) is applied to the P well as the erase voltage Vers, and the electrons of the floating gate are extracted to the substrate, thereby using the block. Wipe data for the unit.

6 is a schematic cross-sectional view of a memory cell array, and it should be noted that only the NAND string unit NU connected to the even bit line BLe and the even bit line selection transistor constituting the bit line selection circuit 30A are exemplified herein. BLSe and even bias transistor BIASe. An N well 220 is formed in the P-type germanium substrate 210, and a P well 230 is formed in the N well 220. One P well 230 corresponds to one block, and a transistor constituting the NAND string unit NU is formed in the P well 230. Further, in the P well 230, formation The even-numbered bit line selection transistor BLSe and the even-numbered bias transistor BIASe of the second selection unit 30A shown in FIG. 2 are formed.

The source line SL is connected to the n-type diffusion region 250 of the source line side selection transistor TS, and the even bit line BLe is connected to the n-type diffusion region 260 of the bit line side selection transistor TD. The p+ diffusion region 270 of the P well 230 and the n+ diffusion region 222 of the N well 220 are connected to the contact portion 280 shared by the N well/P well. The shared contact portion 280 is connected to the internal voltage generating circuit 190, for example, to apply an erase voltage Vers during an erase operation or to discharge a voltage of the P well via the contact portion 280. Moreover, the even bit line BLe is connected to the diffusion region 290 which forms a common node of the even bit line selection transistor BLSe and the even number bias transistor BIASe formed in the P well 230, and the imaginary power supply VPRE is connected to the even number Another diffusion region 292 of the biasing transistor BIASe. The even bit line selection transistor BLSe and the even bias transistor BIASe are low voltage N-type MOS transistors formed by the same process as the memory cell.

Fig. 7 is a view showing a discharge circuit and a drive circuit connected to a bit line selection circuit; It should be noted that only the discharge circuit and the drive circuit connected to the even bit line selection transistor BLSe constituting the bit line selection circuit 30A are shown here. PW in Fig. 7 refers to a P well. The other odd bit line selection transistor BLSo, the even bias transistor BIASe, and the odd bias transistor BIASo constituting the bit line selection circuit 30A are connected to the same discharge circuit and drive circuit as the even bit line selection transistor BLSe.

The row selection circuit 180 includes a drive circuit 300 and a discharge circuit 400. drive The dynamic circuit 300 and the discharge circuit 400 are formed in a P-type germanium substrate or in a well different from the P well 230. The drive circuit 300 is connected to the node N connected to the gate of the even bit line selection transistor BLSe via the wiring L1. The drive circuit 300 includes an N-type drive transistor Q1 connected to the node N. A floating enable signal FEN is connected to the gate of the driving transistor Q1, and during the erasing operation, the floating enable signal FEN shifts to the L level, and the driving transistor Q1 is turned off. Thereby, the even bit line selection transistor BLSe is set to the floating state. Further, the drive circuit 300 appropriately drives the drive transistor Q1 at the time of reading or programming, but the description thereof is omitted here.

Further, on the gate of the even bit line selection transistor BLSe, the discharge circuit 400 is connected via the wiring L2. The discharge circuit 400 includes a first discharge circuit 410 that discharges the gate of the even bit line selection transistor BLSe during the erasing operation, and a second discharge circuit that discharges the nodes of the P well 230, the source line SL, and the virtual power source VPRE. 420.

The first discharge circuit 410 includes two diodes D1 and D2 and a discharge transistor Q2 connected in series to the gate of the even-numbered bit line selection transistor BLSe. The discharge transistor Q2 is connected between the diode D2 and the reference potential (GND), and a discharge enable signal DEN is connected to the gate thereof. When the discharge enable signal DEN is set to the H level, the discharge transistor Q2 is turned on, and the gate of the even bit line selection transistor BLSe is electrically connected to the reference potential via the wiring L2, and a discharge path is generated between the node N and the reference potential.

The diodes D1 and D2 have a threshold Vth, respectively, by passing two diodes D1 and D2 are connected in series to apply a bias voltage which is shifted from the reference potential by 2Vth to the gate of the even bit line selection transistor BLSe. When the P-well voltage Vpw is discharged, the diodes D1 and D2 cause the voltage of the node N to follow the P-well voltage Vpw to be substantially 2Vth from the P-well voltage Vpw, and when the P-well voltage Vpw is discharged to approximately 0V, The even bit line selection transistor BLSe is turned on. In this example, the two diodes D1 and D2 are connected in series, but this is only an example, and the number of the diodes is not necessarily limited to this. The number of the diodes may be a value that is equal to or lower than the breakdown voltage of the TDDB and smaller than the threshold value of the even-numbered bit line selection transistor BLSe as long as the difference between the node N and the P-well voltage Vpw is equal to or lower than the breakdown voltage of the TDDB. Further, the diodes D1, D2 and the discharge transistor Q2 include a transistor having a higher voltage than the even bit line selection transistor BLSe.

The second discharge circuit 420 includes a discharge transistor Q3 connected to the P well 230, a discharge transistor Q4 connected to the source line SL, and a discharge transistor Q5 connected to the virtual power source VPRE. A discharge enable signal DEN is commonly connected to each of the gates of the discharge transistors Q3, Q4, and Q5. When the discharge enable signal DEN is at H level, the discharge transistors Q3, Q4, and Q5 are turned on, and the P well 230 and the source are connected. The line SL and the virtual potential VPRE are electrically connected to the reference potential and discharged. The discharge transistors Q3, Q4, and Q5 include a transistor having a higher voltage than the even bit line selection transistor BLSe.

Next, the erasing operation of this embodiment will be described with reference to the timing chart of FIG. When an erase command, a column address, and the like are transmitted from the external host device to the flash memory 100, the controller 150 selects the block to be erased and executes the erase sequence. At time T0, the drive circuit 300 shifts the floating enable signal FEN to the L level to turn off the drive transistor Q1. Thereby, the transistor BIASe in the P-well 230 of the selected block, BIASo, BLSe, and BLSo are in a floating state. Further, the bit line side selection transistor TD and the source line side selection transistor TS of the selected block are set to be in a floating state, and 0 V is applied to the word line. Then, at time T1, the erase voltage Vers generated by the internal voltage generating circuit 190 is applied to the P well 230 and the N well 220 via the contact portion 280. With the application of the erase voltage Vers, the P well voltage Vpw reaches about 20 V at times T2 to T3, during which the memory cells of the selected block are erased. At the time T3, the application of the erasing voltage Vers is ended. At the time T3 to T4, the discharge enable signal DEN shifts to the H level, and the discharge transistors Q2, Q3, Q4, and Q5 are turned on. Thereby, a discharge path is generated between each gate of the transistors BIASe, BIASo, BLSe, and BLSo and the reference potential, and a discharge path is generated between the P well 230, the source line SL, the virtual power source VPRE, and the reference potential. The gates of the transistors BIASe, BIASo, BLSe, and BLSo, the P well, the source line SL, and the virtual power source VPRE are discharged through the respective discharge paths.

FIG. 9 is a view showing a relationship between the P well voltage Vpw and the gate voltage Vgate of the transistors BIASe, BIASo, BLSe, and BLSo. As illustrated in FIG. 8, at time T3, the application of the erase voltage Vers is completed, and at the same time, the discharge enable signal DEN becomes active, and the P well, the source line SL, the virtual power source VPRE, and the transistors BIASe, BIASo, BLSe, The charge of each gate of BLSo is discharged to the reference potential via the discharge path.

The gate voltage Vgate of the transistors BIASe, BIASo, BLSe, and BLSo is decreased by capacitive coupling with the P well 230, and the discharge paths of the wiring L2, the diodes D1 and D2, and the discharge transistor Q2 are generated. Promote discharge. Gate electric The voltage Vgate follows the P well voltage Vpw so that the potential difference from the P well 230 does not exceed about 2 Vth. That is, the discharge slope of the gate voltage Vgate substantially approximates the discharge slope of the P well voltage Vpw, and follows the P well voltage Vpw with a difference of 2Vth. Therefore, during the discharge period, the voltage applied to the transistors BIASe, BIASo, BLSe, BLSo is controlled to be smaller than the breakdown voltage of the TDDB.

Then, at time T4, the node of the P well voltage Vpw, the source line SL, and the virtual power source VPRE is discharged to approximately 0V. On the other hand, the gate voltage Vgate of the transistors BIASe, BIASo, BLSe, and BLSo is discharged to about 2 Vth by the diodes D1 and D2. Here, if the discharge of the even bit line selection transistor BLSe and the common node BLn of the odd bit line selection transistor BLSo is slow, and the voltage thereof is maintained high, the low voltage even bit line selection transistor BLSe And the odd bit line selection transistor BLSo is likely to break down. However, if the P well voltage Vpw becomes 0V, the voltage of the bit line BL will also become 0V, and if the gate voltage Vgate is 2Vth, the even bit line select transistor BLSe and the odd bit line select transistor BLSo Turning on, the common node BLn is electrically connected to GND, so that the voltage of the common node BLn can be discharged to about 0V.

As described above, according to the present embodiment, at the time of the erasing operation, the gates of the transistors BIASe, BIASo, BLSe, BLSo of the bit line selection circuit 30A are boosted by the capacitive coupling with the P well 230, and subsequently, When the P-well voltage is discharged, the gates are discharged via the discharge path so as to follow the discharge of the P-well voltage. Therefore, it is possible to suppress the breakdown of the transistors BIASe, BIASo, BLSe, and BLSo due to TDDB or the like.

Further, in the above embodiment, an example of the data of the memory cell memory 1 bit is shown, but the memory cell can also memorize the data of the multi-bit. Further, in the above embodiment, an example in which a NAND string is formed on the surface of the substrate is shown, but the NAND string can also be formed stereoscopically on the surface of the substrate.

As described above, the preferred embodiments of the present invention have been described in detail, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the spirit of the invention.

300‧‧‧ drive circuit

400‧‧‧discharge circuit

410‧‧‧1st discharge circuit

420‧‧‧2nd discharge circuit

BIASe‧‧‧ even biased transistor

BIASo‧‧‧odd bias transistor

BLn‧‧‧ bit line

BLe‧‧‧ even bit line

BLo‧‧‧ odd bit line

BLSe‧‧‧ even bit line selection transistor

BLSo‧‧‧odd bit line selection transistor

D1, D2‧‧‧ diode

FEN‧‧‧Floating enable signal

L1, L2‧‧‧ wiring

N‧‧‧ node

NU‧‧‧NAND string unit

PW‧‧‧P trap

Q1‧‧‧Drive transistor

Q2, Q3, Q4, Q5‧‧‧ discharge transistors

SL‧‧‧ source line

VPRE‧‧‧ imaginary potential

Claims (10)

A semiconductor memory device, comprising: a memory cell array formed with a plurality of reverse gate strings, wherein the reverse gate strings are electrically rewritten memory cells connected in series; an erase component, an eraser a memory cell in the selected block of the memory cell array; and a bit line selection circuit that selects a bit line respectively connected to the inverse gate string to form at least one bit of the bit line selection circuit A meta-line selection transistor is formed in the well, the well forming a memory cell, the erasing component comprising: a first component applying an erase voltage to a well of the selected block; and a second component selecting the selected cell The at least one bit line selection transistor formed in the well of the block is set to a floating state; and the third component causes the at least one bit line to be discharged when discharging a voltage of the well of the selected block The gate of the selected transistor is discharged to the reference potential. The semiconductor memory device according to claim 1, wherein the third member generates a discharge path between the gate of the at least one bit line selection transistor and the reference potential. The semiconductor memory device according to claim 1 or 2, wherein the third member includes a first discharge transistor, and the first discharge transistor is used A discharge path is formed between the gate of the at least one bit line selection transistor and the reference potential, and the first discharge transistor is turned on when the voltage of the well is discharged. The semiconductor memory device according to claim 3, wherein the third component includes at least one diode, and the at least one diode selects electricity in the at least one bit line. A gate of the crystal and a reference potential are connected in series to the first discharge transistor. The semiconductor memory device according to claim 4, wherein the at least one diode selects a gate of the at least one bit line selection transistor and the well during a discharge period. A fixed potential difference is generated, the fixed potential difference being less than the time-dependent dielectric breakdown of the at least one bit line selection transistor. The semiconductor memory device according to claim 1 or 2, wherein the third member includes a second discharge transistor and a third discharge transistor, and the second discharge transistor is used in A discharge path is generated between the well and the reference potential, and the third discharge transistor is configured to generate a discharge path between the source line and the reference potential connected in common with the gate of the well, for the first discharge A common discharge enable signal is supplied to each of the gates of the transistor, the second discharge transistor, and the third discharge transistor. The semiconductor memory device according to claim 6, wherein the voltage of the well and the voltage of the source line pass through the second discharge transistor and When the third discharge transistor is discharged to the reference potential, the at least one diode has a threshold larger than a threshold of the at least one bit line selection transistor. The semiconductor memory device of claim 6, wherein the at least one bit line selection transistor comprises an even bit line selection transistor for selecting an even bit line, and for selecting An odd bit line of the odd bit line selects a transistor, and the even bit line select transistor and the odd bit line select transistor are turned on such that the voltage of the common node of both is discharged to the reference potential. The semiconductor memory device according to claim 1 or 2, wherein the at least one diode includes a transistor having a withstand voltage higher than the at least one bit line selection transistor. The semiconductor memory device according to claim 1 or 2, wherein the bit line selection circuit includes an even bias transistor that applies a bias voltage to the even bit line, and an odd bit line An odd-biased transistor that applies a bias voltage, the third component discharges the gates of the even-biased transistor and the odd-biased transistor.