TW201624672A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a substrate, a patterned conducting layer, a first transistor structure and a second transistor structure. The patterned conducting layer is formed on the substrate. The first transistor structure has a first source, a first gate and a first drain. The first transistor structure is electrically connected to the patterned conducting layer through flip-chip bonding. The second transistor structure has a second source, a second gate and a second drain. The second transistor structure is electrically connected to the patterned conducting layer through flip-chip bonding. The first gate is electrically connected to the second source through the patterned conducting layer. The first source is electrically connected to the second drain through the patterned conducting layer.

Description

Semiconductor component and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device which is connected in series by a flip chip bonding technique and a method of fabricating the same.

Compared with the traditional silicon metal oxide semiconductor field effect transistor (Si MOSFET), GaN high electron mobility transistor (GaN HEMT) has a wide range of energy. Band gap, large breakdown voltage, and high carrier mobility. Because gallium nitride high electron mobility transistors possess these characteristics, they enable lower on-resistance at faster switching speeds. However, gallium nitride high electron mobility transistors are inherently depletion mode components, and are used in conjunction with other enhancement mode electronic components, a cascode transistor architecture. That is, as shown in FIG. 1, FIG. 1 is a circuit diagram of a tandem transistor 1. The tandem transistor 1 is formed by a gallium nitride high electron mobility transistor 11 and a field effect transistor 12 (the field effect transistor 12 can be, for example, a tantalum gold oxide half field effect transistor). In the prior art, the gallium nitride high electron mobility transistor 11 and the field effect transistor 12 are mostly combined by, for example, a wire bonding technique. By arranging the field effect transistor 12 at the gate end of the tandem transistor 1, the tandem transistor 1 can be an enhanced operation electronic component and simultaneously possess a high electron mobility of gallium nitride. The advantages of the crystal 11 are. The tandem transistor 1 has a source S, a gate G, and a drain D as well as a general field effect transistor.

However, the tandem connection of the gallium nitride high electron mobility transistor 11 to the field effect transistor 12 by wire bonding techniques creates other problems: (1) additional connecting lines cause additional parasitic inductance. Additional parasitic inductance will cause the component's frequency response (The frequency response is limited to make the component characteristics worse; (2) If the tandem transistor 1 is implemented by the wire bonding technique, the field effect transistor 12 must be implemented in a planar architecture, and the planar architecture is compared to the vertical architecture. The manufacturing cost is high; (3) in order to avoid overlap between the drain of the gallium nitride high electron mobility transistor 11 and other electrodes, it is necessary to increase the passivation layer of the gallium nitride high electron mobility transistor 11 itself. The thickness of the (passivation layer), which also increases the manufacturing cost of the component.

In view of the above problems, the present invention provides a semiconductor device and a method of fabricating the same, which can avoid additional parasitic inductance between the first transistor structure and the second transistor structure due to excessive connection lines, and at the same time achieve cost reduction. .

A semiconductor device in accordance with the present invention includes a substrate, a patterned conductive layer, a first transistor structure, and a second transistor structure. A patterned conductive layer is formed on the substrate. The first transistor structure has a first source, a first gate and a first drain. The first transistor structure is electrically connected to the patterned conductive layer in a flip chip bond. The second transistor structure has a second source, a second gate and a second drain. The second transistor structure is electrically connected to the patterned conductive layer in a flip chip bonding manner. The first gate is electrically connected to the second source via the patterned conductive layer, and the first source is electrically connected to the second drain via the patterned conductive layer.

In an embodiment of the invention, the patterned conductive layer further includes a first conductive region, and the first gate and the second source are electrically connected to the first conductive region.

In an embodiment of the invention, the patterned conductive layer further includes a second conductive region, and the first source and the second drain are electrically connected to the second conductive region.

In an embodiment of the invention, the semiconductor component further includes at least one connecting line, one end of the connecting line is electrically connected to the second drain, and the other end of the connecting line is electrically connected to the second conductive area.

In an embodiment of the invention, the patterned conductive layer further includes a third conductive region, and the second gate is electrically connected to the third conductive region.

In an embodiment of the invention, the patterned conductive layer further includes a fourth conductive region, and the first drain is electrically connected to the fourth conductive region.

In an embodiment of the invention, the first transistor structure is a gallium nitride high electron mobility transistor, and the second transistor structure is a enamel gold oxide half field effect transistor.

A method for fabricating a semiconductor device according to the present invention includes at least the steps of: providing a substrate; forming a patterned conductive layer on the substrate; and electrically connecting a first transistor structure to the patterned conductive layer in a flip chip bonding manner; And electrically connecting a second transistor structure to the patterned conductive layer in a flip chip bonding manner. The first transistor structure has a first source, a first gate and a first drain, and the second transistor has a second source, a second gate and a second drain. The gate is electrically connected to the second source via the patterned conductive layer, and the first source is electrically connected to the second drain via the patterned conductive layer.

In an embodiment of the invention, the patterned conductive layer further has a plurality of conductive regions, and the method for fabricating the semiconductor device further comprises the step of: providing at least one connecting line. One end of the connecting wire is electrically connected to the second drain, and the other end of the connecting wire is electrically connected to one of the conductive regions, and the first source is electrically connected to the conductive region.

In an embodiment of the invention, the first transistor structure is a gallium nitride high electron mobility transistor, and the second transistor structure is a enamel gold oxide half field effect transistor.

In summary, the present invention provides a semiconductor device and a method of fabricating the same, in which a first transistor structure and a second transistor structure are disposed on a substrate having a patterned conductive layer in a flip chip bonding manner to form a stack. Type transistor component. In this way, additional parasitic inductance between the first transistor structure and the second transistor structure due to excessive connection lines can be avoided, and at the same time, the cost reduction effect can be achieved.

1‧‧‧ tandem transistor

11‧‧‧ gallium nitride high electron mobility transistor

12‧‧‧ Field Effect Crystal

31‧‧‧Substrate

32‧‧‧ patterned conductive layer

321‧‧‧First conductive area

322‧‧‧Second conductive area

323‧‧‧ Third conductive area

324‧‧‧4th conductive area

33‧‧‧First crystal structure

331‧‧‧first source

332‧‧‧first gate

333‧‧‧First bungee

34, 34a‧‧‧Second crystal structure

341, 341a‧‧‧ second source

342, 342a‧‧‧ second gate

343, 343a‧‧‧ second bungee

D‧‧‧汲

D1, D2‧‧‧ semiconductor components

F‧‧‧ lead frame

F1‧‧‧first pin

F2‧‧‧second pin

F3‧‧‧ third pin

G‧‧‧ gate

S‧‧‧ source

S10, S20, S30, S40‧‧‧ steps

W1, W2, W3, W4‧‧‧ connecting lines

1 is a circuit diagram of a tandem transistor.

2 is a flow chart showing the steps of a method of fabricating a semiconductor device in accordance with a preferred embodiment of the present invention.

3A is an exploded perspective view of a semiconductor device in accordance with a preferred embodiment of the present invention.

FIG. 3B is a schematic view showing the combination of the semiconductor elements shown in FIG. 3A.

Fig. 3C is a top view of the semiconductor element shown in Fig. 3B.

FIG. 3D is a schematic view showing the combination of the semiconductor element and the lead frame shown in FIG. 3B.

4A is an exploded perspective view of a semiconductor device in accordance with another preferred embodiment of the present invention.

4B is a schematic view showing the combination of the semiconductor elements shown in FIG. 4A.

4C is a top view of the semiconductor element shown in FIG. 4B.

4D is a schematic view showing the combination of the semiconductor element and the lead frame shown in FIG. 4B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device and a method of fabricating the same according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

2 is a flow chart showing the steps of a method for fabricating a semiconductor device according to a preferred embodiment of the present invention, which includes at least steps S10 to S40. The method of fabricating the semiconductor device in this embodiment is for fabricating a semiconductor device, and the semiconductor device can be, for example, the tandem transistor 1 shown in FIG. The tandem transistor 1 includes a gallium nitride high electron mobility transistor 11 and a field effect transistor 12. In the present embodiment, the field effect transistor 12 can be, for example, a silicon oxide MOSFET. In other embodiments, the field effect transistor 12 can also be a non-silicon MOSFET or other various field effect transistors. In addition, in the present embodiment, the gallium nitride high electron mobility transistor 11 and the field effect transistor 12 are all based on a P-type (P-type).

3A is an exploded perspective view of a semiconductor device D1 according to a preferred embodiment of the present invention, FIG. 3B is a schematic view showing the combination of the semiconductor device D1 shown in FIG. 3A, and FIG. 3C is a top view of the semiconductor device D1 shown in FIG. 3B, FIG. It is a schematic diagram of the combination of the semiconductor element D1 and the lead frame F shown in FIG. 3B. The semiconductor element D1 of the present embodiment may be the tandem transistor 1 shown in FIG.

Referring to FIG. 2 to FIG. 3C simultaneously, in step S10, a substrate 31 is provided. The substrate 31 may be a ceramic spacer or other insulating substrate.

Next, in step S20, a patterned conductive layer 32 is formed on the substrate 31. The material of the patterned conductive layer 32 may be metal or other various electrically conductive materials. For example, since the conductivity of silver (Ag) is preferred, the material of the patterned conductive layer 32 may be silver. In addition to silver, since the copper (Cu) is inexpensive to obtain, the material of the patterned conductive layer 32 may be copper. Of course, the material of the patterned conductive layer 32 can also be other kinds of metals or other various conductive materials. quality.

In practice, first, for example, chemical vapor deposition (chemical vapor deposition) A conductive material is deposited on the substrate 31 by deposition, CVD, sputtering, evaporating or the like to form a conductive layer on the substrate 31. A portion of the conductive layer is then removed by, for example, photolithography to form a patterned conductive layer 32 on the substrate 31. In addition, the patterning conductive layer 32 may be formed on the substrate 31 by cutting the copper sheet into a specific shape and a specific size, and then cutting the copper sheet by bonding. Adhered to the substrate 31. In short, the present invention does not limit the manner in which the patterned conductive layer 32 is formed. In some embodiments, the substrate 31 having the patterned conductive layer 32 can also be a circuit board having metal traces.

Next, in step S30, in a flip-chip bonding manner The first transistor structure 33 is electrically connected to the patterned conductive layer 32. In the present embodiment, the first transistor structure 33 can be, for example, a gallium nitride high electron mobility transistor. The first transistor structure 33 has a first source 331 , a first gate 332 , and a first drain 333 . The first source 331 , the first gate 332 , and the first drain 333 are electrically connected to the patterned conductive layer 32 through a flip chip bond. Since the flip chip bonding technique is notified by those of ordinary skill in the art, this will not be described.

Next, in step S40, the second transistor structure is formed by flip chip bonding. 34 is electrically connected to the patterned conductive layer 32. In the present embodiment, the second transistor structure 34 can be, for example, a enamel gold oxide half field effect transistor. The second transistor structure 34 has a second source 341, a second gate 342 and a second drain 343. In this embodiment, the second transistor structure 34 is exemplified by a planar structure of a ruthenium metal oxide half field effect transistor, that is, a second source 341, a second gate 342, and a second drain 343 system. Located on the same side of the second transistor structure 34. The second transistor structure 34 is electrically connected to the patterned conductive layer 32 in a flip-chip bonding manner.

Further, the patterned conductive layer 32 of the embodiment may include a plurality of leads. The electrical region has, for example, a first conductive region 321 and a second conductive region 322. The first gate 332 is electrically connected to the first conductive region 321 in a flip chip bonding manner. The second source 341 is also electrically connected to the first conductive region 321 in a flip chip bonding manner. In this way, the first gate 332 can be electrically connected to the second source 341 via the first conductive region 321 of the patterned conductive layer 32. The first guide The electrical region 321 can serve as the source of the semiconductor element D1.

In addition, the first source 331 is electrically connected to the second conductive region 322 in a flip-chip bonding manner. The second drain 343 is also electrically connected to the second conductive region 322 in a flip chip bonding manner. In this way, the first source 331 can be electrically connected to the second drain 343 via the second conductive region 322 of the patterned conductive layer 32.

In addition, in the embodiment, the patterned conductive layer 32 may further include a third conductive region 323. The second gate 342 is electrically connected to the third conductive region 323 in a flip-chip bonding manner, such that the third conductive region 323 can serve as a gate of the semiconductor device D1.

In addition, in the embodiment, the patterned conductive layer 32 may further include a fourth conductive region 324. The first drain 333 is electrically connected to the fourth conductive region 324 in a flip-chip bonding manner, such that the fourth conductive region 324 can serve as a drain of the semiconductor device D1.

Generally, in this embodiment, the first transistor structure 33 and the second transistor structure 34 are disposed on the substrate 31 having the patterned conductive layer 32 in a flip chip bonding manner to form the semiconductor device D1 (FIG. 1) Illustrated tandem transistor 1). Compared with the prior art, the present embodiment has the following advantages: (1) The first transistor structure 33 and the second transistor structure 34 can avoid excessive parasitic inductance due to wire bonding technology, and the parasitic inductance can be improved. The characteristics of the device; (2) the arrangement and design of the patterned conductive layer 32 can match the electrode distribution of the first transistor structure 33 and the second transistor structure 34 to reduce component fabrication cost and improve yield; In the configuration of the embodiment, the first drain 333 and the other electrodes are less likely to overlap, so that it is not necessary to additionally increase the thickness of the passivation layer of the first transistor structure 33, thereby reducing the manufacturing cost of the device.

In practical applications, the semiconductor component D1 can be combined with a lead frame F having a first lead f1, a second pin f2, and a third pin f3, as shown in FIG. 3D. Shown.

In addition, the semiconductor element D1 may further include a connection line W1, a connection line W2, and a connection line W3. The material of the connecting wire W1, the connecting wire W2, and the connecting wire W3 may include gold, silver, copper, aluminum or other various electrically conductive materials. One end of the connection line W1 is electrically connected to the first conductive area 321 , and the other end of the connection line W1 is electrically connected to the first pin f1 , such that the first pin f1 can serve as the source of the semiconductor element D1 . One end of the connection line W2 is electrically connected to the third conductive area 323, and the other end of the connection line W2 is electrically connected to the second pin f2, so that the second pin f2 can be As the gate of the semiconductor element D1. One end of the connecting wire W3 is electrically connected to the fourth conductive region 324, and the other end of the connecting wire W3 is electrically connected to the third pin f3. Thus, the third pin f3 can serve as the drain of the semiconductor element D1.

Compared with the prior art, this embodiment has the following advantages: (1) Patterning guide The electrical layer 32 can be designed with various lead frames F without using a specific lead frame F; (2) the patterned conductive layer 32 can be designed with various lead frames F and the pins, thereby shortening the connection line W1. The length of the connection line W2 and the connection line W3 is reduced to reduce the inductance; (2) the position of the connection line W1, the connection line W2 and the connection line W3 can be adjusted in accordance with the instrument.

4A is a perspective view of a semiconductor device D2 according to another preferred embodiment of the present invention; 4B is a schematic view of the combination of the semiconductor device D2 shown in FIG. 4A, FIG. 4C is a top view of the semiconductor device D2 shown in FIG. 4B, and FIG. 4D is a combination of the semiconductor device D2 and the lead frame F shown in FIG. 4B. schematic diagram. The semiconductor element D2 of the present embodiment may be the tandem transistor 1 shown in FIG.

The following is only for the semiconductor element D2 (Fig. 4A) and the semiconductor element D1 (Fig. For the description of the differences, refer to the foregoing embodiments, and the details are not described herein again.

The second transistor structure 34 in FIG. 3A is a planar structure, and the first in FIG. 4A The two transistor structures 34a are "vertical structures". In detail, the second transistor structure 34a has a second source 341a, a second gate 342a, and a second drain 343a. The second source 341a and the second gate 342a are located in the second transistor structure 34a. One side of the second drain 343a is located on the other side of the second transistor structure 34a.

Since the second transistor structure 34a is a vertical structure, the semiconductor element D2 An additional cable W4 is required. The material of the connecting wire W4 may include gold, silver, copper, aluminum or other various electrically conductive materials. The connection line W4 can electrically connect the second drain 343a to the second conductive region 322. Specifically, one end of the connection line W4 is electrically connected to the second drain 343a, and the other end of the connection line W4 is electrically connected to the second conductive area 322.

Since the second transistor structure 34a is a vertical structure, the cost is relatively low and the thermal resistance is small. Therefore, the semiconductor device D2 of the present embodiment is more cost-effective than the prior art and the foregoing embodiments. The advantage of small thermal resistance.

In summary, the present invention provides a semiconductor device and a method of fabricating the same, In a flip chip bonding manner, the first transistor structure and the second transistor structure are disposed on a substrate having a patterned conductive layer to form a tandem transistor element. In this way, additional parasitic inductance between the first transistor structure and the second transistor structure due to excessive connection lines can be avoided, and at the same time, the cost reduction effect can be achieved.

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

31‧‧‧Substrate

32‧‧‧ patterned conductive layer

321‧‧‧First conductive area

322‧‧‧Second conductive area

323‧‧‧ Third conductive area

324‧‧‧4th conductive area

33‧‧‧First crystal structure

331‧‧‧first source

332‧‧‧first gate

333‧‧‧First bungee

34‧‧‧Second transistor structure

341‧‧‧Second source

342‧‧‧second gate

343‧‧‧3rd bungee

D1‧‧‧Semiconductor components

Claims (10)

A semiconductor device includes: a substrate; a patterned conductive layer formed on the substrate; a first transistor structure having a first source, a first gate, and a first drain, the first The transistor structure is electrically connected to the patterned conductive layer by flip chip bonding; and a second transistor structure having a second source, a second gate and a second drain, the second The transistor structure is electrically connected to the patterned conductive layer by flip chip bonding, wherein the first gate is electrically connected to the second source via the patterned conductive layer, and the first source passes through the pattern The conductive layer is electrically connected to the second drain. The semiconductor device of claim 1, wherein the patterned conductive layer further comprises a first conductive region, and the first gate and the second source are electrically connected to the first conductive region. The semiconductor device of claim 1, wherein the patterned conductive layer further comprises a second conductive region, and the first source and the second drain are electrically connected to the second conductive region. The semiconductor device of claim 3, further comprising: at least one connecting wire, one end electrically connected to the second drain, and the other end electrically connected to the second conductive region. The semiconductor device of claim 1, wherein the patterned conductive layer further comprises a third conductive region, and the second gate is electrically connected to the third conductive region. The semiconductor device of claim 1, wherein the patterned conductive layer further comprises a fourth conductive region, the first drain electrically connected to the fourth conductive region. The semiconductor device of claim 1, wherein the first transistor structure is a gallium nitride high electron mobility transistor, and the second transistor structure is a enamel gold oxide half field effect transistor. A method for fabricating a semiconductor device, comprising the steps of: providing a substrate; forming a patterned conductive layer on the substrate; Electrically connecting a first transistor structure to the patterned conductive layer in a flip chip bonding manner; and electrically connecting a second transistor structure to the patterned conductive layer in a flip chip bonding manner, wherein the first The first crystal source has a first source, a first gate and a first drain. The second transistor has a second source, a second gate and a second drain. A gate is electrically connected to the second source via the patterned conductive layer, and the first source is electrically connected to the second drain via the patterned conductive layer. The method of fabricating a semiconductor device according to claim 8, wherein the patterned conductive layer further comprises a plurality of conductive regions, and the method for fabricating the semiconductor device further comprises the step of: providing at least one connecting line, wherein the connecting line One end is electrically connected to the second drain, and the other end is electrically connected to one of the conductive regions, and the first source is electrically connected to the conductive region. The method for fabricating a semiconductor device according to claim 8, wherein the first transistor structure is a gallium nitride high electron mobility transistor, and the second transistor structure is a enamel metal oxide half field effect transistor. Crystal.