TW201624495A - The memory fault tolerance technology of motherboard POST procedure - Google Patents

Abstract

The present invention provides a memory fault tolerance technology of motherboard Power-On Self-Test (POST) procedure. The memory fault tolerance technology of motherboard POST procedure includes the following steps: Step 1: turning on the power of a motherboard including at least one memory module. Step 2: the motherboard executing a POST first procedure. Step 3: initializing one of the at least one memory module. Step 4: determining whether initializing one of the at least one memory module is successful, the method entering Step 5 if initializing one of the at least one memory module is unsuccessful and the method entering Step 6 if initializing one of the at least one memory module is successful. Step5: failing tag the one of the at least one memory module and return to Step 3 to initialize the other one of the at least one memory module. Step 6: recording total memory of the at least one memory module and related information. Step 7: the motherboard executing the POST second procedure. Step 8: the motherboard booting in normal mode in accordance with the success of the memory initialization of the at least one memory module.

Description

Memory fault tolerance method for initial detection of motherboard

The invention relates to a method for memory fault tolerance when a motherboard is booted, and more particularly to a memory fault tolerance method for initial booting of a motherboard by using a Complex Programmable Logic Device (CPLD).

As technology advances, almost everyone will have a personal computer. When performing personal computer operations, the first action must be to start the computer. When the operator presses the power switch of the computer, The power supply starts to supply power to the motherboard and other devices. At this time, the voltage is not stable. The control chipset on the motherboard sends a RESET signal to the Central Processing Unit (CPU). The CPU automatically returns to the initial state, but the CPU does not execute the instruction at this moment. When the chipset detects that the power supply has started to supply power stably (of course, the process from unstable to stable is only a matter of moments), it removes the RESET signal, and the CPU immediately begins executing instructions and jumps to the system's basic input/output system (Basic Input). /output System, BIOS) The real startup code.

The first thing to do in the system BIOS startup code is to perform Power-On Self-Test (POST). The main task of POST is to detect whether some key devices in the system exist and can work normally, such as memory and memory. Devices such as slots and display cards. Since POST is the earliest detection process, the display card has not been initialized yet, if the system BIOS Some fatal errors were found during the POST process. For example, if no memory is found or there is a problem with the memory, the system BIOS will directly control the speaker to report the error. The length and number of sounds represent the type of error. Under normal circumstances, the POST process proceeds very quickly, we can hardly feel its existence, and after the POST ends, other code will be called for more complete hardware detection. When all the hardware has passed the test, the system BIOS startup code will perform its last job, starting from the floppy disk, hard drive or CD player according to the boot sequence specified by the operator, to boot from the local disk C. For example, the system BIOS will read and execute the master boot record on the hard disk. The master boot record then finds the first active partition from the partition table, then reads and executes the partition boot record of the active partition, and the partition boot The record will be responsible for reading and executing the operating system (Operating System) installed by the operator, and finally enters the normal working mode.

For today's computer motherboards, more than one memory is usually used. Slots and their memory, so the more common hardware error is the memory slot or the memory itself. When the memory itself is wrong, only part of the memory may be wrong, and the rest. The memory is in a state of normal operation. However, if the system BIOS of the motherboard finds some fatal errors during the POST process, such as if no memory or memory (whether part of the memory or all memory) is found, the system BIOS will directly control it. The speaker sounds to report the error. At this time, the motherboard cannot boot the program normally until the operator eliminates the error before entering the operating system of the computer. Such a motherboard memory debugging mode will cause the operator to be inconvenient to use, because there may be only some memory, and the motherboard can still use the limited memory to continue the boot process to enter the operating system. .

Therefore, for the initial boot test of the motherboard, if a master can be provided The memory fault-tolerant method of the initial test of the board startup allows the motherboard to perform memory detection during the startup process. If some memory fails to be detected, the memory can continue to operate with limited memory, which will be greatly improved. The convenience of the operator in operating the computer.

In view of the above disadvantages of the prior art, the present invention mainly provides a memory fault tolerance method for initial boot detection of a motherboard. The memory fault tolerance method of the initial boot detection procedure of the motherboard of the present invention includes the following steps: Step 1: Start a power supply of the motherboard having at least one memory module; step 2: after the power of the motherboard is turned on, the motherboard performs a self-test first program; and step 3: initializing the at least one memory module One step; determining whether the initializing of the one of the at least one memory module is successful, and if the one of the at least one memory module fails to be initialized, proceeding to step 5, if the If the one of the at least one memory module is successful, proceed to step 6. Step 5: program error marking the one of the at least one memory module, and return to step 3 to initialize the at least one The other of the memory modules; step 6: recording the total amount of memory of the at least one memory module and related information; step 7: the motherboard performs a self-test second program And step 8: the motherboard is normally powered on according to the memory of the initialization of the at least one memory module.

Preferably, the memory fault tolerance method is a modular program.

Preferably, the memory fault tolerance method is executable by a complex programmable logic device.

Preferably, the at least one memory module comprises at least one memory slot and at least one memory.

Preferably, the at least one memory comprises volatile memory and non-volatile memory body.

Preferably, the volatile memory comprises random access memory, dynamic random access memory, static random access memory and synchronous dynamic random access memory.

Preferably, the synchronous dynamic random access memory comprises double data rate synchronous dynamic random access memory.

Preferably, the non-volatile memory comprises a read-only memory.

Preferably, the read-only memory comprises a programmable read-only memory, an erasable programmable read-only memory, a one-time read-only memory, and an electronic erased rewritable read-only memory, wherein the electronic erased type Rewritable read-only memory includes flash memory.

Preferably, the at least one memory slot comprises one of a dual in-line memory module, a single-row package memory module and a RIMM module.

Other objects, advantages and novel features of the invention will be apparent from

S11-S18‧‧‧Steps

The foregoing summary of the preferred embodiments of the invention, as well as For the purposes of illustrating the invention, various examples are now shown in the drawings. However, it should be understood that the invention is not limited to the precise arrangements and devices disclosed.

FIG. 1 is a flow chart showing a method for memory fault tolerance of the initial booting process of the motherboard of the present invention.

Reference will now be made in detail to the exemplary embodiments illustrated in the drawings All patterns are as close as possible The same component symbols are used to represent the same or similar parts. Please note that these drawings are drawn in simplified form and are not drawn to exact scale.

The memory fault tolerance method of the initial detection program of the motherboard of the invention can be used The memory slot of the motherboard and the memory thereof are fault-tolerant, and at least one memory applicable to the memory fault tolerance method of the present invention includes a volatile memory (Volatile memory) and a non-volatile memory (non-Volatile memory). ); volatile memory refers to computer memory that disappears when the current is turned off; unlike volatile memory, the data stored in the memory after the power supply of the non-volatile memory is interrupted It will not disappear, as long as the power is restored, the memory data can be read.

The memory fault tolerance method of the initial detection program of the motherboard of the invention can be adapted Volatile memory used includes: Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), and Static Random Access Memory (SRAM). And synchronous dynamic random-access memory (SDRAM), and SDRAM includes Double Data Rate Synchronous Dynamic Random Access Memory (DDR), and DDR has dual The SDRAM with double data transfer rate has twice the data transmission speed of the system clock. Due to the increased speed, its transmission performance is superior to the traditional SDRAM, and the DDR includes the second generation double data rate synchronous dynamic random access memory ( DDR2), the third generation of double data rate synchronous dynamic random access memory (DDR3) and the latest fourth generation double data rate synchronous dynamic random access memory (DDR4).

The non-volatile memory applicable to the memory fault tolerance method of the present invention includes only Read-Only Memory (ROM); ROM includes programmable read-only memory (Programmable ROM, PROM), Erasable Programmable Read Only Memory (EPROM), One Time Programmable Read Only Memory (OTPROM) and electronic erasable rewritable Electrically-Erasable Programmable Read-Only Memory, wherein the electronically erasable rewritable read-only memory includes a flash memory.

On the other hand, the memory fault tolerance of the initial boot test procedure of the motherboard of the present invention The at least one memory slot applicable to the method includes: a dual in-line memory module (DIMM), a single inline memory module (SIMM), and a RIMM mode. One of the groups (Rambus In-line Memory Module, RIMM).

Figure 1 is a flow chart of a method for illustrating the initial startup of the motherboard of the present invention. The memory fault tolerance method of the test program. Referring to FIG. 1 , the memory fault tolerance method of the initial booting detection process of the motherboard of the present invention includes steps S11-S18. In step S11, the operator first turns on the power of a motherboard having at least one memory module in the computer. The at least one memory module includes at least one memory slot and at least one memory. In step S12, after the power of the motherboard is turned on, the motherboard performs a first program of Power-On Self-Test (POST). In step S13, in the self-test first program, the memory fault tolerance method of the present invention initializes one of the at least one memory modules (the Nth memory module). In step S14, the memory fault tolerance method of the present invention determines whether one of the at least one memory module (the Nth memory module) is initialized, and if the at least one memory module is initialized If one (the Nth memory module) fails, step S15 is performed. If one of the at least one memory module (the Nth memory module) is initialized, step S16 is performed. In step S15, the memory of the present invention is fault tolerant The method performs program error labeling on the one of the at least one memory module (the Nth memory module), and returns to step S13 to initialize the other of the at least one memory module (N- 1 or N+1th memory module). In step S16, the one of the at least one memory module (the Nth memory module) or the other of the at least one memory module (the N-1th or the N+th) The memory module is successfully initialized, and the memory fault tolerance method of the present invention records the total amount of memory and related information of the at least one memory module. In step S17, the motherboard performs a self-test second program to check whether other hardware devices in the motherboard are normal. In step S18, the motherboard performs normal booting according to the memory of the initialization of at least one memory module.

In an embodiment of the present invention, the memory fault tolerance method of the present invention is a module The program can be executed by a Complex Programmable Logic Device (CPLD), which is suitable for implementing various operations and combinational logic, and thus is suitable for the memory of the initial boot test program of the motherboard of the present invention. A fault tolerant method, wherein the complex programmable logic device comprises a plurality of Programmable Array Logic (PAL).

Once the motherboard in the computer is booted through the motherboard of the present invention, the initial detection process The memory fault tolerance method is used to perform the booting process. When the motherboard detects an error in one of the memory modules during the initial boot detection, the memory fault tolerance method of the present invention can perform the faulty memory module. The error labeling and causing the motherboard to detect the next memory module until the motherboard detects the memory module that can be successfully initialized, the memory fault tolerance method of the present invention allows the motherboard to be initialized according to the at least one memory module Successful memory for the motherboard to boot normally.

In describing a representative example of the present invention, the present specification has been proposed to operate the present invention. The method and/or program is illustrated as a specific sequence of steps. However, to some extent, the method or program does not rely on the specific order of steps set forth herein, and the method or program should not be limited to the particular order of the steps described. As will be appreciated by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in this specification should not be construed as limiting the scope of the claims. In addition, the scope of the patent application of the method and/or procedure of the present invention should not be limited to the performance of the steps in the order presented, and those skilled in the art can immediately understand that the order can be changed and still maintain the spirit of the present invention. Within the scope.

Those skilled in the art should be aware that changes can be made to the above examples without departing from the broad inventive concepts. Therefore, it is understood that the invention is not limited to the specific examples of the invention, and is intended to cover the modifications of the invention and the scope of the invention as defined by the appended claims.

S11-S18‧‧‧Steps

Claims (10)

A memory fault tolerance method for initial booting of a motherboard includes the following steps: Step 1: Turn on a power supply of a motherboard having at least one memory module; Step 2: After the power of the motherboard is turned on, perform a Self-testing the first program; step 3: initializing one of the at least one memory module; step 4: determining whether the initializing one of the at least one memory module is successful, if the at least one memory is initialized If one of the body modules fails, step 5 is performed. If one of the at least one memory module is initialized successfully, step 6 is performed; step 5: the at least one memory module is One of the program error labeling, and returns to step 3 to initialize the other of the at least one memory module; Step 6: recording the total amount of memory and related information of the at least one memory module; The motherboard performs a self-test second program; and step 8: the motherboard performs normal booting according to the memory of the initialization of the at least one memory module. The memory fault tolerance method of claim 1, wherein the memory fault tolerance method is a modular program. The memory fault tolerance method of claim 1, wherein the memory fault tolerance method is executable by a complex programmable logic device. The memory fault tolerance method of claim 1, wherein the at least one memory module comprises at least one memory slot and at least one memory. The memory fault tolerance method of claim 4, wherein the at least one memory comprises a volatile memory and a non-volatile memory. The memory fault tolerance method of claim 5, wherein the volatile memory comprises a random access memory, a dynamic random access memory, a static random access memory, and a synchronous dynamic random access memory. . The memory fault tolerance method of claim 6, wherein the synchronous dynamic random access memory comprises double data rate synchronous dynamic random access memory. The memory fault tolerance method of claim 5, wherein the non-volatile memory comprises a read-only memory. The memory fault tolerance method of claim 8, wherein the read-only memory comprises programmable read-only memory, erasable programmable read-only memory, one-time programmable read-only memory, and electronic erase The rewritable read-only memory, wherein the electronic erasable rewritable read-only memory includes flash memory. The memory fault tolerance method of claim 4, wherein the at least one memory slot comprises one of a dual in-line memory module, a single-row package memory module, and a RIMM module.