TW201622109A - Three dimensional stacked semiconductor structure and method for manufacturing the same - Google Patents

Abstract

A 3D stacked semiconductor structure is provided, comprising a plurality of stacks vertically formed on a substrate and disposed parallel to each other, a dielectric layer formed on the stacks, a plurality of conductive plugs independently formed in the dielectric layer; and a metal-oxide-semiconductor (MOS) layer formed on the dielectric layer. One of the stacks at least comprises a plurality of multi-layered pillars, and each of the multi-layered pillars comprises a plurality of insulating layers and a plurality of conductive layers arranged alternately. The MOS layer comprises a plurality of MOS structures connected to the conductive plugs respectively, and function as layer-selectors for selecting and decoding the to-be-operated layer.

Description

Three-dimensional stacked semiconductor structure and manufacturing method thereof 【0001】

The present invention relates to a three-dimensional stacked semiconductor structure and a method of fabricating the same, and more particularly to a three-dimensional stacked semiconductor structure for forming a metal oxide semiconductor (MOS) layer between stacked memory cells and metal routes. (source contacts) as a layer selection, and its structure manufacturing method.

【0002】

A very important feature of non-volatile memory components is the ability to preserve the integrity of the data state when the memory component loses or removes power. Many different types of non-volatile memory components have been proposed in the industry. However, related companies continue to develop new designs or combine existing technologies to stack memory cell planes to achieve a memory structure with higher storage capacity. For example, some three-dimensional stacked NAND (NAND) type flash memory structures have been proposed. However, there are still some problems that need to be solved in the traditional three-dimensional stacked memory structure.

[0003]

Figure 1 is a perspective view of a 3D stacked semiconductor structure. In the first figure, a 3D NAND memory array structure is illustrated as an example. The 3D stacked semiconductor structure includes an array region 11 and a fan-out region 13. The multilayer array is formed on an insulating layer and includes a plurality of word lines 125-1 WL, ..., 125-N WL which are formed isotropically formed with a plurality of stacks. The plurality of stacks includes semiconductor strips 112, 113, 114, 115. The semiconductor strips in the same plane are electrically coupled together by a step structure (also referred to as a bit line structure). The stepped structures 102B, 103B, 104B, 105B (also referred to as pad structures/bit line pads) terminate semiconductor strips (eg, semiconductor strips 102, 103, 104, 105). As shown in the figure, these stepped structures 102B, 103B, 104B, 105B are electrically connected to different bit lines for connection to a decoding circuit for selecting a plane within the array. The stacked semiconductor strips 102, 103, 104, 105 have a source line end to a bit line end direction. The stacked semiconductor strips 102, 103, 104, 105 are terminated at one end by a step structure (pad structure/bit line pads) 102B, 103B, 104B, 105B, and are passed through a string selection lines (SSL). The pole structure 109, the ground select line GSL 127, the word line 125-N WL to 125-1 WL, the ground select line GSL 126, and the other end are terminated by a source line (covered by other portions of the figure). The stacked semiconductor strips 112, 113, 114, 115 are terminated at one end by stepped structures 112A, 113A, 114A, 115A, through SSL gate structure 119, ground select line GSL 126, word lines 125-1 WL through 125-N WL, ground select line GSL 127, and terminated by source line 128 at the other end. The source line 128 includes a staggered stacked insulating layer (such as an oxide layer) and a conductive layer (such as a polysilicon as a gate material), and has a contact hole perpendicular to the stacked structure and a conductive material filled in the hole to externally connect the conductive layers of the layers. .

[0004]

However, the serial select line (SSL) as shown in Fig. 1 is not easy to fabricate in the process. When the size of the 3D stacked semiconductor structure is reduced and more layers and tighter component pitches need to be constructed, the process window is quite narrow and the fabrication is more difficult.

[0005]

In addition, the industry also proposes a PNVG structure, which is another type of 3D stacked vertical gate semiconductor structure, and the reverse bias leakage of the PN diode is critical to the PNVG structure to avoid Increased channel potential leakage. During decoding, the PNVG structure requires complex and fine operational waveforms to avoid PN junction leakage current. A three-phase programming method has also been proposed for decoding PNVG structures. However, this programming method is very complicated and it is not easy to form P+/N.

[0006]

The present invention relates to a three-dimensional stacked semiconductor structure and related fabrication methods. According to an embodiment, a metal-oxide-semiconductor (MOS) layer is formed between the metal routes and the three-dimensional stacked memory cells.

【0007】

According to an embodiment, a three-dimensional stacked semiconductor structure is provided, including: a plurality of stacks vertically formed on a substrate and parallel to each other, a dielectric layer formed on the stacks; and a plurality of conductive plugs Formed independently at the dielectric layer; and a metal oxide semiconductor (MOS) layer is formed over the dielectric layer. One of the stacks includes a plurality of multi-layered pillars, each of the plurality of pillars including a plurality of layers of insulating layers and a plurality of layers of conductive layers alternately stacked. The MOS layer includes a plurality of MOS structures electrically connected to the conductive plugs.

[0008]

According to an embodiment, a method for fabricating a three-dimensional stacked semiconductor structure is provided, comprising: forming a plurality of stacked on a substrate and parallel to each other, wherein one of the stacked layers comprises a plurality of pillars having a plurality of insulating layers and a plurality of layers Conductive layers are alternately stacked; a dielectric layer is formed on the stack; a plurality of conductive plugs are formed independently at the dielectric layer; and a metal oxide semiconductor (MOS) layer is formed on the dielectric layer, and the MOS layer includes A plurality of MOS structures are electrically connected to the conductive plugs, respectively.

【0009】

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings are set forth below. However, the scope of the invention is defined by the scope of the appended claims.

[0036]

11‧‧‧Array area
13‧‧‧Fan area
102, 103, 104, 105, 112, 113, 114, 115, 25-1, 25-2, 25-3, 25-4‧‧ ‧ semiconductor strip
102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A‧‧‧ ladder structure
125-1 WL,...,125-N WL, WL, WL ₀ , WL ₃₁ ‧‧‧ character line
BL, BL _N , BL _N+1 , BL-1, BL-2, BL-3, BL-4‧‧‧ bit lines
109, 119, SSL‧‧‧ tandem selection line
126, 127, GSL‧‧‧ grounding selection line
128, SL‧‧‧ source line
20‧‧‧Substrate
21, 22, 23, 24‧‧‧ Stacking
21-1, 22-1, 23-1, 24-1, 24-2‧‧‧ multilayer columns
211, 221, 231, 241‧‧ insulation
213, 223, 233, 243‧‧‧ conductive layers
215, 225, 235, 245‧‧ ‧ charge trapping layer
21G, 22G, 23G, 24G‧‧‧ gate
26, 36‧‧‧ dielectric layer
27-1, 27-2, 27-3, 27-4‧‧‧ conductive plug
28-1, 28-2, 28-3, 28-4‧‧‧ patterned polycrystalline layer
281a, 282a, 283a, 284a‧‧‧ undoped polysilicon
281b, 282b, 283b, 284b‧‧‧ heavily doped polysilicon
29-1, 29-2, 29-3, 29-4‧‧‧ patterned oxide layer
29S-1‧‧‧ gate oxide
29G-1, 29G-2, 29G-3, 29G-4‧‧‧ island gate
31, 32, 33, 34‧‧‧ MOS structure
35‧‧‧ bit line pad selector
411, 412, 413, 414‧‧ ‧ gate line contact
431, 432, 433, 434‧‧‧ source line contact
451, 452, 453, 454 ‧ ‧ bit line contact
471, 472, 473, 474‧‧‧ bit line connector selector contact
51, 52, 53, 54‧ ‧ layer selection line
MOS‧‧‧metal oxide semiconductor layer
Layer-1, Layer-2, Layer-3, Layer-4‧‧ layer plane
BP1, BP2, BP3, BP4‧‧‧ bit line pads
A1‧‧‧ first area
A2‧‧‧Second area
ML1‧‧‧ first metal layer
ML2‧‧‧ second metal layer
ML3‧‧‧ third metal layer

[0010]

Figure 1 is a perspective view of a 3D stacked semiconductor structure.
2 is a schematic diagram of a three-dimensional stacked semiconductor structure according to an embodiment of the present disclosure.
3 to 6 illustrate a method of fabricating a MOS layer of a three-dimensional stacked semiconductor structure according to an embodiment of the present disclosure.
7 to 9 illustrate a method of manufacturing a metal winding above the MOS layer of FIG. 6 according to an embodiment.
10 and 11 are schematic views respectively showing a MOS layer and a metal winding of a three-dimensional stacked semiconductor structure according to another embodiment of the present disclosure.

[0011]

Embodiments of the disclosure present a three-dimensional stacked semiconductor structure and related fabrication methods. In an embodiment, a metal-oxide-semiconductor (MOS) layer is formed between the metal routes and the three-dimensional stacked memory cells. The single layer MOS layer of an embodiment includes a plurality of MOS structures as layer-selectors to select and decode a to-be-operated plane/layer. Furthermore, the three-dimensional stacked semiconductor structure of the embodiment can be decoded via a simple and reliable method.

[0012]

Embodiments of the present disclosure can be applied to a variety of three-dimensional stacked semiconductor structures. For example, embodiments may be applied, but are not limited to, a three-dimensional PNVG type three-dimensional stacked semiconductor structure, or a conventional finger VG type three-dimensional stacked semiconductor structure. The related embodiments are presented below in conjunction with the drawings to explain in detail the three-dimensional stacked semiconductor structure proposed in the present disclosure and related manufacturing methods. However, the disclosure is not limited to this. The description of the embodiments, such as the detailed structure, the process steps, the application of the materials, and the like, are for illustrative purposes only and are not intended to limit the scope of the disclosure.

[0013]

Furthermore, the disclosure does not show all possible embodiments. The structure and process may be modified and modified to meet the needs of the actual application process without departing from the spirit and scope of the disclosure. Therefore, other implementations not presented in the present disclosure may also be applicable. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.

[0014]

The following embodiments are described by taking a three-dimensional stacked semiconductor structure similar to the PNVG type as an example, but the disclosure is not limited thereto. 2 is a schematic diagram of a three-dimensional stacked semiconductor structure according to an embodiment of the present disclosure. According to an embodiment, a three-dimensional stacked semiconductor structure includes a plurality of stacks 21, 22, 23, 24 vertically formed on a substrate 20 and parallel to each other, and one of the stacks 21, 22, 23, 24 includes A plurality of multi-layered pillars are exemplified by 21-1, 22-1, 23-1, 24-1, 24-2 illustrated in Fig. 2. Each of the multilayer pillar systems includes a plurality of insulating layers 211, 221, 231, 241 (e.g., an oxide layer) and a plurality of conductive layers 213, 223, 233, 243 (e.g., polycrystalline germanium layers) alternately stacked. A pair of insulating layers and conductive layers (for example, insulating layer 211 and conductive layer 213) are an OP layer.

[0015]

Furthermore, one of the stacks 21, 22, 23, 24 also includes a plurality of charging trapping layers 215, 225, 235, 245 formed in the multi-layer cylinders (for example, 21-1, 22-1). , 23-1, 24-1, 24-2) sidewalls, and a plurality of gates 21G, 22G, 23G, 24G (word line WL, tandem select line SSL, and ground select line GSL) are formed in the charge Capture layers 215, 225, 235, 245 and fill adjacent charge trapping layers 215 on the sidewalls of the multilayer pillars (eg, 21-1, 22-1, 23-1, 24-1, 24-2), The gap between 225, 235, 245. The stacks 21, 22, 23, 24 and the gates 21G, 22G, 23G, 24G extend in a first direction (i.e. y-direction).

[0016]

Furthermore, the three-dimensional stacked semiconductor structure of the embodiment also includes a plurality of semiconductor strips 25-1, 25-2, 25-3, 25-4, semiconductor strips 25-1, 25-2, 25-3, Each of 25-4 extends in the second direction (ie x-direction). Wherein the second direction is perpendicular to the first direction. As shown in Fig. 2, each semiconductor strip (e.g., 25-1, 25-2, 25-3, 25-4) is connected to a multi-layered column of different stacks (e.g., 21, 22, 23, 24) of the same planar layer. A conductive layer of a body (for example, 21-1, 22-1, 23-1, 24-1, 24-2). For example, the semiconductor strip 25-1 (extending in the x-direction) is connected to the same planar layer as the multilayer cylinders 21-1, 22-1, 23-1, 24-1 of the different stacks 21, 22, 23, 24. It is the conductive layer 213, 223, 233, 243 of layer-1. Similarly, the semiconductor strip 25-2 is connected to the layers 21-1, 22-1, 23-1, and 24-1 of the different stacks 21, 22, 23, 24 in the same plane layer as the layer-2. Layers 213, 223, 233, 243. The semiconductor strip 25-3 is connected to the conductive layer 213 of the multi-layered pillars 21-1, 22-1, 23-1, and 24-1 of the different stacks 21, 22, 23, and 24, which are designated as layer-3 in the same planar layer. 223, 233, 243; the semiconductor strip 25-4 is connected to the different stacks 21, 22, 23, 24 of the multi-layer cylinders 21-1, 22-1, 23-1, 24-1 located in the same plane layer labeled layer- 4 conductive layers 213, 223, 233, 243. Due to the angle relationship shown in Fig. 2, other multilayer pillars and other semiconductor strips connecting the same planar layer exist but do not appear in the figure.

[0017]

Furthermore, the three-dimensional stacked semiconductor structure of the embodiment also includes a plurality of pad structures, such as bit line pads BP1, BP2, BP3, BP4, electrically connected to the semiconductor strips 25-1, 25-2. , 25-3, 25-4, wherein the semiconductor strips 25-1, 25-2, 25-3, 25-4 located in the same planar layer are electrically connected by one of the pad structures BP1, BP2, BP3, BP4 . For example, the semiconductor strips 25-1 on the same plane labeled Layer-1 are coupled together to the bit line pads BP1; the semiconductor strips 25-2 on the same plane labeled Layer-2 are coupled together to the bit lines. The pads BP2; the semiconductor strips 25-3 located on the same plane labeled Layer-3 are coupled together to the bit line pads BP3; the semiconductor strips 25-4 located on the same plane labeled Layer-4 are coupled together in place. The wire is connected to the BP4.

[0018]

In the three-dimensional stacked semiconductor structure similar to the PNVG type illustrated here, a string selection line (SSL) (ie stack 21) and a ground selection line (GSL) (ie stack 24) are continuously formed. (configured continuously), as if the character line is not broken continuously. Furthermore, the pad structures such as the bit line pads BP1, BP2, BP3, BP4 each include a first area A1 and a second area A2 connected to the first area A1. It should be noted that this disclosure is not limited to this embodiment similar to PNVG, and can be applied to other types of vertical gate (VG) three-dimensional stacked semiconductor structures. The first area A1/the second area A2 is, for example, an N+ area/N area or a P+ area/N area. In one embodiment, an N+ region/N region is formed as the first region A1/second region A2.

[0019]

The three-dimensional stacked semiconductor structure further includes metal routings (eg, first metal layer ML1, second metal layer ML2, third metal layer ML3) of different layers over the stacks such as 21, 22, 23, 24. In accordance with an embodiment of the present disclosure, a TFT metal oxide semiconductor (MOS) layer is formed between the metal windings and the stacks 21, 22, 23, 24 (with three-dimensional stacked memory cells). In an embodiment, the MOS layer formed over a dielectric layer includes a plurality of MOS structures as layer-selectors to select and decode a layer to be operated (to-be-operated plane/layer) ). The details are described below.

[0020]

In the embodiment, the doping type and doping concentration of the first region A1 and the second region A2 of each of the bit line pads BP1, BP2, BP3, and BP4 are based on the MOS above the stacks 21, 22, 23, and 24. The type of structure depends. For example, if the MOS structure is an NMOS, the first region A1 and the second region A2 of the bit line pads BP1, BP2, BP3, BP4 are respectively N+ regions and N regions (ie the doping concentration of the second region A2 is low) Doping concentration in the first region A1). In another embodiment, if the MOS structure is a PMOS, the first area A1 and the second area A2 of the bit line pads BP1, BP2, BP3, BP4 are respectively a P+ area and an N area (ie the first area A1 and the The two-region A2 is doped with different types of dopants).

[0021]

3 to 6 illustrate a method of fabricating a MOS layer of a three-dimensional stacked semiconductor structure according to an embodiment of the present disclosure. The MOS layer of the embodiment is located above the stacks 21, 22, 23, 24 as layer-selectors to select and decode the layer plane to be operated, and metal windings are formed over the MOS layer. 7 to 9 illustrate a method of fabricating a metal winding above the MOS layer of FIG. 6 according to an embodiment. Please refer to FIG. 2 at the same time to refer to the relevant elements in the three-dimensional stacked semiconductor structure with reference to the embodiment.

[0022]

First, a substrate 20 (with a buried oxide layer) is provided to form a plurality of stacks such as 21, 22, 23, 24 perpendicular to the substrate 20, and each stack 21, 22, 23, 24 includes a plurality of multilayer pillars such as 21- 1,22-1,23-1,24-1,24-2. Each of the multilayer pillar systems includes a plurality of insulating layers 211, 221, 231, 241 (e.g., an oxide layer) and a plurality of conductive layers 213, 223, 233, 243 (e.g., polycrystalline germanium layers) alternately stacked (Fig. 2). A pair of insulating layers and conductive layers (for example, insulating layer 211 and conductive layer 213) are an OP layer. Each of the plurality of stacked stacking cells is stacked, wherein a plurality of layer planes (such as Layer-1, Layer-2, Layer-3, Layer-4) are vertically stacked, and the stacked memory cells are arranged in three dimensions. Array. Furthermore, charging trapping layers (such as 215, 225, 235, 245) are formed in the multi-layer cylinders (for example, 21-1, 22-1, 23-1, 24-1, 24-2). a sidewall, and a plurality of gates 21G, 22G, 23G, 24G (word line WL, tandem select line SSL, and ground select line GSL), semiconductor strips (eg, 25-1, 25-2, 25-3, 25-4) and the pad structure (e.g., bit line pads BP1, BP2, BP3, BP4) are formed as shown in Fig. 2.

[0023]

A MOS layer is formed over the stack (e.g., 21, 22, 23, 24). As shown in FIG. 3, a dielectric layer 26, such as an oxide layer, is formed on the stack (e.g., 21, 22, 23, 24) as a dielectric planar layer (providing a planarized surface). Thereafter, a plurality of conductive plugs 27-1, 27-2, 27-3, 27-4 are formed independently along the third direction (ie z-direction) at the dielectric layer 26, corresponding to the bits. Elementary pads (such as BP1, BP2, BP3, BP4) to reach different layer planes (such as Layer-1, Layer-2, Layer-3, Layer-4). These conductive plugs such as 27-1, 27-2, 27-3, 27-4 may also be referred to as MiLC polysilicon plugs. In one embodiment, the conductive plug may be formed by first forming plug holes and filling N+ or P+ polysilicon into the plug hole, and then planarizing by CMP (parking on the dielectric layer 26) or other suitable process. . According to an embodiment, the MOS layer includes a plurality of MOS structures electrically connected to the conductive plugs such as 27-1, 27-2, 27-3, and 27-4, respectively, as a layer selector.

[0024]

The conductive plug can be an N+ polysilicon plug or a P+ polysilicon plug. In one embodiment, if the MOS structure is an NMOS, the conductive plugs such as 27-1, 27-2, 27-3, and 27-4 are N+ polysilicon, wherein the pad structure (such as the bit line pads BP1, BP2, The first region A1 and the second region A2 of BP3, BP4) are an N+ region and an N region, respectively (ie, the doping concentration of the second region A2 is lower than the doping concentration of the first region A1). In one embodiment, if the MOS structure is a PMOS, the conductive plugs such as 27-1, 27-2, 27-3, and 27-4 are P+ polysilicon, wherein the bit line pads BP1, BP2, BP3, and BP4 are One area A1 and the second area A2 are a P+ area and an N area, respectively.

[0025]

After that, the MOS structure is fabricated. First, a plurality of patterned polysilicon layers 28-1, 28-2, 28-3, 28-4 are formed on the dielectric layer 26, and a plurality of patterned oxide layers 29-1, 29-2, 29-3, 29-4 is formed on the patterned polysilicon layer 28-1, 28-2, 28-3, 28-4 as shown in Figs. 4A and 4B. Figure 4B is a cross-sectional view of the patterned oxide layer and patterned polysilicon layer taken along section line 4B-4B of Figure 4A. In FIGS. 4A and 4B, four sets of polycrystalline beams (each including a patterned oxide layer and a patterned polysilicon layer) are respectively connected (eg, overlying) conductive plugs 27-1, 27-2, 27 -3,27-4 as an example for explanation. In the production, an undoped polysilicon can be deposited first, and then an oxide layer is deposited (for double gates and hard masks), followed by patterning.

[0026]

Thereafter, a plurality of island gates 29G-1, 29G-2, 29G-3, 29G-4 are formed as shown in Fig. 5A. Please also refer to FIG. 5B, which is a cross-sectional view of the island-shaped gate 29G-1 taken along the section line 5B-5B of FIG. 5A. When making an island gate, a gate oxide (GOX) (such as 29S-1) may be formed to cover the sidewalls of the patterned polysilicon layer (such as 28-1, 28-2, 28-3, 28-4). A patterned oxide layer (such as 29-1, 29-2, 29-3, 29-4) is formed and a polysilicon layer is deposited thereon, followed by an island gate patterning process. Among them, the island gates 29G-1, 29G-2, 29G-3, 29G-4 cover the patterned oxide layer and the gate oxide. Furthermore, the island gates 29G-1, 29G-2, 29G-3, and 29G-4 are insulated from each other, for example, the island gate 29G-1 is insulated from the island gates 29G-2, 29G-3, and 29G- 4.

[0027]

Next, a self-aligned S/D implantation is performed to dope the patterned polysilicon layer to be an island gate (eg, 29G-1, 29G-2, 29G-3, 29G-4) Part of the patterned polycrystalline germanium layer (such as 28-1, 28-2, 28-3, 28-4) (such as 281a, 282a, 283a, 284a) is undoped polysilicon, but not island The rest of the patterned polysilicon layer (such as 281b, 282b, 283b, 284b) is heavily doped polysilicon as shown in Figure 6. Therefore, the fabrication of the MOS structures 31, 32, 33, 34 is completed, and the MOS structures 31, 32, 33, 34 are electrically connected to the phases via the heavily doped polysilicon portions 281b, 282b, 283b, 284b of the patterned polysilicon layer, respectively. Corresponding conductive plugs 27-1, 27-2, 27-3, 27-4.

[0028]

After forming the MOS layer of the embodiment, a plurality of metal windings are formed over the MOS layer. Please refer to FIGS. 7-9, which illustrate a method of fabricating a metal winding above the MOS layer of FIG. 6 according to an embodiment. As shown in Fig. 7, a dielectric layer 36 is deposited on the MOS layer and subjected to chemical mechanical polishing (CMP). Thereafter, an island gate contact, a source line contact, and a bit line contact are formed. As shown in FIG. 8, a plurality of gate line contacts 411, 412, 413, 414 are formed on the island gates 29G-1, 29G-2 of the MOS structures 31, 32, 33, 34, respectively. 29G-3, 29G-4; several multiple source line contacts 431, 432, 433, 434 are formed in the heavily doped polysilicon (such as 281b, 282b, 283b, 284b) ) is connected to the source line; and a plurality of bit line contacts 451, 452, 453, 454 are formed on the dielectric layer 36.

[0029]

Next, fabrication of a multilayer metal winding is performed over the MOS structure. As shown in FIG. 9, a plurality of layer-selector lines (such as first metal lines) 51, 52, 53, 54 are formed on the gate line contacts 411, 412, 413, 414, respectively, and a source. The pole lines SL are formed on the source line contacts 431, 432, 433, 434 for electrical connection. The layer selection lines 51, 52, 53, 54 are parallel to each other and extend along the first direction (i.e. y-direction), and the source lines SL are parallel to the layer selection lines 51, 52, 53, 54. Thereafter, a plurality of bit lines (eg, second metal lines) BL-1, BL-2, BL-3, BL-4 are formed insulatingly above the layer selection lines 51, 52, 53, 54 as shown in FIG. Shown. The bit lines BL-1, BL-2, BL-3, BL-4 extend in the second direction (i.e. x-direction) and are perpendicular to the layer selection lines 51, 52, 53, 54 and the source line SL.

[0030]

According to the embodiment, regardless of the number of layers of the OP layer, it is only necessary to fabricate the MOS structure of the MOS layer (for example, 31, 32, 33, 34) in a single layer process, thereby simplifying the process and enlarging the process window. The present disclosure is well suited for use in fabricating a reduced size three dimensional stacked semiconductor structure. Furthermore, the decoding method of the three-dimensional stacked semiconductor structure of the embodiment is performed by selecting a word line (WL), a bit line (BL), and an upper transistor (TFT, that is, a MOS structure in the MOS layer to select an OP layer). Performed to decode the memory cells of the three-dimensional vertical gate. Therefore, the decoding method is simple, and it is not necessary to consider whether or not a special operation waveform is required.

[0031]

In addition, the three-dimensional stacked semiconductor structure of the embodiment can also be selectively added to a related process that can reduce the capacitance of the MiLC pad. In general, the MiLC pad capacitance is very high, and the conventional decoding method needs to charge each MiLC pad of the selected bit line, so the total bit capacitance (total BL capacitance) will be due to the number of charged MiLC pads. And it becomes very high. However, according to an embodiment, each MiLC pad can be controlled via a MiLC pad selector, so that the total bit line capacitance can be greatly reduced. When a MiLC pad selector is turned on during decoding, only one MiLC pad is charged. 10 and 11 are schematic views respectively showing a MOS layer and a metal winding of a three-dimensional stacked semiconductor structure according to another embodiment of the present disclosure.

[0032]

As shown in Fig. 10, a plurality of bit line pad selectors (ie MiLC pad selectors for selecting bit line pads to be charged) can be combined with MOS structures (such as 31). , 32, 33, 34) formed at the same time. Please refer to FIG. 5A and the related description of the above MOS structure. In one embodiment, the structure of the bit line pad selector 35 is the same as that of the MOS structure (such as 31, 32, 33, 34), and details thereof will not be described herein. The bit line pad selector 35 for selecting the bit line pads to be charged is perpendicular to the polycrystalline beam. Furthermore, the bit line pad selectors 35 as shown in FIG. 10 can be coupled to corresponding polysilicon strips and formed in corresponding conductive plugs (eg, 27-1, 27-2, 27-3, 27-). 4) Between the MOS structure (such as 31, 32, 33, 34).

[0033]

Thereafter, related contacts and several layers of metal windings are formed. Please refer to Figure 8 and Figure 9 at the same time. As shown in FIG. 11, when the gate line contacts 411, 412, 413, 414 and the source line contacts 431, 432, 433, 434 and the bit line contacts 451, 452, 453, 454 are formed, several are also formed. Bit line pad selector contacts 471, 472, 473, 474. Moreover, when the layer selection lines 51, 52, 53, 54 and the source line SL are formed, a bit line pad selection line (such as 55) is also formed in contact with the bit line pad selector (eg, 471, 472, 473,474). During decoding, when the bit line pad selector 35 is turned on, only one corresponding bit line pad (i.e. MiLC pad) is selected to be charged. According to the decoding mode of this embodiment, the corresponding OP layer is selected via one of the MOS structures (such as 31, 32, 33, 34), and one bit of the intended charge is selected by one of the bit line pad selectors 35. Wire mat. Therefore, the bit line capacitance of the three-dimensional stacked semiconductor structure of the embodiment can be greatly reduced.

[0034]

According to the above embodiment, a MOS layer is formed between the metal winding and the three-dimensional stacked memory cell in the three-dimensional stacked semiconductor structure. The MOS layer includes a plurality of MOS structures as layer-selectors to select and decode layer planes to be operated. According to the embodiment, regardless of the number of layers of the OP layer, it is only necessary to fabricate the MOS structure of the MOS layer in a single layer process, thereby simplifying the process and enlarging the process window. Therefore, the three-dimensional stacked semiconductor structure of the embodiment not only has good reliability of electronic characteristics, but is more suitable for fabricating a small-sized three-dimensional stacked semiconductor structure. Furthermore, the decoding method of the three-dimensional stacked semiconductor structure of the embodiment is performed by selecting a word line (WL), a bit line (BL), and an upper transistor (TFT, ie, a MOS structure in the MOS layer to select an OP layer). The memory of the three-dimensional vertical gate is decoded, so the decoding operation is very simple and reliable. In addition, related processes for reducing the capacitance of the MiLC pad can also be selectively added to substantially reduce the total bit line capacitance of the three-dimensional stacked semiconductor structure of the embodiment. Moreover, the three-dimensional stacked semiconductor structure of the embodiment adopts a non-time consuming and non-expensive process, and is suitable for mass production in production.

[0035]

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

20‧‧‧Substrate

21, 22, 23, 24‧‧‧ Stacking

21-1, 22-1, 23-1, 24-1, 24-2‧‧‧ multilayer columns

211, 221, 231, 241‧‧ insulation

213, 223, 233, 243‧‧‧ conductive layers

215, 225, 235, 245‧‧ ‧ charge trapping layer

25-1, 25-2, 25-3, 25-4‧‧‧ semiconductor strips

21G, 22G, 23G, 24G‧‧‧ gate

Layer-1, Layer-2, Layer-3, Layer-4‧‧ layer plane

BP1, BP2, BP3, BP4‧‧‧ bit line pads

A1‧‧‧ first area

A2‧‧‧Second area

MOS‧‧‧metal oxide semiconductor layer

WL ₀ , WL ₃₁ ‧‧‧ character line

BL _N , BL _N+1 ‧‧‧ bit line

SSL‧‧‧ tandem selection line

GSL‧‧‧ Grounding selection line

Claims (10)

[Item 1] A three-dimensional stacked semiconductor structure comprising:
A plurality of stacks are vertically formed on a substrate and parallel to each other, and one of the stacks includes a plurality of multi-layered pillars, each of the plurality of pillars including a plurality of layers of insulating layers and a plurality of layers of conductive layers Layers are alternately stacked;
a dielectric layer is formed on the stacks;
A plurality of conductive plugs are independently formed at the dielectric layer; and a metal-oxide-semiconductor (MOS) layer is formed on the dielectric layer, and the MOS layer includes a plurality of MOS structures They are electrically connected to the conductive plugs respectively. [Item 2] The three-dimensionally-stacked semiconductor structure of claim 1, wherein the stacked structures extend in a first direction, the three-dimensional stacked semiconductor structure further comprising:
a plurality of semiconductor strips, each of the semiconductor strips extending in a second direction and connecting the conductive layers of the plurality of stacked plurality of pillars in the same planar layer, wherein the second direction is vertical And the plurality of pad structures are electrically connected to the plurality of semiconductor strips, wherein the plurality of semiconductor strips located in the same planar layer are electrically connected by one of the pad structures.
The conductive plugs are respectively connected to different pad structures, and the MOS structures are electrically connected to the conductive plugs respectively as layer-selectors. [Item 3] The three-dimensional stacked semiconductor structure of claim 2, wherein a string selection line (SSL) is configured continuously, and each of the pad structures includes a first region and a second area is connected to the first area,
The first region is an N+ region and the second region is an N region, and the MOS structures are NMOS structures, and the conductive plugs are N+ conductive plugs; or
The first region is a P+ region and the second region is an N region. The MOS structures are PMOS structures, and the conductive plugs are P+ conductive plugs. [Item 4] The three-dimensional stacked semiconductor structure of claim 1, wherein each of the MOS structures comprises:
a patterned polysilicon layer is formed on the boundary layer;
a patterned oxide layer is formed on the patterned polysilicon layer;
a gate oxide (GOX) covering a sidewall of the patterned polysilicon layer; and an island gate formed on the patterned oxide layer to cover the patterned oxide layer and the gate oxide,
The patterned polysilicon layer shielded by the island gate is an undoped polysilicon layer, and the MOS structures are electrically connected to the heavily doped polysilicon portions of the patterned polysilicon layer respectively. The conductive plugs;
The three-dimensional stacked semiconductor structure further includes:
A plurality of gate line contacts are respectively formed on the island gates of the MOS structures;
A plurality of source line contacts are respectively formed at the heavily doped polysilicon portions;
A plurality of bit line contacts are formed on the dielectric layer;
A plurality of layer-selector lines are respectively formed on the gate line contacts, and the layer selection lines are parallel to each other and extend along a first direction;
a source line is formed on the source line contacts, and the source line is parallel to the layer selection lines; and a plurality of bit lines are insulated above the layer selection lines, and the bits are The lines are perpendicular to the layer selection lines and extend along a second direction. [Item 5] The three-dimensionally-stacked semiconductor structure of claim 1, wherein the MOS structures are electrically connected to the conductive plugs through the polysilicon strips formed on the dielectric layer, the MOS layer further comprising:
A plurality of bit line pad selectors are formed perpendicular to the polysilicon strips, and each of the bit line pad selectors is coupled to the corresponding polycrystalline strips and formed in the corresponding Between the conductive plugs and the MOS structures. [Item 6] The three-dimensional stacked semiconductor structure of claim 5, wherein one of the MOS structures comprises:
a patterned polysilicon layer is formed on the boundary layer;
a patterned oxide layer is formed on the patterned polysilicon layer; and an island gate overlies the patterned oxide layer, and the patterned polysilicon layer masked by the island gate is undoped polysilicon. The MOS structures are electrically connected to the conductive plugs via the patterned polysilicon layers, respectively.
The three-dimensional stacked semiconductor structure further includes:
A plurality of bit line pad selector contacts are formed on the bit line pad selector;
A plurality of gate line contacts are respectively formed on the island gates of the MOS structures;
A plurality of source line contacts are respectively formed at the heavily doped polysilicon portions of the patterned polysilicon layer and connected to the source lines;
A plurality of bit line pad selector lines are formed on the bit line pad selector contacts to select bit line pads, and the bit line pad selection lines are along Extending in a first direction;
A plurality of layer-selector lines are respectively formed on the gate line contacts, and the layer selection lines are parallel to each other and extend along the first direction;
a source line is formed on the source line contacts, and the source line is parallel to the layer selection lines;
A plurality of bit line contacts are formed on the dielectric layer; and a plurality of bit lines are insulatively located above the bit line pad selection lines and the layer selection lines, wherein the bits The line is perpendicular to the bit line pad selection lines and the layer selection lines and extends along a second direction. [Item 7] A method of fabricating a three-dimensional stacked semiconductor structure, comprising:
Forming a plurality of stacks perpendicular to a substrate and parallel to each other, one of the stacks comprising a plurality of multi-layered pillars, each of the plurality of pillars comprising a plurality of layers of insulation and a plurality of layers of conductive Layers are alternately stacked;
Forming a dielectric layer on the stacks;
Forming a plurality of conductive plugs independently at the dielectric layer; and forming a metal oxide semiconductor (MOS) layer on the dielectric layer, and the MOS layer includes a plurality of MOS structures electrically connected to the conductive plugs . [Item 8] The manufacturing method of claim 7, wherein the stacking system extends in a first direction, the manufacturing method further comprising:
Forming a plurality of semiconductor strips, each of the semiconductor strips extending in a second direction and connecting the conductive layers of the plurality of stacked plurality of pillars in the same planar layer, wherein the second direction And a plurality of pads are electrically connected to the plurality of semiconductor structures, wherein the semiconductors in the same planar layer are electrically connected to one of the pads,
The conductive plugs are respectively connected to different pad structures, and the MOS structures are electrically connected to the conductive plugs respectively as layer-selectors. [Item 9] The manufacturing method of claim 7, wherein forming each of the MOS structural systems comprises:
Forming a patterned polysilicon layer on the dielectric layer;
Forming a patterned oxide layer on the patterned polysilicon layer;
Forming a gate oxide covering the sidewall of the patterned polysilicon layer;
Forming an island gate on the patterned oxide layer, and self-aligning the source/drain to implant the patterned polysilicon layer, so that the portion of the patterned polysilicon layer masked by the island gate is undoped The heteropolysilicon, the remaining portion of the patterned polysilicon layer not covered by the island gate is heavily doped polysilicon,
The MOS structures are electrically connected to the conductive plugs via the portions of the heavily doped polysilicon of the patterned polysilicon layer. [Item 10] The manufacturing method of claim 7, wherein the MOS structures are respectively electrically connected to the conductive plugs through the polysilicon strips formed on the dielectric layer, and the forming of the MOS layer further comprises:
Forming a plurality of bit line pad selectors perpendicular to the polysilicon strips, and each of the bit line pad selectors is coupled to the corresponding polysilicon strips to select a bit line A bit line pad, wherein the bit line pad selector is located between the corresponding conductive plugs and the MOS structures.