TW201618094A - Backup power supply cell in memory device - Google Patents

Abstract

Example implementations relate to a backup power supply in a memory cell. For example, a parallel backup power supply system can include a memory device. The memory device can include memory that is integrated in the memory device. The memory device can also include a back-up power supply cell that is integrated in the memory device and that provides back-up power supply to the memory.

Description

Backup power supply unit in the memory device

The present invention relates to a backup power supply unit in a memory device.

As the reliance on computing systems continues to grow, the need for reliable power systems and backup solutions for these computing systems continues to grow. For example, the server can provide an architecture for backing up data to flash or permanent memory, and a backup power source for such backup of power to the data after power is lost. The alternate power supply may sometimes contain an energy component such as a capacitor or battery.

According to one aspect of the invention, a backup power supply system is provided that includes: a memory device. The memory device includes: a memory integrated in the memory device; and a backup power supply unit integrated in the memory device to provide backup power to the memory.

According to one aspect of the present invention, a method for providing backup power includes: detecting a primary power supply failure by a controller in a memory device; responsive to the primary The power supply fails to change a power mode associated with the memory in the memory device to become a self-updating mode; a standby power supply unit integrated in the memory device is activated to enable the self-updating mode; Responding to the main power supply The uniformity of the device can be used to deactivate the backup power supply unit.

According to one aspect of the present invention, a method for providing backup power includes: detecting a primary power supply failure by a controller in a memory device; initiating an integrated a backup power supply unit in the memory device to provide backup power to volatile memory integrated in the memory device; using the backup power to transfer data stored in the volatile memory to be integrated The non-volatile memory in the memory device; and when the transfer of data from the volatile memory to the non-volatile memory is completed, the standby power supply unit is deactivated.

100‧‧‧ memory device

102‧‧‧ pins

104‧‧‧Power conditioner

106‧‧‧ Controller

108‧‧‧Reserved power supply unit

110‧‧‧Charger

112‧‧‧Discharge control circuit

114‧‧‧Power switch

116‧‧‧ Busbar

118‧‧‧ memory

118-1, 118-2, 118-3, 118-4, 118-5, 118-6, 118-7, 118-8, 118-9, 118-10, 118-11, 118-12, 118- 13, 118-14, 118-15, 118-16, 118-17‧‧‧ memory chips

200‧‧‧ memory device

202‧‧‧ pins

204‧‧‧Power conditioner

206‧‧‧ Controller

208‧‧‧Reserved power supply unit

210‧‧‧Charger

212‧‧‧Discharge control circuit

214‧‧‧Power switch

218‧‧‧ volatile memory

218-1, 218-2, 218-3, 218-4, 218-5, 218-6, 218-7, 218-8, 218-9‧‧‧ volatile memory chips

230‧‧ ‧ busbar

232‧‧‧Non-volatile memory

232-1, 232-2, 232-3, 232-4, 232-5, 232-6, 232-7, 232-8‧‧‧ Non-volatile memory chips

340, 342, 344, 346‧ ‧ steps

1 is a block diagram depicting an example of a memory device including a backup power supply unit in accordance with the present disclosure; and FIG. 2 is a block diagram showing an example of a memory device including a backup power supply unit in accordance with the present disclosure. FIG. 3 is a flow chart depicting an exemplary method for a backup power supply in accordance with the present disclosure.

A backup power supply system can include a memory device. The memory device can store data utilized by a computing device. A backup power supply system can include an integrated backup power supply unit. The backup power supply unit can provide backup power to the memory integrated in the memory device. If a primary power supply fails, the backup power can be provided to the memory.

The removal of a primary power supply can be predetermined or unscheduled. For example, the predetermined removal of the primary power supply may be the result of predetermined maintenance of the computing device and/or the memory device. The predetermined removal of the primary power supply may be a deliberate power outage of the nodes and/or the loads to add and/or remove nodes to a chassis and/or to a primary power supply and/or network. In another example, the predetermined removal of the primary power supply can be a deliberate power outage to add and/or remove one or more loads from one or more nodes.

The removal of an unscheduled primary power supply may be a failure in the primary power supply. Removal of an unscheduled primary power supply may occur, for example, if the primary power supply fails briefly and/or fails over an extended period of time.

In the event of a primary power failure, it may be desirable to provide backup power services to a memory device associated with a computing device. A backup power supply can be a primary power supply. A backup power supply can provide backup power to the computing device and/or the memory device via a backup power supply unit.

In some methods, the alternate service is provided to a memory device via a backup power supply unit that is not integrated into the memory device. Providing an alternate service via a non-integrated unit requires an infrastructure to provide power from the non-integrated unit to the memory device. The non-integrated unit and associated infrastructure may increase the cost associated with providing services associated with the memory device.

In contrast, an example of the present disclosure consolidates a backup power supply unit into a memory device, thereby eliminating the need for an infrastructure associated with the non-integrated unit. A memory device is defined as a device that provides a memory service to a computing device. For example, a memory pack The device can be a dual in-line memory module (DIMM) and/or a non-volatile dual in-line memory module (NVDIMM), and other types of memory modules. A memory device can include a memory (eg, a memory chip).

As used herein, a memory can include non-volatile memory (eg, permanent memory) and/or volatile memory (eg, non-permanent memory). For example, the memory can include cache memory, random access memory (RAM), and/or non-volatile random access memory (NVRAM), as well as other types of memory. The memory can be integrated in the memory device. For example, the memory device can include a circuit board. The memory can be coupled to the circuit board. For example, the memory can be a memory wafer that is coupled to the circuit board via electrical connections that utilize conductive tracks, pads, and other features that are etched into the board.

A backup power supply unit can provide backup power to the memory. The backup power supply unit can also be integrated in the memory device. In other words, the alternate power supply unit can be coupled to the circuit board via electrical connections utilizing conductive tracks, pads, and other features etched into the memory board of the memory device.

Providing an integrated backup power supply unit can reduce the cost of providing backup services compared to the use of non-integrated units. Providing backup power services via an integrated backup power supply unit does not require an infrastructure associated with the unintegrated unit and the cost of providing the infrastructure.

1 is a block diagram depicting an example of a memory device including a backup power supply unit in accordance with the present disclosure. As depicted in FIG. 1, the memory device 100 includes memory chips 118-1, 118-2, 118-3, 118-4, 118-5, 118-6, 118-7, 118-8, 118-9, 118-10, 118-11, 118-12, 118-13, 118-14, 118-15, 118-16 and Memory in the form of 118-17 (e.g., generally referred to as memory 118), and a backup power supply unit 108. In some examples, more or less memory chips may be contained within the memory device 100 than those shown herein. The memory device 100 also includes a power conditioner 104, a controller 106, a charger 110, a discharge control circuit 112, a power switch 114, and/or a plurality of pins 102.

In some examples, memory device 100 can be a non-transitory storage medium, wherein the term "non-transitory" does not encompass transient transmission signals. As used herein, the backup power supply unit 108 is a device that provides backup power. For example, a unit can be a battery and other backup power devices. The backup power supply unit 108 can be controlled via the controller 106.

The controller 106 can determine a charge amount associated with the backup power supply unit 108. The controller 106 can activate a charger 110 to charge the alternate power supply unit 108. The controller 106 can deactivate the charger 110 to stop the backup power supply unit 108 from being charged. The charger 110 can be utilized to charge the backup power supply unit 108 when the amount of charge of the backup power supply unit 108 is below a threshold. For example, the charger 110 can be controlled by the controller 106 to charge the backup power supply unit 108 when the amount of charge is less than 95%. A charger 110 can, for example, charge the backup power supply unit 108 at the beginning (e.g., power on) of an associated computing device and/or after the primary power source has been restored from the primary power failure.

The charger 110 can receive power from the power conditioner 104. The power conditioner 104 can receive power from the pins 102. The pins 102 can receive power from a computing device. The power provided by the pins 102 may be the same as that required by the charging unit 108. The voltage of the force is related. For example, the power provided through the pins 102 may be 12 volts (v). The power regulator 104 can adjust the 12v to a voltage suitable for charging the unit 108. For example, the power regulator 104 can adjust the 12v input power to an 8v power output that can be utilized by the charger 110 to charge the unit 108. However, the power regulator 104 can adjust the 12v to a voltage higher or lower than 8v.

The controller 106 can provide backup power to the memory 118 in the event of a primary power failure. The controller 106 can activate the discharge control circuit 112 to discharge the backup power supply unit 108. The controller can activate the discharge control circuit 112 to retrieve the backup power supply unit 108. The backup power can be directed through the discharge control circuit 112 and the power switch 114 to the memory 118. The controller can activate the power switch 114 to provide the backup power to the memory 118 in the event of a primary power failure. However, if there is no primary power failure, the power switch can be activated to draw the backup power through the pins 102.

The pins 102 are a coupling point between the memory device 100 and a computing device. The pins 102 can be utilized to transfer data from the memory 118 to the computing device and to and from the alternate power supply unit 108 to transfer power. The pins 102 can conform to a given layout used by the memory device 100. The bus 116 can be utilized to transfer data to and from the memory 118. For example, the bus can be a memory input/output (I/O) bus.

The memory 118 in Figure 1 is a volatile memory. For example, each of the memory chips associated with memory 118 can be a RAM. As long as the memory 118 receives power, the memory 118 can hold the data stored in the memory chips. The volatile memory chip loses the data stored in the memory when a major power failure occurs.

The controller 106 and/or a processor associated with the computing device can detect a failure in the primary power supply. The controller 106 can set the memory chips in one of some power modes. The power mode associated with the memory 118 can define how the device consumes the primary power and/or backup power. For example, the controller 106 can set the memory 118 in a self-updating mode and/or in a standby power mode. A backup power mode is further defined in Figure 2.

A self-updating mode provides the ability to suspend operation of the controller 106 to conserve power without losing the data stored in the memory 118. In a self-updating mode, the data cannot be retrieved from the memory 118, and the data cannot be stored in the memory 118. Setting the memory 118 in a self-refresh mode also saves power by reducing the update rate associated with the memory 118. In some examples, setting the memory 118 in the self-refresh mode may save a greater amount of power than setting the memory 118 to a standby power mode or a mode associated with normal operation of the memory 118.

In the self-refresh mode, the memory 118 draws power from the unit 108. The power drawn from the unit 108 is only sufficient to hold the data stored in the memory 118. In the self-refresh mode, the memory 118 draws power indefinitely until the primary power source returns to the memory device 100.

After the primary power source is restored, the controller 106 can be activated and the memory 118 can be placed in a mode associated with normal operation on the memory 118. After the recovery of the primary power source, the controller 106 can deactivate the backup power supply unit 108 by deactivating the discharge control circuit 112. The controller can also charge the backup power supply unit by activating the charger 110.

During the main power failure, since the memory 118 is placed in a self-refresh mode, the volatile memory 118 can remain under the backup power supply that is not integrated in the memory device 100. The data stored in the memory 118. In other words, the memory device 100 can be a permanent memory without using non-volatile memory.

2 is a block diagram depicting an example of a memory device including a backup power supply unit in accordance with the present disclosure. The memory device 200 includes a form having volatile memory chips 218-1, 218-2, 218-3, 218-4, 218-5, 218-6, 218-7, 218-8, 218-9. Memory (e.g., referred to herein as volatile memory 218) is similar to memory chips 118-1 through 18-17 in Figure 1, and non-volatile memory chips 232-1, 232- 2. 232-3, 232-4, 232-5, 232-6, 232-7, 232-8 (e.g., referred to herein as non-volatile memory 232). The memory device 200 also includes a backup power supply unit 208 that is similar to the backup power supply unit 108. In some examples, more or less volatile memory chips 218-1 through 218-9 and non-volatile memory chips 232-1 through 232- are compared to those shown herein. 8 can be included in the memory device 200. The memory device 200 also includes a power conditioner 204, a controller 206, a charger 210, a discharge control circuit 212, a power switch 214, and a plurality of pins 202, which are similar to a power conditioner 104, A controller 106, a charger 110, a discharge control circuit 112, a power switch 114, and a plurality of pins 102.

2 provides an example of supplying backup power to transfer data stored in the volatile memory 218 to the non-volatile memory 232. In some examples, the controller 206 can identify a primary power failure and set the volatile memory 218 in a self-updating mode.

After the volatile memory 218 is set in the self-refresh mode, the controller 206 can sequentially change the power modes associated with the volatile memory 218 to allow storage in the volatile memory 218. The data can be transferred to non-volatile memory 232. Changing the power mode associated with the volatile memory 218-1 to allow for the transfer of data can include changing from a self-refresh mode to a mode that consumes more energy. For example, a power mode associated with the volatile memory 218 can be changed from a self-refresh mode to a standby power mode.

This alternate power mode can permit the transfer of data from the volatile memory 218. The alternate power mode can consume more energy than the self-updating mode because the standby power mode receives commands from an activated controller and because the backup power mode can support data transfer from the volatile memory 218. However, volatile memory 218 in a standby power mode may use less energy than a normal operation of the volatile memory 218.

A power mode associated with the volatile memory 218 can be sequentially changed from a self-refresh mode to a standby power mode. Sequentially changing the volatile memory 218 from a self-refresh mode to a standby power mode may include individually changing each of the volatile memory chips one after the other. For example, the volatile memory wafer 218-1 can be changed to a standby power mode before the other volatile memory chips 218-2 through 218-9 are changed to a standby power mode. The volatile memory wafer 218-2 can be changed to the standby power mode after the volatile memory chip 218-1 is changed to the standby power mode, but is changed to the standby power in the other volatile memory chips 218-3 to 218-9. The mode is changed to a standby power mode before. The volatile memory wafer 218-3 can be changed after the volatile memory wafers 218-1 and 218-2 are changed to the standby power mode, but are changed in other volatile memory chips 218-4 through 218-9. The standby power mode is changed to the standby power mode before. Volatile memory chip 218-4 may be after the volatile memory chips 218-1 and 218-3 are changed to the standby power mode, but before the other volatile memory chips 218-5 to 218-9 are changed to the standby power mode. Change to this alternate power mode.

The volatile memory wafer 218-5 can be changed after the volatile memory wafers 218-1 and 218-4 are changed to the standby power mode, but are changed in other volatile memory chips 218-6 through 218-9. The standby power mode is changed to the standby power mode before. The volatile memory wafer 218-7 can be changed after the volatile memory wafers 218-1 and 218-6 are changed to the standby power mode, but are changed in other volatile memory chips 218-8 through 218-9. The standby power mode is changed to the standby power mode before. The volatile memory wafer 218-8 can be changed to the standby power mode after the volatile memory chips 218-1 and 218-7 are changed, but the volatile memory wafer 218-9 is changed to the standby power. The mode is changed to the standby power mode before. The volatile memory wafer 218-9 can be changed to the standby power mode after the volatile memory chips 218-1 and 218-8 are changed to the standby power mode.

During operation of the volatile memory 218 in the standby power mode, the data stored in the volatile memory 218 may be transferred to the non-volatile memory 232 during a primary power failure. Transferring data from the volatile memory 218 to the non-volatile memory 232 can store the data such that the primary power failure does not affect the recall of the data from the memory device 200 when the primary power source is activated (eg, , the information has not lost the ability). This data can be transferred from the volatile memory 218 to the non-volatile memory 232 via the bus bar 230. In some examples, bus bar 230 can be similar to bus bar 116 and/or it can be a different bus bar. For example, bus bar 230 can only be utilized to be in volatile memory 218 Data is transferred between the non-volatile memory 232 and the data cannot be transferred to the computing device coupled to the memory device 200.

The transfer of data can be performed cyclically. Cycling the transfer of data may include performing a data transfer from a first memory chip prior to initial transfer of data from a second memory chip. For example, the transfer of data stored in the volatile memory wafer 218-1 can be initiated and completed before the data stored in the volatile memory wafers 218-2 through 218-9 is transferred. The transfer of data stored in the volatile memory wafer 218-2 can be initiated and completed before the data stored in the volatile memory wafers 218-3 through 218-9 is transferred. The transfer of data stored in the volatile memory wafer 218-3 can be initiated and completed before the data stored in the volatile memory wafers 218-4 through 218-9 is transferred. The transfer of data stored in the volatile memory wafer 218-4 can be initiated and completed before the data stored in the volatile memory chips 218-5 through 218-9 is transferred.

The transfer of data stored in the volatile memory wafer 218-5 can be initiated and completed before the data stored in the volatile memory wafers 218-6 through 218-9 is transferred. The transfer of data stored in the volatile memory wafer 218-6 can be initiated and completed before the data stored in the volatile memory wafers 218-7 through 218-9 is transferred. The transfer of data stored in the volatile memory wafer 218-7 can be initiated and completed before the data stored in the volatile memory wafers 218-8 through 218-9 is transferred. The transfer of data stored in the volatile memory wafer 218-8 can be initiated and completed before the data stored in the volatile memory wafer 218-9 is transferred. The transfer of data stored in the volatile memory wafer 218-9 can be initiated after the data stored in the volatile memory wafers 218-1 through 218-8 has been transferred.

Cyclically transferring data can maintain a volatile memory wafer in a standby power mode and maintain the remaining volatile memory wafers in a self-refresh mode. Relative to maintaining all of the volatile memory chips 218 in standby mode, only one volatile memory chip is maintained in the standby power mode, while the remaining volatile memory chips are in self-refresh mode to save energy because of volatilization. The memory chip 218 consumes less energy in the self-refresh mode than the volatile memory chip 218 in the standby mode.

Transferring data to non-volatile memory 232 can include launching all of the non-volatile memory wafers at a time, or initiating each of the non-volatile memory wafers at a given time. For example, each of the non-volatile memory chips 232 can be cyclically activated to receive and store data from the volatile memory wafer 218. Starting a non-volatile memory wafer at a time saves energy relative to starting all of the memory chips at once. Initiating a non-volatile memory wafer at a given time can occur when data transferred from the volatile memory 218 is only stored in a non-volatile memory wafer at a given time.

3 is a flow chart depicting an exemplary method for a backup power supply in accordance with the present disclosure. At 340, a primary power failure can be detected by a controller in a memory device. The controller in the memory device can be alerted by a processor associated with the computing device coupled to the memory device and/or by analyzing power provided by a plurality of pins associated with the memory device The power supply has failed. For example, the controller can detect changes in the voltage being provided by the pins.

At 342, the backup power supply unit integrated in the memory device can be activated to provide backup power to the volatile memory integrated in the memory device. In some examples, the backup power supply can be connected to the memory device before being activated. The power provided by the closed pins is charged, wherein the pins are integrated in the memory device. The pins can be integrated into the memory device as it is formed into a circuit board associated with the memory device. In some examples, the backup power supply can be charged via a connection point that is part of the backup power supply and receives power directly from the computing device, rather than from a pin associated with the memory device. To receive electricity.

At 344, data stored in volatile memory can be transferred to non-volatile memory. The volatile memory can be integrated into the memory device. This data can be transferred using backup power from the alternate power supply unit. At 346, the alternate power supply unit can be deactivated when the transfer of data from volatile memory to non-volatile memory is complete. Deactivating the backup power supply during a major power failure may result in the loss of data stored in the volatile memory. However, the data stored in the non-volatile memory will not be lost. Therefore, the volatile memory in the memory device can function as a non-volatile memory. Compared with using only non-volatile memory in the memory device, the use of volatile memory and non-volatile memory in the same memory device can reduce the cost of the memory device because the cost of the volatile memory is less than Non-volatile memory.

In the present disclosure, reference is made to the accompanying drawings which form a part of the drawings, and in the drawings, FIG. These examples are described in sufficient detail to enable those of ordinary skill in the art to practice this disclosure, and it will be appreciated that other examples can be utilized and can be practiced, electrically, and / or structural changes, without departing from the scope of this disclosure.

The pattern here follows a numbered convention in which the first digit corresponds to The figure number, and the remaining number of digits, identifies a component or component in the figure. The elements shown in the various figures herein may be additional examples that can be added, exchanged, and/or eliminated to facilitate the disclosure. In addition, the proportions of the elements provided in the drawings and the relative dimensions are examples of the disclosure, and should not be taken in a limiting sense.

As used herein, with respect to computer-executable instructions stored in a memory and executable by a processor, such as firmware, etc., "logic" is used to perform a particular described herein. An alternative or additional processing resource, such as an action and/or function, includes hardware such as various forms of transistor logic, special application integrated circuits (ASIC), and the like. Again, as used herein, "a" or "some" something may refer to one or more of such things. For example, "some small machines" may refer to one or more small machines. Moreover, as used herein, "a plurality of things" may refer to more than one such thing.

The above description, examples and data provide a description of the method and application, and the use of the systems and methods of the disclosure. Since many examples can be made without departing from the spirit and scope of the system and method of the present disclosure, this description is merely illustrative of some of the many possible example configurations and embodiments.

100‧‧‧ memory device

102‧‧‧ pins

104‧‧‧Power conditioner

106‧‧‧ Controller

108‧‧‧Reserved power supply unit

110‧‧‧Charger

112‧‧‧Discharge control circuit

114‧‧‧Power switch

116‧‧‧ Busbar

118-1, 118-2, 118-3, 118-4, 118-5, 118-6, 118-7, 118-8, 118-9, 118-10, 118-11, 118-12, 118- 13, 118-14, 118-15, 118-16, 118-17‧‧‧ memory chips

Claims (15)

An alternate power supply system includes: a memory device including: a memory integrated in the memory device; and a backup power supply unit integrated in the memory device to provide Backup power to the memory. The system of claim 1, further comprising a circuit board coupled to the memory and the backup power supply unit. In the system of claim 1, the memory device further includes a plurality of pins to provide a primary power source to the memory device. In the system of claim 3, the memory device further includes a controller to activate the backup power supply unit when a primary power supply fails. The memory device further includes a charger for: charging the backup power supply unit from the plurality of pins via a primary power source; and when the standby power supply unit is fully charged, as in the system of claim 3 Stop the backup power supply unit from being charged. In the system of claim 1, the memory device further includes a power conditioner to change a first voltage to a second voltage provided by the primary power source, wherein the backup power supply unit utilizes the second The voltage is charged. A method for providing backup power, comprising: detecting a primary power supply failure by a controller in a memory device; changing and in the memory in response to the primary power supply failure Memory phase in the device Turning off a power mode to a self-updating mode; initiating a standby power supply unit integrated in the memory device to enable the self-updating mode; and responsive to the unmatched power of the primary power supply to deactivate the standby Power supply unit. The method of claim 7, wherein the memory is a volatile memory. The method of claim 8, wherein the self-refreshing mode enables the volatile memory to retain stored data without a primary power source. The method of claim 8, wherein the transferring the data stored in the volatile memory to the non-volatile memory is performed when the primary power supply is enabled. The method of claim 7, wherein the charging of the backup power supply unit is performed by a charger integrated in the memory device when the primary power supply is enabled. A method for providing backup power, comprising: detecting a primary power supply failure by a controller in a memory device; initiating a backup power supply unit integrated in the memory device, Providing backup power to the volatile memory integrated in the memory device; using the backup power to transfer the data stored in the volatile memory to the non-volatile memory integrated in the memory device; And when the transfer of data from the volatile memory to the non-volatile memory is completed, the standby power supply unit is deactivated. The method of claim 12, which includes the alteration and in the memory device A power mode associated with volatile memory becomes a self-renewing mode. The method of claim 13, wherein transferring the data stored in the volatile memory to the non-volatile memory system comprises arranging a power mode associated with some of the wafers in the volatile memory from the self-refresh mode The backup power mode is sequentially changed, wherein the backup power supply provides additional power to a chip in the standby power mode to transfer data to the non-volatile memory. The method of claim 14, comprising the completion of the transfer of the data to the non-volatile memory to change a power mode associated with each of the chips from the standby power mode to the self-updating mode.