TW201614784A - Semiconductor lead bonding structure and manufacturing process thereof - Google Patents

Semiconductor lead bonding structure and manufacturing process thereof

Info

Publication number
TW201614784A
TW201614784A TW103135050A TW103135050A TW201614784A TW 201614784 A TW201614784 A TW 201614784A TW 103135050 A TW103135050 A TW 103135050A TW 103135050 A TW103135050 A TW 103135050A TW 201614784 A TW201614784 A TW 201614784A
Authority
TW
Taiwan
Prior art keywords
paddle
bonding
pin
manufacturing process
lead
Prior art date
Application number
TW103135050A
Other languages
Chinese (zh)
Other versions
TWI614860B (en
Inventor
Ming-Fen Li
Original Assignee
Ming-Fen Li
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ming-Fen Li filed Critical Ming-Fen Li
Priority to TW103135050A priority Critical patent/TWI614860B/en
Publication of TW201614784A publication Critical patent/TW201614784A/en
Application granted granted Critical
Publication of TWI614860B publication Critical patent/TWI614860B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

Provided are a semiconductor lead bonding structure and a manufacturing process thereof, in which a cover bonding lead of the present invention is employed. The structure comprises at least one paddle and a plurality of pins disposed around the paddle, the pin bonding pads being arranged higher the paddle; at least one die bonded to the paddle and having a top formed thereon a plurality of conductive contacts; and a cover plate having a bottom formed thereon a plurality of independent wires composed by a metal layer, each wire having a plurality of soldering pads connected thereto, the cover plate covering the die and the plurality of pins, each wire being electrically connected with the pin soldering pad of the pin and the conductive contacts of the corresponding die via the solder of the soldering pad. Thus, the present invention uses the cover bonding lead to replace the conventional solder bonding lead or flip-chip packaging method.
TW103135050A 2014-10-08 2014-10-08 Semiconductor wire bonding structure and process thereof TWI614860B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW103135050A TWI614860B (en) 2014-10-08 2014-10-08 Semiconductor wire bonding structure and process thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103135050A TWI614860B (en) 2014-10-08 2014-10-08 Semiconductor wire bonding structure and process thereof

Publications (2)

Publication Number Publication Date
TW201614784A true TW201614784A (en) 2016-04-16
TWI614860B TWI614860B (en) 2018-02-11

Family

ID=56361283

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103135050A TWI614860B (en) 2014-10-08 2014-10-08 Semiconductor wire bonding structure and process thereof

Country Status (1)

Country Link
TW (1) TWI614860B (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI240398B (en) * 2004-03-11 2005-09-21 Advanced Semiconductor Eng Semiconductor package with leads in different wire-bonding planes
US8492911B2 (en) * 2010-07-20 2013-07-23 Lsi Corporation Stacked interconnect heat sink
TWI490988B (en) * 2012-03-21 2015-07-01 Chipmos Technologies Inc Semiconductor package structure

Also Published As

Publication number Publication date
TWI614860B (en) 2018-02-11

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