TW201608691A - Improved through silicon via - Google Patents

Improved through silicon via Download PDF

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TW201608691A
TW201608691A TW103129926A TW103129926A TW201608691A TW 201608691 A TW201608691 A TW 201608691A TW 103129926 A TW103129926 A TW 103129926A TW 103129926 A TW103129926 A TW 103129926A TW 201608691 A TW201608691 A TW 201608691A
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layer
hole
barrier layer
nucleation
precursor
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TWI567919B (en
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馬克 蘇瓦
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烏翠泰克股份有限公司
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Abstract

Through via holes are prepared for metallization using ALD and PEALD processing. Each via is coated with a titanium nitride barrier layer having a thickness ranging from 20 to 200 Å. A ruthenium sealing layer is formed over the titanium nitride barrier layer wherein the sealing layer is formed without oxygen to prevent oxidation of the titanium nitride barrier layer. A ruthenium nucleation layer is formed over the sealing layer wherein the nucleation layer is formed with oxygen in order to oxidize carbon during the application of the Ru nucleation layer. The sealing layer is formed by a PEALD method using plasma excited nitrogen radicals instead of oxygen.

Description

經改良之直通矽貫穿孔 Improved straight through hole 1.發明領域 1. Field of invention

本發明係有關於製備用於金屬化之一直通矽貫穿孔的內表面。特別地,每一直通貫穿孔之一內直徑表面及一底壁表面係以一低電阻擴散障壁層塗覆,以避免不相似之材料經其擴散。一密封層塗敷於擴散障壁層上,以避免障壁層氧化。一成核層塗敷於密封層上。成核層促進金屬核之結晶成核及降低金屬化期間孔隙形成。 The present invention is directed to the preparation of an inner surface of an all-through through-hole for metallization. In particular, one of the inner diameter surfaces and one of the bottom wall surfaces of each of the through holes are coated with a low resistance diffusion barrier layer to prevent dissimilar material from diffusing therethrough. A sealing layer is applied to the diffusion barrier layer to prevent oxidation of the barrier layer. A nucleation layer is applied to the sealing layer. The nucleation layer promotes crystal nucleation of the metal core and reduces pore formation during metallization.

2.相關技藝 2. Related skills

直通矽貫穿孔係用於多層或三維積體電路(IC),以使藉由電絕緣之介電層彼此分開之隔離電路層電互連。直通矽貫穿孔或直通孔貫穿孔包含通過一或多個基材層之孔,此等基材層係藉由以無電沉積或電化學電鍍或相似金屬化技術,以諸如銅之低電阻材料填統此孔而金屬化。對於製造具有較佳性能之較便宜、較小且較輕之電子產品的需求趨使產生以較小孔間距分佈於電路景觀上之較小貫穿孔的需要。此導致需要提供具有範圍12-30μm之直徑及200-600μm之直通孔深度或長度的貫穿孔。此等貫穿孔一般係指具有大於約10且最高達50之孔深度對直徑的比率之 高長徑比的貫穿孔。 The through-through vias are used in multilayer or three-dimensional integrated circuits (ICs) to electrically interconnect the isolated circuit layers separated from each other by electrically insulating dielectric layers. The through-through or through-hole through-holes comprise holes through one or more substrate layers that are filled with a low-resistance material such as copper by electroless deposition or electrochemical plating or similar metallization techniques. This hole is metallized. The need to make cheaper, smaller, and lighter electronic products with better performance tends to create smaller through-holes that are distributed over the circuit landscape with smaller hole spacing. This results in the need to provide a through hole having a diameter of 12-30 μm and a through hole depth or length of 200-600 μm. Such through-holes generally refer to a ratio of hole depth to diameter having a diameter greater than about 10 and up to 50. High aspect ratio through holes.

貫穿孔係藉由濕蝕刻、電化學蝕刻、藉由雷射鑽孔,且更近係藉由離子束研磨或蝕刻(諸如,深反應離子蝕刻(DRIE))形成。貫穿孔完全通過一矽基材,且使形成之內矽壁露出。因為貫穿孔完全通過基材層,貫穿孔之一底壁係以與介電基材層附接或一體成型之一電路層的一導體部份為界限。然後,此等孔以一導電材料(例如,銅、鎢、聚矽、金等)藉由電鍍等填充(金屬化),且此導電材料於以高電阻基材層分開之電路層間提供一用以電連通之路徑。 The through vias are formed by wet etching, electrochemical etching, by laser drilling, and more closely by ion beam milling or etching, such as deep reactive ion etching (DRIE). The through hole completely passes through a substrate and exposes the formed inner wall. Since the through hole completely passes through the substrate layer, one of the bottom walls of the through hole is bounded by a conductor portion of one of the circuit layers attached or integrally formed with the dielectric substrate layer. Then, the holes are filled (metallized) by electroplating or the like with a conductive material (for example, copper, tungsten, polyfluorene, gold, etc.), and the conductive material is provided between circuit layers separated by a high-resistance substrate layer. The path of electrical communication.

一直通矽貫穿孔之一重要性能標準係金屬化或導電芯材於整個直徑上及沿著導電芯材之整個長度提供實質上均勻未受限之電流。抑制電流或使貫穿孔性能以其它方式降解的因素包含於填充材料中之孔隙形成及不均勻的材料性質(例如,不均勻的電阻)。孔隙形成於不相似材料間之邊界處特別有問題,於其間,金屬結晶化不坊勻。不均勻的材料性質亦發生於不相似材料間之邊界處,於其間,不相似材料擴散過此邊界,使不相似材料混合且改變物理性質。此於銅或其它金屬化材料擴散至矽基材內且使性能降解時之貫穿孔係特別有問題。 One of the important performance criteria throughout the through-hole is that the metallized or conductive core material provides a substantially uniform, unconstrained current over the entire diameter and along the entire length of the conductive core. Factors that inhibit current or otherwise degrade the through-hole properties include void formation in the filler material and non-uniform material properties (eg, non-uniform electrical resistance). The formation of pores at the boundary between dissimilar materials is particularly problematic, during which the crystallization of the metal is not uniform. Uneven material properties also occur at the boundaries between dissimilar materials, during which dissimilar materials diffuse across the boundary, mixing dissimilar materials and changing physical properties. This through-hole system is particularly problematic when copper or other metallized material diffuses into the tantalum substrate and degrades performance.

避免不相似材料擴散越過材料邊界之一傳統解決方式係於一貫穿孔內直徑表面上及於其底表面上塗敷一擴散障壁層,以避免擴散越過基材金屬化邊界。但是,因為貫穿孔係於基材及電路相接後金屬化,塗敷於貫穿孔之一底表面的障壁層需具有相對較低之電阻,因為經過金屬 化芯材之電流越過覆蓋貫穿孔底表面之障壁層。因此,塗敷至貫穿孔底表面之障壁層的一問題係除非障壁層具有低電阻,否則阻礙電流至電路層。雖然具有低電阻之傳統障壁層可自諸如氮化鈦(TiN)及氮化鉭(TaN)氮化鈷(CoN)之氮化物形成,此等障壁層傳統上係藉由噴濺塗敷。但是,噴濺無法提供高長徑比的貫穿孔良好性能,因為噴濺不能使貫穿孔塗覆至全深度。特別地,超過約8:1之長徑比,噴濺係不適當。但是,即使於極高長徑比的孔提供完全表面覆蓋之一技術係原子層沉積(ALD),其不能使TiN及其它障壁層塗敷至高長徑徑比的貫穿孔之內表面。 One conventional solution to avoid dissimilar material diffusion across the material boundary is to apply a diffuse barrier layer to the consistent inner diameter surface and to coat the bottom surface thereof to avoid diffusion across the substrate metallization boundary. However, since the through holes are metallized after the substrate and the circuit are connected, the barrier layer applied to one of the bottom surfaces of the through holes needs to have a relatively low resistance because the metal passes through the metal. The current of the core material passes over the barrier layer covering the bottom surface of the through hole. Therefore, a problem of the barrier layer applied to the bottom surface of the through hole is that the current is blocked to the circuit layer unless the barrier layer has a low resistance. Although conventional barrier layers having low electrical resistance can be formed from nitrides such as titanium nitride (TiN) and tantalum nitride (TaN) cobalt nitride (CoN), such barrier layers are conventionally applied by sputtering. However, slopping does not provide good performance for through-holes with high aspect ratios because slopping does not allow the through-holes to be applied to full depth. In particular, more than about 8:1 aspect ratio, splashing is not appropriate. However, even a very high aspect ratio hole provides a complete surface coverage of one of the atomic layer deposition (ALD), which does not allow TiN and other barrier layers to be applied to the inner surface of a high aspect ratio through hole.

雖然導電性TiN障壁層已知避免擴散越過基材金屬化邊界且提供可接受之電流越過底表面,但TiN並非理想地適於金屬化黏著。更特別地,於TiN障壁層上之銅或其它導電性金屬化材料的結晶成核係不可接受。為改良與TiN障壁層之金屬化黏著,已知係於障壁層上塗敷諸如鈀、鉑、鈷、鎳及銠等之貴金屬提供改良之銅黏著及降低障壁層之腐蝕及氧化。但是,此等貴金屬通常不能藉由化學蒸氣沉積(CVD)或物理蒸氣沉積(PVD)方法塗敷,其如噴濺般於高長徑比的貫穿孔提供差的覆蓋。 While conductive TiN barrier layers are known to avoid diffusion across the substrate metallization boundary and provide acceptable current across the bottom surface, TiN is not ideally suited for metallization adhesion. More particularly, the crystalline nucleation of copper or other conductive metallization material on the TiN barrier layer is unacceptable. In order to improve the metallization adhesion to the TiN barrier layer, it is known to apply a noble metal such as palladium, platinum, cobalt, nickel, and antimony to the barrier layer to provide improved copper adhesion and to reduce corrosion and oxidation of the barrier layer. However, such precious metals are generally not coated by chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods, which provide poor coverage such as splattering through the high aspect ratio through holes.

Ma等人於4/5/2007公開之名稱為用於釕材料之原子層沉積方法的美國專利申請案US2007/0077750A1中揭露一種方法,其係使用ALD方法於包含二氧化矽、氮化矽、氧氮化矽、經碳摻雜之氧化矽或SiOxCy材料基材之一介電材料基材上形成一釕材料,及於一包含鉭、氮化鉭、矽氮 化鉭、鈦、氮化鈦、矽氮化鈦、鎢或氮化鎢之障壁層材料上形成一Ru層,且一特別例子係使釕材料沉積於藉由ALD或物理蒸氣沉積(PVD)方法事先形成之氮化鉭上。 A method disclosed in U.S. Patent Application Serial No. US 2007/0077750 A1, the disclosure of which is incorporated herein by reference in its entire entire entire entire entire entire entire entire entire entire entire Forming a germanium material on a dielectric material substrate of a cerium oxynitride, a carbon doped cerium oxide or a SiOxCy material substrate, and comprising a germanium, a tantalum nitride, a germanium nitride A Ru layer is formed on the barrier layer material of tantalum, titanium, titanium nitride, tantalum titanium nitride, tungsten or tungsten nitride, and a special example is to deposit the tantalum material by ALD or physical vapor deposition (PVD) method. Pre-formed on the tantalum nitride.

但是,Ma等人揭露二環戊釕化合物,諸如,雙(乙基環戊二烯基)釕、雙(環戊二烯基)釕,及雙(五甲基環戊二烯基)釕,通常沉積一具有增加電阻、差的黏著性(無法通過膠帶測試)之釕材料,通常需要高於400℃之高吸附溫度,且遭受成核延遲。因此,Ma等人結論含有吡咯基配位子之釕先質係更合需要且低於350℃之沉積溫度係更合需要。 However, Ma et al. disclose dicyclopentanyl compounds such as bis(ethylcyclopentadienyl)fluorene, bis(cyclopentadienyl)fluorene, and bis(pentamethylcyclopentadienyl)fluorene, It is common to deposit a tantalum material that has increased electrical resistance, poor adhesion (not tested by tape), typically requires high adsorption temperatures above 400 °C, and suffers from nucleation delays. Therefore, Ma et al. concluded that a ruthenium containing a pyrrole ligand is more desirable and a deposition temperature below 350 °C is more desirable.

Ma等人進一步揭露藉由先使基材曝露於含有吡咯基配位子之釕先質,然後,使基材曝露於一ALD系統內之氨電漿、氮電漿,或氫電漿,而於基材上形成一釕材料,此ALD系統具有於ALD系統外部或併入其內之電漿產生器。特別地,Ma等人似乎認知雖然釕材料可使用一氧先質塗敷,但由於障壁層沉化使障壁層曝露於氧係不利的。 Ma et al. further disclose that by exposing the substrate to a precursor containing a pyrrolyl ligand, the substrate is then exposed to an ammonia plasma, a nitrogen plasma, or a hydrogen plasma in an ALD system. A germanium material is formed on the substrate, the ALD system having a plasma generator external to or incorporated within the ALD system. In particular, Ma et al. seem to recognize that although the tantalum material can be coated with an oxygen precursor, it is disadvantageous that the barrier layer is exposed to oxygen due to the deposition of the barrier layer.

但是,即使此認知,MA等人揭客一晶種層藉由一起始沉積方法沉積於釕材料上,且一本體層其後係藉由另一沉積方法沉積於其上。換言之,MA等人教示之第二層係藉由除了ALD或PEALD以外之方法於異地塗敷。 However, even with this recognition, MA et al. uncover a seed layer deposited on the tantalum material by an initial deposition method, and a bulk layer is subsequently deposited thereon by another deposition method. In other words, the second layer taught by MA et al. is applied off-site by methods other than ALD or PEALD.

3.發明概要 3. Summary of invention

基於與如上所述之傳統貫穿孔表面塗覆方法及經塗覆的貫穿孔有關之問題,本發明之一目的係藉由以ALD或PEALD沉積方法使一導電性擴散障壁層塗敷於貫穿 孔之露出表面而製備一用於金屬化之直通孔貫穿孔。 Based on the problems associated with conventional through-hole surface coating methods and coated through-holes as described above, it is an object of the present invention to apply a conductive diffusion barrier layer throughout the ALD or PEALD deposition process. A through-hole through-hole for metallization is prepared by exposing the surface of the hole.

本發明之另一目的係藉由一ALD或PEALD沉積方法使一導電性成核層塗敷於貫穿孔擴散障壁層之露出表面,以於金屬化期間使導電芯材料成核。 Another object of the present invention is to apply a conductive nucleation layer to the exposed surface of the through-hole diffusion barrier layer by an ALD or PEALD deposition method to nucleate the conductive core material during metallization.

本發明之另一目的係係藉由於障壁層與導電性成核層之間使一密封層塗敷於障壁層上,以保護障壁層免於在塗敷成核層期間氧化,其中,密封層之塗敷係無氧。 Another object of the present invention is to protect the barrier layer from oxidation during application of the nucleation layer by applying a sealing layer between the barrier layer and the conductive nucleation layer on the barrier layer, wherein the sealing layer The coating is oxygen free.

習知技藝之上述缺點可藉由如下揭露之電子裝置及塗覆方法克服。 The above disadvantages of the prior art can be overcome by the electronic device and coating method disclosed below.

一種電子裝置含有直通貫穿孔,其等係藉由一以一電絕緣介電層為界限之內直徑表面及一以一電路層之一導電部份為界限之底壁表面所形成。電路層係與介電層一體成型地形成。每一貫穿孔係以一具有範圍從20至200Å的厚度之氮化鈦(TiN)障壁層塗覆。每一直通孔係以一形成於氮化鈦障壁層上之釕密封層塗覆,且密封層係無氧而形成。每一直通孔係以一形成於釕密封層上之釕成核層塗覆,且釕成核層係具有氧而形成。 An electronic device includes a through-via through which is formed by an inner diameter surface bounded by an electrically insulating dielectric layer and a bottom wall surface bounded by a conductive portion of a circuit layer. The circuit layer is formed integrally with the dielectric layer. Each through hole is coated with a titanium nitride (TiN) barrier layer having a thickness ranging from 20 to 200 Å. Each of the through vias is coated with a germanium sealing layer formed on the titanium nitride barrier layer, and the sealing layer is formed without oxygen. Each of the through vias is coated with a germanium nucleation layer formed on the germanium sealing layer, and the germanium nucleation layer is formed with oxygen.

釕密封層具有範圍從5至10Å之厚度。釕成核層具有範圍從50至150Å之厚度。釕成核層之電阻係少於釕密封層之電阻。每一直通孔係以塗敷於釕成核層上之銅金屬化。 The ruthenium seal layer has a thickness ranging from 5 to 10 Å. The ruthenium nucleation layer has a thickness ranging from 50 to 150 Å. The 钌 nucleation layer has a lower resistance than the 钌 sealing layer. Each of the through vias is metallized with copper applied to the germanium nucleation layer.

一種製備用於金屬化的基材之方法包含塗覆於諸如一電絕緣介電層之基材中的多數個直通孔貫穿孔。材料層係塗敷於每一直通孔之一內直徑表面及一底壁表面。 A method of making a substrate for metallization includes a plurality of through vias applied to a substrate such as an electrically insulating dielectric layer. A layer of material is applied to one of the inner diameter surface and one bottom wall surface of each of the through holes.

一含有此等直通孔貫穿孔之基材係置放於一適於藉由原子層沉積(ALD)及藉由電漿增強電子層沉積(PEALD)塗敷材料沉積層之加工腔室內。 A substrate containing such through vias is placed in a processing chamber suitable for deposition of a material by atomic layer deposition (ALD) and by plasma enhanced electron layer deposition (PEALD).

一包含一第一材料之障壁層係形成於內直徑表面及底壁表面上。第一材料具有少於300μohm-cm之電阻,且以足夠厚度塗敷以實質上避免一金屬化材料擴散通過障壁層。 A barrier layer comprising a first material is formed on the inner diameter surface and the bottom wall surface. The first material has a resistance of less than 300 [mu]ohm-cm and is applied at a sufficient thickness to substantially prevent diffusion of a metallized material through the barrier layer.

一包含一第二材料之密封層係塗覆於整個障壁層上。第二材料具有少於300μohm-cm之電阻。密封層之沉積係於實質上未造成第一材料層氧化而實行。 A sealing layer comprising a second material is applied over the entire barrier layer. The second material has a resistance of less than 300 μ ohm-cm. The deposition of the sealing layer is carried out without substantially causing oxidation of the first material layer.

一包含第二材料之成核層係塗敷於整個密封層上。成核層之沉積包含使碳氧化。 A nucleation layer comprising a second material is applied over the entire sealing layer. The deposition of the nucleation layer involves oxidation of the carbon.

於沉積每一層期間,加工腔室係於少於1托耳之氣壓,且此三層全部皆係於未使基材自加工腔室移除下形成。於形成所有此等層期間,基材係維持於200與400℃間之一實質上固定溫度。 During deposition of each layer, the processing chamber is at a pressure of less than 1 Torr, and all of the three layers are formed without removing the substrate from the processing chamber. During the formation of all of these layers, the substrate is maintained at a substantially fixed temperature between 200 and 400 °C.

障壁層係自氮化鈦、鈦、氮化鉭、鉭、氮化鎢、氮化鈷,及鎢之任一者形成,且可藉由ALD或PEALD形成。用於形成氮化鈦障壁層之先質包含四(二甲基醯胺基)鈦(TDMAT)及氮。 The barrier layer is formed of any one of titanium nitride, titanium, tantalum nitride, tantalum, tungsten nitride, cobalt nitride, and tungsten, and may be formed by ALD or PEALD. The precursor used to form the titanium nitride barrier layer comprises tetrakis(dimethylammonium)titanium (TDMAT) and nitrogen.

密封層係自藉由PEALD於無氧沉積之釕形成。密封層係使用一包含二環戊釕化合物之第一先質及一包含經電漿激發之氮基團的第二先質塗覆,且未使用氧。 The sealing layer is formed from the ruthenium of anaerobic deposition by PEALD. The sealing layer is coated with a first precursor comprising a dicyclopentanyl compound and a second precursor comprising a plasma excited nitrogen group, and no oxygen is used.

除了成核層係藉由具有氧之熱ALD形成以外,成 核層亦係自釕形成。成核層係使用一包含二環戊釕化合物之第一先質及一包含未經基團化之氧的第二先質形成。 Except that the nucleation layer is formed by thermal ALD with oxygen, The nuclear layer is also formed by self-destruction. The nucleation layer is formed using a first precursor comprising a dicyclopentanyl compound and a second precursor comprising un-encapsulated oxygen.

於形成障壁層、密封層及成核層後,基材係自加工腔室移除,以供以本體銅使直通孔異地金屬化。 After forming the barrier layer, the sealing layer, and the nucleation layer, the substrate is removed from the processing chamber to metallize the through-holes with the bulk copper.

此等及其它方面及優點於以下之說明結合附圖閱讀時會變明顯。 These and other aspects and advantages will become apparent upon reading the following description in conjunction with the drawings.

100‧‧‧基材 100‧‧‧Substrate

105‧‧‧第一電路層 105‧‧‧First circuit layer

110‧‧‧電絕緣介電層 110‧‧‧Electrically insulating dielectric layer

115‧‧‧直通孔貫穿孔 115‧‧‧through hole through hole

120‧‧‧導電部 120‧‧‧Electrical Department

125‧‧‧第二半導體電路層 125‧‧‧Second semiconductor circuit layer

130‧‧‧第二導電部 130‧‧‧Second Conductive Department

135‧‧‧導電芯材 135‧‧‧ Conductive core

150‧‧‧擴散障壁層 150‧‧‧Diffusion barrier

155‧‧‧密封層 155‧‧‧ Sealing layer

160‧‧‧成核層 160‧‧‧ nucleation layer

200‧‧‧氣體沉積系統 200‧‧‧Gas Deposition System

205‧‧‧外腔室壁 205‧‧‧External chamber wall

210‧‧‧加工腔室 210‧‧‧Processing chamber

215‧‧‧支撐盤 215‧‧‧Support disk

220‧‧‧支撐表面 220‧‧‧Support surface

222‧‧‧電阻加熱元件 222‧‧‧Resistive heating element

225‧‧‧載入口 225‧‧‧ entrance

230‧‧‧閘閥 230‧‧‧ gate valve

235‧‧‧非電漿先質入口 235‧‧‧ Non-plasma precursor entry

240‧‧‧電漿先質入口 240‧‧‧Purch precursor entry

245‧‧‧電漿產生器模組 245‧‧‧ Plasma generator module

250‧‧‧頂孔 250‧‧‧ top hole

255‧‧‧加工氣體遞送模組 255‧‧‧Processing gas delivery module

260‧‧‧加工氣體供應模組 260‧‧‧Processing gas supply module

265‧‧‧出口 265‧‧‧Export

270‧‧‧真空泵 270‧‧‧vacuum pump

275‧‧‧出口模組 275‧‧‧Export module

280‧‧‧電子控制器 280‧‧‧Electronic controller

285‧‧‧真空閥模組 285‧‧‧Vacuum valve module

290‧‧‧壓力閘 290‧‧‧pressure gate

295‧‧‧溫度感應器 295‧‧‧temperature sensor

4.圖式簡要說明 4. Brief description of the schema

本發明之特徵會自本發明之詳細說明及為了例示目的而選擇且於附圖顯示之其例示實施例而被最佳瞭解,其中:圖1描述顯示依據本發明之直通貫穿孔的結構一基材層及附接的電路層之例示示意圖。 The features of the present invention are best understood from the detailed description of the present invention and the exemplary embodiments illustrated in the accompanying drawings, wherein FIG. An illustration of a layer of material and an attached circuit layer.

圖2描述適於藉由熱原子層沉積(ALD)及電漿增強原子層沉積(PEALD)使材料沉積層塗敷於貫穿孔表面上之一加工腔室及相關模組之例示示意圖。 2 depicts an exemplary schematic diagram of a processing chamber and associated module suitable for applying a material deposition layer to a surface of a through-hole by thermal atomic layer deposition (ALD) and plasma enhanced atomic layer deposition (PEALD).

5.定義 5. Definition

除非以其它方式作特別指示外,下列定義於各處被使用: The following definitions are used everywhere, unless otherwise specified by other means:

6.元件編號列示 6. Component number list

除非以其它方式作特別指示外,下列元件編號於各處被使用: Unless otherwise specified, the following component numbers are used throughout:

7.例示之直通貫穿孔結構 7. Illustrated straight through hole structure

現參考圖1,一多層(3維)積體電路(IC)或基材(100)之一部份係依據本發明之一非限制性例示實施例以側截面圖示意地顯示。基材(100)包含第一電路層(105),其包含一半導體材料本體層,其係以於一或多個介電材料層界宣之電互連圖案及電組份圖案而圖案化,且一或多個互連圖案係終結於一導電層或於導電層部(120)。電路本體層包含半導體材料,諸如,矽、鍺、砷化鎵等。 Referring now to Figure 1, a portion of a multilayer (3-dimensional) integrated circuit (IC) or substrate (100) is shown schematically in side cross-sectional view in accordance with one non-limiting, exemplary embodiment of the present invention. The substrate (100) includes a first circuit layer (105) including a semiconductor material body layer patterned by one or more dielectric material layer electrical interconnect patterns and electrical component patterns, and One or more interconnect patterns are terminated in a conductive layer or in a conductive layer portion (120). The circuit body layer comprises a semiconductor material such as germanium, germanium, gallium arsenide, or the like.

基材(100)進一步包含一電絕緣介電層(110),其包含電絕緣材料,諸如,二氧化矽、氮化矽、氧氮化矽,及/或經碳摻雜之氧化矽(諸如,SiOxCy)等。 The substrate (100) further includes an electrically insulating dielectric layer (110) comprising an electrically insulating material such as hafnium oxide, tantalum nitride, hafnium oxynitride, and/or carbon doped antimony oxide (such as , SiO x C y ), and the like.

多數個直通孔貫穿孔(115)於相對應於導電部(120)之位置處形成完全通過介電層(110)。另外,導電部(120) 係以置於絕緣介電層(110)與半導體電路層(105)間之單一導體材料層延伸。 A plurality of through hole through holes (115) are formed to completely pass through the dielectric layer (110) at a position corresponding to the conductive portion (120). In addition, the conductive portion (120) The layer is extended by a single layer of conductor material disposed between the insulating dielectric layer (110) and the semiconductor circuit layer (105).

如熟習此項技藝者所瞭解,最後,以虛線顯示之一第二半導體電路層(125)會相對於第一電路層(105)與介電層(110)接合接觸地形成或裝配,且第二電路層會包含第二導電部(130)(或一導體層),其係配置成相對於第一導體焊墊(120)與每一直通孔貫穿孔(115)呈電接觸。 As is known to those skilled in the art, in the end, one of the second semiconductor circuit layers (125) is formed or assembled in a mating contact with the dielectric layer (110) with respect to the first circuit layer (105), and The two circuit layers may include a second conductive portion (130) (or a conductor layer) configured to make electrical contact with each of the through vias (115) relative to the first conductive pad (120).

因此,每一直通孔貫穿孔(115)包含一直通孔,其係形成而完全延伸直通電絕緣介電層(110),使得第一導電部(120)藉由形成每一直通孔(115)而露出。直通孔因而包含一內直徑表面,其係以介電層(110)之電絕緣材料為界限;一底表面,其係以第一導體部(120)之一的導電材料為界限。 Therefore, each of the through-hole through-holes (115) includes a through-hole, which is formed to completely extend the direct-on insulating dielectric layer (110) such that the first conductive portion (120) is formed by each through-hole (115) And exposed. The through via thus comprises an inner diameter surface bounded by an electrically insulating material of the dielectric layer (110); a bottom surface bounded by a conductive material of one of the first conductor portions (120).

直通孔係以一或多種傳統貫穿孔形成技術形成,不受限地包含藉由浸蝕刻、電化學蝕刻、藉由雷射鑽孔,及或藉由離子束研磨或諸如深反應離子蝕刻(DRIE)之蝕刻形成。每一直通孔最終係以形成一導電芯材(135)之一導電材料填充(金屬化)。例示之芯材材料包含銅、鎢、聚矽、金,但是,於本發明實施例,銅係較佳。金屬芯材材料係可藉由傳統無電及電化學電鍍方法形成。導電材料芯材(135)提供一導電路徑,其係自一第一導電部(120)延伸至一相對應之相對的第二導電部(130)。操作時,電流通過導電材料芯材(135)提供第一電路層(105)與第二電路層(125)間之電連流。 Through vias are formed by one or more conventional through hole formation techniques, including, by way of example, dip etching, electrochemical etching, by laser drilling, and or by ion beam milling or such as deep reactive ion etching (DRIE). The etching is formed. Each of the through holes is finally filled (metallized) with a conductive material forming one of the conductive core members (135). The illustrated core material comprises copper, tungsten, polyfluorene, gold, but in the embodiment of the invention, copper is preferred. The metal core material can be formed by conventional electroless and electrochemical plating methods. The conductive material core (135) provides a conductive path extending from a first conductive portion (120) to a corresponding opposing second conductive portion (130). In operation, current is supplied to the electrical connection between the first circuit layer (105) and the second circuit layer (125) through the conductive material core (135).

貫穿孔形成成之一主要需求係提供一能於芯材(135)之整個直徑及整個長度均勻不受限之電流的導電材料心材(135)。抑制電流或以其它方式降解貫穿孔性能之因素包含於導電芯材(135)之孔隙形成,及或沿著芯材長度或直徑之不均勻材料性質,例如,不均勻的電阻。金屬化期間孔隙形成之一主要因素係導電芯材材料與直通孔之內直徑表面及底壁表面差的黏著性。此問題係由本發明藉由提供一成核或晶種層(160)[實黑色]而解決,其係於貫穿孔(115)之內直徑表面及底壁表面處與芯材(135)呈接合接觸。成核層(160)係組配成起始用於使芯材金屬化之金屬導體的結晶化。成核層(160)的存在改良金屬芯材(135)之材料與直通孔之內直徑及底壁表面之黏著,且此降低於芯材(135)邊界端緣處之孔隙形成。特別地,本發明藉由一在原位之原子層沉積方法形成成核層。 One of the main requirements for the formation of through-holes is to provide a conductive material core (135) that is capable of uniformly and unrestricted current throughout the diameter and overall length of the core material (135). Factors that inhibit current or otherwise degrade the performance of the through-hole are included in the formation of pores in the conductive core (135), and in non-uniform material properties along the length or diameter of the core, for example, non-uniform electrical resistance. One of the main factors of pore formation during metallization is the adhesion of the conductive core material to the inner diameter surface and the bottom wall surface of the through hole. This problem is solved by the present invention by providing a nucleation or seed layer (160) [solid black] which is bonded to the core material (135) at the inner diameter surface and the bottom wall surface of the through hole (115). contact. The nucleation layer (160) is assembled to crystallize the metal conductor that is used to metallize the core material. The presence of the nucleation layer (160) improves the adhesion of the material of the metal core material (135) to the inner diameter of the through hole and the surface of the bottom wall, and this reduces the formation of voids at the edge of the boundary of the core material (135). In particular, the present invention forms a nucleation layer by an atomic layer deposition method in situ.

於芯材(135)或其附近產生不均勻材料性質之一主要因素係於金屬化期間導電芯材材料擴散至介電層(110)之電絕緣介電材料內。此問題係由本發明藉由於貫穿孔內於直通孔內直徑表面及底壁表面提供一擴散障壁層(150)[實灰色]解決,其中,擴散障壁層(150)係藉由ALD或PEALD沉積。擴散層(150)係以足夠材料厚度形成,以實質上避免不相似材料(特別是銅)腐蝕擴散層(150)。擴散層(150)係自一具有少於約300ohm-cm之電阻的材料形成,以便使阻礙電流流過於導電芯材(135)與第一導電部(120)間之電界面處的擴散層(150)之底表面達最小。較佳地,擴散層(150) 係自可於少於500℃之反應溫度且較佳係於250至350°之反應溫度範圍藉由一熱ALD方法或一PEALD方法塗敷之一材料形成。 One of the major factors in the production of non-uniform material properties in or near the core material (135) is the diffusion of the conductive core material into the electrically insulating dielectric material of the dielectric layer (110) during metallization. This problem is solved by the present invention by providing a diffusion barrier layer (150) [solid gray] in the through hole in the inner diameter surface and the bottom wall surface of the through hole, wherein the diffusion barrier layer (150) is deposited by ALD or PEALD. The diffusion layer (150) is formed with a sufficient material thickness to substantially prevent the dissimilar material (especially copper) from corroding the diffusion layer (150). The diffusion layer (150) is formed from a material having a resistance of less than about 300 ohm-cm so as to impede current flow over the diffusion layer at the electrical interface between the conductive core (135) and the first conductive portion (120) ( 150) The bottom surface is minimal. Preferably, the diffusion layer (150) It is formed by coating a material by a thermal ALD method or a PEALD method from a reaction temperature range of less than 500 ° C and preferably from 250 to 350 °.

依據本發明之一非限制性例示方面,直通孔貫穿孔(115)係如下般形成。每一直通孔係藉由如上所述之一適當的孔形成技術形成。雖然不同直通孔貫穿孔(115)可具有相同或不同的孔直徑,但任何特定直通孔之直徑較佳範圍係12與30μm之間,但較大直徑之直通孔可藉由本發明加工。每一直通孔(115)之深度或長度實質上係相等於介電層(110)之厚度,其於本發明非限制性例示實施例,對於高長徑比的貫穿孔係於200與600μm之間,但較短長度之直通孔可藉由本發明加工。直通孔(115)間之中心對中心之節距尺寸係50μm或更高,但較小之中心節距尺寸的直通孔可藉由本發明加工。因此,若更高長徑比之貫穿孔可被形成,本發明係適於具有範圍最高達50或更高之孔直徑對孔深度的長徑比之極高長徑比的貫穿孔。 According to one non-limiting exemplary aspect of the invention, the through-hole through-holes (115) are formed as follows. Each through via is formed by a suitable hole formation technique as described above. Although the different through-hole through-holes (115) may have the same or different hole diameters, the diameter of any particular through-holes preferably ranges between 12 and 30 [mu]m, but larger diameter through-holes may be processed by the present invention. The depth or length of each of the through holes (115) is substantially equal to the thickness of the dielectric layer (110). In the non-limiting exemplary embodiment of the present invention, the through holes of the high aspect ratio are between 200 and 600 μm. The through-holes, but shorter lengths, can be processed by the present invention. The center-to-center pitch size between the through holes (115) is 50 μm or more, but a smaller center pitch size through hole can be processed by the present invention. Therefore, if a through-hole having a higher aspect ratio can be formed, the present invention is suitable for a through-hole having a very high aspect ratio ranging from a hole diameter of up to 50 or more to a hole diameter to a hole depth.

每一貫穿孔(115)包含一擴散障壁層(150)其係直接塗敷於貫穿孔之內表面上,包含於藉由介電層(110)形成之內直徑表面上及藉由導電部(120)形成之直通孔底表面上。障壁層(150)被形成以於芯材金屬化期間避免或大量減小金屬化材料(較佳係銅)擴散過障壁層(150)。障壁層(150)包含一具有足夠低之電阻的材料,以提供實質上未受阻礙之電流通過擴散層底表面。於一非限制性例示實施例,障壁層(150)包含氮化鈦(TiN),其係塗敷至20至200Å(2至20nm)範 圍之層厚度。TiN障壁層(150)較佳係藉由熱原子層沉積(ALD)方法或電漿增強原子層沉積(PEALD)方法之任一者塗敷。另外,障壁層(150)包含藉由電漿增強原子層沉積(PEALD)方法塗敷至20至200Å(2至20nm)範圍之層厚度的TiN者。適於本發明之其它例示的障壁層材料包含藉由ALD或PEALD方法形成之鈦、氮化鉭、鉭、氮化鎢,及鎢。於每一情況,障壁層之電阻係低於300ohm-cm且較佳地。 Each of the through holes (115) includes a diffusion barrier layer (150) directly coated on the inner surface of the through hole, and is included on the inner diameter surface formed by the dielectric layer (110) and by the conductive portion (120) ) formed on the bottom surface of the through hole. The barrier layer (150) is formed to avoid or substantially reduce diffusion of the metallized material (preferably copper) through the barrier layer (150) during core metallization. The barrier layer (150) includes a material having a sufficiently low electrical resistance to provide substantially unimpeded current through the bottom surface of the diffusion layer. In a non-limiting, exemplary embodiment, the barrier layer (150) comprises titanium nitride (TiN) applied to a range of 20 to 200 Å (2 to 20 nm). The thickness of the layer. The TiN barrier layer (150) is preferably applied by any one of a thermal atomic layer deposition (ALD) method or a plasma enhanced atomic layer deposition (PEALD) method. In addition, the barrier layer (150) comprises TiN coated to a layer thickness in the range of 20 to 200 Å (2 to 20 nm) by a plasma enhanced atomic layer deposition (PEALD) method. Other exemplary barrier layer materials suitable for the present invention include titanium, tantalum nitride, tantalum, tungsten nitride, and tungsten formed by ALD or PEALD methods. In each case, the barrier layer has a resistance of less than 300 ohm-cm and preferably.

每一貫穿孔(115)包含一密封層(155)[白色區],其係如下所述般於障壁層(150)與一成核層(160)間直接塗敷於擴散障壁層(150)上。密封層(155)係塗敷於直通孔(115)內之障壁層(150)的內直徑表面及底壁表面上,且包含一具有足夠低電阻之材料,例如,具有少於300ohm-cm之電阻,以於底壁表面容許實質上不受阻礙之電流電過。密封層(155)係於無氧形成,且係特別塗敷於障壁層上,以於塗敷成核層(160)避免障壁層材料氧化,成核層(160)之塗敷如下所述般係具有氧而沉積。障壁層之氧化易增加障壁層之電阻,其因而阻礙電流越過底表面流過障壁層(150)。 Each of the through holes (115) includes a sealing layer (155) [white area] which is directly applied to the diffusion barrier layer (150) between the barrier layer (150) and a nucleation layer (160) as follows. . The sealing layer (155) is applied on the inner diameter surface and the bottom wall surface of the barrier layer (150) in the through hole (115), and comprises a material having a sufficiently low electrical resistance, for example, having less than 300 ohm-cm. The resistor is such that the bottom wall surface allows a substantially unimpeded current to pass. The sealing layer (155) is formed without oxygen and is specially coated on the barrier layer to coat the nucleation layer (160) to prevent oxidation of the barrier layer material. The coating of the nucleation layer (160) is as follows. It is deposited with oxygen. Oxidation of the barrier layer tends to increase the electrical resistance of the barrier layer, which thereby impedes current flow through the barrier layer (150) across the bottom surface.

密封層(155)包含釕(Ru),其係以一足夠層厚度塗覆,以於成核層(160)塗敷期間避免氧與障壁層表面反應。於本發明非限制性例示實施例,一包含Ru之密封層(155)係以範圍從5至10Å(0.5至1.0nm)之層厚度塗敷,其中,密封層之塗敷係於未使障壁層材料曝露於氧而實施。密封層(155)係藉由一PEALD方法,使用包含二環戊釕化合物(諸如,雙(乙基環戊二烯基)釕、雙(環戊二烯基)釕,及雙(五甲基環 戊二烯基)釕之一或多者)之第一釕先質而形成。其後,一包含經電漿激發之氮基團的第二先質被引入加工腔室內,以完成Ru之單一單層,且第二先質係自經電漿激發之N2氣體、氨(NH3),及聯氨,或此等的組合之任一者產生。 The sealing layer (155) comprises ruthenium (Ru) which is applied at a sufficient layer thickness to avoid oxygen from reacting with the surface of the barrier layer during coating of the nucleation layer (160). In a non-limiting exemplary embodiment of the invention, a sealing layer (155) comprising Ru is applied at a layer thickness ranging from 5 to 10 Å (0.5 to 1.0 nm), wherein the coating of the sealing layer is not blocked. The layer material is exposed to oxygen. The sealing layer (155) is formed by a PEALD method using a dicyclopentanyl compound such as bis(ethylcyclopentadienyl)fluorene, bis(cyclopentadienyl)fluorene, and bis(pentamethyl). The first ruthenium of one or more of cyclopentadienyl) is formed. Thereafter, a second precursor comprising a plasma-excited nitrogen group is introduced into the processing chamber to complete a single monolayer of Ru, and the second precursor is self-plasma-excited N 2 gas, ammonia ( NH 3 ), and hydrazine, or any combination of these are produced.

每一貫穿孔(115)包含一成核層(160),其係直接塗敷於直通孔(115)內之障壁層(150)之內直徑表面及底壁表面上之密封層(155)上。成核層(160)包含一具有足夠底電阻之材料,以提供實質上不受阻礙電流流過成核層之底表面,例如,少於300ohm-cm。成核層(160)係置於導電芯材(135)與密封層(155)之間,且係特別被提供以於金屬化期間使導電芯材的材料之結晶生長成核。於本發明非限制性例示實施例,成核層之材料係Ru,其係藉由一熱ALD方法塗敷,包含使碳氧化。成核層係塗敷至50至150Å(5-15nm)範圍的厚度。雖然密封層(155)及成核層(160)皆係Ru層,但是由於不同沉積方法,成核層之厚度係少於密封層之電阻。成核層(160)之較低電阻部份係因為釕先質配位子對氧係比對氮具更高反應性而發生。因此,與具有氮而形成之密封層(155)相比,具有氧而形成之成核層(160)係形成具有降低之雜質及相對應之降低電阻。成核層之雜質降低進一步改良金屬化期間之銅成核。 Each of the through holes (115) includes a nucleation layer (160) which is directly applied to the inner diameter surface of the barrier layer (150) in the through hole (115) and the sealing layer (155) on the surface of the bottom wall. The nucleation layer (160) comprises a material having sufficient bottom resistance to provide a substantially unimpeded current flow through the bottom surface of the nucleation layer, for example, less than 300 ohm-cm. A nucleation layer (160) is interposed between the conductive core material (135) and the sealing layer (155) and is specifically provided to cause crystallization of the material of the conductive core material to nucleate during metallization. In a non-limiting exemplary embodiment of the invention, the material of the nucleation layer is Ru, which is applied by a thermal ALD process, including oxidation of carbon. The nucleation layer is applied to a thickness in the range of 50 to 150 Å (5-15 nm). Although both the sealing layer (155) and the nucleation layer (160) are Ru layers, the thickness of the nucleation layer is less than the resistance of the sealing layer due to different deposition methods. The lower resistance portion of the nucleation layer (160) occurs because the ruthenium proton ligand is more reactive toward oxygen than to nitrogen. Therefore, the nucleation layer (160) formed with oxygen forms a reduced impurity and a corresponding reduced resistance as compared with the sealing layer (155) formed with nitrogen. Impurities in the nucleation layer reduce copper nucleation during further metallization.

雖然Ru係用於形成晶種層及成核層之較佳材料,從不同化學,其它材料候選物係可於未偏離本發明下使用,且此等不受限地包含鈀(Pd)、鉑(Pt)、銠(Rh)、銥(Ir)、銀(Ag)、鈷(Co)、鉬(Mo)、鉻(Cr),及鎢(W)。每一貫穿孔(115)包含 一導電性金屬芯材(135)。於本發明非限制性例示實施例,金屬芯材(135)包含本體銅,且本體銅芯材(135)係藉由使用氧化還原反應之傳統無電沉積方法、物理沉積方法、電子束蒸發方法、電化學電鍍(ECP)方法、化學蒸氣沉積(CVD)方法等形成;於異地實施。另外,諸如鎢、聚矽,及金的其它導電性芯材材料係可於未偏離本發明下而使用。 Although Ru is a preferred material for forming a seed layer and a nucleation layer, other material candidates may be used without departing from the invention from various chemistries, and such unrestricted inclusion of palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), silver (Ag), cobalt (Co), molybdenum (Mo), chromium (Cr), and tungsten (W). Each through hole (115) contains A conductive metal core (135). In a non-limiting exemplary embodiment of the present invention, the metal core material (135) comprises bulk copper, and the bulk copper core material (135) is a conventional electroless deposition method using a redox reaction, a physical deposition method, an electron beam evaporation method, Electrochemical plating (ECP) method, chemical vapor deposition (CVD) method, etc. are formed; In addition, other conductive core materials such as tungsten, polyfluorene, and gold may be used without departing from the invention.

更特別地,障壁層(150)、密封層(155),及成核層(160)之每一者係於相同ALD加工腔室中未使基材(100)自ALD方法腔室移除而形成。再者,ALD加工腔室包含一電漿產生品,且係組配成藉由熱ALD及或藉由PEALD實行材料沉積周期。於障壁層、密封層及成核層之塗敷完成後,基材(100)自ALD加工腔室移除至另一位置,以銅使芯材金屬化。其它芯材金屬化材料亦可使用。 More particularly, each of the barrier layer (150), the sealing layer (155), and the nucleation layer (160) is in the same ALD processing chamber without removing the substrate (100) from the ALD method chamber. form. Furthermore, the ALD processing chamber contains a plasma product and is configured to perform a material deposition cycle by thermal ALD and or by PEALD. After the application of the barrier layer, the sealing layer, and the nucleation layer is completed, the substrate (100) is removed from the ALD processing chamber to another location, and the core material is metallized with copper. Other core metallization materials can also be used.

依據本發明之另一方面,障壁層(150)、密封層(155)及成核層(160)係藉由不同的原子層沉積(ALD)及電漿增強原子層沉積(PEALD)方法塗敷。更特別地,氮化鈦障壁層(150)係藉由第一ALD塗覆順序同時於全部的直通孔貫穿孔上形成,釕密封層(155)係藉由於未使障壁層曝露於氧而實行之第二PEALD塗覆順序同時於全部的直通孔貫穿孔之障壁層(150)上形成,且成核層(160)係藉由包含使碳氧化之第三ALD塗覆順序同時於全部的直通孔貫穿孔之密封層(150)上形成。 According to another aspect of the invention, the barrier layer (150), the sealing layer (155) and the nucleation layer (160) are coated by different atomic layer deposition (ALD) and plasma enhanced atomic layer deposition (PEALD) methods. . More specifically, the titanium nitride barrier layer (150) is formed simultaneously on all of the through-hole through-holes by the first ALD coating sequence, and the germanium sealing layer (155) is implemented by not exposing the barrier layer to oxygen. The second PEALD coating sequence is formed simultaneously on the barrier layer (150) of all of the through vias, and the nucleation layer (160) is simultaneously all of the through pass including the third ALD coating sequence for carbon oxidation. The hole is formed through the sealing layer (150) of the through hole.

8.例示之氣體沉積系統及操作模式 8. Exemplary gas deposition system and mode of operation

依據本發明,包含電絕緣介電層(110)及附接電 路層(105)之基材(100)係藉由已知之傳統電路製造技術製造。於一非限制性例示實施例,介電層(110)包含一電絕緣介電材料,諸如,二氧化矽、氮化矽、氧氮化矽,及/或經碳摻雜之氧化矽(諸如,SiOxCy)等。基材(100)可包含一具有25、50、100、200,或300mm之一的直徑之碟狀晶圓。但是,在未偏離本發明下,介電層(110)可具有其它形狀且自其它材料形成。 In accordance with the present invention, a substrate (100) comprising an electrically insulating dielectric layer (110) and an attached circuit layer (105) is fabricated by known conventional circuit fabrication techniques. In a non-limiting, exemplary embodiment, the dielectric layer (110) comprises an electrically insulating dielectric material such as hafnium oxide, hafnium nitride, hafnium oxynitride, and/or carbon doped antimony oxide (such as , SiO x C y ), and the like. The substrate (100) may comprise a disk wafer having a diameter of one of 25, 50, 100, 200, or 300 mm. However, without departing from the invention, the dielectric layer (110) can have other shapes and be formed from other materials.

現參考圖2,一非限制性之例示氣體沉積系統(200)的側截面圖被示意顯示。系統(200)包含一外腔室壁(205),其圍繞一加工腔室(210)。置於加工腔室(210)內部之一支撐盤(215)提供一支撐表面(220),其係於氣體沉積塗覆周期期間使一基材(100)支撐於其上。支撐盤(215)可進一步包含一電阻加熱元件(222),其係置於支撐表面(220)下,可操作使被支撐於支撐表面(220)上之基材(100)加熱至特別氣體沉積塗覆材料及欲被實行之氣體沉積方法會需要之合需要的反應溫度。 Referring now to Figure 2, a side cross-sectional view of a non-limiting exemplary gas deposition system (200) is shown schematically. The system (200) includes an outer chamber wall (205) that surrounds a processing chamber (210). A support disk (215) disposed within the processing chamber (210) provides a support surface (220) that supports a substrate (100) thereon during a gas deposition coating cycle. The support disk (215) may further comprise a resistive heating element (222) disposed under the support surface (220) operable to heat the substrate (100) supported on the support surface (220) to a particular gas deposit The coating material and the gas deposition method to be carried out will require the desired reaction temperature.

系統(200)包含一載入口(225),其具有一閘閥(230),其可用於使一欲被氣體沉積塗覆之基材(100)通過外腔室壁(205),以使一或多個欲被沉積塗覆之基材(100)停置於支撐表面(220)上。每一基材之裝載及卸下可以手動進行,例如,使用晶圓鉗子等,使欲被沉積塗覆之基材通過口閘閥(230)及載入口(225)。另外,一自動的晶圓裝載及缷下裝置(未示出)可與沉積系統(200)組合使用,且可於一氣體沉積塗覆周期開始時操作而自動地裝載基材,及於氣體沉積 塗覆周期結束時自動地移除基材。特別地,一自動的裝載及卸下系統有利地能使基材於未破壞真空下裝載及缷下,藉此,降低沉積周期之間的泵回時間。 The system (200) includes a loading port (225) having a gate valve (230) operable to pass a substrate (100) to be coated by gas deposition through the outer chamber wall (205) to Or a plurality of substrates (100) to be deposited and deposited are placed on the support surface (220). The loading and unloading of each substrate can be performed manually, for example, using wafer pliers or the like to pass the substrate to be deposited and coated through the port gate valve (230) and the loading port (225). In addition, an automated wafer loading and raking device (not shown) can be used in combination with the deposition system (200) and can be automatically loaded with substrates at the beginning of a gas deposition coating cycle, as well as for gas deposition. The substrate is automatically removed at the end of the coating cycle. In particular, an automated loading and unloading system advantageously enables the substrate to be loaded and raked under unbroken vacuum, thereby reducing pumping time between deposition cycles.

系統(200)包含一非電漿先質入口(235),其直接通過外壁(205),用於使第一及或第二先質於無電漿激發下直接遞送至加工腔室(210)內。系統(200)包含一電漿先質入口(240),其通過一電漿產生器模組(245)之一外壁,使一第一或第二先質遞送至電漿產生器模組(245)內以供電漿激發。遞送至電漿產生器模組(245)內之先質經由一頂孔(250)進入加工腔室(210)。 The system (200) includes a non-plasma precursor inlet (235) that passes directly through the outer wall (205) for direct delivery of the first and second precursors to the processing chamber (210) without plasma excitation. . The system (200) includes a plasma precursor inlet (240) that passes a first or second precursor to the plasma generator module through an outer wall of a plasma generator module (245) (245) ) is excited by the power supply slurry. The precursor delivered to the plasma generator module (245) enters the processing chamber (210) via a top hole (250).

每一先質入口係與一加工氣體遞送模組(255)呈流體連通,且結合加工氣體供應模組(260)。加工氣體供應模組(260)容置以各種加工材料填充之容器,其可包含以液態、固態及氣態之加工材料填充之容器。加工氣體遞送模組(255)包含一或多個起泡器等(未示出),以供產生各種先質供應,例如,自固體或液體先質來源材料萃取;及各種流動控制元件,包含脈衝閥(未示出),用於使先質蒸氣之脈衝遞送至適當先質口(235)及(240),其中,每一先質脈衝具有一合需要的脈衝,其提供一適於欲被實行之特別ALD或PEALD塗覆方法的含量之先質蒸氣。 Each precursor inlet is in fluid communication with a process gas delivery module (255) and incorporates a process gas supply module (260). The process gas supply module (260) houses a container filled with various processing materials, which may include a container filled with a processing material in a liquid, solid, and gaseous state. The process gas delivery module (255) includes one or more bubblers or the like (not shown) for producing various precursor supplies, for example, extraction from solid or liquid precursor sources; and various flow control elements, including a pulse valve (not shown) for delivering a pulse of precursor vapor to the appropriate precursors (235) and (240), wherein each precursor pulse has a desired pulse, which provides a suitable The precursor vapor of the content of the particular ALD or PEALD coating process being practiced.

另外,加工氣體供應模組(260)包含或係連接至一惰性氣體供應,且氣體遞送模組(255)係組配成使惰性氣體遞送至先質口(235)及(240)之每一者。惰性氣體流動係藉由氣體遞送模組(255)調節,其可操作控制使惰性氣體連續 流遞送通過每一先質口,或調節惰性氣體流使間歇惰性氣體流通過先質入口(235)及(240)之任一者或二者遞送至加工腔室(210)內所需之惰性氣體的壓力及流速。於任一情況,惰性氣體流可作為一載體氣體,其係用於使先質蒸氣載送至加工腔室(210)。另外,先質周期之間,僅惰性氣體流經加工腔室以沖刷或沖洗加工腔室(210)。 Additionally, the process gas supply module (260) includes or is coupled to an inert gas supply, and the gas delivery module (255) is configured to deliver inert gas to each of the precursors (235) and (240) By. The inert gas flow is regulated by a gas delivery module (255) that is operable to control the inert gas continuously Flow is delivered through each of the precursors, or the inert gas stream is adjusted to allow the batch of inert gas to pass through any one or both of the precursor inlets (235) and (240) to the desired inertness in the processing chamber (210). Gas pressure and flow rate. In either case, the inert gas stream can be used as a carrier gas for carrying the precursor vapor to the processing chamber (210). Additionally, between the precursor cycles, only inert gas flows through the processing chamber to flush or flush the processing chamber (210).

PEALD系統(200)包含一出口(265),其與一真空泵(270)呈流體流通,且真空泵(270)操作藉由使氣體經由出口(265)自加工腔室移除而使加工腔室(210)抽空。自加工腔室移除之氣體包含一沉積塗覆周期之任何未反應先質材料及或任何反應副產物。另外,一出口模組(275)包含一壓力閘(290)等,其使局部氣體壓力讀數提供至一電子控制器(280)及可藉由電子控制器(280)操作之一真空閥模組(285),以密封一導引至真空泵之導管。另外,設有一或多個溫度感應器(295)以監測局部溫度及使溫度資訊報導給電子控制器(280)。 The PEALD system (200) includes an outlet (265) that is in fluid communication with a vacuum pump (270) and the vacuum pump (270) operates to cause the processing chamber by removing gas from the processing chamber via the outlet (265) ( 210) Take time out. The gas removed from the processing chamber contains any unreacted precursor material and any reaction by-products during the deposition cycle. In addition, an outlet module (275) includes a pressure brake (290) or the like that provides local gas pressure readings to an electronic controller (280) and a vacuum valve module operable by the electronic controller (280) (285) to seal a conduit leading to the vacuum pump. Additionally, one or more temperature sensors (295) are provided to monitor the local temperature and report temperature information to the electronic controller (280).

操作時,系統(200)可用於使薄膜材料塗層塗敷至如上所述之基材(100)。基材(100)係支撐於支撐盤(215)上,且第一電路層(105)係與支撐表面(220)接觸,且介電層(110)向上面對頂孔(250)。經由先質口(235)及頂孔(250)進入腔室(210)之加工氣體膨脹填充腔室(210)且沖擊介電層(110)之一頂表面,且一些加工氣體進入貫穿孔(115)與其表面反應。加工氣體與基材(100)之任何露出表面反應,且於至少包含基材層(110)之頂表面及貫穿孔(115)之內壁表面 (包含藉由第一導電部(120)形成之底表面)之所有露出表面上形成薄膜沉積層。 In operation, the system (200) can be used to apply a coating of film material to the substrate (100) as described above. The substrate (100) is supported on the support disk (215), and the first circuit layer (105) is in contact with the support surface (220), and the dielectric layer (110) faces the top hole (250) upward. The process gas entering the chamber (210) through the precursor (235) and the top hole (250) expands the filling chamber (210) and impacts a top surface of the dielectric layer (110), and some processing gas enters the through hole ( 115) Reacts with its surface. The processing gas reacts with any exposed surface of the substrate (100) and includes at least a top surface of the substrate layer (110) and an inner wall surface of the through hole (115) A thin film deposition layer is formed on all of the exposed surfaces (including the bottom surface formed by the first conductive portion (120)).

如所知,每一ALD塗覆周期係以二個自限制反應為基礎。一第一先質與一基材之露出表面間之第一自限制反應於基材之露出表面上產生固體材料之第一半單層,且一第二先質與基材之露出表面間之第二自限制反應於基材之露出表面上產生固體材料之第二半單層。更特別地,與露出表面之二個別且獨立之自限制先質反應被實施使一合需要的材料之單一單層沉積於露出表面上。再者,由於此反應之自限制性質,單一材料單層之厚度係實質上被預定且約等於材料之單一原子層,即,每一單層具有0.5至1.5Å之大約厚度,其係依至少包含溫度、先質蒸氣壓力及體積、加工腔室內部之氣體壓力,及曝露時間之各種生長條件而定。因為於大部份應力,需要至少5個單層塗敷以提供一最小功能性材料塗覆厚度,此二自限制反應係重複5次,以使5個欲被沉積之塗覆材料單層被沉積。但是,更普遍地,100至200個單層且於某些情況最高達約1000個單層之ALD塗覆厚度被用於以合意之表面塗層塗覆基材,以便利用表面塗層提供之材料性質。 As is known, each ALD coating cycle is based on two self-limiting reactions. a first self-limiting reaction between a first precursor and an exposed surface of a substrate produces a first semi-monolayer of solid material on the exposed surface of the substrate, and a second precursor and the exposed surface of the substrate A second self-limiting reaction produces a second semi-monolayer of solid material on the exposed surface of the substrate. More specifically, a separate and independent self-limiting precursor reaction with the exposed surface is performed to deposit a single monolayer of the desired material onto the exposed surface. Furthermore, due to the self-limiting nature of the reaction, the thickness of a single layer of a single material is substantially predetermined and approximately equal to a single atomic layer of the material, i.e., each single layer has an approximate thickness of from 0.5 to 1.5 Å, which is at least It includes temperature, precursor vapor pressure and volume, gas pressure inside the processing chamber, and various growth conditions for exposure time. Because for most stresses, at least 5 single layer coatings are required to provide a minimum functional material coating thickness, and the two self-limiting reactions are repeated 5 times to allow 5 coating layers to be deposited to be single layered. Deposition. More generally, however, an ALD coating thickness of from 100 to 200 monolayers and in some cases up to about 1000 monolayers is used to coat the substrate with a desired surface coating for use with a surface coating. Material properties.

系統(200)係組配成用於以貯存於電子控制器(280)內且可由使用者選擇或程式化之操作模式選單為基礎之自動塗覆周期操作。於一非限制性範例,使用者可輸入或選擇一加工型式(例如,ALD、PEALD),且選擇化學作用,例如,第一先質、第二先質、反應溫度,及合意之單 層數。另外,惰性氣體流及模組參數可與曝露時間為使用者可選擇,對於長的曝露時間,可包含於沉積周期期間關閉真空出口閥(285)。一旦塗覆周期參數被選定,系統(200)係實施選定之塗覆順序,其係藉由自動塗敷單層至合意之表面塗覆完全形成至合意單層數量為止。其後,使用者可移除基材,安裝另一基材,且對於一新的基材重複相同塗覆周期,或可實施其它塗覆周期以使另外沉積塗覆層增加至相同基材。 The system (200) is configured for automatic coating cycle operation based on an operating mode menu stored in the electronic controller (280) and selectable or programmable by the user. In a non-limiting example, a user may enter or select a processing pattern (eg, ALD, PEALD) and select a chemical action, such as a first precursor, a second precursor, a reaction temperature, and a desired list The number of layers. Additionally, the inert gas flow and module parameters can be selected by the user for exposure time, and for long exposure times, the vacuum outlet valve (285) can be closed during the deposition cycle. Once the coating cycle parameters are selected, the system (200) performs the selected coating sequence by automatically applying a single layer to the desired surface coating to fully form to the desired number of monolayers. Thereafter, the user can remove the substrate, install another substrate, and repeat the same coating cycle for a new substrate, or other coating cycles can be implemented to add additional deposition coatings to the same substrate.

另外,使用者可輸入一系列之塗覆周期,其中,第一材料塗覆於露出表面上至合意之厚度或單層周期數,且其後,第二材料塗覆於露出表面上,於第一材料層上,至合意之厚度或單層周期數,如此等等,以塗敷另外之材料塗層。於此例示之塗敷,使用者輸入二或更多個塗覆程式,且每一程式係對於此二或更多塗覆材料之特一者特定一不同加工型式(若有)、一不同化學或第一及第二先質之組合(若有)、一不同反應溫度(若有),及一不同之合意的厚度或單層數量(若有)。一旦二或更多塗覆周期之塗覆周期參數被選定及輸入,系統(200)自動地實施第一塗覆序列至第一表面塗層完全形成至合意之單層數量為止。其後,系統(200)使用不同參數自動實施第二塗覆序列,至第二表面塗層完全形成至合意的單層數量為止。其後,系統(200)使用不同參數自動實施第三塗覆序列,至第三表面塗層完全形成至合意的單層數量為止。 In addition, the user can input a series of coating cycles, wherein the first material is applied to the exposed surface to a desired thickness or number of single layer cycles, and thereafter, the second material is applied to the exposed surface, On a layer of material, to a desired thickness or number of single layer cycles, and so on, to coat a further coating of material. For the exemplified coating, the user inputs two or more coating programs, and each program specifies a different processing pattern (if any), a different chemistry for the one or more coating materials. Or a combination of the first and second precursors (if any), a different reaction temperature (if any), and a different desired thickness or number of monolayers, if any. Once the coating cycle parameters for two or more coating cycles are selected and input, the system (200) automatically implements the first coating sequence until the first surface coating is fully formed to the desired number of monolayers. Thereafter, the system (200) automatically implements the second coating sequence using different parameters until the second surface coating is fully formed to the desired number of monolayers. Thereafter, the system (200) automatically implements the third coating sequence using different parameters until the third surface coating is fully formed to the desired number of monolayers.

其後,使用者可移除基材,安裝另外基材,及使 其對於一新基材重複二或更多個塗覆周期。 Thereafter, the user can remove the substrate, install additional substrates, and It repeats two or more coating cycles for a new substrate.

可用於依據本發明使三或更多個材料塗覆層塗敷於貫穿孔之內表面的一例示氣體沉積系統(200)係描述於相關之已公開的美國專利申請案2010/018325A1,其名稱係電漿原子層沉積系統及方法,於2009年12月28日由Becker等人申請,此案在此被完整併入以供參考。 An exemplary gas deposition system (200) that can be used to apply three or more material coating layers to the inner surface of a through-hole according to the present invention is described in the related published U.S. Patent Application Serial No. 2010/018, 325, the name of which is incorporated herein by reference. A plasma atomic layer deposition system and method, filed on December 28, 2009 by Becker et al., the entire disclosure of which is hereby incorporated by reference.

9.用於形成障壁層之例示塗覆方法 9. An exemplary coating method for forming a barrier layer

於本發明之一非限制性例示實施例,貫穿孔內表面係以一包含氮化鈦(TiN)之障壁層(150)塗覆。障壁層(150)係如下般使用上述系統(200)塗敷至範圍從20至200Å之層厚度。 In one non-limiting exemplary embodiment of the invention, the inner surface of the through-hole is coated with a barrier layer (150) comprising titanium nitride (TiN). The barrier layer (150) is applied to the thickness of the layer ranging from 20 to 200 Å using the system (200) described below.

-基材(100)係經由閘閥(230)及入口(225)嵌入加工腔室(210)內,且置於支撐表面(220)上,且介電層(110)之一頂表面面向頂孔(250),即,貫穿孔之開口端面向頂孔(250)。於本範例,基材層(100)係一100、200或300mm之晶圓,且每一晶圓係每次加工一個。但是,可於未偏離本發明下,多數個基材(100)可以批式加工。 - the substrate (100) is embedded in the processing chamber (210) via the gate valve (230) and the inlet (225), and placed on the support surface (220), and the top surface of one of the dielectric layers (110) faces the top hole (250), that is, the open end of the through hole faces the top hole (250). In this example, the substrate layer (100) is a 100, 200 or 300 mm wafer, and each wafer is processed one at a time. However, a plurality of substrates (100) can be processed in batches without departing from the invention.

-閘閥(230)係自動地或由使用者關閉。系統(200)操作使基材(100)加熱至一合意的反應溫度,且真空泵(270)連續操作以使腔室抽空達到一合意的反應壓力。於本範例,用於TiN障壁層沉積之較佳反應或基材溫度係270℃與400℃之間,且合意的反應壓力係1與100μtorr(1.33-133.32mPa)之間。但是,於未偏離本發明下,用於TiN之其它反應溫度TiN(例如,範圍從200-500℃)及其它反應壓力(例如,範圍 從1至10,000μtorr)可使用。 - The gate valve (230) is automatically or closed by the user. The system (200) operates to heat the substrate (100) to a desired reaction temperature, and the vacuum pump (270) operates continuously to evacuate the chamber to a desired reaction pressure. In this example, the preferred reaction or substrate temperature for TiN barrier layer deposition is between 270 ° C and 400 ° C, and the desired reaction pressure is between 1 and 100 μtorr (1.33-133.32 mPa). However, other reaction temperatures TiN (for example, ranging from 200 to 500 ° C) and other reaction pressures (for example, ranges) for TiN are not deviated from the present invention. It can be used from 1 to 10,000 μtorr).

-腔室係藉由經由先質入口(235)及(240)之一者或二者或經由另外孔口(未示出)送至腔室內之連續或間歇之惰性氣體流而沖洗,以移除水分及其它污染物。 - the chamber is flushed by a continuous or intermittent flow of inert gas delivered to the chamber via one or both of the precursor inlets (235) and (240) or via another orifice (not shown) In addition to moisture and other pollutants.

-第一熱ALD塗覆周期被起始以使TiN障壁層塗覆至基材(100)之露出表面上。 A first thermal ALD coating cycle is initiated to apply a TiN barrier layer to the exposed surface of the substrate (100).

-包含四(二甲基醯胺基)鈦(TDMAT)之第一金屬有機先質係經由第一先質入口(235)引至加工腔室內。第一先質係以藉由使一脈衝閥(未示出)操作一段脈衝時間而產生之一蒸氣脈衝引入,其中,脈衝時間係與蒸氣脈衝內所含之第一先質蒸氣的體積呈比例。第一先質脈衝可與從加工氣體遞送模組(255)流至第一先質入口(235)之一連續惰性氣體流混合。 - a first metal organic precursor comprising tetrakis(dimethylammonium)titanium (TDMAT) is introduced into the processing chamber via a first precursor inlet (235). The first precursor is introduced by generating a vapor pulse by operating a pulse valve (not shown) for a pulse time, wherein the pulse time is proportional to the volume of the first precursor vapor contained in the vapor pulse. . The first precursor pulse can be mixed with a continuous stream of inert gas flowing from the process gas delivery module (255) to the first precursor inlet (235).

-(1)第一先質與基材(100)之露出表面反應一段等於預定曝露時間的時間。曝露時間可為系統設計之函數。例如,先質脈衝對基材之曝露時間可實質上等於直空泵(270)汲取等於加工腔室(210)之總體積加上經由出口(265)導引至加工腔室內之氣體導管的另外體積的氣體體積所花的時間。於此情況,曝露時間可於10-2000msec之等級。對於更長曝露時間,例如,最高達約60秒,真空閥(285)可被關閉以避免先質離開加工腔室,持續一合意之曝露時間。 - (1) The first precursor reacts with the exposed surface of the substrate (100) for a period of time equal to the predetermined exposure time. Exposure time can be a function of system design. For example, the exposure time of the precursor pulse to the substrate can be substantially equal to the total volume of the straight air pump (270) being equal to the total volume of the processing chamber (210) plus the gas conduit that is directed to the processing chamber via the outlet (265). The time it takes for the volume of gas to be volume. In this case, the exposure time can be on the order of 10-2000 msec. For longer exposure times, for example, up to about 60 seconds, the vacuum valve (285) can be closed to prevent the precursor from leaving the processing chamber for a desired exposure time.

-較佳地,每一先質脈衝時間(脈衝閥打開時間)被最佳化,以於單一脈衝提供足夠先質蒸氣體積,以使欲被塗覆之基材的露出表面實質上飽和或與其完全反應。換言之, 每一先質脈衝包含足夠先質,以於先質脈衝通過加工腔室(210)所花之時間內完成上述之與露出表面的自限制反應。 Preferably, each precursor pulse time (pulse valve opening time) is optimized to provide a sufficient precursor vapor volume in a single pulse to substantially saturate or expose the exposed surface of the substrate to be coated Complete reaction. In other words, Each precursor pulse contains sufficient precursor to complete the self-limiting reaction with the exposed surface during the time taken by the precursor pulse through the processing chamber (210).

-(2)第一沖洗周期被實施,其中,加工腔室(210)被沖洗以移除所有微量的第一先質。此可包含簡單地使真空泵及連續惰氣流沖刷腔室,以移除等於加工腔室(210)及導引至腔室之流動導管之體積的2-5倍之氣體體積。 - (2) A first flush cycle is performed in which the processing chamber (210) is flushed to remove all traces of the first precursor. This may include simply flushing the vacuum pump and continuous inert gas flow to remove a gas volume equal to 2-5 times the volume of the processing chamber (210) and the flow conduit leading to the chamber.

-(3)包含氮之第二先質經由第一先質入口(235)引至加工腔室內。諸如氨(NH3)之第二先質係藉由使一脈衝閥(未示出)操作一段脈衝時間而產生之一蒸氣脈衝引入,其中,脈衝時間係與蒸氣脈衝內所含之第二先質蒸氣的體積呈比例。第二先質脈衝可與從加工氣體遞送模組流至第一先質入口(235)之一連續惰性氣體流混合。 - (3) The second precursor comprising nitrogen is introduced into the processing chamber via the first precursor inlet (235). The second precursor system such as ammonia (NH 3) by the pair of the pulsing valve (not shown) is operated for a time pulse is generated one pulse is introduced vapor, wherein the vapor system and the pulse time of the second pulse contained in the first The volume of the mass vapor is proportional. The second precursor pulse can be mixed with a continuous inert gas stream flowing from the process gas delivery module to the first precursor inlet (235).

-第二先質能與基材(100)之露出表面反應一段等於預定曝露時間的時間。 - the second precursor can react with the exposed surface of the substrate (100) for a period of time equal to the predetermined exposure time.

-(4)第二沖洗周期被實施,其中,加工腔室(210)被沖洗以移除所有微量之第二先質。 - (4) A second flush cycle is performed in which the processing chamber (210) is flushed to remove all traces of the second precursor.

-上述4步驟周期係可用以產生障壁層(150)之單一單層的一熱ALD沉積方法的一範例,其中,障壁層包含TiN。此4步驟方法被重複以塗敷另外之單層,至達到一合意的障壁層厚度為止。 The above 4-step cycle is an example of a thermal ALD deposition process that can be used to create a single monolayer of barrier layers (150), wherein the barrier layer comprises TiN. This 4-step process is repeated to apply another monolayer until a desired barrier layer thickness is achieved.

於本發明之塗敷障壁層(150)之另一實施例,TiN可藉由PEALD塗敷。雖然相同之4步驟方法被實施,第二先質係以電漿激發之氮基團替代,其係經由頂孔(250)從電漿產生器(245)遞送至加工腔室(210)內。電漿基團係自經由第 二先質入口(240)從加工氣體遞送模組(255)遞送至電漿產生器(245)內之第二先質衍生。特別地,第二先質可包含氮氣(N2)、氮及氫氣之混合物或氨之任一者。於所有其它方面,上述用於形成障壁層之方法係實質上相同。 In another embodiment of the coated barrier layer (150) of the present invention, TiN can be applied by PEALD. While the same 4-step process is implemented, the second precursor is replaced with a plasma-excited nitrogen group that is delivered from the plasma generator (245) to the processing chamber (210) via the top hole (250). The plasma group is derived from a second precursor that is delivered from the process gas delivery module (255) to the plasma generator (245) via the second precursor inlet (240). In particular, the second precursor may comprise nitrogen (N 2 ), a mixture of nitrogen and hydrogen, or ammonia. In all other respects, the above described methods for forming the barrier layer are substantially identical.

於上述範例之任一者,先質係預熱至約75℃達成用於衝脈之合意蒸氣壓。最小障壁層厚度(約20Å)係藉由實施約34-40個單層塗敷而達成,其中,每一單層具有約0.5至0.6Å之厚度。最大障壁層厚度(約200Å)係藉由實施約333-400個單層塗敷而達成。 In any of the above examples, the precursor is preheated to about 75 ° C to achieve a desired vapor pressure for the pulse. The minimum barrier layer thickness (about 20 Å) is achieved by performing about 34-40 single layer coatings, wherein each single layer has a thickness of about 0.5 to 0.6 Å. The maximum barrier layer thickness (about 200 Å) is achieved by performing about 333-400 single layer coatings.

10.用於形成密封層之例示塗覆方法(無氧) 10. An exemplary coating method for forming a sealing layer (oxygen free)

於本發明之一非限制性例示實施例,貫穿孔內表面係以一包含釕(Ru)之密封層(155)塗覆。密封層(155)係如下所述般使用上述系統(200)塗敷至範圍從5至10Å之層厚度。基材溫度可改變成範圍250至350℃之溫度以塗敷密封層(155)。但是,於一較佳方法,約300℃之相同沉積溫度被用以沉積障壁層、密封層,及成核層。 In one non-limiting, exemplary embodiment of the invention, the inner surface of the through-hole is coated with a seal layer (155) comprising ruthenium (Ru). The sealing layer (155) is applied to the thickness of the layer ranging from 5 to 10 Å using the above system (200) as described below. The substrate temperature can be changed to a temperature ranging from 250 to 350 ° C to apply a sealing layer (155). However, in a preferred method, the same deposition temperature of about 300 ° C is used to deposit the barrier layer, the sealing layer, and the nucleation layer.

-(1)包含二環戊釕化合物之第一先質係經由第一先質入口(235)引至加工腔室內。二環戊釕化合物不受限地包含雙(乙基環戊二烯基)釕、雙(環戊二烯基)釕,及雙(五甲基環戊二烯基)釕。特別地,雙(乙基環戊二烯基)釕之化學化合物=(EtCp)2Ru=Ru(C5H4C2H5)2,雙(環戊二烯基)釕=Cp2Ru=Ru(C5H5)2,且雙(五甲基環戊二烯基)釕=(Me5Cp)2Ru=Ru(C5(CH3)5)2 - (1) The first precursor comprising the dicyclopentanyl compound is introduced into the processing chamber via the first precursor inlet (235). The dicyclopentanyl compound does not include, without limitation, bis(ethylcyclopentadienyl)fluorene, bis(cyclopentadienyl)fluorene, and bis(pentamethylcyclopentadienyl)fluorene. In particular, the chemical compound of bis(ethylcyclopentadienyl)fluorene = (EtCp)2Ru=Ru(C5H4C2H5)2, bis(cyclopentadienyl)fluorene=Cp2Ru=Ru(C5H5)2, and double ( Pentamethylcyclopentadienyl) 钌=(Me5Cp)2Ru=Ru(C5(CH3)5)2

-第一先質係以藉由使一脈衝閥(未示出)操作一段脈衝 時間而產生之一蒸氣脈衝引入,其中,脈衝時間係與蒸氣脈衝內所含之第一先質蒸氣的體積呈比例。第一先質脈衝可與從加工氣體遞送模組流至第一先質入口(235)之一連續惰性氣體流混合。二環戊釕化合物脈衝與障壁層(150)之表面反應形成密封層(155)之第一半單層。 - a first precursor to operate a pulse by operating a pulse valve (not shown) A vapor pulse is introduced in time, wherein the pulse time is proportional to the volume of the first precursor vapor contained within the vapor pulse. The first precursor pulse can be mixed with a continuous inert gas stream flowing from the process gas delivery module to the first precursor inlet (235). The dicyclopentanyl compound pulse reacts with the surface of the barrier layer (150) to form a first semi-monolayer of the sealing layer (155).

-(2)第一沖洗周期被實施,其中,加工腔室(210)被沖洗以移除所有微量之第一先質。 - (2) A first flush cycle is implemented in which the processing chamber (210) is flushed to remove all traces of the first precursor.

-(3)包含氮及氫氣體之混合物的第二先質經由第二先質入口(240)流入電漿產生器(245)。電漿產生器被點燃激發氮及氫,其等與基材之露出表面反應,完成Ru之第一單層形成。氫氣被引入分解藉由第一先質沉積於TiN障壁層上之第一Ru半單層,但是,於未偏離本發明下,本塗覆步驟可於無氫實施。完成之單層具有約0.5Å之厚度,且係於無氧形成,以避免障壁層(150)氧化。第二先質可包含N2氣體、氨,及聯氨之任一者,此等係藉由一電漿來源激發。 - (3) A second precursor comprising a mixture of nitrogen and hydrogen gas flows into the plasma generator (245) via the second precursor inlet (240). The plasma generator is ignited to excite nitrogen and hydrogen, which react with the exposed surface of the substrate to complete the formation of the first monolayer of Ru. Hydrogen is introduced into the first Ru semi-monolayer deposited on the TiN barrier layer by the first precursor, but the coating step can be carried out without hydrogen without departing from the invention. The finished single layer has a thickness of about 0.5 Å and is formed without oxygen to avoid oxidation of the barrier layer (150). The second precursor may comprise any of N 2 gas, ammonia, and hydrazine, which are excited by a plasma source.

-(4)第二沖洗周期被實施,其中,加工腔室(210)被沖洗以移除所有微量之第二先質。 - (4) A second flush cycle is performed in which the processing chamber (210) is flushed to remove all traces of the second precursor.

上述之4步驟周期係可用於產生密封層(155)之單一單層的PEALD沉積方法之一範例,其中,密封層包含Ru,其係於無氧下藉由二環戊釕化合物形成。此4步驟方法被重複塗敷另外之Ru單層,至達成合意的密封層厚度為止。最小密封層厚度(約5Å)係藉由實施紡10個單層塗敷而達成,其中,每一單層具有約0.5Å之厚度。最大密封層厚度(約10Å)係藉由實施約20個單層塗敷而達成。一較厚之密封層塗敷 可於未偏離本發明下使用。 The 4-step cycle described above is an example of a single single layer PEALD deposition process that can be used to create a sealing layer (155) wherein the sealing layer comprises Ru which is formed by a dicyclopentanyl compound without oxygen. This 4-step process is repeated with additional Ru monolayers until a desired seal layer thickness is achieved. The minimum seal layer thickness (about 5 Å) is achieved by performing 10 single layer coatings, wherein each single layer has a thickness of about 0.5 Å. The maximum seal layer thickness (about 10 Å) is achieved by performing about 20 single layer coatings. a thicker seal coating It can be used without departing from the invention.

11.用於形成成核層之例示塗覆方法(具有氧) 11. An exemplary coating method for forming a nucleation layer (with oxygen)

於本發明之一非限制性例示實施例,已以障壁層(150)及密封層(155)塗覆之貫穿孔內表面係以一包含釕(Ru)成核層(160)塗覆。成核層(160)係如下般使用上述之系統(200)以範圍從50至150Å之層厚度塗敷於Ru密封層(155)上。基材溫度可改變成範圍250至350℃之溫度,以塗敷成核層(160)。但是,一較佳方法係以維持於相同溫度(例如,300℃)之基材沉積障壁層、密封層及成核層。 In one non-limiting exemplary embodiment of the invention, the inner surface of the through-hole that has been coated with the barrier layer (150) and the sealing layer (155) is coated with a ruthenium-containing layer (160). The nucleation layer (160) is applied to the Ru sealing layer (155) in a thickness ranging from 50 to 150 Å using the system (200) described above. The substrate temperature can be varied to a temperature in the range of 250 to 350 ° C to coat the nucleation layer (160). However, a preferred method is to deposit a barrier layer, a sealing layer, and a nucleation layer on a substrate maintained at the same temperature (e.g., 300 ° C).

-(1)包含二環戊釕化合物之第一先質經由第一先質入口(235)引入加工腔室內。第一先質係以藉由使一脈衝閥(未示出)操作一段脈衝時間而產生之一蒸氣脈衝引入,其中,脈衝時間係與蒸氣脈衝內所含之第一先質蒸氣的體積成比例。第一先質脈衝可與從加工氣體遞送模組流至第一先質入口(235)之一連續惰性氣體流混合。二環戊釕化合物脈衝與密封層(155)之表面反應,形成成核層(160)之Ru的第一半單層。 - (1) The first precursor comprising the dicyclopentanyl compound is introduced into the processing chamber via the first precursor inlet (235). The first precursor is introduced by generating a vapor pulse by operating a pulse valve (not shown) for a pulse time, wherein the pulse time is proportional to the volume of the first precursor vapor contained in the vapor pulse. . The first precursor pulse can be mixed with a continuous inert gas stream flowing from the process gas delivery module to the first precursor inlet (235). The dicyclopentanyl compound pulse reacts with the surface of the sealing layer (155) to form the first semi-monolayer of Ru of the nucleation layer (160).

-(2)第一沖洗周期被實施,其中,加工腔室(210)被沖洗以移除所有微量之第一先質。 - (2) A first flush cycle is implemented in which the processing chamber (210) is flushed to remove all traces of the first precursor.

-(3)包含氧之第二先質係經由第一先質入口(235)引至加工腔室內。第二先質係以藉由使一脈衝閥(未示出)操作一段脈衝時間而產生之一蒸氣脈衝引入,其中,脈衝時間係與蒸氣脈衝內所含之第二先質蒸氣的體積成比例。第二先質脈衝可與從加工氣體遞送模組流至第一先質入口(235)之 一連續惰性氣體流混合。氧與藉由第一先質形成之第一單層的表面反應,完成與氧形成之Ru的第一半單層之形成。氧先質可於未使TiN障壁層氧化而使用,因為密封層(155)避免氧與障壁層(150)反應。再者,於導電金屬芯材(135)金屬化期間,於形成支撐銅結晶成核及與成核層(160)黏著之成核層期間,氧使碳氧化。此反應之特徵如下: - (3) A second precursor comprising oxygen is introduced into the processing chamber via a first precursor inlet (235). The second precursor is introduced by generating a vapor pulse by operating a pulse valve (not shown) for a pulse time, wherein the pulse time is proportional to the volume of the second precursor vapor contained in the vapor pulse. . The second precursor pulse can flow from the process gas delivery module to the first precursor inlet (235) A continuous stream of inert gas is mixed. Oxygen reacts with the surface of the first monolayer formed by the first precursor to complete the formation of the first semi-monolayer of Ru formed with oxygen. The oxygen precursor can be used without oxidizing the TiN barrier layer because the sealing layer (155) prevents oxygen from reacting with the barrier layer (150). Further, during metallization of the conductive metal core (135), oxygen oxidizes the carbon during formation of a nucleation layer that supports copper crystal nucleation and adhesion to the nucleation layer (160). The characteristics of this reaction are as follows:

.O2脈衝:O2->O(吸附) . O2 pulse: O2->O (adsorption)

.Ru先質脈衝:Ru(C5H4C2H5)2(吸附)+O(吸附)->Ru+CO2+H2O . Ru precursor pulse: Ru(C5H4C2H5)2(adsorption)+O(adsorption)->Ru+CO2+H2O

-(4)第二沖洗周期被實施,其中,加工腔室(210)被沖洗以移除所有微量之第二先質。 - (4) A second flush cycle is performed in which the processing chamber (210) is flushed to remove all traces of the second precursor.

上述之4步驟周期係可用於產生Ru成核層(160)之單一單層的一熱ALD沉積方法之一範例,其中,成核層包含Ru,其係具有氧而形成。此4步驟之方法被重複以塗敷另外之單層,至達成合意的成核層厚度為止。最小成核層厚度(約50Å)係藉由實施約100個單層塗敷而達成,其中,每一單層具有約0.5Å之厚度。最大成核層厚度(約150Å)係藉由實施約300個單層塗敷而達成。較厚之成核層塗敷可於未偏離本發明下使用。 The 4-step cycle described above is an example of a thermal ALD deposition process that can be used to produce a single monolayer of Ru nucleation layer (160), wherein the nucleation layer comprises Ru, which is formed with oxygen. This 4-step process is repeated to apply additional monolayers until a desired nucleation layer thickness is achieved. The minimum nucleation layer thickness (about 50 Å) is achieved by performing about 100 single layer coatings, wherein each single layer has a thickness of about 0.5 Å. The maximum nucleation layer thickness (about 150 Å) is achieved by performing about 300 single layer coatings. The thicker nucleation layer coating can be used without departing from the invention.

更普遍地,含有金屬之二環戊釕化合物(諸如,雙(乙基環戊二烯基)釕、雙(環戊二烯基)釕,及雙(五甲基環戊二烯基)釕)對於密封層及成核層之形成係較佳。但是,其它釕先質可使用,其包含含有釕及至少一吡咯基配位子之吡咯基釕先質。此等材料可自甲基環戊二烯基吡咯基釕 ((MeCp)(Py)Ru)衍生。 More generally, metal-containing dicyclopentanyl compounds such as bis(ethylcyclopentadienyl)fluorene, bis(cyclopentadienyl)fluorene, and bis(pentamethylcyclopentadienyl)fluorene The formation of the sealing layer and the nucleation layer is preferred. However, other ruthenium precursors can be used which comprise pyrrole ruthenium precursors containing ruthenium and at least one pyrrolyl ligand. Methylcyclopentadienylpyrrolyl hydrazone ((MeCp)(Py)Ru) derived.

亦由熟習此項技藝者所瞭解,雖然本發明已以較佳實施例作如上說明,但不限於此。上述本發明之各種特徵及方面可個別或結合使用。再者,雖然本發明係以其於一特殊環境及用於特別應用(例如,使沉積塗層塗敷至直通孔貫穿孔之內表面)之實施的情況下而作說明,但熟習此項技藝者會瞭解其使用性不限於此,且本發明可有利地用於欲以改良IC性能之方式形成沉積層之任何數量的環境及實施。因此,如下所示之申請專利範圍需以此處揭露之本發明的完整寬度及精神作闡釋。 It is also apparent to those skilled in the art that although the invention has been described above in terms of preferred embodiments, it is not limited thereto. The various features and aspects of the invention described above may be used individually or in combination. Furthermore, although the present invention is described in the context of its implementation in a particular environment and for special applications (eg, application of a deposition coating to the inner surface of a through-hole through-hole), it is familiar to the art. It will be appreciated that its usability is not limited in this respect, and that the present invention can be advantageously utilized in any number of environments and implementations that are intended to form a deposited layer in a manner that improves IC performance. Therefore, the scope of the invention as set forth below is to be construed as the full scope and spirit of the invention disclosed herein.

100‧‧‧基材 100‧‧‧Substrate

105‧‧‧第一電路層 105‧‧‧First circuit layer

110‧‧‧電絕緣介電層 110‧‧‧Electrically insulating dielectric layer

115‧‧‧直通孔貫穿孔 115‧‧‧through hole through hole

120‧‧‧導電部 120‧‧‧Electrical Department

125‧‧‧第二半導體電路層 125‧‧‧Second semiconductor circuit layer

130‧‧‧第二導電部 130‧‧‧Second Conductive Department

135‧‧‧導電芯材 135‧‧‧ Conductive core

150‧‧‧擴散障壁層 150‧‧‧Diffusion barrier

155‧‧‧密封層 155‧‧‧ Sealing layer

160‧‧‧成核層 160‧‧‧ nucleation layer

Claims (29)

一種電子裝置,包含藉由一內直徑表面及一底壁表面形成之直通貫穿孔,其中,所有表面係以如下塗覆:-一氮化鈦障壁層,其具有範圍從20至200Å之厚度;-一釕密封層,其形成於該氮化鈦障壁層上,其中,該密封層係於未使該障壁層曝露於氧而形成;及-一釕成核層,其係形成於該密封層上,其中,該成核層係具有氧而形成。 An electronic device comprising a through-through hole formed by an inner diameter surface and a bottom wall surface, wherein all surfaces are coated as follows: a titanium nitride barrier layer having a thickness ranging from 20 to 200 Å; a sealing layer formed on the titanium nitride barrier layer, wherein the sealing layer is formed without exposing the barrier layer to oxygen; and a germanium nucleation layer is formed on the sealing layer Above, wherein the nucleation layer is formed by oxygen. 如請求項1之電子裝置,其中,該釕密封層具有範圍從5至10Å之厚度。 The electronic device of claim 1, wherein the ruthenium sealing layer has a thickness ranging from 5 to 10 Å. 如請求項2之電子裝置,其中,該釕成核層具有範圍從50至150Å之厚度。 The electronic device of claim 2, wherein the enamel layer has a thickness ranging from 50 to 150 Å. 如請求項3之電子裝置,其中,釕成核層之電阻係少於該釕成核層之電阻。 The electronic device of claim 3, wherein the 钌 nucleation layer has a resistance less than the resistance of the 钌 nucleation layer. 如請求項4之電子裝置,其中,該直通貫穿孔係以銅藉由使該銅塗敷於該釕成核層上而金屬化。 The electronic device of claim 4, wherein the through-via is metallized with copper by applying the copper to the tantalum nucleation layer. 一種積體電裝置總成,包含:- 一介電基材層,其包含電絕緣材料;- 一電路層,其係支撐於該介電基材層上,包含一以電裝置及互連圖案圖案化之半導體材料層;- 一導電層,其係置於該介電層與該電路層之間,至少包含與該等互連圖案之至少一者呈電連通之導電層部; - 一直通孔貫穿孔,其完全通過該介電基材層至該導電層,包含一以該介電基材層為界限之內直徑表面,及一以該等導電層部之一者為界限之底部表面;- 一障壁層,其形成於該內直徑表面及該底壁表面之每一者上,包含一具有少於300μohm-cm之電阻的第一材料,其中,該障壁層係以足夠層厚度形成,以避免貫穿孔金屬化材料經其擴散;- 一密封層,其形成於該內直徑表面及該底壁表面之每一者上之該障壁層上,包含一具有少於300μohm-cm之電阻的第二材料,其中,該密封層之形成係於未使該第一材料層曝露於氧而實行;-一成核層,其形成於該內直徑表面及該底壁表面之每一者上之該密封層上,包含該第二材料,其中,該成核層之形成包含使碳氧化。 An integrated electrical device assembly comprising: - a dielectric substrate layer comprising an electrically insulating material; - a circuit layer supported on the dielectric substrate layer, comprising an electrical device and an interconnect pattern a patterned semiconductor material layer; - a conductive layer disposed between the dielectric layer and the circuit layer, comprising at least a conductive layer portion in electrical communication with at least one of the interconnect patterns; a through-hole through-hole that completely passes through the dielectric substrate layer to the conductive layer, including an inner diameter surface bounded by the dielectric substrate layer, and one of the conductive layer portions a bottom surface; a barrier layer formed on each of the inner diameter surface and the bottom wall surface, comprising a first material having an electrical resistance of less than 300 μ ohm-cm, wherein the barrier layer is sufficient a layer thickness is formed to prevent diffusion of the through-hole metallization material therethrough; - a sealing layer formed on the inner diameter surface and the barrier layer layer on each of the bottom wall surfaces, comprising one having less than 300 μohm- a second material of the resistance of cm, wherein the formation of the sealing layer is performed without exposing the first material layer to oxygen; a nucleation layer formed on the inner diameter surface and the bottom wall surface The second sealing layer comprises a second material, wherein the nucleating layer is formed to oxidize carbon. 如請求項6之半導體基材,其中,該第一材料包含氮化鈦、鈦、氮化鉭、鉭、氮化鎢、氮化鈷,及鎢之任一者。 The semiconductor substrate of claim 6, wherein the first material comprises any one of titanium nitride, titanium, tantalum nitride, tantalum, tungsten nitride, cobalt nitride, and tungsten. 如請求項7之半導體基材,其中,該障壁層厚度係於19與201Å之間。 The semiconductor substrate of claim 7, wherein the barrier layer has a thickness between 19 and 201 Å. 如請求項7之半導體基材,其中,該第二材料包含釕。 The semiconductor substrate of claim 7, wherein the second material comprises ruthenium. 如請求項9之半導體基材,其中,該密封層厚度係於4與11Å之間,且該成核層厚度係於49Å與151Å之間。 The semiconductor substrate of claim 9, wherein the sealing layer has a thickness between 4 and 11 Å, and the nucleation layer has a thickness between 49 Å and 151 Å. 如請求項9之半導體基材,其中,該密封層沉積於該障壁層包含於該直通孔之露出表面上形成多數個釕單層,其中,該等多數個單層之每一者係藉由使一二環戊釕化 合物與該直通孔之該等露出表面反應,其後,使經電漿產生之氮基團與該直通孔之該等露出表面反應而形成。 The semiconductor substrate of claim 9, wherein the sealing layer is deposited on the exposed surface of the barrier layer to form a plurality of monolayers, wherein each of the plurality of monolayers is Dicyclopentane The compound reacts with the exposed surfaces of the through holes, and thereafter, the nitrogen groups generated by the plasma are formed by reacting with the exposed surfaces of the through holes. 如請求項6之半導體基材,其中,該直通孔貫穿孔具有少於30μm之直徑及多於200μm之直通孔深度。 The semiconductor substrate of claim 6, wherein the through hole through hole has a diameter of less than 30 μm and a through hole depth of more than 200 μm. 如請求項6之半導體基材,其中,該金屬化材料包含本體銅。 The semiconductor substrate of claim 6 wherein the metallization material comprises bulk copper. 一種用於製備用於金屬化之直通孔貫穿孔之方法,其中,該直通孔包含一內直徑表面及一底壁表面,該方法包含:- 使一包含至少一直通孔貫穿孔之基材置於一加工腔室內,該加工腔室係適於藉由原子層沉積(ALD)及藉由電漿增強原子層沉積(PEALD)塗敷材料沉積層;- 於該至少一直通孔貫穿孔之該內直徑表面及該底壁表面之每一者上形成一包含一第一材料之障壁層,其中,該第一材料具有少於300μohm-cm之電阻,且係以足夠厚度塗敷,以避免一金屬化材料經由該障壁層擴散;- 於該整個障壁層上形成一包含一第二材料之密封層,其中,該第二材料具有少於300μohm-cm之電阻,且該密封層之沉積係於未使該第一材料層曝露氧而實行;及- 於該整個密封層上形成一包含該第二材料之成核層,其中,該成核層之該形成包含使碳氧化。 A method for preparing a through-hole through-hole for metallization, wherein the through-hole comprises an inner diameter surface and a bottom wall surface, the method comprising: - placing a substrate comprising at least a through-hole through-hole In a processing chamber, the processing chamber is adapted to coat a material deposition layer by atomic layer deposition (ALD) and by plasma enhanced atomic layer deposition (PEALD); - at least the through hole through hole Forming a barrier layer comprising a first material on each of the inner diameter surface and the bottom wall surface, wherein the first material has a resistance of less than 300 μohm-cm and is coated with a sufficient thickness to avoid The metallized material is diffused through the barrier layer; a sealing layer comprising a second material is formed on the entire barrier layer, wherein the second material has a resistance of less than 300 μohm-cm, and the deposition of the sealing layer is The first material layer is not exposed to oxygen; and a nucleation layer comprising the second material is formed over the entire sealing layer, wherein the formation of the nucleation layer comprises oxidizing carbon. 如請求項14之方法,進一步包含:- 於該障壁層、該密封層,及該成核層之每一者形成期 間,使該加工腔室維持於少於1托耳之氣壓;及- 於未使該基材自該加工腔室移除下形成該障壁層、該密封層,及該成核層之每一者。 The method of claim 14, further comprising: - forming a period of each of the barrier layer, the sealing layer, and the nucleation layer Maintaining the processing chamber at a pressure of less than 1 Torr; and - forming the barrier layer, the sealing layer, and each of the nucleation layers without removing the substrate from the processing chamber By. 如請求項15之方法,進一步包含於該障壁層、該密封層,及該成核層之每一者形成期間,使該基材維持於一固定溫度。 The method of claim 15, further comprising maintaining the substrate at a fixed temperature during formation of the barrier layer, the sealing layer, and the nucleation layer. 如請求項16之方法,其中,該固定溫度係於199與401℃間之溫度。 The method of claim 16, wherein the fixed temperature is between 199 and 401 °C. 如請求項17之方法,進一步包含於該障壁層、該密封層,及該成核層之至少二者形成期間,使該基材維持於至少二不同固定溫度。 The method of claim 17, further comprising maintaining the substrate at at least two different fixed temperatures during formation of at least two of the barrier layer, the sealing layer, and the nucleation layer. 如請求項18之方法,其中,該等至少二不同固定溫度之每一者係於199至501℃間之溫度。 The method of claim 18, wherein each of the at least two different fixed temperatures is at a temperature between 199 and 501 °C. 如請求項14之方法,進一步包含自氮化鈦、鈦、氮化鉭、鉭、氮化鎢、氮化鈷,及鎢之至少一者形成該障壁層。 The method of claim 14, further comprising forming the barrier layer from at least one of titanium nitride, titanium, tantalum nitride, tantalum, tungsten nitride, cobalt nitride, and tungsten. 如請求項20之方法,進一步包含藉由熱原子層沉積形成該障壁層。 The method of claim 20, further comprising forming the barrier layer by thermal atomic layer deposition. 如請求項20之方法,進一步包含藉由電漿增強原子層沉積形成該障壁層。 The method of claim 20, further comprising forming the barrier layer by plasma enhanced atomic layer deposition. 如請求項14之方法,其中,該第一材料包含氮化鈦,該方法進一步包含藉由下述形成該障壁層之步驟:- 使該至少一直通孔貫穿孔之每一者的該內直徑表面及該底壁表面曝露於一包含四(二甲基醯胺基)鈦(TDMAT)之第一先質,持續一足以完成該TDMAT與該內直徑表面 及該底壁表面之自限制反應的曝露時間;- 沖洗來自該加工腔室之該TDMAT及反應副產物;- 使該至少一直通孔貫穿孔之每一者的該內直徑表面及該底壁表面曝露於一包含氮之第二先質,持續一段曝露時間,以完成該氮與該內直徑表面及該底壁表面之自限制反應;- 沖洗來自該加工腔室之該氮及反應副產物;- 重複該等如上之曝露及沖洗步驟,至該第一材料厚度係19至201Å(1.9-20.1nm)之間為止。 The method of claim 14, wherein the first material comprises titanium nitride, the method further comprising the step of forming the barrier layer by: - making the inner diameter of the at least all through hole through each of the holes The surface and the surface of the bottom wall are exposed to a first precursor comprising tetrakis(dimethylammonium)titanium (TDMAT) for a duration sufficient to complete the TDMAT and the inner diameter surface And an exposure time of the self-limiting reaction of the bottom wall surface; - flushing the TDMAT and reaction by-products from the processing chamber; - the inner diameter surface and the bottom wall of each of the at least all through holes The surface is exposed to a second precursor comprising nitrogen for a period of exposure to complete the self-limiting reaction of the nitrogen with the inner diameter surface and the bottom wall surface; - flushing the nitrogen and reaction by-products from the processing chamber ;- Repeat the above exposure and rinsing steps until the thickness of the first material is between 19 and 201 Å (1.9-20.1 nm). 如請求項23之方法,進一步包含藉由一熱原子層沉積方法形成該障壁層,其中,該第二先質包含氨(NH3)。 The method of claim 23, further comprising forming the barrier layer by a thermal atomic layer deposition method, wherein the second precursor comprises ammonia (NH 3 ). 如請求項23之方法,進一步包含藉由一電漿增強原子層沉積方法形成該障壁層,其中,該第二先質包含經電漿激發之氮基團。 The method of claim 23, further comprising forming the barrier layer by a plasma enhanced atomic layer deposition method, wherein the second precursor comprises a plasma excited nitrogen group. 如請求項14之方法,其中,該第二材料包含釕。 The method of claim 14, wherein the second material comprises ruthenium. 如請求項26之方法,進一步包含藉由下述於該障壁層上形成該密封層:- 使該至少一直通孔貫穿孔之該內直徑表面及該底壁表面曝露於一包含一二環戊釕化合物之第一先質,持續一足以完成該二環戊釕化合物與該內直徑表面及該底壁表面之自限制反應的曝露時間;- 沖洗來自該加工腔室之該二環戊釕化合物;- 使該至少一直通孔貫穿孔之該內直徑及該底壁曝露於一包含經電漿產生之氮基團且無氧之第二先質; - 沖洗來自該加工腔室之該等氮基團及反應副產物;- 重複該等如上之曝露及沖洗步驟,至該密封層厚度係至少4Å為止。 The method of claim 26, further comprising forming the sealing layer on the barrier layer by: - exposing the inner diameter surface of the at least all through hole through hole and the surface of the bottom wall to a dicyclopentane a first precursor of the ruthenium compound, for an exposure time sufficient to complete a self-limiting reaction of the bicyclopentanyl compound with the inner diameter surface and the bottom wall surface; - flushing the bicyclopentanyl compound from the processing chamber The inner diameter of the at least all through hole through hole and the bottom wall are exposed to a second precursor comprising a plasma-generated nitrogen group and being oxygen-free; - flushing the nitrogen groups and reaction by-products from the processing chamber; - repeating the exposure and rinsing steps as above until the sealing layer has a thickness of at least 4 Å. 如請求項27之方法,進一步包含藉由下述於該密封層上形成該成核層之步驟:- 使該至少一直通孔貫穿孔之該內直徑表面及該底壁表面曝露於一包含一二環戊釕化合物之第一先質;- 沖洗來自該加工腔室之該二環戊釕化合物及反應副產物;- 使該至少一直通孔貫穿孔之該內直徑表面及該底壁表面曝露於一未經基團化之氧的第二先質;- 沖洗來自該加工腔室之該氧及反應副產物;- 重複該等如上之曝露及沖洗步驟,至該成核層厚度係至少49Å為止。 The method of claim 27, further comprising the step of forming the nucleation layer on the sealing layer by: - exposing the inner diameter surface of the at least all through hole through hole and the surface of the bottom wall to include one a first precursor of a dicyclopentanyl compound; - rinsing the dicyclopentanyl compound and reaction by-products from the processing chamber; - exposing the inner diameter surface of the at least all through hole through hole and the surface of the bottom wall a second precursor of un-encapsulated oxygen; - flushing the oxygen and reaction by-products from the processing chamber; - repeating the exposure and rinsing steps as described above, until the nucleation layer has a thickness of at least 49 Å until. 如請求項28之方法,進一步包含以銅使該直通孔金屬化,其中,該銅係塗覆於該成核層上。 The method of claim 28, further comprising metallizing the through via with copper, wherein the copper is applied to the nucleation layer.
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